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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_rcc.h 00004 * @author MCD Application Team 00005 * @brief Header file of RCC HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_HAL_RCC_H 00038 #define __STM32L4xx_HAL_RCC_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx_hal_def.h" 00046 00047 /** @addtogroup STM32L4xx_HAL_Driver 00048 * @{ 00049 */ 00050 00051 /** @addtogroup RCC 00052 * @{ 00053 */ 00054 00055 /* Exported types ------------------------------------------------------------*/ 00056 /** @defgroup RCC_Exported_Types RCC Exported Types 00057 * @{ 00058 */ 00059 00060 /** 00061 * @brief RCC PLL configuration structure definition 00062 */ 00063 typedef struct 00064 { 00065 uint32_t PLLState; /*!< The new state of the PLL. 00066 This parameter can be a value of @ref RCC_PLL_Config */ 00067 00068 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 00069 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 00070 00071 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 00072 This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. 00073 This parameter must be a number between Min_Data = 1 and Max_Data = 8 on the other devices */ 00074 00075 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 00076 This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ 00077 00078 uint32_t PLLP; /*!< PLLP: Division factor for SAI clock. 00079 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 00080 00081 uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks. 00082 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 00083 00084 uint32_t PLLR; /*!< PLLR: Division for the main system clock. 00085 User have to set the PLLR parameter correctly to not exceed max frequency 120MHZ 00086 on STM32L4Rx/STM32L4Sx devices else 80MHz on the other devices. 00087 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 00088 00089 }RCC_PLLInitTypeDef; 00090 00091 /** 00092 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition 00093 */ 00094 typedef struct 00095 { 00096 uint32_t OscillatorType; /*!< The oscillators to be configured. 00097 This parameter can be a value of @ref RCC_Oscillator_Type */ 00098 00099 uint32_t HSEState; /*!< The new state of the HSE. 00100 This parameter can be a value of @ref RCC_HSE_Config */ 00101 00102 uint32_t LSEState; /*!< The new state of the LSE. 00103 This parameter can be a value of @ref RCC_LSE_Config */ 00104 00105 uint32_t HSIState; /*!< The new state of the HSI. 00106 This parameter can be a value of @ref RCC_HSI_Config */ 00107 00108 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 00109 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices. 00110 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */ 00111 00112 uint32_t LSIState; /*!< The new state of the LSI. 00113 This parameter can be a value of @ref RCC_LSI_Config */ 00114 00115 uint32_t MSIState; /*!< The new state of the MSI. 00116 This parameter can be a value of @ref RCC_MSI_Config */ 00117 00118 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). 00119 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 00120 00121 uint32_t MSIClockRange; /*!< The MSI frequency range. 00122 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 00123 00124 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices). 00125 This parameter can be a value of @ref RCC_HSI48_Config */ 00126 00127 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 00128 00129 }RCC_OscInitTypeDef; 00130 00131 /** 00132 * @brief RCC System, AHB and APB busses clock configuration structure definition 00133 */ 00134 typedef struct 00135 { 00136 uint32_t ClockType; /*!< The clock to be configured. 00137 This parameter can be a value of @ref RCC_System_Clock_Type */ 00138 00139 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 00140 This parameter can be a value of @ref RCC_System_Clock_Source */ 00141 00142 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 00143 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 00144 00145 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 00146 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 00147 00148 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 00149 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 00150 00151 }RCC_ClkInitTypeDef; 00152 00153 /** 00154 * @} 00155 */ 00156 00157 /* Exported constants --------------------------------------------------------*/ 00158 /** @defgroup RCC_Exported_Constants RCC Exported Constants 00159 * @{ 00160 */ 00161 00162 /** @defgroup RCC_Timeout_Value Timeout Values 00163 * @{ 00164 */ 00165 #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 00166 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 00167 /** 00168 * @} 00169 */ 00170 00171 /** @defgroup RCC_Oscillator_Type Oscillator Type 00172 * @{ 00173 */ 00174 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ 00175 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ 00176 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ 00177 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ 00178 #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ 00179 #define RCC_OSCILLATORTYPE_MSI 0x00000010U /*!< MSI to configure */ 00180 #if defined(RCC_HSI48_SUPPORT) 00181 #define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ 00182 #endif /* RCC_HSI48_SUPPORT */ 00183 /** 00184 * @} 00185 */ 00186 00187 /** @defgroup RCC_HSE_Config HSE Config 00188 * @{ 00189 */ 00190 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 00191 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 00192 #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ 00193 /** 00194 * @} 00195 */ 00196 00197 /** @defgroup RCC_LSE_Config LSE Config 00198 * @{ 00199 */ 00200 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ 00201 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 00202 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ 00203 /** 00204 * @} 00205 */ 00206 00207 /** @defgroup RCC_HSI_Config HSI Config 00208 * @{ 00209 */ 00210 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 00211 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 00212 00213 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ 00214 defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 00215 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ 00216 #else 00217 #define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */ 00218 #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ 00219 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ 00220 /** 00221 * @} 00222 */ 00223 00224 /** @defgroup RCC_LSI_Config LSI Config 00225 * @{ 00226 */ 00227 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 00228 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 00229 /** 00230 * @} 00231 */ 00232 00233 /** @defgroup RCC_MSI_Config MSI Config 00234 * @{ 00235 */ 00236 #define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ 00237 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ 00238 00239 #define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ 00240 /** 00241 * @} 00242 */ 00243 00244 #if defined(RCC_HSI48_SUPPORT) 00245 /** @defgroup RCC_HSI48_Config HSI48 Config 00246 * @{ 00247 */ 00248 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 00249 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ 00250 /** 00251 * @} 00252 */ 00253 #else 00254 /** @defgroup RCC_HSI48_Config HSI48 Config 00255 * @{ 00256 */ 00257 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 00258 /** 00259 * @} 00260 */ 00261 #endif /* RCC_HSI48_SUPPORT */ 00262 00263 /** @defgroup RCC_PLL_Config PLL Config 00264 * @{ 00265 */ 00266 #define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ 00267 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ 00268 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ 00269 /** 00270 * @} 00271 */ 00272 00273 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 00274 * @{ 00275 */ 00276 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 00277 #define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */ 00278 #define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */ 00279 #define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */ 00280 #define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */ 00281 #define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */ 00282 #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ 00283 #define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */ 00284 #define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */ 00285 #define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */ 00286 #define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */ 00287 #define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */ 00288 #define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */ 00289 #define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */ 00290 #define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */ 00291 #define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */ 00292 #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ 00293 #define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */ 00294 #define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */ 00295 #define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */ 00296 #define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */ 00297 #define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */ 00298 #define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */ 00299 #define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */ 00300 #define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */ 00301 #define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */ 00302 #define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */ 00303 #define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */ 00304 #define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */ 00305 #define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */ 00306 #define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */ 00307 #else 00308 #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ 00309 #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ 00310 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 00311 /** 00312 * @} 00313 */ 00314 00315 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider 00316 * @{ 00317 */ 00318 #define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */ 00319 #define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */ 00320 #define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */ 00321 #define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */ 00322 /** 00323 * @} 00324 */ 00325 00326 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider 00327 * @{ 00328 */ 00329 #define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */ 00330 #define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */ 00331 #define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */ 00332 #define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */ 00333 /** 00334 * @} 00335 */ 00336 00337 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 00338 * @{ 00339 */ 00340 #define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ 00341 #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */ 00342 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ 00343 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ 00344 /** 00345 * @} 00346 */ 00347 00348 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output 00349 * @{ 00350 */ 00351 #if defined(RCC_PLLSAI2_SUPPORT) 00352 #define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */ 00353 #else 00354 #define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */ 00355 #endif /* RCC_PLLSAI2_SUPPORT */ 00356 #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */ 00357 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ 00358 /** 00359 * @} 00360 */ 00361 00362 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output 00363 * @{ 00364 */ 00365 #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */ 00366 #define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */ 00367 #define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */ 00368 /** 00369 * @} 00370 */ 00371 00372 #if defined(RCC_PLLSAI2_SUPPORT) 00373 00374 /** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output 00375 * @{ 00376 */ 00377 #define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */ 00378 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 00379 #define RCC_PLLSAI2_DSICLK RCC_PLLSAI2CFGR_PLLSAI2QEN /*!< PLLDSICLK selection from PLLSAI2 */ 00380 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 00381 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 00382 #define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */ 00383 #else 00384 #define RCC_PLLSAI2_LTDCCLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLLTDCCLK selection from PLLSAI2 */ 00385 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 00386 /** 00387 * @} 00388 */ 00389 00390 #endif /* RCC_PLLSAI2_SUPPORT */ 00391 00392 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 00393 * @{ 00394 */ 00395 #define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */ 00396 #define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */ 00397 #define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */ 00398 #define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */ 00399 #define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */ 00400 #define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */ 00401 #define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */ 00402 #define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */ 00403 #define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */ 00404 #define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */ 00405 #define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */ 00406 #define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */ 00407 /** 00408 * @} 00409 */ 00410 00411 /** @defgroup RCC_System_Clock_Type System Clock Type 00412 * @{ 00413 */ 00414 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 00415 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 00416 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 00417 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 00418 /** 00419 * @} 00420 */ 00421 00422 /** @defgroup RCC_System_Clock_Source System Clock Source 00423 * @{ 00424 */ 00425 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ 00426 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ 00427 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ 00428 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ 00429 /** 00430 * @} 00431 */ 00432 00433 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 00434 * @{ 00435 */ 00436 #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ 00437 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 00438 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 00439 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 00440 /** 00441 * @} 00442 */ 00443 00444 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 00445 * @{ 00446 */ 00447 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 00448 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 00449 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 00450 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 00451 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 00452 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 00453 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 00454 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 00455 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 00456 /** 00457 * @} 00458 */ 00459 00460 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source 00461 * @{ 00462 */ 00463 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 00464 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 00465 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 00466 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 00467 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 00468 /** 00469 * @} 00470 */ 00471 00472 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 00473 * @{ 00474 */ 00475 #define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ 00476 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 00477 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 00478 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 00479 /** 00480 * @} 00481 */ 00482 00483 /** @defgroup RCC_MCO_Index MCO Index 00484 * @{ 00485 */ 00486 #define RCC_MCO1 0x00000000U 00487 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 00488 /** 00489 * @} 00490 */ 00491 00492 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 00493 * @{ 00494 */ 00495 #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ 00496 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 00497 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ 00498 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ 00499 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ 00500 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ 00501 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ 00502 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ 00503 #if defined(RCC_HSI48_SUPPORT) 00504 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */ 00505 #endif /* RCC_HSI48_SUPPORT */ 00506 /** 00507 * @} 00508 */ 00509 00510 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler 00511 * @{ 00512 */ 00513 #define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ 00514 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ 00515 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ 00516 #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ 00517 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */ 00518 /** 00519 * @} 00520 */ 00521 00522 /** @defgroup RCC_Interrupt Interrupts 00523 * @{ 00524 */ 00525 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 00526 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 00527 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 00528 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 00529 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 00530 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 00531 #define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ 00532 #if defined(RCC_PLLSAI2_SUPPORT) 00533 #define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ 00534 #endif /* RCC_PLLSAI2_SUPPORT */ 00535 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ 00536 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 00537 #if defined(RCC_HSI48_SUPPORT) 00538 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 00539 #endif /* RCC_HSI48_SUPPORT */ 00540 /** 00541 * @} 00542 */ 00543 00544 /** @defgroup RCC_Flag Flags 00545 * Elements values convention: XXXYYYYYb 00546 * - YYYYY : Flag position in the register 00547 * - XXX : Register index 00548 * - 001: CR register 00549 * - 010: BDCR register 00550 * - 011: CSR register 00551 * - 100: CRRCR register 00552 * @{ 00553 */ 00554 /* Flags in the CR register */ 00555 #define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ 00556 #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ 00557 #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ 00558 #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ 00559 #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ 00560 #if defined(RCC_PLLSAI2_SUPPORT) 00561 #define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */ 00562 #endif /* RCC_PLLSAI2_SUPPORT */ 00563 00564 /* Flags in the BDCR register */ 00565 #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ 00566 #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ 00567 00568 /* Flags in the CSR register */ 00569 #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ 00570 #define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos) /*!< Firewall reset flag */ 00571 #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ 00572 #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ 00573 #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ 00574 #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ 00575 #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ 00576 #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 00577 #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 00578 00579 #if defined(RCC_HSI48_SUPPORT) 00580 /* Flags in the CRRCR register */ 00581 #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ 00582 #endif /* RCC_HSI48_SUPPORT */ 00583 /** 00584 * @} 00585 */ 00586 00587 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 00588 * @{ 00589 */ 00590 #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ 00591 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 00592 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 00593 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 00594 /** 00595 * @} 00596 */ 00597 00598 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 00599 * @{ 00600 */ 00601 #define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ 00602 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ 00603 /** 00604 * @} 00605 */ 00606 00607 /** 00608 * @} 00609 */ 00610 00611 /* Exported macros -----------------------------------------------------------*/ 00612 00613 /** @defgroup RCC_Exported_Macros RCC Exported Macros 00614 * @{ 00615 */ 00616 00617 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 00618 * @brief Enable or disable the AHB1 peripheral clock. 00619 * @note After reset, the peripheral clock (used for registers read/write access) 00620 * is disabled and the application software has to enable this clock before 00621 * using it. 00622 * @{ 00623 */ 00624 00625 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 00626 __IO uint32_t tmpreg; \ 00627 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 00628 /* Delay after an RCC peripheral clock enabling */ \ 00629 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 00630 UNUSED(tmpreg); \ 00631 } while(0) 00632 00633 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 00634 __IO uint32_t tmpreg; \ 00635 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 00636 /* Delay after an RCC peripheral clock enabling */ \ 00637 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 00638 UNUSED(tmpreg); \ 00639 } while(0) 00640 00641 #if defined(DMAMUX1) 00642 #define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \ 00643 __IO uint32_t tmpreg; \ 00644 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 00645 /* Delay after an RCC peripheral clock enabling */ \ 00646 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 00647 UNUSED(tmpreg); \ 00648 } while(0) 00649 #endif /* DMAMUX1 */ 00650 00651 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 00652 __IO uint32_t tmpreg; \ 00653 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 00654 /* Delay after an RCC peripheral clock enabling */ \ 00655 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 00656 UNUSED(tmpreg); \ 00657 } while(0) 00658 00659 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 00660 __IO uint32_t tmpreg; \ 00661 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 00662 /* Delay after an RCC peripheral clock enabling */ \ 00663 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 00664 UNUSED(tmpreg); \ 00665 } while(0) 00666 00667 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 00668 __IO uint32_t tmpreg; \ 00669 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 00670 /* Delay after an RCC peripheral clock enabling */ \ 00671 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 00672 UNUSED(tmpreg); \ 00673 } while(0) 00674 00675 #if defined(DMA2D) 00676 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 00677 __IO uint32_t tmpreg; \ 00678 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 00679 /* Delay after an RCC peripheral clock enabling */ \ 00680 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 00681 UNUSED(tmpreg); \ 00682 } while(0) 00683 #endif /* DMA2D */ 00684 00685 #if defined(GFXMMU) 00686 #define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ 00687 __IO uint32_t tmpreg; \ 00688 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ 00689 /* Delay after an RCC peripheral clock enabling */ \ 00690 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ 00691 UNUSED(tmpreg); \ 00692 } while(0) 00693 #endif /* GFXMMU */ 00694 00695 00696 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) 00697 00698 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) 00699 00700 #if defined(DMAMUX1) 00701 #define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) 00702 #endif /* DMAMUX1 */ 00703 00704 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) 00705 00706 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) 00707 00708 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) 00709 00710 #if defined(DMA2D) 00711 #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) 00712 #endif /* DMA2D */ 00713 00714 #if defined(GFXMMU) 00715 #define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) 00716 #endif /* GFXMMU */ 00717 00718 /** 00719 * @} 00720 */ 00721 00722 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 00723 * @brief Enable or disable the AHB2 peripheral clock. 00724 * @note After reset, the peripheral clock (used for registers read/write access) 00725 * is disabled and the application software has to enable this clock before 00726 * using it. 00727 * @{ 00728 */ 00729 00730 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 00731 __IO uint32_t tmpreg; \ 00732 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 00733 /* Delay after an RCC peripheral clock enabling */ \ 00734 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 00735 UNUSED(tmpreg); \ 00736 } while(0) 00737 00738 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 00739 __IO uint32_t tmpreg; \ 00740 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 00741 /* Delay after an RCC peripheral clock enabling */ \ 00742 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 00743 UNUSED(tmpreg); \ 00744 } while(0) 00745 00746 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 00747 __IO uint32_t tmpreg; \ 00748 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 00749 /* Delay after an RCC peripheral clock enabling */ \ 00750 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 00751 UNUSED(tmpreg); \ 00752 } while(0) 00753 00754 #if defined(GPIOD) 00755 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 00756 __IO uint32_t tmpreg; \ 00757 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 00758 /* Delay after an RCC peripheral clock enabling */ \ 00759 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 00760 UNUSED(tmpreg); \ 00761 } while(0) 00762 #endif /* GPIOD */ 00763 00764 #if defined(GPIOE) 00765 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 00766 __IO uint32_t tmpreg; \ 00767 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 00768 /* Delay after an RCC peripheral clock enabling */ \ 00769 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 00770 UNUSED(tmpreg); \ 00771 } while(0) 00772 #endif /* GPIOE */ 00773 00774 #if defined(GPIOF) 00775 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 00776 __IO uint32_t tmpreg; \ 00777 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 00778 /* Delay after an RCC peripheral clock enabling */ \ 00779 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 00780 UNUSED(tmpreg); \ 00781 } while(0) 00782 #endif /* GPIOF */ 00783 00784 #if defined(GPIOG) 00785 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 00786 __IO uint32_t tmpreg; \ 00787 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 00788 /* Delay after an RCC peripheral clock enabling */ \ 00789 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 00790 UNUSED(tmpreg); \ 00791 } while(0) 00792 #endif /* GPIOG */ 00793 00794 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 00795 __IO uint32_t tmpreg; \ 00796 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 00797 /* Delay after an RCC peripheral clock enabling */ \ 00798 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 00799 UNUSED(tmpreg); \ 00800 } while(0) 00801 00802 #if defined(GPIOI) 00803 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 00804 __IO uint32_t tmpreg; \ 00805 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ 00806 /* Delay after an RCC peripheral clock enabling */ \ 00807 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ 00808 UNUSED(tmpreg); \ 00809 } while(0) 00810 #endif /* GPIOI */ 00811 00812 #if defined(USB_OTG_FS) 00813 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ 00814 __IO uint32_t tmpreg; \ 00815 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ 00816 /* Delay after an RCC peripheral clock enabling */ \ 00817 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ 00818 UNUSED(tmpreg); \ 00819 } while(0) 00820 #endif /* USB_OTG_FS */ 00821 00822 #define __HAL_RCC_ADC_CLK_ENABLE() do { \ 00823 __IO uint32_t tmpreg; \ 00824 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 00825 /* Delay after an RCC peripheral clock enabling */ \ 00826 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 00827 UNUSED(tmpreg); \ 00828 } while(0) 00829 00830 #if defined(DCMI) 00831 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 00832 __IO uint32_t tmpreg; \ 00833 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ 00834 /* Delay after an RCC peripheral clock enabling */ \ 00835 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ 00836 UNUSED(tmpreg); \ 00837 } while(0) 00838 #endif /* DCMI */ 00839 00840 #if defined(AES) 00841 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 00842 __IO uint32_t tmpreg; \ 00843 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 00844 /* Delay after an RCC peripheral clock enabling */ \ 00845 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 00846 UNUSED(tmpreg); \ 00847 } while(0) 00848 #endif /* AES */ 00849 00850 #if defined(HASH) 00851 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 00852 __IO uint32_t tmpreg; \ 00853 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 00854 /* Delay after an RCC peripheral clock enabling */ \ 00855 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 00856 UNUSED(tmpreg); \ 00857 } while(0) 00858 #endif /* HASH */ 00859 00860 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 00861 __IO uint32_t tmpreg; \ 00862 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 00863 /* Delay after an RCC peripheral clock enabling */ \ 00864 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 00865 UNUSED(tmpreg); \ 00866 } while(0) 00867 00868 #if defined(OCTOSPIM) 00869 #define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ 00870 __IO uint32_t tmpreg; \ 00871 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ 00872 /* Delay after an RCC peripheral clock enabling */ \ 00873 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ 00874 UNUSED(tmpreg); \ 00875 } while(0) 00876 #endif /* OCTOSPIM */ 00877 00878 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 00879 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 00880 __IO uint32_t tmpreg; \ 00881 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ 00882 /* Delay after an RCC peripheral clock enabling */ \ 00883 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ 00884 UNUSED(tmpreg); \ 00885 } while(0) 00886 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 00887 00888 00889 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) 00890 00891 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) 00892 00893 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) 00894 00895 #if defined(GPIOD) 00896 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) 00897 #endif /* GPIOD */ 00898 00899 #if defined(GPIOE) 00900 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) 00901 #endif /* GPIOE */ 00902 00903 #if defined(GPIOF) 00904 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) 00905 #endif /* GPIOF */ 00906 00907 #if defined(GPIOG) 00908 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) 00909 #endif /* GPIOG */ 00910 00911 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) 00912 00913 #if defined(GPIOI) 00914 #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) 00915 #endif /* GPIOI */ 00916 00917 #if defined(USB_OTG_FS) 00918 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); 00919 #endif /* USB_OTG_FS */ 00920 00921 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) 00922 00923 #if defined(DCMI) 00924 #define __HAL_RCC_DCMI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) 00925 #endif /* DCMI */ 00926 00927 #if defined(AES) 00928 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); 00929 #endif /* AES */ 00930 00931 #if defined(HASH) 00932 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) 00933 #endif /* HASH */ 00934 00935 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) 00936 00937 #if defined(OCTOSPIM) 00938 #define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) 00939 #endif /* OCTOSPIM */ 00940 00941 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 00942 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) 00943 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 00944 00945 /** 00946 * @} 00947 */ 00948 00949 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 00950 * @brief Enable or disable the AHB3 peripheral clock. 00951 * @note After reset, the peripheral clock (used for registers read/write access) 00952 * is disabled and the application software has to enable this clock before 00953 * using it. 00954 * @{ 00955 */ 00956 00957 #if defined(FMC_BANK1) 00958 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 00959 __IO uint32_t tmpreg; \ 00960 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 00961 /* Delay after an RCC peripheral clock enabling */ \ 00962 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 00963 UNUSED(tmpreg); \ 00964 } while(0) 00965 #endif /* FMC_BANK1 */ 00966 00967 #if defined(QUADSPI) 00968 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 00969 __IO uint32_t tmpreg; \ 00970 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ 00971 /* Delay after an RCC peripheral clock enabling */ \ 00972 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ 00973 UNUSED(tmpreg); \ 00974 } while(0) 00975 #endif /* QUADSPI */ 00976 00977 #if defined(OCTOSPI1) 00978 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ 00979 __IO uint32_t tmpreg; \ 00980 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ 00981 /* Delay after an RCC peripheral clock enabling */ \ 00982 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ 00983 UNUSED(tmpreg); \ 00984 } while(0) 00985 #endif /* OCTOSPI1 */ 00986 00987 #if defined(OCTOSPI2) 00988 #define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ 00989 __IO uint32_t tmpreg; \ 00990 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ 00991 /* Delay after an RCC peripheral clock enabling */ \ 00992 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ 00993 UNUSED(tmpreg); \ 00994 } while(0) 00995 #endif /* OCTOSPI2 */ 00996 00997 #if defined(FMC_BANK1) 00998 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) 00999 #endif /* FMC_BANK1 */ 01000 01001 #if defined(QUADSPI) 01002 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) 01003 #endif /* QUADSPI */ 01004 01005 #if defined(OCTOSPI1) 01006 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) 01007 #endif /* OCTOSPI1 */ 01008 01009 #if defined(OCTOSPI2) 01010 #define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) 01011 #endif /* OCTOSPI2 */ 01012 01013 /** 01014 * @} 01015 */ 01016 01017 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 01018 * @brief Enable or disable the APB1 peripheral clock. 01019 * @note After reset, the peripheral clock (used for registers read/write access) 01020 * is disabled and the application software has to enable this clock before 01021 * using it. 01022 * @{ 01023 */ 01024 01025 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 01026 __IO uint32_t tmpreg; \ 01027 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 01028 /* Delay after an RCC peripheral clock enabling */ \ 01029 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 01030 UNUSED(tmpreg); \ 01031 } while(0) 01032 01033 #if defined(TIM3) 01034 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 01035 __IO uint32_t tmpreg; \ 01036 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 01037 /* Delay after an RCC peripheral clock enabling */ \ 01038 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 01039 UNUSED(tmpreg); \ 01040 } while(0) 01041 #endif /* TIM3 */ 01042 01043 #if defined(TIM4) 01044 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 01045 __IO uint32_t tmpreg; \ 01046 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 01047 /* Delay after an RCC peripheral clock enabling */ \ 01048 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 01049 UNUSED(tmpreg); \ 01050 } while(0) 01051 #endif /* TIM4 */ 01052 01053 #if defined(TIM5) 01054 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 01055 __IO uint32_t tmpreg; \ 01056 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 01057 /* Delay after an RCC peripheral clock enabling */ \ 01058 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 01059 UNUSED(tmpreg); \ 01060 } while(0) 01061 #endif /* TIM5 */ 01062 01063 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 01064 __IO uint32_t tmpreg; \ 01065 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 01066 /* Delay after an RCC peripheral clock enabling */ \ 01067 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 01068 UNUSED(tmpreg); \ 01069 } while(0) 01070 01071 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 01072 __IO uint32_t tmpreg; \ 01073 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 01074 /* Delay after an RCC peripheral clock enabling */ \ 01075 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 01076 UNUSED(tmpreg); \ 01077 } while(0) 01078 01079 #if defined(LCD) 01080 #define __HAL_RCC_LCD_CLK_ENABLE() do { \ 01081 __IO uint32_t tmpreg; \ 01082 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ 01083 /* Delay after an RCC peripheral clock enabling */ \ 01084 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ 01085 UNUSED(tmpreg); \ 01086 } while(0) 01087 #endif /* LCD */ 01088 01089 #if defined(RCC_APB1ENR1_RTCAPBEN) 01090 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 01091 __IO uint32_t tmpreg; \ 01092 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 01093 /* Delay after an RCC peripheral clock enabling */ \ 01094 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 01095 UNUSED(tmpreg); \ 01096 } while(0) 01097 #endif /* RCC_APB1ENR1_RTCAPBEN */ 01098 01099 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 01100 __IO uint32_t tmpreg; \ 01101 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 01102 /* Delay after an RCC peripheral clock enabling */ \ 01103 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 01104 UNUSED(tmpreg); \ 01105 } while(0) 01106 01107 #if defined(SPI2) 01108 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 01109 __IO uint32_t tmpreg; \ 01110 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 01111 /* Delay after an RCC peripheral clock enabling */ \ 01112 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 01113 UNUSED(tmpreg); \ 01114 } while(0) 01115 #endif /* SPI2 */ 01116 01117 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 01118 __IO uint32_t tmpreg; \ 01119 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 01120 /* Delay after an RCC peripheral clock enabling */ \ 01121 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 01122 UNUSED(tmpreg); \ 01123 } while(0) 01124 01125 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 01126 __IO uint32_t tmpreg; \ 01127 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 01128 /* Delay after an RCC peripheral clock enabling */ \ 01129 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 01130 UNUSED(tmpreg); \ 01131 } while(0) 01132 01133 #if defined(USART3) 01134 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 01135 __IO uint32_t tmpreg; \ 01136 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 01137 /* Delay after an RCC peripheral clock enabling */ \ 01138 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 01139 UNUSED(tmpreg); \ 01140 } while(0) 01141 #endif /* USART3 */ 01142 01143 #if defined(UART4) 01144 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 01145 __IO uint32_t tmpreg; \ 01146 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 01147 /* Delay after an RCC peripheral clock enabling */ \ 01148 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 01149 UNUSED(tmpreg); \ 01150 } while(0) 01151 #endif /* UART4 */ 01152 01153 #if defined(UART5) 01154 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 01155 __IO uint32_t tmpreg; \ 01156 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 01157 /* Delay after an RCC peripheral clock enabling */ \ 01158 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 01159 UNUSED(tmpreg); \ 01160 } while(0) 01161 #endif /* UART5 */ 01162 01163 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 01164 __IO uint32_t tmpreg; \ 01165 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 01166 /* Delay after an RCC peripheral clock enabling */ \ 01167 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 01168 UNUSED(tmpreg); \ 01169 } while(0) 01170 01171 #if defined(I2C2) 01172 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 01173 __IO uint32_t tmpreg; \ 01174 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 01175 /* Delay after an RCC peripheral clock enabling */ \ 01176 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 01177 UNUSED(tmpreg); \ 01178 } while(0) 01179 #endif /* I2C2 */ 01180 01181 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 01182 __IO uint32_t tmpreg; \ 01183 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 01184 /* Delay after an RCC peripheral clock enabling */ \ 01185 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 01186 UNUSED(tmpreg); \ 01187 } while(0) 01188 01189 #if defined(I2C4) 01190 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 01191 __IO uint32_t tmpreg; \ 01192 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 01193 /* Delay after an RCC peripheral clock enabling */ \ 01194 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 01195 UNUSED(tmpreg); \ 01196 } while(0) 01197 #endif /* I2C4 */ 01198 01199 #if defined(CRS) 01200 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 01201 __IO uint32_t tmpreg; \ 01202 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 01203 /* Delay after an RCC peripheral clock enabling */ \ 01204 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 01205 UNUSED(tmpreg); \ 01206 } while(0) 01207 #endif /* CRS */ 01208 01209 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 01210 __IO uint32_t tmpreg; \ 01211 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ 01212 /* Delay after an RCC peripheral clock enabling */ \ 01213 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ 01214 UNUSED(tmpreg); \ 01215 } while(0) 01216 01217 #if defined(CAN2) 01218 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 01219 __IO uint32_t tmpreg; \ 01220 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \ 01221 /* Delay after an RCC peripheral clock enabling */ \ 01222 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \ 01223 UNUSED(tmpreg); \ 01224 } while(0) 01225 #endif /* CAN2 */ 01226 01227 #if defined(USB) 01228 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 01229 __IO uint32_t tmpreg; \ 01230 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ 01231 /* Delay after an RCC peripheral clock enabling */ \ 01232 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ 01233 UNUSED(tmpreg); \ 01234 } while(0) 01235 #endif /* USB */ 01236 01237 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 01238 __IO uint32_t tmpreg; \ 01239 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 01240 /* Delay after an RCC peripheral clock enabling */ \ 01241 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 01242 UNUSED(tmpreg); \ 01243 } while(0) 01244 01245 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 01246 __IO uint32_t tmpreg; \ 01247 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ 01248 /* Delay after an RCC peripheral clock enabling */ \ 01249 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ 01250 UNUSED(tmpreg); \ 01251 } while(0) 01252 01253 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 01254 __IO uint32_t tmpreg; \ 01255 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ 01256 /* Delay after an RCC peripheral clock enabling */ \ 01257 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ 01258 UNUSED(tmpreg); \ 01259 } while(0) 01260 01261 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 01262 __IO uint32_t tmpreg; \ 01263 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 01264 /* Delay after an RCC peripheral clock enabling */ \ 01265 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 01266 UNUSED(tmpreg); \ 01267 } while(0) 01268 01269 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 01270 __IO uint32_t tmpreg; \ 01271 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 01272 /* Delay after an RCC peripheral clock enabling */ \ 01273 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 01274 UNUSED(tmpreg); \ 01275 } while(0) 01276 01277 #if defined(SWPMI1) 01278 #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \ 01279 __IO uint32_t tmpreg; \ 01280 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ 01281 /* Delay after an RCC peripheral clock enabling */ \ 01282 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ 01283 UNUSED(tmpreg); \ 01284 } while(0) 01285 #endif /* SWPMI1 */ 01286 01287 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 01288 __IO uint32_t tmpreg; \ 01289 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 01290 /* Delay after an RCC peripheral clock enabling */ \ 01291 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 01292 UNUSED(tmpreg); \ 01293 } while(0) 01294 01295 01296 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) 01297 01298 #if defined(TIM3) 01299 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) 01300 #endif /* TIM3 */ 01301 01302 #if defined(TIM4) 01303 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) 01304 #endif /* TIM4 */ 01305 01306 #if defined(TIM5) 01307 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) 01308 #endif /* TIM5 */ 01309 01310 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) 01311 01312 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) 01313 01314 #if defined(LCD) 01315 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); 01316 #endif /* LCD */ 01317 01318 #if defined(RCC_APB1ENR1_RTCAPBEN) 01319 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); 01320 #endif /* RCC_APB1ENR1_RTCAPBEN */ 01321 01322 #if defined(SPI2) 01323 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) 01324 #endif /* SPI2 */ 01325 01326 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) 01327 01328 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) 01329 01330 #if defined(USART3) 01331 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) 01332 #endif /* USART3 */ 01333 01334 #if defined(UART4) 01335 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) 01336 #endif /* UART4 */ 01337 01338 #if defined(UART5) 01339 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) 01340 #endif /* UART5 */ 01341 01342 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) 01343 01344 #if defined(I2C2) 01345 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) 01346 #endif /* I2C2 */ 01347 01348 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) 01349 01350 #if defined(I2C4) 01351 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) 01352 #endif /* I2C4 */ 01353 01354 #if defined(CRS) 01355 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); 01356 #endif /* CRS */ 01357 01358 #define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) 01359 01360 #if defined(CAN2) 01361 #define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) 01362 #endif /* CAN2 */ 01363 01364 #if defined(USB) 01365 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); 01366 #endif /* USB */ 01367 01368 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) 01369 01370 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) 01371 01372 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) 01373 01374 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) 01375 01376 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) 01377 01378 #if defined(SWPMI1) 01379 #define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) 01380 #endif /* SWPMI1 */ 01381 01382 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) 01383 01384 /** 01385 * @} 01386 */ 01387 01388 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 01389 * @brief Enable or disable the APB2 peripheral clock. 01390 * @note After reset, the peripheral clock (used for registers read/write access) 01391 * is disabled and the application software has to enable this clock before 01392 * using it. 01393 * @{ 01394 */ 01395 01396 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 01397 __IO uint32_t tmpreg; \ 01398 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 01399 /* Delay after an RCC peripheral clock enabling */ \ 01400 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 01401 UNUSED(tmpreg); \ 01402 } while(0) 01403 01404 #define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \ 01405 __IO uint32_t tmpreg; \ 01406 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ 01407 /* Delay after an RCC peripheral clock enabling */ \ 01408 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ 01409 UNUSED(tmpreg); \ 01410 } while(0) 01411 01412 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 01413 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 01414 __IO uint32_t tmpreg; \ 01415 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ 01416 /* Delay after an RCC peripheral clock enabling */ \ 01417 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ 01418 UNUSED(tmpreg); \ 01419 } while(0) 01420 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 01421 01422 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 01423 __IO uint32_t tmpreg; \ 01424 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 01425 /* Delay after an RCC peripheral clock enabling */ \ 01426 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 01427 UNUSED(tmpreg); \ 01428 } while(0) 01429 01430 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 01431 __IO uint32_t tmpreg; \ 01432 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 01433 /* Delay after an RCC peripheral clock enabling */ \ 01434 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 01435 UNUSED(tmpreg); \ 01436 } while(0) 01437 01438 #if defined(TIM8) 01439 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 01440 __IO uint32_t tmpreg; \ 01441 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 01442 /* Delay after an RCC peripheral clock enabling */ \ 01443 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 01444 UNUSED(tmpreg); \ 01445 } while(0) 01446 #endif /* TIM8 */ 01447 01448 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 01449 __IO uint32_t tmpreg; \ 01450 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 01451 /* Delay after an RCC peripheral clock enabling */ \ 01452 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 01453 UNUSED(tmpreg); \ 01454 } while(0) 01455 01456 01457 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 01458 __IO uint32_t tmpreg; \ 01459 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 01460 /* Delay after an RCC peripheral clock enabling */ \ 01461 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 01462 UNUSED(tmpreg); \ 01463 } while(0) 01464 01465 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 01466 __IO uint32_t tmpreg; \ 01467 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 01468 /* Delay after an RCC peripheral clock enabling */ \ 01469 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 01470 UNUSED(tmpreg); \ 01471 } while(0) 01472 01473 #if defined(TIM17) 01474 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 01475 __IO uint32_t tmpreg; \ 01476 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 01477 /* Delay after an RCC peripheral clock enabling */ \ 01478 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 01479 UNUSED(tmpreg); \ 01480 } while(0) 01481 #endif /* TIM17 */ 01482 01483 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 01484 __IO uint32_t tmpreg; \ 01485 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 01486 /* Delay after an RCC peripheral clock enabling */ \ 01487 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 01488 UNUSED(tmpreg); \ 01489 } while(0) 01490 01491 #if defined(SAI2) 01492 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 01493 __IO uint32_t tmpreg; \ 01494 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 01495 /* Delay after an RCC peripheral clock enabling */ \ 01496 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 01497 UNUSED(tmpreg); \ 01498 } while(0) 01499 #endif /* SAI2 */ 01500 01501 #if defined(DFSDM1_Filter0) 01502 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ 01503 __IO uint32_t tmpreg; \ 01504 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ 01505 /* Delay after an RCC peripheral clock enabling */ \ 01506 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ 01507 UNUSED(tmpreg); \ 01508 } while(0) 01509 #endif /* DFSDM1_Filter0 */ 01510 01511 #if defined(LTDC) 01512 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ 01513 __IO uint32_t tmpreg; \ 01514 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ 01515 /* Delay after an RCC peripheral clock enabling */ \ 01516 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ 01517 UNUSED(tmpreg); \ 01518 } while(0) 01519 #endif /* LTDC */ 01520 01521 #if defined(DSI) 01522 #define __HAL_RCC_DSI_CLK_ENABLE() do { \ 01523 __IO uint32_t tmpreg; \ 01524 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ 01525 /* Delay after an RCC peripheral clock enabling */ \ 01526 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ 01527 UNUSED(tmpreg); \ 01528 } while(0) 01529 #endif /* DSI */ 01530 01531 01532 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) 01533 01534 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 01535 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) 01536 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 01537 01538 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 01539 01540 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 01541 01542 #if defined(TIM8) 01543 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) 01544 #endif /* TIM8 */ 01545 01546 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 01547 01548 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) 01549 01550 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 01551 01552 #if defined(TIM17) 01553 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 01554 #endif /* TIM17 */ 01555 01556 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 01557 01558 #if defined(SAI2) 01559 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) 01560 #endif /* SAI2 */ 01561 01562 #if defined(DFSDM1_Filter0) 01563 #define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) 01564 #endif /* DFSDM1_Filter0 */ 01565 01566 #if defined(LTDC) 01567 #define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) 01568 #endif /* LTDC */ 01569 01570 #if defined(DSI) 01571 #define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) 01572 #endif /* DSI */ 01573 01574 /** 01575 * @} 01576 */ 01577 01578 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 01579 * @brief Check whether the AHB1 peripheral clock is enabled or not. 01580 * @note After reset, the peripheral clock (used for registers read/write access) 01581 * is disabled and the application software has to enable this clock before 01582 * using it. 01583 * @{ 01584 */ 01585 01586 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET) 01587 01588 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET) 01589 01590 #if defined(DMAMUX1) 01591 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != RESET) 01592 #endif /* DMAMUX1 */ 01593 01594 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET) 01595 01596 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET) 01597 01598 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET) 01599 01600 #if defined(DMA2D) 01601 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != RESET) 01602 #endif /* DMA2D */ 01603 01604 #if defined(GFXMMU) 01605 #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != RESET) 01606 #endif /* GFXMMU */ 01607 01608 01609 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET) 01610 01611 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET) 01612 01613 #if defined(DMAMUX1) 01614 #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == RESET) 01615 #endif /* DMAMUX1 */ 01616 01617 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET) 01618 01619 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET) 01620 01621 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET) 01622 01623 #if defined(DMA2D) 01624 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == RESET) 01625 #endif /* DMA2D */ 01626 01627 #if defined(GFXMMU) 01628 #define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == RESET) 01629 #endif /* GFXMMU */ 01630 01631 /** 01632 * @} 01633 */ 01634 01635 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 01636 * @brief Check whether the AHB2 peripheral clock is enabled or not. 01637 * @note After reset, the peripheral clock (used for registers read/write access) 01638 * is disabled and the application software has to enable this clock before 01639 * using it. 01640 * @{ 01641 */ 01642 01643 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET) 01644 01645 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != RESET) 01646 01647 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET) 01648 01649 #if defined(GPIOD) 01650 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET) 01651 #endif /* GPIOD */ 01652 01653 #if defined(GPIOE) 01654 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET) 01655 #endif /* GPIOE */ 01656 01657 #if defined(GPIOF) 01658 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET) 01659 #endif /* GPIOF */ 01660 01661 #if defined(GPIOG) 01662 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET) 01663 #endif /* GPIOG */ 01664 01665 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET) 01666 01667 #if defined(GPIOI) 01668 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != RESET) 01669 #endif /* GPIOI */ 01670 01671 #if defined(USB_OTG_FS) 01672 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET) 01673 #endif /* USB_OTG_FS */ 01674 01675 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET) 01676 01677 #if defined(DCMI) 01678 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != RESET) 01679 #endif /* DCMI */ 01680 01681 #if defined(AES) 01682 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET) 01683 #endif /* AES */ 01684 01685 #if defined(HASH) 01686 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != RESET) 01687 #endif /* HASH */ 01688 01689 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET) 01690 01691 01692 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET) 01693 01694 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET) 01695 01696 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET) 01697 01698 #if defined(GPIOD) 01699 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET) 01700 #endif /* GPIOD */ 01701 01702 #if defined(GPIOE) 01703 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET) 01704 #endif /* GPIOE */ 01705 01706 #if defined(GPIOF) 01707 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET) 01708 #endif /* GPIOF */ 01709 01710 #if defined(GPIOG) 01711 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET) 01712 #endif /* GPIOG */ 01713 01714 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET) 01715 01716 #if defined(GPIOI) 01717 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == RESET) 01718 #endif /* GPIOI */ 01719 01720 #if defined(USB_OTG_FS) 01721 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET) 01722 #endif /* USB_OTG_FS */ 01723 01724 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET) 01725 01726 #if defined(DCMI) 01727 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == RESET) 01728 #endif /* DCMI */ 01729 01730 #if defined(AES) 01731 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET) 01732 #endif /* AES */ 01733 01734 #if defined(HASH) 01735 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == RESET) 01736 #endif /* HASH */ 01737 01738 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET) 01739 01740 /** 01741 * @} 01742 */ 01743 01744 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 01745 * @brief Check whether the AHB3 peripheral clock is enabled or not. 01746 * @note After reset, the peripheral clock (used for registers read/write access) 01747 * is disabled and the application software has to enable this clock before 01748 * using it. 01749 * @{ 01750 */ 01751 01752 #if defined(FMC_BANK1) 01753 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET) 01754 #endif /* FMC_BANK1 */ 01755 01756 #if defined(QUADSPI) 01757 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET) 01758 #endif /* QUADSPI */ 01759 01760 #if defined(FMC_BANK1) 01761 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET) 01762 #endif /* FMC_BANK1 */ 01763 01764 #if defined(QUADSPI) 01765 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET) 01766 #endif /* QUADSPI */ 01767 01768 /** 01769 * @} 01770 */ 01771 01772 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 01773 * @brief Check whether the APB1 peripheral clock is enabled or not. 01774 * @note After reset, the peripheral clock (used for registers read/write access) 01775 * is disabled and the application software has to enable this clock before 01776 * using it. 01777 * @{ 01778 */ 01779 01780 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET) 01781 01782 #if defined(TIM3) 01783 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET) 01784 #endif /* TIM3 */ 01785 01786 #if defined(TIM4) 01787 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET) 01788 #endif /* TIM4 */ 01789 01790 #if defined(TIM5) 01791 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET) 01792 #endif /* TIM5 */ 01793 01794 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET) 01795 01796 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET) 01797 01798 #if defined(LCD) 01799 #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET) 01800 #endif /* LCD */ 01801 01802 #if defined(RCC_APB1ENR1_RTCAPBEN) 01803 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != RESET) 01804 #endif /* RCC_APB1ENR1_RTCAPBEN */ 01805 01806 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET) 01807 01808 #if defined(SPI2) 01809 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET) 01810 #endif /* SPI2 */ 01811 01812 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET) 01813 01814 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET) 01815 01816 #if defined(USART3) 01817 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET) 01818 #endif /* USART3 */ 01819 01820 #if defined(UART4) 01821 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET) 01822 #endif /* UART4 */ 01823 01824 #if defined(UART5) 01825 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET) 01826 #endif /* UART5 */ 01827 01828 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET) 01829 01830 #if defined(I2C2) 01831 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET) 01832 #endif /* I2C2 */ 01833 01834 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET) 01835 01836 #if defined(I2C4) 01837 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != RESET) 01838 #endif /* I2C4 */ 01839 01840 #if defined(CRS) 01841 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != RESET) 01842 #endif /* CRS */ 01843 01844 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET) 01845 01846 #if defined(CAN2) 01847 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != RESET) 01848 #endif /* CAN2 */ 01849 01850 #if defined(USB) 01851 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != RESET) 01852 #endif /* USB */ 01853 01854 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET) 01855 01856 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET) 01857 01858 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET) 01859 01860 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET) 01861 01862 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET) 01863 01864 #if defined(SWPMI1) 01865 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET) 01866 #endif /* SWPMI1 */ 01867 01868 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET) 01869 01870 01871 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET) 01872 01873 #if defined(TIM3) 01874 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET) 01875 #endif /* TIM3 */ 01876 01877 #if defined(TIM4) 01878 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET) 01879 #endif /* TIM4 */ 01880 01881 #if defined(TIM5) 01882 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET) 01883 #endif /* TIM5 */ 01884 01885 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET) 01886 01887 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET) 01888 01889 #if defined(LCD) 01890 #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET) 01891 #endif /* LCD */ 01892 01893 #if defined(RCC_APB1ENR1_RTCAPBEN) 01894 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == RESET) 01895 #endif /* RCC_APB1ENR1_RTCAPBEN */ 01896 01897 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET) 01898 01899 #if defined(SPI2) 01900 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET) 01901 #endif /* SPI2 */ 01902 01903 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET) 01904 01905 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET) 01906 01907 #if defined(USART3) 01908 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET) 01909 #endif /* USART3 */ 01910 01911 #if defined(UART4) 01912 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET) 01913 #endif /* UART4 */ 01914 01915 #if defined(UART5) 01916 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET) 01917 #endif /* UART5 */ 01918 01919 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET) 01920 01921 #if defined(I2C2) 01922 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET) 01923 #endif /* I2C2 */ 01924 01925 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET) 01926 01927 #if defined(I2C4) 01928 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == RESET) 01929 #endif /* I2C4 */ 01930 01931 #if defined(CRS) 01932 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == RESET) 01933 #endif /* CRS */ 01934 01935 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET) 01936 01937 #if defined(CAN2) 01938 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == RESET) 01939 #endif /* CAN2 */ 01940 01941 #if defined(USB) 01942 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == RESET) 01943 #endif /* USB */ 01944 01945 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET) 01946 01947 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET) 01948 01949 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET) 01950 01951 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET) 01952 01953 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET) 01954 01955 #if defined(SWPMI1) 01956 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET) 01957 #endif /* SWPMI1 */ 01958 01959 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET) 01960 01961 /** 01962 * @} 01963 */ 01964 01965 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 01966 * @brief Check whether the APB2 peripheral clock is enabled or not. 01967 * @note After reset, the peripheral clock (used for registers read/write access) 01968 * is disabled and the application software has to enable this clock before 01969 * using it. 01970 * @{ 01971 */ 01972 01973 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET) 01974 01975 #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET) 01976 01977 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 01978 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET) 01979 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 01980 01981 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET) 01982 01983 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET) 01984 01985 #if defined(TIM8) 01986 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET) 01987 #endif /* TIM8 */ 01988 01989 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET) 01990 01991 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET) 01992 01993 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET) 01994 01995 #if defined(TIM17) 01996 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET) 01997 #endif /* TIM17 */ 01998 01999 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET) 02000 02001 #if defined(SAI2) 02002 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET) 02003 #endif /* SAI2 */ 02004 02005 #if defined(DFSDM1_Filter0) 02006 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET) 02007 #endif /* DFSDM1_Filter0 */ 02008 02009 #if defined(LTDC) 02010 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != RESET) 02011 #endif /* LTDC */ 02012 02013 #if defined(DSI) 02014 #define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != RESET) 02015 #endif /* DSI */ 02016 02017 02018 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET) 02019 02020 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 02021 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET) 02022 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 02023 02024 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET) 02025 02026 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET) 02027 02028 #if defined(TIM8) 02029 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET) 02030 #endif /* TIM8 */ 02031 02032 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET) 02033 02034 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET) 02035 02036 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET) 02037 02038 #if defined(TIM17) 02039 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET) 02040 #endif /* TIM17 */ 02041 02042 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET) 02043 02044 #if defined(SAI2) 02045 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET) 02046 #endif /* SAI2 */ 02047 02048 #if defined(DFSDM1_Filter0) 02049 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET) 02050 #endif /* DFSDM1_Filter0 */ 02051 02052 #if defined(LTDC) 02053 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == RESET) 02054 #endif /* LTDC */ 02055 02056 #if defined(DSI) 02057 #define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == RESET) 02058 #endif /* DSI */ 02059 02060 /** 02061 * @} 02062 */ 02063 02064 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 02065 * @brief Force or release AHB1 peripheral reset. 02066 * @{ 02067 */ 02068 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU) 02069 02070 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 02071 02072 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 02073 02074 #if defined(DMAMUX1) 02075 #define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) 02076 #endif /* DMAMUX1 */ 02077 02078 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 02079 02080 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 02081 02082 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 02083 02084 #if defined(DMA2D) 02085 #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 02086 #endif /* DMA2D */ 02087 02088 #if defined(GFXMMU) 02089 #define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) 02090 #endif /* GFXMMU */ 02091 02092 02093 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) 02094 02095 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 02096 02097 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 02098 02099 #if defined(DMAMUX1) 02100 #define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) 02101 #endif /* DMAMUX1 */ 02102 02103 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 02104 02105 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 02106 02107 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 02108 02109 #if defined(DMA2D) 02110 #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 02111 #endif /* DMA2D */ 02112 02113 #if defined(GFXMMU) 02114 #define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) 02115 #endif /* GFXMMU */ 02116 02117 /** 02118 * @} 02119 */ 02120 02121 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 02122 * @brief Force or release AHB2 peripheral reset. 02123 * @{ 02124 */ 02125 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU) 02126 02127 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 02128 02129 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 02130 02131 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 02132 02133 #if defined(GPIOD) 02134 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 02135 #endif /* GPIOD */ 02136 02137 #if defined(GPIOE) 02138 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 02139 #endif /* GPIOE */ 02140 02141 #if defined(GPIOF) 02142 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 02143 #endif /* GPIOF */ 02144 02145 #if defined(GPIOG) 02146 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 02147 #endif /* GPIOG */ 02148 02149 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 02150 02151 #if defined(GPIOI) 02152 #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) 02153 #endif /* GPIOI */ 02154 02155 #if defined(USB_OTG_FS) 02156 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) 02157 #endif /* USB_OTG_FS */ 02158 02159 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 02160 02161 #if defined(DCMI) 02162 #define __HAL_RCC_DCMI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST) 02163 #endif /* DCMI */ 02164 02165 #if defined(AES) 02166 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 02167 #endif /* AES */ 02168 02169 #if defined(HASH) 02170 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 02171 #endif /* HASH */ 02172 02173 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 02174 02175 #if defined(OCTOSPIM) 02176 #define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) 02177 #endif /* OCTOSPIM */ 02178 02179 #if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) 02180 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) 02181 #endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ 02182 02183 02184 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) 02185 02186 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 02187 02188 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 02189 02190 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 02191 02192 #if defined(GPIOD) 02193 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 02194 #endif /* GPIOD */ 02195 02196 #if defined(GPIOE) 02197 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 02198 #endif /* GPIOE */ 02199 02200 #if defined(GPIOF) 02201 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 02202 #endif /* GPIOF */ 02203 02204 #if defined(GPIOG) 02205 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 02206 #endif /* GPIOG */ 02207 02208 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 02209 02210 #if defined(GPIOI) 02211 #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) 02212 #endif /* GPIOI */ 02213 02214 #if defined(USB_OTG_FS) 02215 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) 02216 #endif /* USB_OTG_FS */ 02217 02218 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 02219 02220 #if defined(DCMI) 02221 #define __HAL_RCC_DCMI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST) 02222 #endif /* DCMI */ 02223 02224 #if defined(AES) 02225 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 02226 #endif /* AES */ 02227 02228 #if defined(HASH) 02229 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 02230 #endif /* HASH */ 02231 02232 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 02233 02234 #if defined(OCTOSPIM) 02235 #define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) 02236 #endif /* OCTOSPIM */ 02237 02238 #if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) 02239 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) 02240 #endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ 02241 02242 /** 02243 * @} 02244 */ 02245 02246 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 02247 * @brief Force or release AHB3 peripheral reset. 02248 * @{ 02249 */ 02250 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU) 02251 02252 #if defined(FMC_BANK1) 02253 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 02254 #endif /* FMC_BANK1 */ 02255 02256 #if defined(QUADSPI) 02257 #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) 02258 #endif /* QUADSPI */ 02259 02260 #if defined(OCTOSPI1) 02261 #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) 02262 #endif /* OCTOSPI1 */ 02263 02264 #if defined(OCTOSPI2) 02265 #define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) 02266 #endif /* OCTOSPI2 */ 02267 02268 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) 02269 02270 #if defined(FMC_BANK1) 02271 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 02272 #endif /* FMC_BANK1 */ 02273 02274 #if defined(QUADSPI) 02275 #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) 02276 #endif /* QUADSPI */ 02277 02278 #if defined(OCTOSPI1) 02279 #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) 02280 #endif /* OCTOSPI1 */ 02281 02282 #if defined(OCTOSPI2) 02283 #define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) 02284 #endif /* OCTOSPI2 */ 02285 02286 /** 02287 * @} 02288 */ 02289 02290 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 02291 * @brief Force or release APB1 peripheral reset. 02292 * @{ 02293 */ 02294 #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU) 02295 02296 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 02297 02298 #if defined(TIM3) 02299 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 02300 #endif /* TIM3 */ 02301 02302 #if defined(TIM4) 02303 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 02304 #endif /* TIM4 */ 02305 02306 #if defined(TIM5) 02307 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 02308 #endif /* TIM5 */ 02309 02310 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 02311 02312 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 02313 02314 #if defined(LCD) 02315 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) 02316 #endif /* LCD */ 02317 02318 #if defined(SPI2) 02319 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 02320 #endif /* SPI2 */ 02321 02322 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 02323 02324 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 02325 02326 #if defined(USART3) 02327 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 02328 #endif /* USART3 */ 02329 02330 #if defined(UART4) 02331 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 02332 #endif /* UART4 */ 02333 02334 #if defined(UART5) 02335 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 02336 #endif /* UART5 */ 02337 02338 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 02339 02340 #if defined(I2C2) 02341 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 02342 #endif /* I2C2 */ 02343 02344 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 02345 02346 #if defined(I2C4) 02347 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 02348 #endif /* I2C4 */ 02349 02350 #if defined(CRS) 02351 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 02352 #endif /* CRS */ 02353 02354 #define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) 02355 02356 #if defined(CAN2) 02357 #define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) 02358 #endif /* CAN2 */ 02359 02360 #if defined(USB) 02361 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) 02362 #endif /* USB */ 02363 02364 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 02365 02366 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) 02367 02368 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) 02369 02370 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 02371 02372 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 02373 02374 #if defined(SWPMI1) 02375 #define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) 02376 #endif /* SWPMI1 */ 02377 02378 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 02379 02380 02381 #define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U) 02382 02383 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 02384 02385 #if defined(TIM3) 02386 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 02387 #endif /* TIM3 */ 02388 02389 #if defined(TIM4) 02390 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 02391 #endif /* TIM4 */ 02392 02393 #if defined(TIM5) 02394 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 02395 #endif /* TIM5 */ 02396 02397 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 02398 02399 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 02400 02401 #if defined(LCD) 02402 #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) 02403 #endif /* LCD */ 02404 02405 #if defined(SPI2) 02406 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 02407 #endif /* SPI2 */ 02408 02409 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 02410 02411 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 02412 02413 #if defined(USART3) 02414 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 02415 #endif /* USART3 */ 02416 02417 #if defined(UART4) 02418 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 02419 #endif /* UART4 */ 02420 02421 #if defined(UART5) 02422 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 02423 #endif /* UART5 */ 02424 02425 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 02426 02427 #if defined(I2C2) 02428 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 02429 #endif /* I2C2 */ 02430 02431 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 02432 02433 #if defined(I2C4) 02434 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 02435 #endif /* I2C4 */ 02436 02437 #if defined(CRS) 02438 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 02439 #endif /* CRS */ 02440 02441 #define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) 02442 02443 #if defined(CAN2) 02444 #define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) 02445 #endif /* CAN2 */ 02446 02447 #if defined(USB) 02448 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) 02449 #endif /* USB */ 02450 02451 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 02452 02453 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) 02454 02455 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) 02456 02457 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 02458 02459 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 02460 02461 #if defined(SWPMI1) 02462 #define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) 02463 #endif /* SWPMI1 */ 02464 02465 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 02466 02467 /** 02468 * @} 02469 */ 02470 02471 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 02472 * @brief Force or release APB2 peripheral reset. 02473 * @{ 02474 */ 02475 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU) 02476 02477 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 02478 02479 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) 02480 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) 02481 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ 02482 02483 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 02484 02485 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 02486 02487 #if defined(TIM8) 02488 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 02489 #endif /* TIM8 */ 02490 02491 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 02492 02493 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 02494 02495 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 02496 02497 #if defined(TIM17) 02498 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 02499 #endif /* TIM17 */ 02500 02501 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 02502 02503 #if defined(SAI2) 02504 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 02505 #endif /* SAI2 */ 02506 02507 #if defined(DFSDM1_Filter0) 02508 #define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) 02509 #endif /* DFSDM1_Filter0 */ 02510 02511 #if defined(LTDC) 02512 #define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) 02513 #endif /* LTDC */ 02514 02515 #if defined(DSI) 02516 #define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) 02517 #endif /* DSI */ 02518 02519 02520 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) 02521 02522 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 02523 02524 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) 02525 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) 02526 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ 02527 02528 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 02529 02530 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 02531 02532 #if defined(TIM8) 02533 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 02534 #endif /* TIM8 */ 02535 02536 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 02537 02538 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 02539 02540 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 02541 02542 #if defined(TIM17) 02543 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 02544 #endif /* TIM17 */ 02545 02546 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 02547 02548 #if defined(SAI2) 02549 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 02550 #endif /* SAI2 */ 02551 02552 #if defined(DFSDM1_Filter0) 02553 #define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) 02554 #endif /* DFSDM1_Filter0 */ 02555 02556 #if defined(LTDC) 02557 #define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) 02558 #endif /* LTDC */ 02559 02560 #if defined(DSI) 02561 #define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) 02562 #endif /* DSI */ 02563 02564 /** 02565 * @} 02566 */ 02567 02568 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 02569 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 02570 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02571 * power consumption. 02572 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02573 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02574 * @{ 02575 */ 02576 02577 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 02578 02579 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 02580 02581 #if defined(DMAMUX1) 02582 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) 02583 #endif /* DMAMUX1 */ 02584 02585 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 02586 02587 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 02588 02589 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 02590 02591 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 02592 02593 #if defined(DMA2D) 02594 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 02595 #endif /* DMA2D */ 02596 02597 #if defined(GFXMMU) 02598 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) 02599 #endif /* GFXMMU */ 02600 02601 02602 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 02603 02604 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 02605 02606 #if defined(DMAMUX1) 02607 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) 02608 #endif /* DMAMUX1 */ 02609 02610 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 02611 02612 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 02613 02614 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 02615 02616 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 02617 02618 #if defined(DMA2D) 02619 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 02620 #endif /* DMA2D */ 02621 02622 #if defined(GFXMMU) 02623 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) 02624 #endif /* GFXMMU */ 02625 02626 /** 02627 * @} 02628 */ 02629 02630 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 02631 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 02632 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02633 * power consumption. 02634 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02635 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02636 * @{ 02637 */ 02638 02639 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 02640 02641 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 02642 02643 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 02644 02645 #if defined(GPIOD) 02646 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 02647 #endif /* GPIOD */ 02648 02649 #if defined(GPIOE) 02650 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 02651 #endif /* GPIOE */ 02652 02653 #if defined(GPIOF) 02654 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 02655 #endif /* GPIOF */ 02656 02657 #if defined(GPIOG) 02658 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 02659 #endif /* GPIOG */ 02660 02661 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 02662 02663 #if defined(GPIOI) 02664 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) 02665 #endif /* GPIOI */ 02666 02667 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 02668 02669 #if defined(SRAM3) 02670 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) 02671 #endif /* SRAM3 */ 02672 02673 #if defined(USB_OTG_FS) 02674 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) 02675 #endif /* USB_OTG_FS */ 02676 02677 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) 02678 02679 #if defined(DCMI) 02680 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) 02681 #endif /* DCMI */ 02682 02683 #if defined(AES) 02684 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 02685 #endif /* AES */ 02686 02687 #if defined(HASH) 02688 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) 02689 #endif /* HASH */ 02690 02691 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 02692 02693 #if defined(OCTOSPIM) 02694 #define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) 02695 #endif /* OCTOSPIM */ 02696 02697 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 02698 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) 02699 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 02700 02701 02702 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 02703 02704 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 02705 02706 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 02707 02708 #if defined(GPIOD) 02709 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 02710 #endif /* GPIOD */ 02711 02712 #if defined(GPIOE) 02713 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 02714 #endif /* GPIOE */ 02715 02716 #if defined(GPIOF) 02717 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 02718 #endif /* GPIOF */ 02719 02720 #if defined(GPIOG) 02721 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 02722 #endif /* GPIOG */ 02723 02724 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 02725 02726 #if defined(GPIOI) 02727 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) 02728 #endif /* GPIOI */ 02729 02730 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 02731 02732 #if defined(SRAM3) 02733 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) 02734 #endif /* SRAM3 */ 02735 02736 #if defined(USB_OTG_FS) 02737 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) 02738 #endif /* USB_OTG_FS */ 02739 02740 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) 02741 02742 #if defined(DCMI) 02743 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) 02744 #endif /* DCMI */ 02745 02746 #if defined(AES) 02747 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 02748 #endif /* AES */ 02749 02750 #if defined(HASH) 02751 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) 02752 #endif /* HASH */ 02753 02754 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 02755 02756 #if defined(OCTOSPIM) 02757 #define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) 02758 #endif /* OCTOSPIM */ 02759 02760 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 02761 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) 02762 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 02763 02764 /** 02765 * @} 02766 */ 02767 02768 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable 02769 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 02770 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02771 * power consumption. 02772 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02773 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02774 * @{ 02775 */ 02776 02777 #if defined(QUADSPI) 02778 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) 02779 #endif /* QUADSPI */ 02780 02781 #if defined(OCTOSPI1) 02782 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) 02783 #endif /* OCTOSPI1 */ 02784 02785 #if defined(OCTOSPI2) 02786 #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) 02787 #endif /* OCTOSPI2 */ 02788 02789 #if defined(FMC_BANK1) 02790 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 02791 #endif /* FMC_BANK1 */ 02792 02793 #if defined(QUADSPI) 02794 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) 02795 #endif /* QUADSPI */ 02796 02797 #if defined(OCTOSPI1) 02798 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) 02799 #endif /* OCTOSPI1 */ 02800 02801 #if defined(OCTOSPI2) 02802 #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) 02803 #endif /* OCTOSPI2 */ 02804 02805 #if defined(FMC_BANK1) 02806 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 02807 #endif /* FMC_BANK1 */ 02808 02809 /** 02810 * @} 02811 */ 02812 02813 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 02814 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 02815 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02816 * power consumption. 02817 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02818 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02819 * @{ 02820 */ 02821 02822 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 02823 02824 #if defined(TIM3) 02825 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 02826 #endif /* TIM3 */ 02827 02828 #if defined(TIM4) 02829 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 02830 #endif /* TIM4 */ 02831 02832 #if defined(TIM5) 02833 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 02834 #endif /* TIM5 */ 02835 02836 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 02837 02838 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 02839 02840 #if defined(LCD) 02841 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) 02842 #endif /* LCD */ 02843 02844 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 02845 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 02846 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 02847 02848 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 02849 02850 #if defined(SPI2) 02851 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 02852 #endif /* SPI2 */ 02853 02854 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 02855 02856 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 02857 02858 #if defined(USART3) 02859 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 02860 #endif /* USART3 */ 02861 02862 #if defined(UART4) 02863 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 02864 #endif /* UART4 */ 02865 02866 #if defined(UART5) 02867 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 02868 #endif /* UART5 */ 02869 02870 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 02871 02872 #if defined(I2C2) 02873 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 02874 #endif /* I2C2 */ 02875 02876 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 02877 02878 #if defined(I2C4) 02879 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 02880 #endif /* I2C4 */ 02881 02882 #if defined(CRS) 02883 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 02884 #endif /* CRS */ 02885 02886 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) 02887 02888 #if defined(CAN2) 02889 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) 02890 #endif /* CAN2 */ 02891 02892 #if defined(USB) 02893 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) 02894 #endif /* USB */ 02895 02896 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 02897 02898 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) 02899 02900 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) 02901 02902 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 02903 02904 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 02905 02906 #if defined(SWPMI1) 02907 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) 02908 #endif /* SWPMI1 */ 02909 02910 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 02911 02912 02913 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 02914 02915 #if defined(TIM3) 02916 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 02917 #endif /* TIM3 */ 02918 02919 #if defined(TIM4) 02920 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 02921 #endif /* TIM4 */ 02922 02923 #if defined(TIM5) 02924 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 02925 #endif /* TIM5 */ 02926 02927 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 02928 02929 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 02930 02931 #if defined(LCD) 02932 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) 02933 #endif /* LCD */ 02934 02935 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 02936 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 02937 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 02938 02939 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 02940 02941 #if defined(SPI2) 02942 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 02943 #endif /* SPI2 */ 02944 02945 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 02946 02947 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 02948 02949 #if defined(USART3) 02950 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 02951 #endif /* USART3 */ 02952 02953 #if defined(UART4) 02954 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 02955 #endif /* UART4 */ 02956 02957 #if defined(UART5) 02958 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 02959 #endif /* UART5 */ 02960 02961 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 02962 02963 #if defined(I2C2) 02964 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 02965 #endif /* I2C2 */ 02966 02967 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 02968 02969 #if defined(I2C4) 02970 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 02971 #endif /* I2C4 */ 02972 02973 #if defined(CRS) 02974 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 02975 #endif /* CRS */ 02976 02977 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) 02978 02979 #if defined(CAN2) 02980 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) 02981 #endif /* CAN2 */ 02982 02983 #if defined(USB) 02984 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) 02985 #endif /* USB */ 02986 02987 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 02988 02989 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) 02990 02991 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) 02992 02993 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 02994 02995 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 02996 02997 #if defined(SWPMI1) 02998 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) 02999 #endif /* SWPMI1 */ 03000 03001 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 03002 03003 /** 03004 * @} 03005 */ 03006 03007 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 03008 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 03009 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03010 * power consumption. 03011 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 03012 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03013 * @{ 03014 */ 03015 03016 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 03017 03018 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 03019 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) 03020 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 03021 03022 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 03023 03024 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 03025 03026 #if defined(TIM8) 03027 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 03028 #endif /* TIM8 */ 03029 03030 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 03031 03032 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 03033 03034 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 03035 03036 #if defined(TIM17) 03037 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 03038 #endif /* TIM17 */ 03039 03040 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 03041 03042 #if defined(SAI2) 03043 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 03044 #endif /* SAI2 */ 03045 03046 #if defined(DFSDM1_Filter0) 03047 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) 03048 #endif /* DFSDM1_Filter0 */ 03049 03050 #if defined(LTDC) 03051 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) 03052 #endif /* LTDC */ 03053 03054 #if defined(DSI) 03055 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) 03056 #endif /* DSI */ 03057 03058 03059 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 03060 03061 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 03062 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) 03063 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 03064 03065 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 03066 03067 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 03068 03069 #if defined(TIM8) 03070 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 03071 #endif /* TIM8 */ 03072 03073 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 03074 03075 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 03076 03077 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 03078 03079 #if defined(TIM17) 03080 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 03081 #endif /* TIM17 */ 03082 03083 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 03084 03085 #if defined(SAI2) 03086 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 03087 #endif /* SAI2 */ 03088 03089 #if defined(DFSDM1_Filter0) 03090 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) 03091 #endif /* DFSDM1_Filter0 */ 03092 03093 #if defined(LTDC) 03094 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) 03095 #endif /* LTDC */ 03096 03097 #if defined(DSI) 03098 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) 03099 #endif /* DSI */ 03100 03101 /** 03102 * @} 03103 */ 03104 03105 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status 03106 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 03107 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03108 * power consumption. 03109 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 03110 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03111 * @{ 03112 */ 03113 03114 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET) 03115 03116 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET) 03117 03118 #if defined(DMAMUX1) 03119 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET) 03120 #endif /* DMAMUX1 */ 03121 03122 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET) 03123 03124 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET) 03125 03126 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET) 03127 03128 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET) 03129 03130 #if defined(DMA2D) 03131 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != RESET) 03132 #endif /* DMA2D */ 03133 03134 #if defined(GFXMMU) 03135 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != RESET) 03136 #endif /* GFXMMU */ 03137 03138 03139 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET) 03140 03141 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET) 03142 03143 #if defined(DMAMUX1) 03144 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET) 03145 #endif /* DMAMUX1 */ 03146 03147 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET) 03148 03149 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET) 03150 03151 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET) 03152 03153 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET) 03154 03155 #if defined(DMA2D) 03156 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == RESET) 03157 #endif /* DMA2D */ 03158 03159 #if defined(GFXMMU) 03160 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == RESET) 03161 #endif /* GFXMMU */ 03162 03163 /** 03164 * @} 03165 */ 03166 03167 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status 03168 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 03169 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03170 * power consumption. 03171 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 03172 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03173 * @{ 03174 */ 03175 03176 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET) 03177 03178 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET) 03179 03180 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET) 03181 03182 #if defined(GPIOD) 03183 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET) 03184 #endif /* GPIOD */ 03185 03186 #if defined(GPIOE) 03187 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET) 03188 #endif /* GPIOE */ 03189 03190 #if defined(GPIOF) 03191 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET) 03192 #endif /* GPIOF */ 03193 03194 #if defined(GPIOG) 03195 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET) 03196 #endif /* GPIOG */ 03197 03198 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET) 03199 03200 #if defined(GPIOI) 03201 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != RESET) 03202 #endif /* GPIOI */ 03203 03204 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET) 03205 03206 #if defined(SRAM3) 03207 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != RESET) 03208 #endif /* SRAM3 */ 03209 03210 #if defined(USB_OTG_FS) 03211 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET) 03212 #endif /* USB_OTG_FS */ 03213 03214 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET) 03215 03216 #if defined(DCMI) 03217 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != RESET) 03218 #endif /* DCMI */ 03219 03220 #if defined(AES) 03221 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET) 03222 #endif /* AES */ 03223 03224 #if defined(HASH) 03225 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != RESET) 03226 #endif /* HASH */ 03227 03228 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET) 03229 03230 #if defined(OCTOSPIM) 03231 #define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != RESET) 03232 #endif /* OCTOSPIM */ 03233 03234 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 03235 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != RESET) 03236 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 03237 03238 03239 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET) 03240 03241 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET) 03242 03243 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET) 03244 03245 #if defined(GPIOD) 03246 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET) 03247 #endif /* GPIOD */ 03248 03249 #if defined(GPIOE) 03250 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET) 03251 #endif /* GPIOE */ 03252 03253 #if defined(GPIOF) 03254 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET) 03255 #endif /* GPIOF */ 03256 03257 #if defined(GPIOG) 03258 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET) 03259 #endif /* GPIOG */ 03260 03261 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET) 03262 03263 #if defined(GPIOI) 03264 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == RESET) 03265 #endif /* GPIOI */ 03266 03267 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET) 03268 03269 #if defined(SRAM3) 03270 #define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == RESET) 03271 #endif /* SRAM3 */ 03272 03273 #if defined(USB_OTG_FS) 03274 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET) 03275 #endif /* USB_OTG_FS */ 03276 03277 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET) 03278 03279 #if defined(DCMI) 03280 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == RESET) 03281 #endif /* DCMI */ 03282 03283 #if defined(AES) 03284 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET) 03285 #endif /* AES */ 03286 03287 #if defined(HASH) 03288 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == RESET) 03289 #endif /* HASH */ 03290 03291 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET) 03292 03293 #if defined(OCTOSPIM) 03294 #define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == RESET) 03295 #endif /* OCTOSPIM */ 03296 03297 #if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) 03298 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == RESET) 03299 #endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ 03300 03301 /** 03302 * @} 03303 */ 03304 03305 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status 03306 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 03307 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03308 * power consumption. 03309 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 03310 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03311 * @{ 03312 */ 03313 03314 #if defined(QUADSPI) 03315 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET) 03316 #endif /* QUADSPI */ 03317 03318 #if defined(OCTOSPI1) 03319 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != RESET) 03320 #endif /* OCTOSPI1 */ 03321 03322 #if defined(OCTOSPI2) 03323 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != RESET) 03324 #endif /* OCTOSPI2 */ 03325 03326 #if defined(FMC_BANK1) 03327 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET) 03328 #endif /* FMC_BANK1 */ 03329 03330 03331 #if defined(QUADSPI) 03332 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET) 03333 #endif /* QUADSPI */ 03334 03335 #if defined(OCTOSPI1) 03336 #define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == RESET) 03337 #endif /* OCTOSPI1 */ 03338 03339 #if defined(OCTOSPI2) 03340 #define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == RESET) 03341 #endif /* OCTOSPI2 */ 03342 03343 #if defined(FMC_BANK1) 03344 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET) 03345 #endif /* FMC_BANK1 */ 03346 03347 /** 03348 * @} 03349 */ 03350 03351 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 03352 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 03353 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03354 * power consumption. 03355 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 03356 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03357 * @{ 03358 */ 03359 03360 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET) 03361 03362 #if defined(TIM3) 03363 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET) 03364 #endif /* TIM3 */ 03365 03366 #if defined(TIM4) 03367 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET) 03368 #endif /* TIM4 */ 03369 03370 #if defined(TIM5) 03371 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET) 03372 #endif /* TIM5 */ 03373 03374 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET) 03375 03376 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET) 03377 03378 #if defined(LCD) 03379 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET) 03380 #endif /* LCD */ 03381 03382 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 03383 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET) 03384 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 03385 03386 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET) 03387 03388 #if defined(SPI2) 03389 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET) 03390 #endif /* SPI2 */ 03391 03392 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET) 03393 03394 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET) 03395 03396 #if defined(USART3) 03397 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET) 03398 #endif /* USART3 */ 03399 03400 #if defined(UART4) 03401 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET) 03402 #endif /* UART4 */ 03403 03404 #if defined(UART5) 03405 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET) 03406 #endif /* UART5 */ 03407 03408 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET) 03409 03410 #if defined(I2C2) 03411 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET) 03412 #endif /* I2C2 */ 03413 03414 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET) 03415 03416 #if defined(I2C4) 03417 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != RESET) 03418 #endif /* I2C4 */ 03419 03420 #if defined(CRS) 03421 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET) 03422 #endif /* CRS */ 03423 03424 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET) 03425 03426 #if defined(CAN2) 03427 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != RESET) 03428 #endif /* CAN2 */ 03429 03430 #if defined(USB) 03431 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != RESET) 03432 #endif /* USB */ 03433 03434 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET) 03435 03436 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET) 03437 03438 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET) 03439 03440 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET) 03441 03442 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET) 03443 03444 #if defined(SWPMI1) 03445 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET) 03446 #endif /* SWPMI1 */ 03447 03448 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET) 03449 03450 03451 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET) 03452 03453 #if defined(TIM3) 03454 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET) 03455 #endif /* TIM3 */ 03456 03457 #if defined(TIM4) 03458 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET) 03459 #endif /* TIM4 */ 03460 03461 #if defined(TIM5) 03462 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET) 03463 #endif /* TIM5 */ 03464 03465 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET) 03466 03467 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET) 03468 03469 #if defined(LCD) 03470 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET) 03471 #endif /* LCD */ 03472 03473 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 03474 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET) 03475 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 03476 03477 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET) 03478 03479 #if defined(SPI2) 03480 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET) 03481 #endif /* SPI2 */ 03482 03483 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET) 03484 03485 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET) 03486 03487 #if defined(USART3) 03488 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET) 03489 #endif /* USART3 */ 03490 03491 #if defined(UART4) 03492 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET) 03493 #endif /* UART4 */ 03494 03495 #if defined(UART5) 03496 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET) 03497 #endif /* UART5 */ 03498 03499 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET) 03500 03501 #if defined(I2C2) 03502 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET) 03503 #endif /* I2C2 */ 03504 03505 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET) 03506 03507 #if defined(I2C4) 03508 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == RESET) 03509 #endif /* I2C4 */ 03510 03511 #if defined(CRS) 03512 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET) 03513 #endif /* CRS */ 03514 03515 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET) 03516 03517 #if defined(CAN2) 03518 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == RESET) 03519 #endif /* CAN2 */ 03520 03521 #if defined(USB) 03522 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == RESET) 03523 #endif /* USB */ 03524 03525 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET) 03526 03527 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET) 03528 03529 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET) 03530 03531 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET) 03532 03533 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET) 03534 03535 #if defined(SWPMI1) 03536 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET) 03537 #endif /* SWPMI1 */ 03538 03539 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET) 03540 03541 /** 03542 * @} 03543 */ 03544 03545 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 03546 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 03547 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03548 * power consumption. 03549 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 03550 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03551 * @{ 03552 */ 03553 03554 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET) 03555 03556 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 03557 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET) 03558 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 03559 03560 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET) 03561 03562 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET) 03563 03564 #if defined(TIM8) 03565 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET) 03566 #endif /* TIM8 */ 03567 03568 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET) 03569 03570 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET) 03571 03572 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET) 03573 03574 #if defined(TIM17) 03575 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET) 03576 #endif /* TIM17 */ 03577 03578 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET) 03579 03580 #if defined(SAI2) 03581 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET) 03582 #endif /* SAI2 */ 03583 03584 #if defined(DFSDM1_Filter0) 03585 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET) 03586 #endif /* DFSDM1_Filter0 */ 03587 03588 #if defined(LTDC) 03589 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != RESET) 03590 #endif /* LTDC */ 03591 03592 #if defined(DSI) 03593 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != RESET) 03594 #endif /* DSI */ 03595 03596 03597 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET) 03598 03599 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 03600 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET) 03601 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 03602 03603 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET) 03604 03605 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET) 03606 03607 #if defined(TIM8) 03608 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET) 03609 #endif /* TIM8 */ 03610 03611 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET) 03612 03613 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET) 03614 03615 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET) 03616 03617 #if defined(TIM17) 03618 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET) 03619 #endif /* TIM17 */ 03620 03621 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET) 03622 03623 #if defined(SAI2) 03624 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET) 03625 #endif /* SAI2 */ 03626 03627 #if defined(DFSDM1_Filter0) 03628 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET) 03629 #endif /* DFSDM1_Filter0 */ 03630 03631 #if defined(LTDC) 03632 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == RESET) 03633 #endif /* LTDC */ 03634 03635 #if defined(DSI) 03636 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == RESET) 03637 #endif /* DSI */ 03638 03639 /** 03640 * @} 03641 */ 03642 03643 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 03644 * @{ 03645 */ 03646 03647 /** @brief Macros to force or release the Backup domain reset. 03648 * @note This function resets the RTC peripheral (including the backup registers) 03649 * and the RTC clock source selection in RCC_CSR register. 03650 * @note The BKPSRAM is not affected by this reset. 03651 * @retval None 03652 */ 03653 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 03654 03655 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 03656 03657 /** 03658 * @} 03659 */ 03660 03661 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 03662 * @{ 03663 */ 03664 03665 /** @brief Macros to enable or disable the RTC clock. 03666 * @note As the RTC is in the Backup domain and write access is denied to 03667 * this domain after reset, you have to enable write access using 03668 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 03669 * (to be done once after reset). 03670 * @note These macros must be used after the RTC clock source was selected. 03671 * @retval None 03672 */ 03673 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 03674 03675 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 03676 03677 /** 03678 * @} 03679 */ 03680 03681 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). 03682 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 03683 * It is used (enabled by hardware) as system clock source after startup 03684 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 03685 * of the HSE used directly or indirectly as system clock (if the Clock 03686 * Security System CSS is enabled). 03687 * @note HSI can not be stopped if it is used as system clock source. In this case, 03688 * you have to select another source of the system clock then stop the HSI. 03689 * @note After enabling the HSI, the application software should wait on HSIRDY 03690 * flag to be set indicating that HSI clock is stable and can be used as 03691 * system clock source. 03692 * This parameter can be: ENABLE or DISABLE. 03693 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 03694 * clock cycles. 03695 * @retval None 03696 */ 03697 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 03698 03699 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 03700 03701 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. 03702 * @note The calibration is used to compensate for the variations in voltage 03703 * and temperature that influence the frequency of the internal HSI RC. 03704 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 03705 * (default is RCC_HSICALIBRATION_DEFAULT). 03706 * This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices). 03707 * @retval None 03708 */ 03709 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 03710 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) 03711 03712 /** 03713 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) 03714 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup. 03715 * @note The enable of this function has not effect on the HSION bit. 03716 * This parameter can be: ENABLE or DISABLE. 03717 * @retval None 03718 */ 03719 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS) 03720 03721 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS) 03722 03723 /** 03724 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 03725 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 03726 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 03727 * speed because of the HSI startup time. 03728 * @note The enable of this function has not effect on the HSION bit. 03729 * This parameter can be: ENABLE or DISABLE. 03730 * @retval None 03731 */ 03732 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 03733 03734 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 03735 03736 /** 03737 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). 03738 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 03739 * It is used (enabled by hardware) as system clock source after 03740 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 03741 * of failure of the HSE used directly or indirectly as system clock 03742 * (if the Clock Security System CSS is enabled). 03743 * @note MSI can not be stopped if it is used as system clock source. 03744 * In this case, you have to select another source of the system 03745 * clock then stop the MSI. 03746 * @note After enabling the MSI, the application software should wait on 03747 * MSIRDY flag to be set indicating that MSI clock is stable and can 03748 * be used as system clock source. 03749 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 03750 * clock cycles. 03751 * @retval None 03752 */ 03753 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION) 03754 03755 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION) 03756 03757 /** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value. 03758 * @note The calibration is used to compensate for the variations in voltage 03759 * and temperature that influence the frequency of the internal MSI RC. 03760 * Refer to the Application Note AN3300 for more details on how to 03761 * calibrate the MSI. 03762 * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value 03763 * (default is RCC_MSICALIBRATION_DEFAULT). 03764 * This parameter must be a number between 0 and 255. 03765 * @retval None 03766 */ 03767 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ 03768 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos) 03769 03770 /** 03771 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode 03772 * @note After restart from Reset , the MSI clock is around 4 MHz. 03773 * After stop the startup clock can be MSI (at any of its possible 03774 * frequencies, the one that was used before entering stop mode) or HSI. 03775 * After Standby its frequency can be selected between 4 possible values 03776 * (1, 2, 4 or 8 MHz). 03777 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready 03778 * (MSIRDY=1). 03779 * @note The MSI clock range after reset can be modified on the fly. 03780 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 03781 * This parameter must be one of the following values: 03782 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 03783 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 03784 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 03785 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 03786 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 03787 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 03788 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 03789 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 03790 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 03791 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 03792 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 03793 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 03794 * @retval None 03795 */ 03796 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ 03797 do { \ 03798 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \ 03799 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \ 03800 } while(0) 03801 03802 /** 03803 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode 03804 * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). 03805 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 03806 * This parameter must be one of the following values: 03807 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 03808 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 03809 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 03810 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 03811 * @retval None 03812 */ 03813 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \ 03814 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U) 03815 03816 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 03817 * @retval MSI clock range. 03818 * This parameter must be one of the following values: 03819 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 03820 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 03821 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 03822 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 03823 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 03824 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 03825 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 03826 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 03827 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 03828 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 03829 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 03830 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 03831 */ 03832 #define __HAL_RCC_GET_MSI_RANGE() \ 03833 ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \ 03834 READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \ 03835 READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U) 03836 03837 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 03838 * @note After enabling the LSI, the application software should wait on 03839 * LSIRDY flag to be set indicating that LSI clock is stable and can 03840 * be used to clock the IWDG and/or the RTC. 03841 * @note LSI can not be disabled if the IWDG is running. 03842 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 03843 * clock cycles. 03844 * @retval None 03845 */ 03846 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) 03847 03848 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) 03849 03850 /** 03851 * @brief Macro to configure the External High Speed oscillator (HSE). 03852 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 03853 * supported by this macro. User should request a transition to HSE Off 03854 * first and then HSE On or HSE Bypass. 03855 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 03856 * software should wait on HSERDY flag to be set indicating that HSE clock 03857 * is stable and can be used to clock the PLL and/or system clock. 03858 * @note HSE state can not be changed if it is used directly or through the 03859 * PLL as system clock. In this case, you have to select another source 03860 * of the system clock then change the HSE state (ex. disable it). 03861 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 03862 * @note This function reset the CSSON bit, so if the clock security system(CSS) 03863 * was previously enabled you have to enable it again after calling this 03864 * function. 03865 * @param __STATE__ specifies the new state of the HSE. 03866 * This parameter can be one of the following values: 03867 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 03868 * 6 HSE oscillator clock cycles. 03869 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 03870 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 03871 * @retval None 03872 */ 03873 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 03874 do { \ 03875 if((__STATE__) == RCC_HSE_ON) \ 03876 { \ 03877 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 03878 } \ 03879 else if((__STATE__) == RCC_HSE_BYPASS) \ 03880 { \ 03881 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 03882 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 03883 } \ 03884 else \ 03885 { \ 03886 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 03887 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 03888 } \ 03889 } while(0) 03890 03891 /** 03892 * @brief Macro to configure the External Low Speed oscillator (LSE). 03893 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 03894 * supported by this macro. User should request a transition to LSE Off 03895 * first and then LSE On or LSE Bypass. 03896 * @note As the LSE is in the Backup domain and write access is denied to 03897 * this domain after reset, you have to enable write access using 03898 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 03899 * (to be done once after reset). 03900 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 03901 * software should wait on LSERDY flag to be set indicating that LSE clock 03902 * is stable and can be used to clock the RTC. 03903 * @param __STATE__ specifies the new state of the LSE. 03904 * This parameter can be one of the following values: 03905 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 03906 * 6 LSE oscillator clock cycles. 03907 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 03908 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 03909 * @retval None 03910 */ 03911 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 03912 do { \ 03913 if((__STATE__) == RCC_LSE_ON) \ 03914 { \ 03915 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 03916 } \ 03917 else if((__STATE__) == RCC_LSE_BYPASS) \ 03918 { \ 03919 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 03920 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 03921 } \ 03922 else \ 03923 { \ 03924 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 03925 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 03926 } \ 03927 } while(0) 03928 03929 #if defined(RCC_HSI48_SUPPORT) 03930 03931 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 03932 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 03933 * @note After enabling the HSI48, the application software should wait on HSI48RDY 03934 * flag to be set indicating that HSI48 clock is stable. 03935 * This parameter can be: ENABLE or DISABLE. 03936 * @retval None 03937 */ 03938 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 03939 03940 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 03941 03942 #endif /* RCC_HSI48_SUPPORT */ 03943 03944 /** @brief Macros to configure the RTC clock (RTCCLK). 03945 * @note As the RTC clock configuration bits are in the Backup domain and write 03946 * access is denied to this domain after reset, you have to enable write 03947 * access using the Power Backup Access macro before to configure 03948 * the RTC clock source (to be done once after reset). 03949 * @note Once the RTC clock is configured it cannot be changed unless the 03950 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 03951 * a Power On Reset (POR). 03952 * 03953 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 03954 * This parameter can be one of the following values: 03955 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 03956 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 03957 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 03958 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 03959 * 03960 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 03961 * work in STOP and STANDBY modes, and can be used as wakeup source. 03962 * However, when the HSE clock is used as RTC clock source, the RTC 03963 * cannot be used in STOP and STANDBY modes. 03964 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 03965 * RTC clock source). 03966 * @retval None 03967 */ 03968 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 03969 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 03970 03971 03972 /** @brief Macro to get the RTC clock source. 03973 * @retval The returned value can be one of the following: 03974 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 03975 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 03976 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 03977 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 03978 */ 03979 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 03980 03981 /** @brief Macros to enable or disable the main PLL. 03982 * @note After enabling the main PLL, the application software should wait on 03983 * PLLRDY flag to be set indicating that PLL clock is stable and can 03984 * be used as system clock source. 03985 * @note The main PLL can not be disabled if it is used as system clock source 03986 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 03987 * @retval None 03988 */ 03989 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) 03990 03991 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) 03992 03993 /** @brief Macro to configure the PLL clock source. 03994 * @note This function must be used only when the main PLL is disabled. 03995 * @param __PLLSOURCE__ specifies the PLL entry clock source. 03996 * This parameter can be one of the following values: 03997 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 03998 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 03999 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 04000 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 04001 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). 04002 * @retval None 04003 * 04004 */ 04005 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ 04006 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 04007 04008 /** @brief Macro to configure the PLL source division factor M. 04009 * @note This function must be used only when the main PLL is disabled. 04010 * @param __PLLM__ specifies the division factor for PLL VCO input clock 04011 * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. 04012 * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. 04013 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 04014 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 04015 * of 16 MHz to limit PLL jitter. 04016 * @retval None 04017 * 04018 */ 04019 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ 04020 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U) 04021 04022 /** 04023 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 04024 * @note This function must be used only when the main PLL is disabled. 04025 * 04026 * @param __PLLSOURCE__ specifies the PLL entry clock source. 04027 * This parameter can be one of the following values: 04028 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 04029 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 04030 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 04031 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 04032 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). 04033 * 04034 * @param __PLLM__ specifies the division factor for PLL VCO input clock. 04035 * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. 04036 * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. 04037 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 04038 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 04039 * of 16 MHz to limit PLL jitter. 04040 * 04041 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. 04042 * This parameter must be a number between 8 and 86. 04043 * @note You have to set the PLLN parameter correctly to ensure that the VCO 04044 * output frequency is between 64 and 344 MHz. 04045 * 04046 * @param __PLLP__ specifies the division factor for SAI clock. 04047 * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x 04048 * else (2 to 31). 04049 * 04050 * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks. 04051 * This parameter must be in the range (2, 4, 6 or 8). 04052 * @note If the USB OTG FS is used in your application, you have to set the 04053 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 04054 * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work 04055 * correctly. 04056 * @param __PLLR__ specifies the division factor for the main system clock. 04057 * @note You have to set the PLLR parameter correctly to not exceed 80MHZ. 04058 * This parameter must be in the range (2, 4, 6 or 8). 04059 * @retval None 04060 */ 04061 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 04062 04063 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 04064 (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ 04065 (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \ 04066 ((uint32_t)(__PLLP__) << 27U)) 04067 #else 04068 04069 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 04070 (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ 04071 (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \ 04072 (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) 04073 04074 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 04075 04076 /** @brief Macro to get the oscillator used as PLL clock source. 04077 * @retval The oscillator used as PLL clock source. The returned value can be one 04078 * of the following: 04079 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 04080 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. 04081 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 04082 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 04083 */ 04084 #define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)) 04085 04086 /** 04087 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) 04088 * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime 04089 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot 04090 * be stopped if used as System Clock. 04091 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. 04092 * This parameter can be one or a combination of the following values: 04093 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve 04094 * high-quality audio performance on SAI interface in case. 04095 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), 04096 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). 04097 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) 04098 * @retval None 04099 */ 04100 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 04101 04102 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 04103 04104 /** 04105 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) 04106 * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. 04107 * This parameter can be one of the following values: 04108 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve 04109 * high-quality audio performance on SAI interface in case. 04110 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), 04111 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). 04112 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) 04113 * @retval SET / RESET 04114 */ 04115 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 04116 04117 /** 04118 * @brief Macro to configure the system clock source. 04119 * @param __SYSCLKSOURCE__ specifies the system clock source. 04120 * This parameter can be one of the following values: 04121 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. 04122 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 04123 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 04124 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. 04125 * @retval None 04126 */ 04127 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 04128 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 04129 04130 /** @brief Macro to get the clock source used as system clock. 04131 * @retval The clock source used as system clock. The returned value can be one 04132 * of the following: 04133 * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock. 04134 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 04135 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 04136 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. 04137 */ 04138 #define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS)) 04139 04140 /** 04141 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 04142 * @note As the LSE is in the Backup domain and write access is denied to 04143 * this domain after reset, you have to enable write access using 04144 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 04145 * (to be done once after reset). 04146 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. 04147 * This parameter can be one of the following values: 04148 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 04149 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 04150 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 04151 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 04152 * @retval None 04153 */ 04154 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 04155 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__)) 04156 04157 /** 04158 * @brief Macro to configure the wake up from stop clock. 04159 * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. 04160 * This parameter can be one of the following values: 04161 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source 04162 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 04163 * @retval None 04164 */ 04165 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ 04166 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__)) 04167 04168 04169 /** @brief Macro to configure the MCO clock. 04170 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 04171 * This parameter can be one of the following values: 04172 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 04173 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 04174 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source 04175 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 04176 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee 04177 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source 04178 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 04179 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 04180 @if STM32L443xx 04181 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 04182 @endif 04183 @if STM32L4A6xx 04184 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 04185 @endif 04186 * @param __MCODIV__ specifies the MCO clock prescaler. 04187 * This parameter can be one of the following values: 04188 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 04189 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 04190 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 04191 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 04192 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 04193 */ 04194 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 04195 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 04196 04197 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 04198 * @brief macros to manage the specified RCC Flags and interrupts. 04199 * @{ 04200 */ 04201 04202 /** @brief Enable RCC interrupt(s). 04203 * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled. 04204 * This parameter can be any combination of the following values: 04205 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 04206 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 04207 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 04208 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 04209 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 04210 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 04211 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt 04212 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 04213 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 04214 @if STM32L443xx 04215 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 04216 @endif 04217 @if STM32L4A6xx 04218 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 04219 @endif 04220 * @retval None 04221 */ 04222 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 04223 04224 /** @brief Disable RCC interrupt(s). 04225 * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled. 04226 * This parameter can be any combination of the following values: 04227 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 04228 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 04229 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 04230 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 04231 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 04232 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 04233 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt 04234 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 04235 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 04236 @if STM32L443xx 04237 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 04238 @endif 04239 @if STM32L4A6xx 04240 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 04241 @endif 04242 * @retval None 04243 */ 04244 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 04245 04246 /** @brief Clear the RCC's interrupt pending bits. 04247 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 04248 * This parameter can be any combination of the following values: 04249 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 04250 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 04251 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 04252 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 04253 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 04254 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 04255 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt 04256 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 04257 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 04258 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 04259 @if STM32L443xx 04260 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 04261 @endif 04262 @if STM32L4A6xx 04263 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 04264 @endif 04265 * @retval None 04266 */ 04267 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 04268 04269 /** @brief Check whether the RCC interrupt has occurred or not. 04270 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 04271 * This parameter can be one of the following values: 04272 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 04273 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 04274 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 04275 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 04276 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 04277 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 04278 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt 04279 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 04280 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 04281 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 04282 @if STM32L443xx 04283 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 04284 @endif 04285 @if STM32L4A6xx 04286 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 04287 @endif 04288 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 04289 */ 04290 #define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__)) 04291 04292 /** @brief Set RMVF bit to clear the reset flags. 04293 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 04294 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 04295 * @retval None 04296 */ 04297 #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF) 04298 04299 /** @brief Check whether the selected RCC flag is set or not. 04300 * @param __FLAG__ specifies the flag to check. 04301 * This parameter can be one of the following values: 04302 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 04303 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 04304 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 04305 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready 04306 * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready 04307 * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2 04308 @if STM32L443xx 04309 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 04310 @endif 04311 @if STM32L4A6xx 04312 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 04313 @endif 04314 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 04315 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 04316 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 04317 * @arg @ref RCC_FLAG_BORRST BOR reset 04318 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 04319 * @arg @ref RCC_FLAG_PINRST Pin reset 04320 * @arg @ref RCC_FLAG_FWRST FIREWALL reset 04321 * @arg @ref RCC_FLAG_SFTRST Software reset 04322 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 04323 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 04324 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 04325 * @retval The new state of __FLAG__ (TRUE or FALSE). 04326 */ 04327 #if defined(RCC_HSI48_SUPPORT) 04328 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 04329 ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ 04330 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 04331 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ 04332 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) 04333 #else 04334 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 04335 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 04336 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \ 04337 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) 04338 #endif /* RCC_HSI48_SUPPORT */ 04339 04340 /** 04341 * @} 04342 */ 04343 04344 /** 04345 * @} 04346 */ 04347 04348 /* Private constants ---------------------------------------------------------*/ 04349 /** @defgroup RCC_Private_Constants RCC Private Constants 04350 * @{ 04351 */ 04352 /* Defines used for Flags */ 04353 #define CR_REG_INDEX 1U 04354 #define BDCR_REG_INDEX 2U 04355 #define CSR_REG_INDEX 3U 04356 #if defined(RCC_HSI48_SUPPORT) 04357 #define CRRCR_REG_INDEX 4U 04358 #endif /* RCC_HSI48_SUPPORT */ 04359 04360 #define RCC_FLAG_MASK 0x1FU 04361 /** 04362 * @} 04363 */ 04364 04365 /* Private macros ------------------------------------------------------------*/ 04366 /** @addtogroup RCC_Private_Macros 04367 * @{ 04368 */ 04369 04370 #if defined(RCC_HSI48_SUPPORT) 04371 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 04372 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 04373 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 04374 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ 04375 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ 04376 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 04377 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 04378 #else 04379 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 04380 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 04381 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 04382 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ 04383 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 04384 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 04385 #endif /* RCC_HSI48_SUPPORT */ 04386 04387 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 04388 ((__HSE__) == RCC_HSE_BYPASS)) 04389 04390 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 04391 ((__LSE__) == RCC_LSE_BYPASS)) 04392 04393 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 04394 04395 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) 04396 04397 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 04398 04399 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) 04400 04401 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U) 04402 04403 #if defined(RCC_HSI48_SUPPORT) 04404 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 04405 #endif /* RCC_HSI48_SUPPORT */ 04406 04407 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ 04408 ((__PLL__) == RCC_PLL_ON)) 04409 04410 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ 04411 ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ 04412 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 04413 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 04414 04415 #if defined(RCC_PLLM_DIV_1_16_SUPPORT) 04416 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 04417 #else 04418 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) 04419 #endif /*RCC_PLLM_DIV_1_16_SUPPORT */ 04420 04421 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 04422 04423 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 04424 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 04425 #else 04426 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) 04427 #endif /*RCC_PLLP_DIV_2_31_SUPPORT */ 04428 04429 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 04430 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 04431 04432 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 04433 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 04434 04435 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ 04436 (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \ 04437 (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \ 04438 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U)) 04439 04440 #if defined(RCC_PLLSAI2_SUPPORT) 04441 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 04442 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ 04443 (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \ 04444 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U)) 04445 #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 04446 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ 04447 (((__VALUE__) & RCC_PLLSAI2_DSICLK) == RCC_PLLSAI2_DSICLK) || \ 04448 (((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \ 04449 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U)) 04450 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 04451 #endif /* RCC_PLLSAI2_SUPPORT */ 04452 04453 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 04454 ((__RANGE__) == RCC_MSIRANGE_1) || \ 04455 ((__RANGE__) == RCC_MSIRANGE_2) || \ 04456 ((__RANGE__) == RCC_MSIRANGE_3) || \ 04457 ((__RANGE__) == RCC_MSIRANGE_4) || \ 04458 ((__RANGE__) == RCC_MSIRANGE_5) || \ 04459 ((__RANGE__) == RCC_MSIRANGE_6) || \ 04460 ((__RANGE__) == RCC_MSIRANGE_7) || \ 04461 ((__RANGE__) == RCC_MSIRANGE_8) || \ 04462 ((__RANGE__) == RCC_MSIRANGE_9) || \ 04463 ((__RANGE__) == RCC_MSIRANGE_10) || \ 04464 ((__RANGE__) == RCC_MSIRANGE_11)) 04465 04466 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ 04467 ((__RANGE__) == RCC_MSIRANGE_5) || \ 04468 ((__RANGE__) == RCC_MSIRANGE_6) || \ 04469 ((__RANGE__) == RCC_MSIRANGE_7)) 04470 04471 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U)) 04472 04473 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ 04474 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 04475 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 04476 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 04477 04478 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 04479 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 04480 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 04481 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 04482 ((__HCLK__) == RCC_SYSCLK_DIV512)) 04483 04484 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 04485 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 04486 ((__PCLK__) == RCC_HCLK_DIV16)) 04487 04488 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ 04489 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 04490 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 04491 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 04492 04493 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) 04494 04495 #if defined(RCC_HSI48_SUPPORT) 04496 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 04497 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 04498 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 04499 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 04500 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 04501 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 04502 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 04503 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 04504 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) 04505 #else 04506 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 04507 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 04508 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 04509 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 04510 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 04511 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 04512 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 04513 ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) 04514 #endif /* RCC_HSI48_SUPPORT */ 04515 04516 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 04517 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 04518 ((__DIV__) == RCC_MCODIV_16)) 04519 04520 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 04521 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 04522 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 04523 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 04524 04525 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ 04526 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 04527 /** 04528 * @} 04529 */ 04530 04531 /* Include RCC HAL Extended module */ 04532 #include "stm32l4xx_hal_rcc_ex.h" 04533 04534 /* Exported functions --------------------------------------------------------*/ 04535 /** @addtogroup RCC_Exported_Functions 04536 * @{ 04537 */ 04538 04539 04540 /** @addtogroup RCC_Exported_Functions_Group1 04541 * @{ 04542 */ 04543 04544 /* Initialization and de-initialization functions ******************************/ 04545 HAL_StatusTypeDef HAL_RCC_DeInit(void); 04546 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 04547 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 04548 04549 /** 04550 * @} 04551 */ 04552 04553 /** @addtogroup RCC_Exported_Functions_Group2 04554 * @{ 04555 */ 04556 04557 /* Peripheral Control functions ************************************************/ 04558 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 04559 void HAL_RCC_EnableCSS(void); 04560 uint32_t HAL_RCC_GetSysClockFreq(void); 04561 uint32_t HAL_RCC_GetHCLKFreq(void); 04562 uint32_t HAL_RCC_GetPCLK1Freq(void); 04563 uint32_t HAL_RCC_GetPCLK2Freq(void); 04564 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 04565 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 04566 /* CSS NMI IRQ handler */ 04567 void HAL_RCC_NMI_IRQHandler(void); 04568 /* User Callbacks in non blocking mode (IT mode) */ 04569 void HAL_RCC_CSSCallback(void); 04570 04571 /** 04572 * @} 04573 */ 04574 04575 /** 04576 * @} 04577 */ 04578 04579 /** 04580 * @} 04581 */ 04582 04583 /** 04584 * @} 04585 */ 04586 04587 #ifdef __cplusplus 04588 } 04589 #endif 04590 04591 #endif /* __STM32L4xx_HAL_RCC_H */ 04592 04593 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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