Initialization and Configuration functions. More...

Functions
HAL_StatusTypeDef	HAL_RCC_DeInit (void)
	Reset the RCC clock configuration to the default reset state.
HAL_StatusTypeDef	HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
	Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef	HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
	Initialize the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkInitStruct.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
           ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]
      This section provides functions allowing to configure the internal and external oscillators
      (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
       and APB2).

    [..] Internal/external clock and PLL configuration
         (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
             the PLL as System clock source.

         (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
             It can be used to generate the clock for the USB OTG FS (48 MHz).
             The number of flash wait states is automatically adjusted when MSI range is updated with
             HAL_RCC_OscConfig() and the MSI is used as System clock source.

         (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
             clock source.

         (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
             through the PLL as System clock source. Can be used also optionally as RTC clock source.

         (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.

         (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
           (++) The first output is used to generate the high speed system clock (up to 80MHz).
           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
                the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
           (++) The third output is used to generate an accurate clock to achieve
                high-quality audio performance on SAI interface.

         (+) PLLSAI1 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
           (++) The first output is used to generate SAR ADC1 clock.
           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
                the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
           (++) The Third output is used to generate an accurate clock to achieve
                high-quality audio performance on SAI interface.

         (+) PLLSAI2 (clocked by HSI , HSE or MSI) providing up to two independent output clocks:
           (++) The first output is used to generate SAR ADC2 clock.
           (++) The second  output is used to generate an accurate clock to achieve
                high-quality audio performance on SAI interface.

         (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
            (HSE used directly or through PLL as System clock source), the System clock
             is automatically switched to HSI and an interrupt is generated if enabled.
             The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
             exception vector.

         (+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or
             main PLL clock (through a configurable prescaler) on PA8 pin.

    [..] System, AHB and APB busses clocks configuration
         (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
             HSE and main PLL.
             The AHB clock (HCLK) is derived from System clock through configurable
             prescaler and used to clock the CPU, memory and peripherals mapped
             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
             from AHB clock through configurable prescalers and used to clock
             the peripherals mapped on these busses. You can use
             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.

         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:

           (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLSAI1) or (PLLSAI2) or
                from an external clock mapped on the SAI_CKIN pin.
                You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
           (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
                divided by 2 to 31.
                You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
                to configure this clock.
           (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz
                to work correctly, while the SDMMC1 and RNG peripherals require a frequency
                equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1
                through PLLQ divider. You have to enable the peripheral clock and use
                HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
           (+@) IWDG clock which is always the LSI clock.


         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz.
             The clock source frequency should be adapted depending on the device voltage range
             as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.

Table 1. HCLK clock frequency for STM32L4Rx/STM32L4Sx devices +--------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |--------------------------------------| | | voltage range 1 | voltage range 2 | | | 1.2 V | 1.0 V | |-----------------|-------------------|------------------| |0WS(1 CPU cycles)| 0 < HCLK <= 20 | 0 < HCLK <= 8 | |-----------------|-------------------|------------------| |1WS(2 CPU cycles)| 20 < HCLK <= 40 | 8 < HCLK <= 16 | |-----------------|-------------------|------------------| |2WS(3 CPU cycles)| 40 < HCLK <= 60 | 16 < HCLK <= 26 | |-----------------|-------------------|------------------| |3WS(4 CPU cycles)| 60 < HCLK <= 80 | 16 < HCLK <= 26 | |-----------------|-------------------|------------------| |4WS(5 CPU cycles)| 80 < HCLK <= 100 | 16 < HCLK <= 26 | |-----------------|-------------------|------------------| |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 | +--------------------------------------------------------+

Table 2. HCLK clock frequency for other STM32L4 devices +-------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |-------------------------------------| | | voltage range 1 | voltage range 2 | | | 1.2 V | 1.0 V | |-----------------|------------------|------------------| |0WS(1 CPU cycles)| 0 < HCLK <= 16 | 0 < HCLK <= 6 | |-----------------|------------------|------------------| |1WS(2 CPU cycles)| 16 < HCLK <= 32 | 6 < HCLK <= 12 | |-----------------|------------------|------------------| |2WS(3 CPU cycles)| 32 < HCLK <= 48 | 12 < HCLK <= 18 | |-----------------|------------------|------------------| |3WS(4 CPU cycles)| 48 < HCLK <= 64 | 18 < HCLK <= 26 | |-----------------|------------------|------------------| |4WS(5 CPU cycles)| 64 < HCLK <= 80 | 18 < HCLK <= 26 | +-------------------------------------------------------+

Function Documentation

HAL_StatusTypeDef HAL_RCC_ClockConfig	(	RCC_ClkInitTypeDef *	RCC_ClkInitStruct,
		uint32_t	FLatency
	)

Initialize the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkInitStruct.

Parameters:

RCC_ClkInitStruct	pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC peripheral.
FLatency	FLASH Latency This parameter can be one of the following values: FLASH_LATENCY_0 FLASH 0 Latency cycle FLASH_LATENCY_1 FLASH 1 Latency cycle FLASH_LATENCY_2 FLASH 2 Latency cycles FLASH_LATENCY_3 FLASH 3 Latency cycles FLASH_LATENCY_4 FLASH 4 Latency cycles

Note:: The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated by HAL_RCC_GetHCLKFreq() function called within this function; The MSI is used by default as system clock source after startup from Reset, wake-up from STANDBY mode. After restart from Reset, the MSI frequency is set to its default value 4 MHz.; The HSI can be selected as system clock source after from STOP modes or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).; A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source is ready.; You can use HAL_RCC_GetClockConfig() function to know which clock is currently used as system clock source.; Depending on the device voltage range, the software has to set correctly HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency (for more details refer to section above "Initialization/de-initialization functions")

Return values:

None

Definition at line 941 of file stm32l4xx_hal_rcc.c.

References __HAL_FLASH_GET_LATENCY, __HAL_FLASH_SET_LATENCY, __HAL_RCC_GET_SYSCLK_SOURCE, RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, assert_param, CLOCKSWITCH_TIMEOUT_VALUE, RCC_ClkInitTypeDef::ClockType, HAL_GetTick(), HAL_InitTick(), HAL_RCC_GetSysClockFreq(), IS_FLASH_LATENCY, IS_RCC_CLOCKTYPE, IS_RCC_HCLK, IS_RCC_PCLK, IS_RCC_SYSCLKSOURCE, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, RCC_SYSCLK_DIV1, RCC_SYSCLK_DIV2, RCC_SYSCLKSOURCE_HSE, RCC_SYSCLKSOURCE_MSI, RCC_SYSCLKSOURCE_PLLCLK, RCC_ClkInitTypeDef::SYSCLKSource, and TICK_INT_PRIORITY.

HAL_StatusTypeDef HAL_RCC_DeInit ( void )

Reset the RCC clock configuration to the default reset state.

Note:

The default reset state of the clock configuration is given below:

MSI ON and used as system clock source
HSE, HSI, PLL, PLLSAI1 and PLLISAI2 OFF
AHB, APB1 and APB2 prescaler set to 1.
CSS, MCO1 OFF
All interrupts disabled
All interrupt and reset flags cleared

This function doesn't modify the configuration of the

Peripheral clocks
LSI, LSE and RTC clocks

Return values:

HAL status

Definition at line 276 of file stm32l4xx_hal_rcc.c.

References CLOCKSWITCH_TIMEOUT_VALUE, HAL_GetTick(), HAL_InitTick(), MSI_TIMEOUT_VALUE, MSI_VALUE, PLL_TIMEOUT_VALUE, RCC_MSIRANGE_6, and TICK_INT_PRIORITY.

HAL_StatusTypeDef HAL_RCC_OscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Initialize the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.

Parameters:

RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC Oscillators.

Note:: The PLL is not disabled when used as system clock.; Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.; Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. User should request a transition to HSE Off first and then HSE On or HSE Bypass.

Return values:

HAL status

Definition at line 400 of file stm32l4xx_hal_rcc.c.

Functions

Detailed Description

Function Documentation