STM32L486xx HAL User Manual
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Enable or disable the APB1 peripheral clock. More...
Defines | |
#define | __HAL_RCC_TIM2_CLK_ENABLE() |
#define | __HAL_RCC_TIM3_CLK_ENABLE() |
#define | __HAL_RCC_TIM4_CLK_ENABLE() |
#define | __HAL_RCC_TIM5_CLK_ENABLE() |
#define | __HAL_RCC_TIM6_CLK_ENABLE() |
#define | __HAL_RCC_TIM7_CLK_ENABLE() |
#define | __HAL_RCC_LCD_CLK_ENABLE() |
#define | __HAL_RCC_WWDG_CLK_ENABLE() |
#define | __HAL_RCC_SPI2_CLK_ENABLE() |
#define | __HAL_RCC_SPI3_CLK_ENABLE() |
#define | __HAL_RCC_USART2_CLK_ENABLE() |
#define | __HAL_RCC_USART3_CLK_ENABLE() |
#define | __HAL_RCC_UART4_CLK_ENABLE() |
#define | __HAL_RCC_UART5_CLK_ENABLE() |
#define | __HAL_RCC_I2C1_CLK_ENABLE() |
#define | __HAL_RCC_I2C2_CLK_ENABLE() |
#define | __HAL_RCC_I2C3_CLK_ENABLE() |
#define | __HAL_RCC_CAN1_CLK_ENABLE() |
#define | __HAL_RCC_PWR_CLK_ENABLE() |
#define | __HAL_RCC_DAC1_CLK_ENABLE() |
#define | __HAL_RCC_OPAMP_CLK_ENABLE() |
#define | __HAL_RCC_LPTIM1_CLK_ENABLE() |
#define | __HAL_RCC_LPUART1_CLK_ENABLE() |
#define | __HAL_RCC_SWPMI1_CLK_ENABLE() |
#define | __HAL_RCC_LPTIM2_CLK_ENABLE() |
#define | __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) |
#define | __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) |
#define | __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) |
#define | __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) |
#define | __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) |
#define | __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) |
#define | __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); |
#define | __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) |
#define | __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) |
#define | __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) |
#define | __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) |
#define | __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) |
#define | __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) |
#define | __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) |
#define | __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) |
#define | __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) |
#define | __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) |
#define | __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) |
#define | __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) |
#define | __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) |
#define | __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) |
#define | __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) |
#define | __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) |
#define | __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) |
Enable or disable the APB1 peripheral clock.
#define __HAL_RCC_CAN1_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) |
Definition at line 1358 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_CAN1_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1209 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_DAC1_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) |
Definition at line 1370 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_DAC1_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1245 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_I2C1_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) |
Definition at line 1342 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_I2C1_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1163 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_I2C2_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) |
Definition at line 1345 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_I2C2_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1172 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_I2C3_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) |
Definition at line 1348 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_I2C3_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1181 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_LCD_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); |
Definition at line 1315 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_LCD_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1080 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_LPTIM1_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) |
Definition at line 1374 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_LPTIM1_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1261 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_LPTIM2_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) |
Definition at line 1382 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_LPTIM2_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1287 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_LPUART1_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) |
Definition at line 1376 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_LPUART1_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1269 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_OPAMP_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) |
Definition at line 1372 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_OPAMP_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1253 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_PWR_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) |
Definition at line 1368 of file stm32l4xx_hal_rcc.h.
Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_DisableLSCO(), HAL_RCCEx_EnableLSCO(), HAL_RCCEx_PeriphCLKConfig(), and RCC_SetFlashLatencyFromMSIRange().
#define __HAL_RCC_PWR_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1237 of file stm32l4xx_hal_rcc.h.
Referenced by HAL_RCC_OscConfig(), HAL_RCCEx_DisableLSCO(), HAL_RCCEx_EnableLSCO(), HAL_RCCEx_PeriphCLKConfig(), and RCC_SetFlashLatencyFromMSIRange().
#define __HAL_RCC_SPI2_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) |
Definition at line 1323 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_SPI2_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1108 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_SPI3_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) |
Definition at line 1326 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_SPI3_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1117 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_SWPMI1_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) |
Definition at line 1379 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_SWPMI1_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1278 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_TIM2_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) |
Definition at line 1296 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_TIM2_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1025 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_TIM3_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) |
Definition at line 1299 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_TIM3_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1034 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_TIM4_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) |
Definition at line 1303 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_TIM4_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1044 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_TIM5_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) |
Definition at line 1307 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_TIM5_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1054 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_TIM6_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) |
Definition at line 1310 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_TIM6_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1063 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_TIM7_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) |
Definition at line 1312 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_TIM7_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1071 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_UART4_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) |
Definition at line 1335 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_UART4_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1144 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_UART5_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) |
Definition at line 1339 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_UART5_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1154 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_USART2_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) |
Definition at line 1328 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_USART2_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1125 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_USART3_CLK_DISABLE | ( | ) | CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) |
Definition at line 1331 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_USART3_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1134 of file stm32l4xx_hal_rcc.h.
#define __HAL_RCC_WWDG_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ UNUSED(tmpreg); \ } while(0)
Definition at line 1099 of file stm32l4xx_hal_rcc.h.