STM32L486xx HAL User Manual: stm32l4xx_hal_rcc

Header file of RCC HAL Extended module. More...

#include "stm32l4xx_hal_def.h"

Data Structures
struct	RCC_PLLSAI1InitTypeDef
	PLLSAI1 Clock structure definition. More...
struct	RCC_PLLSAI2InitTypeDef
	PLLSAI2 Clock structure definition. More...
struct	RCC_PeriphCLKInitTypeDef
	RCC extended clocks structure definition. More...
Defines
#define	RCC_LSCOSOURCE_LSI 0x00000000U
#define	RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL
#define	RCC_PERIPHCLK_USART1 0x00000001U
#define	RCC_PERIPHCLK_USART2 0x00000002U
#define	RCC_PERIPHCLK_USART3 0x00000004U
#define	RCC_PERIPHCLK_UART4 0x00000008U
#define	RCC_PERIPHCLK_UART5 0x00000010U
#define	RCC_PERIPHCLK_LPUART1 0x00000020U
#define	RCC_PERIPHCLK_I2C1 0x00000040U
#define	RCC_PERIPHCLK_I2C2 0x00000080U
#define	RCC_PERIPHCLK_I2C3 0x00000100U
#define	RCC_PERIPHCLK_LPTIM1 0x00000200U
#define	RCC_PERIPHCLK_LPTIM2 0x00000400U
#define	RCC_PERIPHCLK_SAI1 0x00000800U
#define	RCC_PERIPHCLK_SAI2 0x00001000U
#define	RCC_PERIPHCLK_USB 0x00002000U
#define	RCC_PERIPHCLK_ADC 0x00004000U
#define	RCC_PERIPHCLK_SWPMI1 0x00008000U
#define	RCC_PERIPHCLK_DFSDM1 0x00010000U
#define	RCC_PERIPHCLK_RTC 0x00020000U
#define	RCC_PERIPHCLK_RNG 0x00040000U
#define	RCC_PERIPHCLK_SDMMC1 0x00080000U
#define	RCC_USART1CLKSOURCE_PCLK2 0x00000000U
#define	RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
#define	RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
#define	RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 \| RCC_CCIPR_USART1SEL_1)
#define	RCC_USART2CLKSOURCE_PCLK1 0x00000000U
#define	RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
#define	RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
#define	RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 \| RCC_CCIPR_USART2SEL_1)
#define	RCC_USART3CLKSOURCE_PCLK1 0x00000000U
#define	RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
#define	RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
#define	RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 \| RCC_CCIPR_USART3SEL_1)
#define	RCC_UART4CLKSOURCE_PCLK1 0x00000000U
#define	RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
#define	RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
#define	RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 \| RCC_CCIPR_UART4SEL_1)
#define	RCC_UART5CLKSOURCE_PCLK1 0x00000000U
#define	RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
#define	RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
#define	RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 \| RCC_CCIPR_UART5SEL_1)
#define	RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U
#define	RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define	RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define	RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 \| RCC_CCIPR_LPUART1SEL_1)
#define	RCC_I2C1CLKSOURCE_PCLK1 0x00000000U
#define	RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
#define	RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
#define	RCC_I2C2CLKSOURCE_PCLK1 0x00000000U
#define	RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
#define	RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
#define	RCC_I2C3CLKSOURCE_PCLK1 0x00000000U
#define	RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
#define	RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
#define	RCC_SAI1CLKSOURCE_PLLSAI1 0x00000000U
#define	RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0
#define	RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1
#define	RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL
#define	RCC_SAI2CLKSOURCE_PLLSAI1 0x00000000U
#define	RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0
#define	RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1
#define	RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL
#define	RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
#define	RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
#define	RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
#define	RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
#define	RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U
#define	RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0
#define	RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1
#define	RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL
#define	RCC_SDMMC1CLKSOURCE_NONE 0x00000000U
#define	RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
#define	RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define	RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
#define	RCC_RNGCLKSOURCE_NONE 0x00000000U
#define	RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
#define	RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define	RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
#define	RCC_USBCLKSOURCE_NONE 0x00000000U
#define	RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
#define	RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
#define	RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
#define	RCC_ADCCLKSOURCE_NONE 0x00000000U
#define	RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
#define	RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1
#define	RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL
#define	RCC_SWPMI1CLKSOURCE_PCLK1 0x00000000U
#define	RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL
#define	RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U
#define	RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL
#define	RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19
#define	__HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__)
	Macro to configure the PLLSAI1 clock multiplication and division factors.
#define	__HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
	Macro to configure the PLLSAI1 clock multiplication factor N.
#define	__HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)
	Macro to configure the PLLSAI1 clock division factor P.
#define	__HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
	Macro to configure the PLLSAI1 clock division factor Q.
#define	__HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
	Macro to configure the PLLSAI1 clock division factor R.
#define	__HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
	Macros to enable or disable the PLLSAI1.
#define	__HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
#define	__HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
	Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
#define	__HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
#define	__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
	Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
#define	__HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__)
	Macro to configure the PLLSAI2 clock multiplication and division factors.
#define	__HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
	Macro to configure the PLLSAI2 clock multiplication factor N.
#define	__HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)
	Macro to configure the PLLSAI2 clock division factor P.
#define	__HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
	Macro to configure the PLLSAI2 clock division factor R.
#define	__HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
	Macros to enable or disable the PLLSAI2.
#define	__HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
#define	__HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
	Macros to enable or disable each clock output (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK).
#define	__HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
#define	__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
	Macro to get clock output enable status (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK).
#define	__HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))
	Macro to configure the SAI1 clock source.
#define	__HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))
	Macro to get the SAI1 clock source.
#define	__HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__))
	Macro to configure the SAI2 clock source.
#define	__HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL))
	Macro to get the SAI2 clock source.
#define	__HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))
	Macro to configure the I2C1 clock (I2C1CLK).
#define	__HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))
	Macro to get the I2C1 clock source.
#define	__HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))
	Macro to configure the I2C2 clock (I2C2CLK).
#define	__HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))
	Macro to get the I2C2 clock source.
#define	__HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))
	Macro to configure the I2C3 clock (I2C3CLK).
#define	__HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))
	Macro to get the I2C3 clock source.
#define	__HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))
	Macro to configure the USART1 clock (USART1CLK).
#define	__HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))
	Macro to get the USART1 clock source.
#define	__HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))
	Macro to configure the USART2 clock (USART2CLK).
#define	__HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))
	Macro to get the USART2 clock source.
#define	__HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))
	Macro to configure the USART3 clock (USART3CLK).
#define	__HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))
	Macro to get the USART3 clock source.
#define	__HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))
	Macro to configure the UART4 clock (UART4CLK).
#define	__HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))
	Macro to get the UART4 clock source.
#define	__HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__))
	Macro to configure the UART5 clock (UART5CLK).
#define	__HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))
	Macro to get the UART5 clock source.
#define	__HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))
	Macro to configure the LPUART1 clock (LPUART1CLK).
#define	__HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))
	Macro to get the LPUART1 clock source.
#define	__HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))
	Macro to configure the LPTIM1 clock (LPTIM1CLK).
#define	__HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))
	Macro to get the LPTIM1 clock source.
#define	__HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__))
	Macro to configure the LPTIM2 clock (LPTIM2CLK).
#define	__HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))
	Macro to get the LPTIM2 clock source.
#define	__HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__))
	Macro to configure the SDMMC1 clock.
#define	__HAL_RCC_GET_SDMMC1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
	Macro to get the SDMMC1 clock.
#define	__HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))
	Macro to configure the RNG clock.
#define	__HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
	Macro to get the RNG clock.
#define	__HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))
	Macro to configure the USB clock (USBCLK).
#define	__HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
	Macro to get the USB clock source.
#define	__HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__))
	Macro to configure the ADC interface clock.
#define	__HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))
	Macro to get the ADC clock source.
#define	__HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__))
	Macro to configure the SWPMI1 clock.
#define	__HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL))
	Macro to get the SWPMI1 clock source.
#define	__HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__))
	Macro to configure the DFSDM1 clock.
#define	__HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL))
	Macro to get the DFSDM1 clock source.
#define	__HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
	Enable PLLSAI1RDY interrupt.
#define	__HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
	Disable PLLSAI1RDY interrupt.
#define	__HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)
	Clear the PLLSAI1RDY interrupt pending bit.
#define	__HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)
	Check whether PLLSAI1RDY interrupt has occurred or not.
#define	__HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))
	Check whether the PLLSAI1RDY flag is set or not.
#define	__HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
	Enable PLLSAI2RDY interrupt.
#define	__HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
	Disable PLLSAI2RDY interrupt.
#define	__HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)
	Clear the PLLSAI2RDY interrupt pending bit.
#define	__HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)
	Check whether the PLLSAI2RDY interrupt has occurred or not.
#define	__HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))
	Check whether the PLLSAI2RDY flag is set or not.
#define	__HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
	Enable the RCC LSE CSS Extended Interrupt Line.
#define	__HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
	Disable the RCC LSE CSS Extended Interrupt Line.
#define	__HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
	Enable the RCC LSE CSS Event Line.
#define	__HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
	Disable the RCC LSE CSS Event Line.
#define	__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
	Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
#define	__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
	Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
#define	__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
	Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
#define	__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
	Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
#define	__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()
	Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
#define	__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()
	Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
#define	__HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
	Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
#define	__HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
	Clear the RCC LSE CSS EXTI flag.
#define	__HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
	Generate a Software interrupt on the RCC LSE CSS EXTI line.
#define	IS_RCC_LSCOSOURCE(__SOURCE__)
#define	IS_RCC_PERIPHCLOCK(__SELECTION__)
#define	IS_RCC_USART1CLKSOURCE(__SOURCE__)
#define	IS_RCC_USART2CLKSOURCE(__SOURCE__)
#define	IS_RCC_USART3CLKSOURCE(__SOURCE__)
#define	IS_RCC_UART4CLKSOURCE(__SOURCE__)
#define	IS_RCC_UART5CLKSOURCE(__SOURCE__)
#define	IS_RCC_LPUART1CLKSOURCE(__SOURCE__)
#define	IS_RCC_I2C1CLKSOURCE(__SOURCE__)
#define	IS_RCC_I2C2CLKSOURCE(__SOURCE__)
#define	IS_RCC_I2C3CLKSOURCE(__SOURCE__)
#define	IS_RCC_SAI1CLK(__SOURCE__)
#define	IS_RCC_SAI2CLK(__SOURCE__)
#define	IS_RCC_LPTIM1CLK(__SOURCE__)
#define	IS_RCC_LPTIM2CLK(__SOURCE__)
#define	IS_RCC_SDMMC1CLKSOURCE(__SOURCE__)
#define	IS_RCC_RNGCLKSOURCE(__SOURCE__)
#define	IS_RCC_USBCLKSOURCE(__SOURCE__)
#define	IS_RCC_ADCCLKSOURCE(__SOURCE__)
#define	IS_RCC_SWPMI1CLKSOURCE(__SOURCE__)
#define	IS_RCC_DFSDM1CLKSOURCE(__SOURCE__)
#define	IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
#define	IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
#define	IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
#define	IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) \|\| ((__VALUE__) == 17U))
#define	IS_RCC_PLLSAI1Q_VALUE(__VALUE__)
#define	IS_RCC_PLLSAI1R_VALUE(__VALUE__)
#define	IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
#define	IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
#define	IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
#define	IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) \|\| ((__VALUE__) == 17U))
#define	IS_RCC_PLLSAI2R_VALUE(__VALUE__)
Functions
HAL_StatusTypeDef	HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
	Initialize the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void	HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
	Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
uint32_t	HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
	Return the peripheral clock frequency for peripherals with clock source from PLLSAIs.
HAL_StatusTypeDef	HAL_RCCEx_EnablePLLSAI1 (RCC_PLLSAI1InitTypeDef *PLLSAI1Init)
	Enable PLLSAI1.
HAL_StatusTypeDef	HAL_RCCEx_DisablePLLSAI1 (void)
	Disable PLLSAI1.
HAL_StatusTypeDef	HAL_RCCEx_EnablePLLSAI2 (RCC_PLLSAI2InitTypeDef *PLLSAI2Init)
	Enable PLLSAI2.
HAL_StatusTypeDef	HAL_RCCEx_DisablePLLSAI2 (void)
	Disable PLLISAI2.
void	HAL_RCCEx_WakeUpStopCLKConfig (uint32_t WakeUpClk)
	Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
void	HAL_RCCEx_StandbyMSIRangeConfig (uint32_t MSIRange)
	Configure the MSI range after standby mode.
void	HAL_RCCEx_EnableLSECSS (void)
	Enable the LSE Clock Security System.
void	HAL_RCCEx_DisableLSECSS (void)
	Disable the LSE Clock Security System.
void	HAL_RCCEx_EnableLSECSS_IT (void)
	Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
void	HAL_RCCEx_LSECSS_IRQHandler (void)
	Handle the RCC LSE Clock Security System interrupt request.
__weak void	HAL_RCCEx_LSECSS_Callback (void)
	RCCEx LSE Clock Security System interrupt callback.
void	HAL_RCCEx_EnableLSCO (uint32_t LSCOSource)
	Select the Low Speed clock source to output on LSCO pin (PA2).
void	HAL_RCCEx_DisableLSCO (void)
	Disable the Low Speed clock output.
void	HAL_RCCEx_EnableMSIPLLMode (void)
	Enable the PLL-mode of the MSI.
void	HAL_RCCEx_DisableMSIPLLMode (void)
	Disable the PLL-mode of the MSI.

Detailed Description

Header file of RCC HAL Extended module.

Author:: MCD Application Team

Attention:

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Definition in file stm32l4xx_hal_rcc_ex.h.

Data Structures

Defines

Functions

Detailed Description

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