Flags

Elements values convention: XXXYYYYYb. More...

Defines
#define	RCC_FLAG_MSIRDY   ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)
#define	RCC_FLAG_HSIRDY   ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)
#define	RCC_FLAG_HSERDY   ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)
#define	RCC_FLAG_PLLRDY   ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)
#define	RCC_FLAG_PLLSAI1RDY   ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos)
#define	RCC_FLAG_PLLSAI2RDY   ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos)
#define	RCC_FLAG_LSERDY   ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)
#define	RCC_FLAG_LSECSSD   ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)
#define	RCC_FLAG_LSIRDY   ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)
#define	RCC_FLAG_FWRST   ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos)
#define	RCC_FLAG_OBLRST   ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)
#define	RCC_FLAG_PINRST   ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)
#define	RCC_FLAG_BORRST   ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)
#define	RCC_FLAG_SFTRST   ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)
#define	RCC_FLAG_IWDGRST   ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)
#define	RCC_FLAG_WWDGRST   ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)
#define	RCC_FLAG_LPWRRST   ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)

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Detailed Description

Elements values convention: XXXYYYYYb.

• YYYYY : Flag position in the register
• XXX : Register index
  • 001: CR register
  • 010: BDCR register
  • 011: CSR register
  • 100: CRRCR register

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Define Documentation

#define RCC_FLAG_BORRST   ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)

BOR reset flag

Definition at line 573 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_FWRST   ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos)

Firewall reset flag

Definition at line 570 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_HSERDY   ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)

HSE Ready flag

Definition at line 557 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_HSIRDY   ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)

HSI Ready flag

Definition at line 556 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_IWDGRST   ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)

Independent Watchdog reset flag

Definition at line 575 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_LPWRRST   ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)

Low-Power reset flag

Definition at line 577 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_LSECSSD   ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)

LSE Clock Security System Interrupt flag

Definition at line 566 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_LSERDY   ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)

LSE Ready flag

Definition at line 565 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_LSIRDY   ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)

LSI Ready flag

Definition at line 569 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_MSIRDY   ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)

MSI Ready flag

Definition at line 555 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_OBLRST   ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)

Option Byte Loader reset flag

Definition at line 571 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_PINRST   ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)

PIN reset flag

Definition at line 572 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_PLLRDY   ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)

PLL Ready flag

Definition at line 558 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_PLLSAI1RDY   ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos)

PLLSAI1 Ready flag

Definition at line 559 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_PLLSAI2RDY   ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos)

PLLSAI2 Ready flag

Definition at line 561 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_SFTRST   ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)

Software Reset flag

Definition at line 574 of file stm32l4xx_hal_rcc.h.

#define RCC_FLAG_WWDGRST   ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)

Window watchdog reset flag

Definition at line 576 of file stm32l4xx_hal_rcc.h.