Main Project
RISC-V Simulator
A comprehensive, open-source simulation environment for the RISC-V Instruction Set Architecture, designed for both teaching and architectural research.
Simulation Targets
- Behavioral (C-based): Single-cycle simulator, fast functional simulation of RISC-V programs
- RTL (Verilog): 5-stage in-order pipeline compiled and simulated with Verilator
Supported Extensions
- RV32I / RV64I — Base integer ISA
- M extension — Integer multiplication/division
- B extension — Bit manipulation
- CSR — Control and status registers
OS & Device Support
- Runs Linux 6.x (Debian RISC-V) — full boot to login 🎉
- Runs xv6 operating system (MIT)
- OpenSBI firmware (M-mode), VirtIO block device
- PLIC, CLINT, UART, HTIF device emulation
Use Cases
- Computer Architecture courses (UPV)
- RTL design and verification labs
- RISC-V ISA exploration and testing
- OS porting and kernel development
Architecture Overview
The simulator consists of two independent simulation paths sharing the same RISC-V program interface:
A fast, single-cycle functional model written in C. Executes RISC-V programs instruction by instruction, useful for testing program correctness and ISA exploration without RTL complexity. Supports interactive debugging and tracing.
A 5-stage in-order pipeline (IF → ID → EX → MEM → WB) implemented in Verilog and compiled with Verilator for cycle-accurate simulation. Includes hazard detection, forwarding paths, branch prediction, and full peripheral support for running real operating systems.
Linux Boot Files
Pre-built binary files to boot Debian Linux 6.6.82 (rv64gc) on the simulator.
These files are too large for the Git repository and are hosted directly here.
Convert image.qcow2 to raw format before use:
qemu-img convert -f qcow2 -O raw image.qcow2 image.raw
| File | Size | Description | Download |
|---|---|---|---|
| fw_jump.bin | ~275 KB | OpenSBI firmware (fw_jump, generic platform, rv64gc) | fw_jump.bin |
| kernel | ~22 MB | Linux 6.6.82 kernel Image (Debian rv64gc, uncompressed) | kernel |
| initrd | ~49 MB | Debian RISC-V initrd image | initrd |
| image.qcow2 | ~288 MB | Debian RISC-V root filesystem (qcow2 — convert to raw before use) | image.qcow2 |
linux/ directory of the simulator. Run with:
./build/riscv-sim -i linux/run.txt then >> run.
How to Cite
If you use the RISC-V Simulator in your research or teaching, please cite:
Universitat Politècnica de València, 2023.
Available at: https://github.com/jflich/RISCV-simulator