Publications — José Flich

Performance Isolation for Inference Processes in Edge GPU Systems P

J.J. Martín, J. Flich, C. Hernández

CoRR (arXiv:2601.07600), 2026

Comparative Evaluation of GPU Sharing Methods for Inference Tasks C

J.J. Martín-Osuna, J. Flich, C. Hernández

ACACES 2025 (HiPEAC Summer School), pp. 203–206, Fiuggi, Italy, Jul. 2025

SIRENA: SparsIty-REpetition aware Nibble-based hardware Accelerator for convolutional neural networks J

L. Medina, J. Flich

Journal of Systems Architecture, vol. 168, 2025

Exploiting neural networks bit-level redundancy to mitigate the impact of faults at inference J

I. Catalán, J. Flich, C. Hernández

Journal of Supercomputing, vol. 81(1), Jan. 2025

Scalable Neural Network Training: Distributed Data-Parallel Approaches W

F. Vázquez-Novoa, P. López, J. Flich, R.M. Badia

SC Workshops 2025, pp. 2088–2099

HPC Platform for Railway Safety-Critical Functionalities Based on Artificial Intelligence J

M. Labayen, L. Medina-Chaveli, F. Eizaguirre, J. Flich, N. Aginako

Applied Sciences, vol. 13(15), 2023

NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips C

X. Iturbe, N. Abderrahmane, J. Flich et al.

DATE 2023, pp. 1–6

Towards Efficient Neural Network Model Parallelism on Multi-FPGA Platforms C

D. Rodriguez, R. Tornero, J. Flich

DATE 2023, pp. 1–6

An Open-Source FPGA Platform for Shared-Memory Heterogeneous Many-Core Architecture Exploration C

R. Tornero, D. Rodriguez, J.M. Martínez, J. Flich

DCIS 2023, pp. 1–6

Toward Matrix Multiplication for Deep Learning Inference on the Xilinx Versal C

J. Lei, J. Flich, E.S. Quintana-Ortí

PDP 2023, pp. 227–234

On the Potentials of Input Repetition in CNN Networks for Reducing Multiplications W

L. Medina, J. Flich

ECML/PKDD Workshops 2023, pp. 138–152

GEMM-Like Convolution for Deep Learning Inference on the Xilinx Versal W

J. Lei, H. Martínez, J. Flich, E.S. Quintana-Ortí

ISC Workshops 2023, pp. 593–604

Toward matrix multiplication for deep learning inference on the Xilinx Versal P

J. Lei, J. Flich, E.S. Quintana-Ortí

CoRR (arXiv:2302.07594), 2023

Enabling dynamic and intelligent workflows for HPC, data analytics, and AI convergence J

J. Ejarque, R.M. Badia, J. Flich et al.

Future Generation Computer Systems, vol. 134, pp. 414–429, 2022

The SELENE Deep Learning Acceleration Framework for Safety-related Applications C

L. Medina, S. Carrion, P. Andreu, T. Picornell, J. Flich et al.

DATE 2022, pp. 636–639

Efficient Inference of Image-Based Neural Network Models in Reconfigurable Systems With Pruning And Quantization C

J. Flich, L. Medina, I. Catalán, C. Hernández, A. Bragagnolo, F. Auzanneau, D. Briand

ICIP 2022, pp. 2491–2495

The DeepHealth Toolkit: A Key European Free and Open-Source Software for Deep Learning and Computer Vision B

M. Aldinucci, D. Atienza, F. Bolelli, J. Flich et al.

Technologies and Applications for Big Data Value, pp. 183–202, Springer, 2022

Enforcing Predictability of Many-Cores With DCFNoC J

T. Picornell, J. Flich, C. Hernández, J. Duato

IEEE Transactions on Computers, vol. 70(2), pp. 270–283, 2021

UPR: Deadlock-Free Dynamic Network Reconfiguration by Exploiting Channel Dependency Graph Compatibility J

J.J. Crespo, J.L. Sánchez, F.J. Alfaro-Cortés, J. Flich, J. Duato

Journal of Supercomputing, vol. 77(11), pp. 12826–12856, 2021

From a FPGA Prototyping Platform to a Computing Platform: The MANGO Experience C

J. Flich, R. Tornero, D. Rodriguez, D. Russo, J.M. Martínez, C. Hernández

DATE 2021, pp. 7–12

Improving the Robustness of Redundant Execution with Register File Randomization C

I. Tuzov, P. Andreu, L. Medina, T. Picornell, A. Robles, P. López, J. Flich, C. Hernández

ICCAD 2021, pp. 1–9

The RECIPE Approach to Challenges in Deeply Heterogeneous High Performance Systems P

G. Agosta, W. Fornaciari, D. Atienza, R. Canal, A. Cilardo, J. Flich, C. Hernández et al.

CoRR (arXiv:2103.03044), 2021

HP-DCFNoC: High Performance Distributed Dynamic TDM Scheduler Based on DCFNoC Theory J

T. Picornell, J. Flich, J. Duato, C. Hernández

IEEE Access, vol. 8, pp. 194836–194849, 2020

The RECIPE Approach to Challenges in Deeply Heterogeneous High Performance Systems J

G. Agosta, W. Fornaciari, D. Atienza, R. Canal, A. Cilardo, J. Flich, C. Hernández et al.

Microprocessors and Microsystems, vol. 77, p. 103185, 2020

SELENE: Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems C

C. Hernández, J. Flich, R. Paredes et al.

DSD 2020, pp. 370–377

Distributed Training on a Highly Heterogeneous HPC System C

J. Flich, C. Hernández, E. Quiñones, R. Paredes

SAMOS 2020, pp. 359–370

Guest Editors' Introduction: Emerging Networks-on-Chip Designs, Technologies, and Applications J

E. Fusella, M. Nikdast, I. O'Connor, J. Flich, S. Pasricha

ACM J. Emerg. Technol. Comput. Syst., vol. 15(1), pp. 1:1–1:2, 2019

DCFNoC: A Delayed Conflict-Free Time Division Multiplexing Network on Chip C

T. Picornell, J. Flich, C. Hernández, J. Duato

DAC 2019, p. 95

Challenges in Deeply Heterogeneous High Performance Systems C

G. Agosta, W. Fornaciari, D. Atienza, R. Canal, A. Cilardo, J. Flich, C. Hernández et al.

DSD 2019, pp. 428–435

A Low-Latency and Flexible TDM NoC for Strong Isolation in Security-Critical Systems C

M. Gorgues Alonso, J. Flich, M. Turki, D. Bertozzi

MCSoC 2019, pp. 149–156

Exploring manycore architectures for next-generation HPC systems through the MANGO approach J

J. Flich, G. Agosta, P. Ampletzer, D. Atienza et al.

Microprocessors and Microsystems, vol. 61, pp. 154–170, 2018

PROSA: Protocol-Driven Network on Chip Architecture J

M. Gorgues Alonso, J. Flich

IEEE Transactions on Parallel and Distributed Systems, vol. 29(7), pp. 1560–1574, 2018

Path Setup for Hybrid NoC Architectures Exploiting Flooding and Standby J

E. Fusella, J. Flich, A. Cilardo

IEEE Transactions on Parallel and Distributed Systems, vol. 28(5), pp. 1403–1416, 2017

MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems C

J. Flich, G. Agosta, P. Ampletzer, D. Atienza et al.

DSD 2017, pp. 478–485

ICARO-PAPM: Congestion Management with Selective Queue Power-Gating C

J.V. Escamilla, J. Flich, M.R. Casu

HPCS 2017, pp. 259–266

Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration C

J. Flich, A. Cilardo, M. Kovač, R. Tornero, M. Gagliardi, E. Fusella, J.M. Martínez, T. Picornell

PARCO 2017, pp. 381–389

End-Point Congestion Filter for Adaptive Routing with Congestion-Insensitive Performance J

M. Gorgues, J. Flich

IEEE Computer Architecture Letters, vol. 15(1), pp. 9–12, 2016

CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs J

D. Zoni, J. Flich, W. Fornaciari

IEEE Transactions on Parallel and Distributed Systems, vol. 27(6), pp. 1603–1616, 2016

Enabling HPC for QoS-sensitive applications: The MANGO approach C

J. Flich, G. Agosta, P. Ampletzer, D. Atienza, C. Brandolese, A. Cilardo, W. Fornaciari et al.

DATE 2016, pp. 702–707

Increasing the Efficiency of Latency-Driven DVFS with a Smart NoC Congestion Management Strategy C

J.V. Escamilla, M.R. Casu, J. Flich

MCSoC 2016, pp. 241–248

PROSA: Protocol-driven NoC architecture C

M. Gorgues Alonso, J. Flich

NOCS 2016, pp. 1–8

Logic-based implementation of fault-tolerant routing in 3D network-on-chips C

B. Niazmand, S.P. Azad, J. Flich, J. Raik, G. Jervan, T. Hollstein

NOCS 2016, pp. 1–8

Efficient and Cost-Effective Hybrid Congestion Control for HPC Interconnection Networks J

J. Escudero-Sahuquillo, E.G. Gran, P.J. García, J. Flich, T. Skeie, O. Lysne, F.J. Quiles, J. Duato

IEEE Transactions on Parallel and Distributed Systems, vol. 26(1), pp. 107–119, 2015

The fast evolving landscape of on-chip communication J

D. Bertozzi, G. Dimitrakopoulos, J. Flich, S. Sonntag

Design Automation for Embedded Systems, vol. 19(1-2), pp. 59–76, 2015

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems J

A. Roca, C. Hernández, M. Lodde, J. Flich

Computers & Electrical Engineering, vol. 45, pp. 374–385, 2015

The MANGO FET-HPC Project: An Overview C

J. Flich, G. Agosta, P. Ampletzer, D. Atienza, A. Cilardo, W. Fornaciari, M. Kovac, F. Roudet, D. Zoni

CSE 2015, pp. 351–354

d²-LBDR: Distance-driven routing to handle permanent failures in 2D mesh NOCs C

R. Bishnoi, V. Laxmi, M.S. Gaur, J. Flich

DATE 2015, pp. 800–805

Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration C

M. Balboni, J. Flich, D. Bertozzi

DATE 2015, pp. 806–811

Proceedings of NOCS 2015 (9th Int. Symp. on Networks-on-Chip) E

Editors: A. Ivanov, D. Marculescu, P.P. Pande, J. Flich, K. Pattabiraman

ACM, 2015

Efficient Routing in Heterogeneous SoC Designs with Small Implementation Overhead J

J. Cano, J. Flich, A. Roca, J. Duato, M. Coppola, R. Locatelli

IEEE Transactions on Computers, vol. 63(3), pp. 557–569, 2014

Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing J

M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, J. Flich, H. Tenhunen

IEEE Transactions on Computers, vol. 63(3), pp. 718–733, 2014

Runtime home mapping for effective memory resource usage J

M. Lodde, J. Flich

Microprocessors and Microsystems, vol. 38(4), pp. 276–291, 2014

Achieving balanced buffer utilization with a proper co-design of flow control and routing algorithm C

M. Gorgues, D. Xiang, J. Flich, Z. Yu, J. Duato

NOCS 2014, pp. 25–32

ICARO: Congestion isolation in networks-on-chip C

J.V. Escamilla, J. Flich, P.J. García

NOCS 2014, pp. 159–166

An Effective and Feasible Congestion Management Technique for High-Performance MINs with Tag-Based Distributed Routing J

J. Escudero-Sahuquillo, P.J. García, F.J. Quiles, J. Flich, J. Duato

IEEE Transactions on Parallel and Distributed Systems, vol. 24(10), pp. 1918–1929, 2013

A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs J

A. Ghiribaldi, D. Ludovici, F. Triviño, A. Strano, J. Flich, J.L. Sánchez, F.J. Alfaro, M. Favalli, D. Bertozzi

ACM Trans. Embed. Comput. Syst., vol. 12(4), pp. 106:1–106:29, 2013

Silicon-aware distributed switch architecture for on-chip networks J

A. Roca, C. Hernández, J. Flich, F. Silla, J. Duato

Journal of Systems Architecture, vol. 59(7), pp. 505–515, 2013

Making the Network Scalable: Inter-subnet Routing in InfiniBand C

B. Bogdanski, B.D. Johnsen, S.A. Reinemo, J. Flich

Euro-Par 2013, pp. 685–698

Head-of-Line Blocking Avoidance in Networks-on-Chip W

J.V. Escamilla, J. Flich, P.J. García

IPDPS Workshops 2013, pp. 796–805

An NoC and Cache Hierarchy Substrate to Address Effective Virtualization and Fault-Tolerance C

M. Lodde, J. Flich

NOCS 2013, pp. 1–8

Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations C

D. Zoni, J. Flich, W. Fornaciari

PATMOS 2013, pp. 231–234

A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms J

J. Flich, T. Skeie, A. Mejia, O. Lysne, P. López, A. Robles, J. Duato, M. Koibuchi, T. Rokicki, J.C. Sancho

IEEE Transactions on Parallel and Distributed Systems, vol. 23(3), pp. 405–425, 2012

On the Impact of Within-Die Process Variation in GALS-Based NoC Performance J

C. Hernández, A. Roca, F. Silla, J. Flich, J. Duato

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., vol. 31(2), pp. 294–307, 2012

Network-on-Chip virtualization in Chip-Multiprocessor Systems J

F. Triviño, J.L. Sánchez, F.J. Alfaro, J. Flich

Journal of Systems Architecture, vol. 58(3-4), pp. 126–139, 2012

DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAs C

A. Roca, J. Flich, G. Dimitrakopoulos

FPL 2012, pp. 394–399

Enabling High-Performance Crossbars through a Floorplan-Aware Design C

A. Roca, C. Hernández, J. Flich, F. Silla, J. Duato

ICPP 2012, pp. 269–278

OSR-Lite: Fast and deadlock-free NoC reconfiguration framework C

A. Strano, D. Bertozzi, F. Triviño, J.L. Sánchez, F.J. Alfaro, J. Flich

ICSAMOS 2012, pp. 86–95

Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems J

S. Rodrigo, J. Flich, A. Roca, S. Medardoni, D. Bertozzi, J. Camacho, F. Silla, J. Duato

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., vol. 30(4), pp. 534–547, 2011

OBQA: Smart and cost-efficient queue scheme for Head-of-Line blocking elimination in fat-trees J

J. Escudero-Sahuquillo, P.J. García, F.J. Quiles, J. Flich, J. Duato

Journal of Parallel and Distributed Computing, vol. 71(11), pp. 1460–1472, 2011

Characterizing the impact of process variation on 45 nm NoC-based CMPs J

C. Hernández, A. Roca, J. Flich, F. Silla, J. Duato

Journal of Parallel and Distributed Computing, vol. 71(5), pp. 651–663, 2011

Virtualizing network-on-chip resources in chip-multiprocessors J

F. Triviño, J.L. Sánchez, F.J. Alfaro, J. Flich

Microprocessors and Microsystems, vol. 35(2), pp. 230–245, 2011

A low-latency modular switch for CMP systems J

A. Roca, J. Flich, F. Silla, J. Duato

Microprocessors and Microsystems, vol. 35(8), pp. 742–754, 2011

A Communication-Driven Routing Technique for Application-Specific NoCs J

R. Tornero, J.M. Orduna, A. Mejia, J. Flich, J. Duato

Int. J. Parallel Program., vol. 39(3), pp. 357–374, 2011

A Distributed Switch Architecture for On-Chip Networks C

A. Roca, C. Hernández, J. Flich, F. Silla, J. Duato

ICPP 2011, pp. 21–30

PC-Mesh: A Dynamic Parallel Concentrated Mesh C

J. Camacho Villanueva, J. Flich, A. Roca, J. Duato

ICPP 2011, pp. 642–651

HPC-Mesh: A Homogeneous Parallel Concentrated Mesh for Fault-Tolerance and Energy Savings C

J. Camacho Villanueva, J. Flich

ANCS 2011, pp. 69–80

Fault-Tolerant Vertical Link Design for Effective 3D Stacking J

C. Hernández, A. Roca, J. Flich, F. Silla, J. Duato

IEEE Computer Architecture Letters, vol. 10(2), pp. 41–44, 2011

Flow Control · Switch Architecture B

J. Flich

Encyclopedia of Parallel Computing, Springer, 2011

Buffer Management Strategies to Reduce HoL Blocking J

T. Nachiondo Frínós, J. Flich, J. Duato

IEEE Transactions on Parallel and Distributed Systems, vol. 21(6), pp. 739–753, 2010

Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing C

S. Rodrigo, J. Flich, A. Roca, S. Medardoni, D. Bertozzi, J. Camacho, F. Silla, J. Duato

NOCS 2010, pp. 25–32

Improving the Performance of GALS-Based NoCs in the Presence of Process Variation C

C. Hernández, A. Roca, F. Silla, J. Flich, J. Duato

NOCS 2010, pp. 35–42

A Switch Architecture Guaranteeing QoS Provision and HOL Blocking Elimination J

A. Martínez, P.J. García, F.J. Alfaro, J.L. Sánchez, J. Flich, F.J. Quiles, J. Duato

IEEE Transactions on Parallel and Distributed Systems, vol. 20(1), pp. 13–24, Jan. 2009 · PDF

An Efficient and Deadlock-Free Network Reconfiguration Protocol J

O. Lysne, J. Montañana, J. Flich, J. Duato, T. Pinkston, T. Skeie

IEEE Transactions on Computers, vol. 57(6), pp. 762–779, Jun. 2008 · PDF

On the Potential of NoC Virtualization for Multicore Chips J

J. Flich, R. Mocholí, J. Duato, T. Sodring, A.G. Solheim, T. Skeie, O. Lysne

Scalable Computing: Practice and Experience, vol. 9, pp. 165–177, Sep. 2008 · PDF

Logic-Based Distributed Routing for NoCs J

J. Flich, J. Duato

IEEE Computer Architecture Letters, vol. 7(1), pp. 13–16, Jan. 2008 · PDF

Decongestants for Clogged Networks J

P. Garcia, J. Flich, J. Duato, F.J. Quiles, I. Johnson, F. Naven

IEEE Potentials Magazine, vol. 26(6), pp. 36–41, Nov. 2007 · PDF

Integrated QoS Provision and Congestion Management for Interconnection Networks C

A. Martinez, P.J. García, F.J. Alfaro, J.L. Sánchez, J. Flich, F.J. Quiles, J. Duato

Euro-Par 2007, LNCS 4641, pp. 837–847 · PDF

Efficient, Scalable Congestion Management for Interconnection Networks J

P. Garcia, F.J. Quiles, J. Flich, J. Duato, I. Johnson, F. Naven

IEEE Micro, vol. 26(5), pp. 52–66, Sep. 2006 · PDF

Towards a Cost-Effective Interconnection Network Architecture with QoS and Congestion Management Support C

A. Martinez, P.J. García, F.J. Alfaro, J.L. Sánchez, J. Flich, F.J. Quiles, J. Duato

Euro-Par 2006, LNCS 4128, pp. 884–895 · PDF

An Scalable Methodology for Computing Fault-Free Paths in InfiniBand Torus Networks C

J.M. Montañana, J. Flich, A. Robles, J. Duato

ISHPC 2005, LNCS, pp. 79–92 · PDF