José Flich Cardo

José Flich Cardo

Full Professor (Catedrático de Universidad)

Parallel Architectures Group (GAP) · ETSINF · Universitat Politècnica de València

My research spans hardware design for AI/ML acceleration, fault-tolerant computing, high-performance heterogeneous architectures, and Networks-on-Chip. I lead and participate in EU and national research projects, I serve as an Expert Evaluator for the European Commission (Horizon Europe, KDT JU), and I am the author of the open-source RISC-V Simulator for teaching and research.

150+
Publications
13+
PhD Students Supervised
15+
EU/National Projects
25+
Years of Research

Research Areas

AI / DL Hardware Acceleration

Efficient inference on FPGAs and GPUs; sparsity exploitation, quantization, and CNN accelerator design.

Fault Tolerance & Safety-Critical Systems

Reliability in AI inference, redundant execution, and safety platforms for autonomous and HPC systems.

Heterogeneous HPC Architectures

FPGA-based many-core platforms, distributed training, and HPC/AI convergence (MANGO, RECIPE, SELENE).

Networks-on-Chip (NoC)

Routing algorithms, congestion management, TDM-based predictable NoCs, fault tolerance, and virtualization.

RISC-V Architecture & Simulation

Open-source RISC-V simulator (behavioral + 5-stage Verilog core) for teaching and architectural exploration.

High-Performance Interconnects

InfiniBand-like networks, congestion management, deadlock-free routing, and fault-tolerant reconfiguration.

View full research overview →

Recent Publications

Performance Isolation for Inference Processes in Edge GPU Systems
J.J. Martín-Osuna, J. Flich, C. Hernández
CoRR (arXiv:2601.07600) · Preprint · 2026
Comparative Evaluation of GPU Sharing Methods for Inference Tasks
J.J. Martín-Osuna, J. Flich, C. Hernández
ACACES 2025 · Conference · 2025
SIRENA: SparsIty-REpetition aware Nibble-based hardware Accelerator for convolutional neural networks
L. Medina, J. Flich
Journal of Systems Architecture, vol. 168 · Journal · 2025
Exploiting neural networks bit-level redundancy to mitigate the impact of faults at inference
I. Catalán, J. Flich, C. Hernández
Journal of Supercomputing, vol. 81(1) · Journal · 2025
NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips
X. Iturbe, N. Abderrahmane, J. Flich et al.
DATE 2023 · Conference · 2023
All publications →

News

Apr 2026
RISC-V Simulator milestone: full Linux 6.6.82 (Debian rv64gc) boot to login, including OpenSBI, VirtIO, and Sstc timer.
Feb 2026
Izan Catalán Gallach successfully defended his PhD thesis on fault tolerance via bit-level redundancy in neural networks.
Nov 2025
David Rodríguez Agut successfully defended his PhD thesis on efficient multi-FPGA platforms for CNN inference.
Apr 2026
New preprint on performance isolation for AI inference in edge GPU systems.
2025
Papers on SIRENA CNN accelerator (J. Systems Architecture) and fault tolerance in NN inference (J. Supercomputing) published.
2024
New EU projects started: DEAI (KDT JU) and Inteligencia Sostenible en el Borde (AEI).

Quick Links

Full publication list Research projects RISC-V Simulator PhD students & team DBLP profile ORCID: 0000-0001-8581-6284

Affiliation

Universitat Politècnica de València

Dept. Informática de Sistemas y Computadores (DISCA)

Escola Tècnica Superior d'Enginyeria Informàtica (ETSINF)

Parallel Architectures Group (GAP)