Research

Computer architecture · AI acceleration · Networks-on-Chip · Safety-critical systems

Current Research Areas

AI / Deep Learning Hardware Acceleration

Design of hardware accelerators for efficient CNN/DNN inference. Research directions include:

  • Exploiting sparsity and input repetition in convolutional networks to reduce multiplications (SIRENA accelerator)
  • Quantization-aware inference (nibble-based arithmetic, INT4/INT8)
  • FPGA and GPU-based inference optimization
  • GEMM-like convolution kernels on heterogeneous hardware (Xilinx Versal, multi-FPGA)
  • Distributed data-parallel training for HPC systems
FPGA CNN Inference Quantization Sparsity Distributed Training
Fault Tolerance & Safety-Critical Computing

Ensuring reliability and functional safety in high-performance and AI systems:

  • Bit-level redundancy exploitation in neural networks to mitigate inference faults
  • Register file randomization for robust redundant execution
  • Self-monitored dependable platforms for safety-critical applications (SELENE project)
  • Deep learning acceleration frameworks for safety-related applications
  • Predictability enforcement in many-core systems (DCFNoC)
Fault Tolerance Safety-Critical Redundant Execution AI Reliability
Heterogeneous HPC Architectures

Next-generation computing platforms combining diverse processing elements:

  • Open-source FPGA platform for shared-memory heterogeneous many-core exploration (MANGO project)
  • HPC/AI convergence: workflows combining simulation, data analytics, and ML
  • Distributed training on deeply heterogeneous systems
  • Neural network model parallelism on multi-FPGA platforms
  • Neuromorphic sensing-processing 3D-integrated chips (NimbleAI project)
HPC FPGA Many-core HPC/AI Convergence Neuromorphic
Networks-on-Chip (NoC)

Foundational expertise in on-chip interconnection networks:

  • Routing algorithms (LBDR, topology-agnostic deterministic routing)
  • Congestion management (ICARO, end-point filters)
  • TDM-based predictable NoCs: DCFNoC and HP-DCFNoC for real-time guarantees
  • Protocol-driven NoC architectures (PROSA)
  • NoC virtualization and reconfiguration (OSR, UPR)
  • Fault-tolerant routing and 3D NoC design
NoC Routing Congestion Control TDM Virtualization
RISC-V Architecture & Simulation

Open-source simulator for RISC-V architecture, used for teaching and research:

  • Behavioral single-cycle simulator (C-based)
  • 5-stage in-order pipeline implemented in Verilog (Verilator-based)
  • Support for RISC-V extension M (integer multiplication/division) and B (bit manipulation)
  • Running real OS: xv6 operating system
  • Device emulation: PLIC, CLINT, UART
RISC-V Verilog Verilator Computer Architecture
High-Performance Off-Chip Interconnects

InfiniBand and fat-tree based interconnects for HPC clusters:

  • Topology-agnostic routing algorithms (survey and evaluation)
  • Deadlock-free network reconfiguration protocols
  • Hybrid congestion control for HPC interconnection networks
  • Head-of-line blocking elimination in fat-trees (OBQA scheme)
  • Inter-subnet routing scalability for InfiniBand
InfiniBand Fat-tree Routing Congestion Management

Selected Key Publications

A selection of representative papers across research areas. See the full publication list for the complete record.

AI / DL Acceleration
SIRENA: SparsIty-REpetition aware Nibble-based hardware Accelerator for CNNs
L. Medina, J. Flich
J. Syst. Archit. · Journal · 2025
Toward Matrix Multiplication for Deep Learning Inference on the Xilinx Versal
J. Lei, J. Flich, E.S. Quintana-Ortí
PDP 2023 · Conference
Efficient Inference of Image-Based Neural Network Models in Reconfigurable Systems
J. Flich, L. Medina, I. Catalán et al.
ICIP 2022 · Conference
Fault Tolerance
Exploiting neural networks bit-level redundancy to mitigate the impact of faults at inference
I. Catalán, J. Flich, C. Hernández
J. Supercomput. · Journal · 2025
Enforcing Predictability of Many-Cores With DCFNoC
T. Picornell, J. Flich, C. Hernández, J. Duato
IEEE Trans. Computers · Journal · 2021
Improving the Robustness of Redundant Execution with Register File Randomization
I. Tuzov, P. Andreu, L. Medina, J. Flich et al.
ICCAD 2021 · Conference
Networks-on-Chip
A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms
J. Flich, T. Skeie, A. Mejia, O. Lysne et al.
IEEE TPDS · Journal · 2012
PROSA: Protocol-Driven Network on Chip Architecture
M. Gorgues Alonso, J. Flich
IEEE TPDS · Journal · 2018
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems
S. Rodrigo, J. Flich, A. Roca et al.
IEEE TCAD · Journal · 2011
HPC Architectures
Exploring manycore architectures for next-generation HPC systems through the MANGO approach
J. Flich, G. Agosta, D. Atienza et al.
Microprocess. Microsystems · Journal · 2018
Enabling dynamic and intelligent workflows for HPC, data analytics, and AI convergence
J. Ejarque, R.M. Badia, J. Flich et al.
Future Gener. Comput. Syst. · Journal · 2022
From a FPGA Prototyping Platform to a Computing Platform: The MANGO Experience
J. Flich, R. Tornero, D. Rodriguez et al.
DATE 2021 · Conference

Research Collaborators

I collaborate with researchers from leading institutions including:

Politecnico di Milano (Italy)
EPFL — École Polytechnique Fédérale de Lausanne (Switzerland)
Univ. of Naples Federico II (Italy)
BSC — Barcelona Supercomputing Center
Simula Research Lab (Norway)
Univ. of Bologna (Italy)
Politecnico di Torino (Italy)
Univ. of Castilla–La Mancha
Univ. de Zaragoza