EU-funded and national research projects in HPC, AI, Networks-on-Chip, and safety-critical computing
A comprehensive, open-source simulation environment for the RISC-V ISA, designed for teaching and architectural research. Features a fast single-cycle behavioral simulator (C) and a cycle-accurate 5-stage in-order pipeline (Verilog + Verilator). Supports RV32/RV64 with extensions I, M, F, D, A, B, C, V, privileged ISA, and full OS mode.
Milestone (Apr 2026): Full Linux 6.6.82 (Debian rv64gc) boot to login — including OpenSBI, VirtIO block device, PLIC/CLINT interrupt handling, and Sstc timer extension.
Advancing Trust, Safety, and Sustainability in Europe. Developing decentralized edge AI systems with a focus on trustworthiness, safety certification, and energy efficiency for European industrial and embedded applications. Ref: 101139892.
Sustainable intelligence at the edge: research on efficient AI inference for edge platforms, combining hardware acceleration, energy optimization, and reliability. Part of a coordinated national project (PID2023-146569NB-C21).
High Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems. Building open RISC-V based domain-specific hardware ecosystems for safety-critical and high-performance applications. Ref: 101112274.
Enabling Dynamic and Intelligent Workflows in the Future EuroHPC Ecosystem. Developed adaptive workflow management for HPC/AI convergence, integrating data analytics and ML into supercomputing pipelines. Ref: 955558.
Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems. Design of a self-monitored HPC platform targeting automotive, aerospace, and industrial safety-critical applications, with focus on deep learning acceleration under strict safety requirements (ISO 26262 / IEC 61508). Ref: 871467.
Deep-Learning and HPC to Boost Biomedical Applications for Health. Development of the DeepHealth Toolkit — an open-source European library for deep learning and computer vision, targeting biomedical and health-care applications running on HPC and cloud infrastructures. Ref: 825111.
Exploring Manycore Architectures for Next-GeneratiOn HPC Systems. Designed and prototyped an open, flexible many-accelerator FPGA-based platform for HPC architecture research, providing reconfigurable compute nodes with heterogeneous accelerators and a custom NoC.
Novel Architectures for Nanoscale On-Chip communication. Explored advanced routing, reconfiguration, fault-tolerance, and testing mechanisms for nanoscale Networks-on-Chip, addressing the challenges of emerging manufacturing technologies and process variability.
Communication, Computing, and Applications in Systems. Research on high-performance communication systems and on-chip network architectures for multicore systems, with emphasis on quality of service and congestion management.
Consolidated national research project focused on parallel architectures and interconnection networks. Brought together multiple Spanish research groups to advance the state of the art in multiprocessor interconnects and on-chip networks.
Multiple grants from the Spanish National Research Program (CICYT / MINECO) on topics including routing algorithms for parallel and distributed systems, fault-tolerant networks, and high-performance interconnection architectures.