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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_tim.h 00004 * @author MCD Application Team 00005 * @brief Header file of TIM HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef STM32L4xx_HAL_TIM_H 00038 #define STM32L4xx_HAL_TIM_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx_hal_def.h" 00046 00047 /** @addtogroup STM32L4xx_HAL_Driver 00048 * @{ 00049 */ 00050 00051 /** @addtogroup TIM 00052 * @{ 00053 */ 00054 00055 /* Exported types ------------------------------------------------------------*/ 00056 /** @defgroup TIM_Exported_Types TIM Exported Types 00057 * @{ 00058 */ 00059 00060 /** 00061 * @brief TIM Time base Configuration Structure definition 00062 */ 00063 typedef struct 00064 { 00065 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 00066 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 00067 00068 uint32_t CounterMode; /*!< Specifies the counter mode. 00069 This parameter can be a value of @ref TIM_Counter_Mode */ 00070 00071 uint32_t Period; /*!< Specifies the period value to be loaded into the active 00072 Auto-Reload Register at the next update event. 00073 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 00074 00075 uint32_t ClockDivision; /*!< Specifies the clock division. 00076 This parameter can be a value of @ref TIM_ClockDivision */ 00077 00078 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 00079 reaches zero, an update event is generated and counting restarts 00080 from the RCR value (N). 00081 This means in PWM mode that (N+1) corresponds to: 00082 - the number of PWM periods in edge-aligned mode 00083 - the number of half PWM period in center-aligned mode 00084 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 00085 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 00086 00087 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 00088 This parameter can be a value of @ref TIM_AutoReloadPreload */ 00089 } TIM_Base_InitTypeDef; 00090 00091 /** 00092 * @brief TIM Output Compare Configuration Structure definition 00093 */ 00094 typedef struct 00095 { 00096 uint32_t OCMode; /*!< Specifies the TIM mode. 00097 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 00098 00099 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 00100 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 00101 00102 uint32_t OCPolarity; /*!< Specifies the output polarity. 00103 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 00104 00105 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 00106 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 00107 @note This parameter is valid only for timer instances supporting break feature. */ 00108 00109 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 00110 This parameter can be a value of @ref TIM_Output_Fast_State 00111 @note This parameter is valid only in PWM1 and PWM2 mode. */ 00112 00113 00114 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00115 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 00116 @note This parameter is valid only for timer instances supporting break feature. */ 00117 00118 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00119 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 00120 @note This parameter is valid only for timer instances supporting break feature. */ 00121 } TIM_OC_InitTypeDef; 00122 00123 /** 00124 * @brief TIM One Pulse Mode Configuration Structure definition 00125 */ 00126 typedef struct 00127 { 00128 uint32_t OCMode; /*!< Specifies the TIM mode. 00129 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 00130 00131 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 00132 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 00133 00134 uint32_t OCPolarity; /*!< Specifies the output polarity. 00135 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 00136 00137 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 00138 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 00139 @note This parameter is valid only for timer instances supporting break feature. */ 00140 00141 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00142 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 00143 @note This parameter is valid only for timer instances supporting break feature. */ 00144 00145 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00146 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 00147 @note This parameter is valid only for timer instances supporting break feature. */ 00148 00149 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 00150 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00151 00152 uint32_t ICSelection; /*!< Specifies the input. 00153 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00154 00155 uint32_t ICFilter; /*!< Specifies the input capture filter. 00156 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00157 } TIM_OnePulse_InitTypeDef; 00158 00159 /** 00160 * @brief TIM Input Capture Configuration Structure definition 00161 */ 00162 typedef struct 00163 { 00164 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 00165 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00166 00167 uint32_t ICSelection; /*!< Specifies the input. 00168 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00169 00170 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 00171 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 00172 00173 uint32_t ICFilter; /*!< Specifies the input capture filter. 00174 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00175 } TIM_IC_InitTypeDef; 00176 00177 /** 00178 * @brief TIM Encoder Configuration Structure definition 00179 */ 00180 typedef struct 00181 { 00182 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 00183 This parameter can be a value of @ref TIM_Encoder_Mode */ 00184 00185 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 00186 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00187 00188 uint32_t IC1Selection; /*!< Specifies the input. 00189 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00190 00191 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 00192 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 00193 00194 uint32_t IC1Filter; /*!< Specifies the input capture filter. 00195 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00196 00197 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 00198 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00199 00200 uint32_t IC2Selection; /*!< Specifies the input. 00201 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00202 00203 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 00204 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 00205 00206 uint32_t IC2Filter; /*!< Specifies the input capture filter. 00207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00208 } TIM_Encoder_InitTypeDef; 00209 00210 /** 00211 * @brief Clock Configuration Handle Structure definition 00212 */ 00213 typedef struct 00214 { 00215 uint32_t ClockSource; /*!< TIM clock sources 00216 This parameter can be a value of @ref TIM_Clock_Source */ 00217 uint32_t ClockPolarity; /*!< TIM clock polarity 00218 This parameter can be a value of @ref TIM_Clock_Polarity */ 00219 uint32_t ClockPrescaler; /*!< TIM clock prescaler 00220 This parameter can be a value of @ref TIM_Clock_Prescaler */ 00221 uint32_t ClockFilter; /*!< TIM clock filter 00222 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00223 } TIM_ClockConfigTypeDef; 00224 00225 /** 00226 * @brief TIM Clear Input Configuration Handle Structure definition 00227 */ 00228 typedef struct 00229 { 00230 uint32_t ClearInputState; /*!< TIM clear Input state 00231 This parameter can be ENABLE or DISABLE */ 00232 uint32_t ClearInputSource; /*!< TIM clear Input sources 00233 This parameter can be a value of @ref TIM_ClearInput_Source */ 00234 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 00235 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 00236 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 00237 This parameter can be a value of @ref TIM_ClearInput_Prescaler */ 00238 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 00239 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00240 } TIM_ClearInputConfigTypeDef; 00241 00242 /** 00243 * @brief TIM Master configuration Structure definition 00244 * @note Advanced timers provide TRGO2 internal line which is redirected 00245 * to the ADC 00246 */ 00247 typedef struct 00248 { 00249 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 00250 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 00251 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection 00252 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ 00253 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 00254 This parameter can be a value of @ref TIM_Master_Slave_Mode */ 00255 } TIM_MasterConfigTypeDef; 00256 00257 /** 00258 * @brief TIM Slave configuration Structure definition 00259 */ 00260 typedef struct 00261 { 00262 uint32_t SlaveMode; /*!< Slave mode selection 00263 This parameter can be a value of @ref TIM_Slave_Mode */ 00264 uint32_t InputTrigger; /*!< Input Trigger source 00265 This parameter can be a value of @ref TIM_Trigger_Selection */ 00266 uint32_t TriggerPolarity; /*!< Input Trigger polarity 00267 This parameter can be a value of @ref TIM_Trigger_Polarity */ 00268 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 00269 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 00270 uint32_t TriggerFilter; /*!< Input trigger filter 00271 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00272 00273 } TIM_SlaveConfigTypeDef; 00274 00275 /** 00276 * @brief TIM Break input(s) and Dead time configuration Structure definition 00277 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 00278 * filter and polarity. 00279 */ 00280 typedef struct 00281 { 00282 uint32_t OffStateRunMode; /*!< TIM off state in run mode 00283 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 00284 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode 00285 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 00286 uint32_t LockLevel; /*!< TIM Lock level 00287 This parameter can be a value of @ref TIM_Lock_level */ 00288 uint32_t DeadTime; /*!< TIM dead Time 00289 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 00290 uint32_t BreakState; /*!< TIM Break State 00291 This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 00292 uint32_t BreakPolarity; /*!< TIM Break input polarity 00293 This parameter can be a value of @ref TIM_Break_Polarity */ 00294 uint32_t BreakFilter; /*!< Specifies the break input filter. 00295 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00296 uint32_t Break2State; /*!< TIM Break2 State 00297 This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ 00298 uint32_t Break2Polarity; /*!< TIM Break2 input polarity 00299 This parameter can be a value of @ref TIM_Break2_Polarity */ 00300 uint32_t Break2Filter; /*!< TIM break2 input filter. 00301 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00302 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state 00303 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 00304 } TIM_BreakDeadTimeConfigTypeDef; 00305 00306 /** 00307 * @brief HAL State structures definition 00308 */ 00309 typedef enum 00310 { 00311 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 00312 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 00313 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 00314 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 00315 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 00316 } HAL_TIM_StateTypeDef; 00317 00318 /** 00319 * @brief HAL Active channel structures definition 00320 */ 00321 typedef enum 00322 { 00323 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 00324 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 00325 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 00326 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 00327 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ 00328 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ 00329 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 00330 } HAL_TIM_ActiveChannel; 00331 00332 /** 00333 * @brief TIM Time Base Handle Structure definition 00334 */ 00335 typedef struct __TIM_HandleTypeDef 00336 { 00337 TIM_TypeDef *Instance; /*!< Register base address */ 00338 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 00339 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 00340 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 00341 This array is accessed by a @ref DMA_Handle_index */ 00342 HAL_LockTypeDef Lock; /*!< Locking object */ 00343 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 00344 00345 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 00346 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 00347 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 00348 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 00349 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 00350 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 00351 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 00352 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 00353 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 00354 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 00355 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 00356 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 00357 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 00358 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ 00359 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ 00360 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 00361 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 00362 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 00363 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 00364 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 00365 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 00366 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 00367 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 00368 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ 00369 00370 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 00371 } TIM_HandleTypeDef; 00372 00373 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 00374 /** 00375 * @brief HAL TIM Callback ID enumeration definition 00376 */ 00377 typedef enum 00378 { 00379 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U, /*!< TIM Base MspInit Callback ID */ 00380 HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U, /*!< TIM Base MspDeInit Callback ID */ 00381 HAL_TIM_IC_MSPINIT_CB_ID = 0x02U, /*!< TIM IC MspInit Callback ID */ 00382 HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U, /*!< TIM IC MspDeInit Callback ID */ 00383 HAL_TIM_OC_MSPINIT_CB_ID = 0x04U, /*!< TIM OC MspInit Callback ID */ 00384 HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U, /*!< TIM OC MspDeInit Callback ID */ 00385 HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U, /*!< TIM PWM MspInit Callback ID */ 00386 HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U, /*!< TIM PWM MspDeInit Callback ID */ 00387 HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U, /*!< TIM One Pulse MspInit Callback ID */ 00388 HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U, /*!< TIM One Pulse MspDeInit Callback ID */ 00389 HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU, /*!< TIM Encoder MspInit Callback ID */ 00390 HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU, /*!< TIM Encoder MspDeInit Callback ID */ 00391 HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU, /*!< TIM Hall Sensor MspDeInit Callback ID */ 00392 HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU, /*!< TIM Hall Sensor MspDeInit Callback ID */ 00393 00394 HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU, /*!< TIM Period Elapsed Callback ID */ 00395 HAL_TIM_TRIGGER_CB_ID = 0x0FU, /*!< TIM Trigger Callback ID */ 00396 HAL_TIM_IC_CAPTURE_CB_ID = 0x10U, /*!< TIM Input Capture Callback ID */ 00397 HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x11U, /*!< TIM Output Compare Delay Elapsed Callback ID */ 00398 HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x12U, /*!< TIM PWM Pulse Finished Callback ID */ 00399 HAL_TIM_ERROR_CB_ID = 0x13U, /*!< TIM Error Callback ID */ 00400 HAL_TIM_COMMUTATION_CB_ID = 0x14U, /*!< TIM Commutation Callback ID */ 00401 HAL_TIM_BREAK_CB_ID = 0x15U, /*!< TIM Break Callback ID */ 00402 HAL_TIM_BREAK2_CB_ID = 0x16U /*!< TIM Break2 Callback ID */ 00403 00404 } HAL_TIM_CallbackIDTypeDef; 00405 00406 /** 00407 * @brief HAL TIM Callback pointer definition 00408 */ 00409 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 00410 00411 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 00412 00413 /** 00414 * @} 00415 */ 00416 /* End of exported types -----------------------------------------------------*/ 00417 00418 /* Exported constants --------------------------------------------------------*/ 00419 /** @defgroup TIM_Exported_Constants TIM Exported Constants 00420 * @{ 00421 */ 00422 00423 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 00424 * @{ 00425 */ 00426 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ 00427 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 00428 #define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */ 00429 /** 00430 * @} 00431 */ 00432 00433 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 00434 * @{ 00435 */ 00436 #define TIM_DMABASE_CR1 0x00000000U 00437 #define TIM_DMABASE_CR2 0x00000001U 00438 #define TIM_DMABASE_SMCR 0x00000002U 00439 #define TIM_DMABASE_DIER 0x00000003U 00440 #define TIM_DMABASE_SR 0x00000004U 00441 #define TIM_DMABASE_EGR 0x00000005U 00442 #define TIM_DMABASE_CCMR1 0x00000006U 00443 #define TIM_DMABASE_CCMR2 0x00000007U 00444 #define TIM_DMABASE_CCER 0x00000008U 00445 #define TIM_DMABASE_CNT 0x00000009U 00446 #define TIM_DMABASE_PSC 0x0000000AU 00447 #define TIM_DMABASE_ARR 0x0000000BU 00448 #define TIM_DMABASE_RCR 0x0000000CU 00449 #define TIM_DMABASE_CCR1 0x0000000DU 00450 #define TIM_DMABASE_CCR2 0x0000000EU 00451 #define TIM_DMABASE_CCR3 0x0000000FU 00452 #define TIM_DMABASE_CCR4 0x00000010U 00453 #define TIM_DMABASE_BDTR 0x00000011U 00454 #define TIM_DMABASE_DCR 0x00000012U 00455 #define TIM_DMABASE_DMAR 0x00000013U 00456 #define TIM_DMABASE_OR1 0x00000014U 00457 #define TIM_DMABASE_CCMR3 0x00000015U 00458 #define TIM_DMABASE_CCR5 0x00000016U 00459 #define TIM_DMABASE_CCR6 0x00000017U 00460 #define TIM_DMABASE_OR2 0x00000018U 00461 #define TIM_DMABASE_OR3 0x00000019U 00462 /** 00463 * @} 00464 */ 00465 00466 /** @defgroup TIM_Event_Source TIM Event Source 00467 * @{ 00468 */ 00469 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 00470 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 00471 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 00472 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 00473 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 00474 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 00475 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 00476 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 00477 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ 00478 /** 00479 * @} 00480 */ 00481 00482 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 00483 * @{ 00484 */ 00485 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 00486 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 00487 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 00488 /** 00489 * @} 00490 */ 00491 00492 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 00493 * @{ 00494 */ 00495 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 00496 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 00497 /** 00498 * @} 00499 */ 00500 00501 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 00502 * @{ 00503 */ 00504 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 00505 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 00506 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 00507 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 00508 /** 00509 * @} 00510 */ 00511 00512 /** @defgroup TIM_Counter_Mode TIM Counter Mode 00513 * @{ 00514 */ 00515 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 00516 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 00517 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 00518 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 00519 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 00520 /** 00521 * @} 00522 */ 00523 00524 /** @defgroup TIM_ClockDivision TIM Clock Division 00525 * @{ 00526 */ 00527 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 00528 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 00529 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 00530 /** 00531 * @} 00532 */ 00533 00534 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 00535 * @{ 00536 */ 00537 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 00538 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 00539 /** 00540 * @} 00541 */ 00542 00543 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 00544 * @{ 00545 */ 00546 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 00547 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 00548 00549 /** 00550 * @} 00551 */ 00552 00553 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 00554 * @{ 00555 */ 00556 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 00557 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 00558 /** 00559 * @} 00560 */ 00561 00562 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 00563 * @{ 00564 */ 00565 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 00566 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 00567 /** 00568 * @} 00569 */ 00570 00571 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 00572 * @{ 00573 */ 00574 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 00575 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 00576 /** 00577 * @} 00578 */ 00579 00580 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 00581 * @{ 00582 */ 00583 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 00584 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 00585 /** 00586 * @} 00587 */ 00588 00589 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 00590 * @{ 00591 */ 00592 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 00593 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 00594 /** 00595 * @} 00596 */ 00597 00598 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 00599 * @{ 00600 */ 00601 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 00602 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 00603 /** 00604 * @} 00605 */ 00606 00607 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 00608 * @{ 00609 */ 00610 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 00611 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 00612 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 00613 /** 00614 * @} 00615 */ 00616 00617 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 00618 * @{ 00619 */ 00620 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be 00621 connected to IC1, IC2, IC3 or IC4, respectively */ 00622 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be 00623 connected to IC2, IC1, IC4 or IC3, respectively */ 00624 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 00625 /** 00626 * @} 00627 */ 00628 00629 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 00630 * @{ 00631 */ 00632 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 00633 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 00634 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 00635 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 00636 /** 00637 * @} 00638 */ 00639 00640 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 00641 * @{ 00642 */ 00643 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 00644 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 00645 /** 00646 * @} 00647 */ 00648 00649 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 00650 * @{ 00651 */ 00652 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 00653 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 00654 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 00655 /** 00656 * @} 00657 */ 00658 00659 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 00660 * @{ 00661 */ 00662 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 00663 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 00664 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 00665 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 00666 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 00667 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 00668 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 00669 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 00670 /** 00671 * @} 00672 */ 00673 00674 /** @defgroup TIM_Commutation_Source TIM Commutation Source 00675 * @{ 00676 */ 00677 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 00678 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 00679 /** 00680 * @} 00681 */ 00682 00683 /** @defgroup TIM_DMA_sources TIM DMA Sources 00684 * @{ 00685 */ 00686 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 00687 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 00688 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 00689 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 00690 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 00691 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ 00692 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 00693 /** 00694 * @} 00695 */ 00696 00697 /** @defgroup TIM_Flag_definition TIM Flag Definition 00698 * @{ 00699 */ 00700 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 00701 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 00702 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 00703 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 00704 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 00705 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ 00706 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ 00707 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 00708 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 00709 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 00710 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ 00711 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ 00712 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 00713 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 00714 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 00715 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 00716 /** 00717 * @} 00718 */ 00719 00720 /** @defgroup TIM_Channel TIM Channel 00721 * @{ 00722 */ 00723 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 00724 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 00725 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 00726 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 00727 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ 00728 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ 00729 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 00730 /** 00731 * @} 00732 */ 00733 00734 /** @defgroup TIM_Clock_Source TIM Clock Source 00735 * @{ 00736 */ 00737 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 00738 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 00739 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 00740 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 00741 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 00742 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 00743 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 00744 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 00745 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 00746 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 00747 /** 00748 * @} 00749 */ 00750 00751 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 00752 * @{ 00753 */ 00754 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 00755 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 00756 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 00757 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 00758 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 00759 /** 00760 * @} 00761 */ 00762 00763 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 00764 * @{ 00765 */ 00766 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 00767 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 00768 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 00769 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 00770 /** 00771 * @} 00772 */ 00773 00774 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 00775 * @{ 00776 */ 00777 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 00778 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 00779 /** 00780 * @} 00781 */ 00782 00783 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 00784 * @{ 00785 */ 00786 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 00787 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 00788 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 00789 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 00790 /** 00791 * @} 00792 */ 00793 00794 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 00795 * @{ 00796 */ 00797 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 00798 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 00799 /** 00800 * @} 00801 */ 00802 00803 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 00804 * @{ 00805 */ 00806 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 00807 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 00808 /** 00809 * @} 00810 */ 00811 /** @defgroup TIM_Lock_level TIM Lock level 00812 * @{ 00813 */ 00814 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 00815 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 00816 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 00817 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 00818 /** 00819 * @} 00820 */ 00821 00822 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 00823 * @{ 00824 */ 00825 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 00826 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 00827 /** 00828 * @} 00829 */ 00830 00831 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 00832 * @{ 00833 */ 00834 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 00835 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 00836 /** 00837 * @} 00838 */ 00839 00840 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable 00841 * @{ 00842 */ 00843 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ 00844 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ 00845 /** 00846 * @} 00847 */ 00848 00849 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity 00850 * @{ 00851 */ 00852 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 00853 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 00854 /** 00855 * @} 00856 */ 00857 00858 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 00859 * @{ 00860 */ 00861 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 00862 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event 00863 (if none of the break inputs BRK and BRK2 is active) */ 00864 /** 00865 * @} 00866 */ 00867 00868 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 00869 * @{ 00870 */ 00871 #define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 00872 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ 00873 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ 00874 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ 00875 /** 00876 * @} 00877 */ 00878 00879 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 00880 * @{ 00881 */ 00882 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 00883 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 00884 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 00885 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 00886 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 00887 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 00888 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 00889 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 00890 /** 00891 * @} 00892 */ 00893 00894 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) 00895 * @{ 00896 */ 00897 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ 00898 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ 00899 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ 00900 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ 00901 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ 00902 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ 00903 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ 00904 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ 00905 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ 00906 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ 00907 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ 00908 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ 00909 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ 00910 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ 00911 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 00912 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 00913 /** 00914 * @} 00915 */ 00916 00917 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 00918 * @{ 00919 */ 00920 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 00921 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 00922 /** 00923 * @} 00924 */ 00925 00926 /** @defgroup TIM_Slave_Mode TIM Slave mode 00927 * @{ 00928 */ 00929 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 00930 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 00931 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 00932 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 00933 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 00934 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ 00935 /** 00936 * @} 00937 */ 00938 00939 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 00940 * @{ 00941 */ 00942 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 00943 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 00944 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 00945 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 00946 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 00947 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 00948 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 00949 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 00950 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ 00951 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ 00952 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ 00953 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ 00954 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ 00955 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ 00956 /** 00957 * @} 00958 */ 00959 00960 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 00961 * @{ 00962 */ 00963 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 00964 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 00965 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 00966 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 00967 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 00968 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 00969 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 00970 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 00971 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ 00972 /** 00973 * @} 00974 */ 00975 00976 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 00977 * @{ 00978 */ 00979 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 00980 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 00981 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 00982 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 00983 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 00984 /** 00985 * @} 00986 */ 00987 00988 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 00989 * @{ 00990 */ 00991 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 00992 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 00993 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 00994 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 00995 /** 00996 * @} 00997 */ 00998 00999 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 01000 * @{ 01001 */ 01002 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 01003 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 01004 /** 01005 * @} 01006 */ 01007 01008 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 01009 * @{ 01010 */ 01011 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01012 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01013 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01014 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01015 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01016 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01017 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01018 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01019 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01020 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01021 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01022 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01023 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01024 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01025 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01026 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01027 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01028 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 01029 /** 01030 * @} 01031 */ 01032 01033 /** @defgroup DMA_Handle_index TIM DMA Handle Index 01034 * @{ 01035 */ 01036 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 01037 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 01038 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 01039 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 01040 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 01041 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 01042 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 01043 /** 01044 * @} 01045 */ 01046 01047 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 01048 * @{ 01049 */ 01050 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 01051 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 01052 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 01053 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 01054 /** 01055 * @} 01056 */ 01057 01058 /** @defgroup TIM_Break_System TIM Break System 01059 * @{ 01060 */ 01061 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ 01062 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ 01063 #define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */ 01064 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ 01065 /** 01066 * @} 01067 */ 01068 01069 /** 01070 * @} 01071 */ 01072 /* End of exported constants -------------------------------------------------*/ 01073 01074 /* Exported macros -----------------------------------------------------------*/ 01075 /** @defgroup TIM_Exported_Macros TIM Exported Macros 01076 * @{ 01077 */ 01078 01079 /** @brief Reset TIM handle state. 01080 * @param __HANDLE__ TIM handle. 01081 * @retval None 01082 */ 01083 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 01084 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 01085 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 01086 (__HANDLE__)->Base_MspInitCallback = NULL; \ 01087 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 01088 (__HANDLE__)->IC_MspInitCallback = NULL; \ 01089 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 01090 (__HANDLE__)->OC_MspInitCallback = NULL; \ 01091 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 01092 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 01093 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 01094 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 01095 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 01096 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 01097 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 01098 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ 01099 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ 01100 } while(0) 01101 #else 01102 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) 01103 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 01104 01105 /** 01106 * @brief Enable the TIM peripheral. 01107 * @param __HANDLE__ TIM handle 01108 * @retval None 01109 */ 01110 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 01111 01112 /** 01113 * @brief Enable the TIM main Output. 01114 * @param __HANDLE__ TIM handle 01115 * @retval None 01116 */ 01117 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 01118 01119 /** 01120 * @brief Disable the TIM peripheral. 01121 * @param __HANDLE__ TIM handle 01122 * @retval None 01123 */ 01124 #define __HAL_TIM_DISABLE(__HANDLE__) \ 01125 do { \ 01126 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 01127 { \ 01128 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 01129 { \ 01130 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 01131 } \ 01132 } \ 01133 } while(0) 01134 01135 /** 01136 * @brief Disable the TIM main Output. 01137 * @param __HANDLE__ TIM handle 01138 * @retval None 01139 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled 01140 */ 01141 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 01142 do { \ 01143 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 01144 { \ 01145 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 01146 { \ 01147 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 01148 } \ 01149 } \ 01150 } while(0) 01151 01152 /** 01153 * @brief Disable the TIM main Output. 01154 * @param __HANDLE__ TIM handle 01155 * @retval None 01156 * @note The Main Output Enable of a timer instance is disabled unconditionally 01157 */ 01158 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 01159 01160 /** @brief Enable the specified TIM interrupt. 01161 * @param __HANDLE__ specifies the TIM Handle. 01162 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 01163 * This parameter can be one of the following values: 01164 * @arg TIM_IT_UPDATE: Update interrupt 01165 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 01166 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 01167 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 01168 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 01169 * @arg TIM_IT_COM: Commutation interrupt 01170 * @arg TIM_IT_TRIGGER: Trigger interrupt 01171 * @arg TIM_IT_BREAK: Break interrupt 01172 * @retval None 01173 */ 01174 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 01175 01176 /** @brief Disable the specified TIM interrupt. 01177 * @param __HANDLE__ specifies the TIM Handle. 01178 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 01179 * This parameter can be one of the following values: 01180 * @arg TIM_IT_UPDATE: Update interrupt 01181 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 01182 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 01183 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 01184 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 01185 * @arg TIM_IT_COM: Commutation interrupt 01186 * @arg TIM_IT_TRIGGER: Trigger interrupt 01187 * @arg TIM_IT_BREAK: Break interrupt 01188 * @retval None 01189 */ 01190 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 01191 01192 /** @brief Enable the specified DMA request. 01193 * @param __HANDLE__ specifies the TIM Handle. 01194 * @param __DMA__ specifies the TIM DMA request to enable. 01195 * This parameter can be one of the following values: 01196 * @arg TIM_DMA_UPDATE: Update DMA request 01197 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 01198 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 01199 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 01200 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 01201 * @arg TIM_DMA_COM: Commutation DMA request 01202 * @arg TIM_DMA_TRIGGER: Trigger DMA request 01203 * @retval None 01204 */ 01205 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 01206 01207 /** @brief Disable the specified DMA request. 01208 * @param __HANDLE__ specifies the TIM Handle. 01209 * @param __DMA__ specifies the TIM DMA request to disable. 01210 * This parameter can be one of the following values: 01211 * @arg TIM_DMA_UPDATE: Update DMA request 01212 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 01213 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 01214 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 01215 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 01216 * @arg TIM_DMA_COM: Commutation DMA request 01217 * @arg TIM_DMA_TRIGGER: Trigger DMA request 01218 * @retval None 01219 */ 01220 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 01221 01222 /** @brief Check whether the specified TIM interrupt flag is set or not. 01223 * @param __HANDLE__ specifies the TIM Handle. 01224 * @param __FLAG__ specifies the TIM interrupt flag to check. 01225 * This parameter can be one of the following values: 01226 * @arg TIM_FLAG_UPDATE: Update interrupt flag 01227 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 01228 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 01229 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 01230 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 01231 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 01232 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 01233 * @arg TIM_FLAG_COM: Commutation interrupt flag 01234 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 01235 * @arg TIM_FLAG_BREAK: Break interrupt flag 01236 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 01237 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 01238 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 01239 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 01240 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 01241 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 01242 * @retval The new state of __FLAG__ (TRUE or FALSE). 01243 */ 01244 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 01245 01246 /** @brief Clear the specified TIM interrupt flag. 01247 * @param __HANDLE__ specifies the TIM Handle. 01248 * @param __FLAG__ specifies the TIM interrupt flag to clear. 01249 * This parameter can be one of the following values: 01250 * @arg TIM_FLAG_UPDATE: Update interrupt flag 01251 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 01252 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 01253 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 01254 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 01255 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 01256 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 01257 * @arg TIM_FLAG_COM: Commutation interrupt flag 01258 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 01259 * @arg TIM_FLAG_BREAK: Break interrupt flag 01260 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 01261 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 01262 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 01263 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 01264 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 01265 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 01266 * @retval The new state of __FLAG__ (TRUE or FALSE). 01267 */ 01268 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 01269 01270 /** 01271 * @brief Check whether the specified TIM interrupt source is enabled or not. 01272 * @param __HANDLE__ TIM handle 01273 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 01274 * This parameter can be one of the following values: 01275 * @arg TIM_IT_UPDATE: Update interrupt 01276 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 01277 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 01278 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 01279 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 01280 * @arg TIM_IT_COM: Commutation interrupt 01281 * @arg TIM_IT_TRIGGER: Trigger interrupt 01282 * @arg TIM_IT_BREAK: Break interrupt 01283 * @retval The state of TIM_IT (SET or RESET). 01284 */ 01285 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 01286 01287 /** @brief Clear the TIM interrupt pending bits. 01288 * @param __HANDLE__ TIM handle 01289 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 01290 * This parameter can be one of the following values: 01291 * @arg TIM_IT_UPDATE: Update interrupt 01292 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 01293 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 01294 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 01295 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 01296 * @arg TIM_IT_COM: Commutation interrupt 01297 * @arg TIM_IT_TRIGGER: Trigger interrupt 01298 * @arg TIM_IT_BREAK: Break interrupt 01299 * @retval None 01300 */ 01301 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 01302 01303 /** 01304 * @brief Indicates whether or not the TIM Counter is used as downcounter. 01305 * @param __HANDLE__ TIM handle. 01306 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 01307 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder 01308 mode. 01309 */ 01310 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 01311 01312 /** 01313 * @brief Set the TIM Prescaler on runtime. 01314 * @param __HANDLE__ TIM handle. 01315 * @param __PRESC__ specifies the Prescaler new value. 01316 * @retval None 01317 */ 01318 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 01319 01320 /** 01321 * @brief Set the TIM Counter Register value on runtime. 01322 * @param __HANDLE__ TIM handle. 01323 * @param __COUNTER__ specifies the Counter register new value. 01324 * @retval None 01325 */ 01326 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 01327 01328 /** 01329 * @brief Get the TIM Counter Register value on runtime. 01330 * @param __HANDLE__ TIM handle. 01331 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 01332 */ 01333 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \ 01334 ((__HANDLE__)->Instance->CNT) 01335 01336 /** 01337 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 01338 * @param __HANDLE__ TIM handle. 01339 * @param __AUTORELOAD__ specifies the Counter register new value. 01340 * @retval None 01341 */ 01342 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 01343 do{ \ 01344 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 01345 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 01346 } while(0) 01347 01348 /** 01349 * @brief Get the TIM Autoreload Register value on runtime. 01350 * @param __HANDLE__ TIM handle. 01351 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 01352 */ 01353 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ 01354 ((__HANDLE__)->Instance->ARR) 01355 01356 /** 01357 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 01358 * @param __HANDLE__ TIM handle. 01359 * @param __CKD__ specifies the clock division value. 01360 * This parameter can be one of the following value: 01361 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 01362 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 01363 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 01364 * @retval None 01365 */ 01366 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 01367 do{ \ 01368 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 01369 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 01370 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 01371 } while(0) 01372 01373 /** 01374 * @brief Get the TIM Clock Division value on runtime. 01375 * @param __HANDLE__ TIM handle. 01376 * @retval The clock division can be one of the following values: 01377 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 01378 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 01379 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 01380 */ 01381 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ 01382 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 01383 01384 /** 01385 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. 01386 * @param __HANDLE__ TIM handle. 01387 * @param __CHANNEL__ TIM Channels to be configured. 01388 * This parameter can be one of the following values: 01389 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01390 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01391 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01392 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01393 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 01394 * This parameter can be one of the following values: 01395 * @arg TIM_ICPSC_DIV1: no prescaler 01396 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 01397 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 01398 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 01399 * @retval None 01400 */ 01401 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 01402 do{ \ 01403 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 01404 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 01405 } while(0) 01406 01407 /** 01408 * @brief Get the TIM Input Capture prescaler on runtime. 01409 * @param __HANDLE__ TIM handle. 01410 * @param __CHANNEL__ TIM Channels to be configured. 01411 * This parameter can be one of the following values: 01412 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 01413 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 01414 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 01415 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 01416 * @retval The input capture prescaler can be one of the following values: 01417 * @arg TIM_ICPSC_DIV1: no prescaler 01418 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 01419 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 01420 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 01421 */ 01422 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 01423 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 01424 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 01425 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 01426 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 01427 01428 /** 01429 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 01430 * @param __HANDLE__ TIM handle. 01431 * @param __CHANNEL__ TIM Channels to be configured. 01432 * This parameter can be one of the following values: 01433 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01434 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01435 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01436 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01437 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 01438 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 01439 * @param __COMPARE__ specifies the Capture Compare register new value. 01440 * @retval None 01441 */ 01442 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 01443 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 01444 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 01445 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 01446 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ 01447 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ 01448 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) 01449 01450 /** 01451 * @brief Get the TIM Capture Compare Register value on runtime. 01452 * @param __HANDLE__ TIM handle. 01453 * @param __CHANNEL__ TIM Channel associated with the capture compare register 01454 * This parameter can be one of the following values: 01455 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 01456 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 01457 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 01458 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 01459 * @arg TIM_CHANNEL_5: get capture/compare 5 register value 01460 * @arg TIM_CHANNEL_6: get capture/compare 6 register value 01461 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 01462 */ 01463 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 01464 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 01465 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 01466 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 01467 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ 01468 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ 01469 ((__HANDLE__)->Instance->CCR6)) 01470 01471 /** 01472 * @brief Set the TIM Output compare preload. 01473 * @param __HANDLE__ TIM handle. 01474 * @param __CHANNEL__ TIM Channels to be configured. 01475 * This parameter can be one of the following values: 01476 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01477 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01478 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01479 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01480 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 01481 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 01482 * @retval None 01483 */ 01484 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 01485 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 01486 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 01487 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 01488 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ 01489 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ 01490 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) 01491 01492 /** 01493 * @brief Reset the TIM Output compare preload. 01494 * @param __HANDLE__ TIM handle. 01495 * @param __CHANNEL__ TIM Channels to be configured. 01496 * This parameter can be one of the following values: 01497 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01498 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01499 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01500 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01501 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 01502 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 01503 * @retval None 01504 */ 01505 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 01506 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ 01507 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ 01508 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ 01509 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ 01510 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ 01511 ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) 01512 01513 /** 01514 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 01515 * @param __HANDLE__ TIM handle. 01516 * @note When the URS bit of the TIMx_CR1 register is set, only counter 01517 * overflow/underflow generates an update interrupt or DMA request (if 01518 * enabled) 01519 * @retval None 01520 */ 01521 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \ 01522 ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 01523 01524 /** 01525 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 01526 * @param __HANDLE__ TIM handle. 01527 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 01528 * following events generate an update interrupt or DMA request (if 01529 * enabled): 01530 * _ Counter overflow underflow 01531 * _ Setting the UG bit 01532 * _ Update generation through the slave mode controller 01533 * @retval None 01534 */ 01535 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ 01536 ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 01537 01538 /** 01539 * @brief Set the TIM Capture x input polarity on runtime. 01540 * @param __HANDLE__ TIM handle. 01541 * @param __CHANNEL__ TIM Channels to be configured. 01542 * This parameter can be one of the following values: 01543 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01544 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01545 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01546 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01547 * @param __POLARITY__ Polarity for TIx source 01548 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 01549 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 01550 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 01551 * @retval None 01552 */ 01553 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 01554 do{ \ 01555 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 01556 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 01557 }while(0) 01558 01559 /** 01560 * @} 01561 */ 01562 /* End of exported macros ----------------------------------------------------*/ 01563 01564 /* Private constants ---------------------------------------------------------*/ 01565 /** @defgroup TIM_Private_Constants TIM Private Constants 01566 * @{ 01567 */ 01568 /* The counter of a timer instance is disabled only if all the CCx and CCxN 01569 channels have been disabled */ 01570 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 01571 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) 01572 /** 01573 * @} 01574 */ 01575 /* End of private constants --------------------------------------------------*/ 01576 01577 /* Private macros ------------------------------------------------------------*/ 01578 /** @defgroup TIM_Private_Macros TIM Private Macros 01579 * @{ 01580 */ 01581 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ 01582 ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ 01583 ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) 01584 01585 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 01586 ((__BASE__) == TIM_DMABASE_CR2) || \ 01587 ((__BASE__) == TIM_DMABASE_SMCR) || \ 01588 ((__BASE__) == TIM_DMABASE_DIER) || \ 01589 ((__BASE__) == TIM_DMABASE_SR) || \ 01590 ((__BASE__) == TIM_DMABASE_EGR) || \ 01591 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 01592 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 01593 ((__BASE__) == TIM_DMABASE_CCER) || \ 01594 ((__BASE__) == TIM_DMABASE_CNT) || \ 01595 ((__BASE__) == TIM_DMABASE_PSC) || \ 01596 ((__BASE__) == TIM_DMABASE_ARR) || \ 01597 ((__BASE__) == TIM_DMABASE_RCR) || \ 01598 ((__BASE__) == TIM_DMABASE_CCR1) || \ 01599 ((__BASE__) == TIM_DMABASE_CCR2) || \ 01600 ((__BASE__) == TIM_DMABASE_CCR3) || \ 01601 ((__BASE__) == TIM_DMABASE_CCR4) || \ 01602 ((__BASE__) == TIM_DMABASE_BDTR) || \ 01603 ((__BASE__) == TIM_DMABASE_CCMR3) || \ 01604 ((__BASE__) == TIM_DMABASE_CCR5) || \ 01605 ((__BASE__) == TIM_DMABASE_CCR6) || \ 01606 ((__BASE__) == TIM_DMABASE_OR1) || \ 01607 ((__BASE__) == TIM_DMABASE_OR2) || \ 01608 ((__BASE__) == TIM_DMABASE_OR3)) 01609 01610 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 01611 01612 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 01613 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 01614 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 01615 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 01616 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 01617 01618 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 01619 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 01620 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 01621 01622 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 01623 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 01624 01625 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 01626 ((__STATE__) == TIM_OCFAST_ENABLE)) 01627 01628 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 01629 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 01630 01631 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 01632 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 01633 01634 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 01635 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 01636 01637 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 01638 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 01639 01640 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 01641 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 01642 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 01643 01644 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 01645 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 01646 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 01647 01648 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 01649 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 01650 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 01651 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 01652 01653 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 01654 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 01655 01656 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 01657 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 01658 ((__MODE__) == TIM_ENCODERMODE_TI12)) 01659 01660 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 01661 01662 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 01663 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 01664 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 01665 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 01666 ((__CHANNEL__) == TIM_CHANNEL_5) || \ 01667 ((__CHANNEL__) == TIM_CHANNEL_6) || \ 01668 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 01669 01670 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 01671 ((__CHANNEL__) == TIM_CHANNEL_2)) 01672 01673 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 01674 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 01675 ((__CHANNEL__) == TIM_CHANNEL_3)) 01676 01677 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 01678 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 01679 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 01680 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 01681 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 01682 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 01683 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 01684 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 01685 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 01686 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) 01687 01688 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 01689 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 01690 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 01691 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 01692 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 01693 01694 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 01695 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 01696 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 01697 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 01698 01699 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 01700 01701 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 01702 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 01703 01704 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 01705 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 01706 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 01707 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 01708 01709 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 01710 01711 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 01712 ((__STATE__) == TIM_OSSR_DISABLE)) 01713 01714 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 01715 ((__STATE__) == TIM_OSSI_DISABLE)) 01716 01717 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 01718 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 01719 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 01720 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 01721 01722 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 01723 01724 01725 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 01726 ((__STATE__) == TIM_BREAK_DISABLE)) 01727 01728 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 01729 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 01730 01731 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ 01732 ((__STATE__) == TIM_BREAK2_DISABLE)) 01733 01734 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ 01735 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) 01736 01737 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 01738 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 01739 01740 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) 01741 01742 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 01743 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 01744 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 01745 ((__SOURCE__) == TIM_TRGO_OC1) || \ 01746 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 01747 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 01748 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 01749 ((__SOURCE__) == TIM_TRGO_OC4REF)) 01750 01751 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ 01752 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ 01753 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ 01754 ((__SOURCE__) == TIM_TRGO2_OC1) || \ 01755 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ 01756 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ 01757 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 01758 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 01759 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ 01760 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ 01761 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ 01762 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ 01763 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ 01764 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ 01765 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ 01766 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ 01767 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) 01768 01769 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 01770 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 01771 01772 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 01773 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 01774 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 01775 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 01776 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ 01777 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 01778 01779 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 01780 ((__MODE__) == TIM_OCMODE_PWM2) || \ 01781 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ 01782 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ 01783 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ 01784 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) 01785 01786 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 01787 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 01788 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 01789 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 01790 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 01791 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ 01792 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ 01793 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) 01794 01795 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 01796 ((__SELECTION__) == TIM_TS_ITR1) || \ 01797 ((__SELECTION__) == TIM_TS_ITR2) || \ 01798 ((__SELECTION__) == TIM_TS_ITR3) || \ 01799 ((__SELECTION__) == TIM_TS_TI1F_ED) || \ 01800 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 01801 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 01802 ((__SELECTION__) == TIM_TS_ETRF)) 01803 01804 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 01805 ((__SELECTION__) == TIM_TS_ITR1) || \ 01806 ((__SELECTION__) == TIM_TS_ITR2) || \ 01807 ((__SELECTION__) == TIM_TS_ITR3) || \ 01808 ((__SELECTION__) == TIM_TS_NONE)) 01809 01810 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 01811 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 01812 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 01813 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 01814 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 01815 01816 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 01817 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 01818 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 01819 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 01820 01821 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 01822 01823 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 01824 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 01825 01826 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 01827 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 01828 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 01829 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 01830 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 01831 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 01832 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 01833 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 01834 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 01835 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 01836 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 01837 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 01838 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 01839 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 01840 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 01841 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 01842 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 01843 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) 01844 01845 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 01846 01847 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 01848 01849 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ 01850 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ 01851 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \ 01852 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) 01853 01854 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__HANDLE__) ((((READ_REG((__HANDLE__)->Instance->SMCR)&TIM_SMCR_SMS) == TIM_SLAVEMODE_TRIGGER) || \ 01855 ((READ_REG((__HANDLE__)->Instance->SMCR)&TIM_SMCR_SMS) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) ? 1UL : 0UL) 01856 01857 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 01858 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 01859 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 01860 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 01861 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 01862 01863 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 01864 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ 01865 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ 01866 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ 01867 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) 01868 01869 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 01870 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 01871 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 01872 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 01873 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 01874 01875 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 01876 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 01877 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 01878 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 01879 ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 01880 01881 /** 01882 * @} 01883 */ 01884 /* End of private macros -----------------------------------------------------*/ 01885 01886 /* Include TIM HAL Extended module */ 01887 #include "stm32l4xx_hal_tim_ex.h" 01888 01889 /* Exported functions --------------------------------------------------------*/ 01890 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 01891 * @{ 01892 */ 01893 01894 /** @addtogroup TIM_Exported_Functions_Group1 Time Base functions 01895 * @brief Time Base functions 01896 * @{ 01897 */ 01898 /* Time Base functions ********************************************************/ 01899 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 01900 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 01901 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 01902 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 01903 /* Blocking mode: Polling */ 01904 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 01905 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 01906 /* Non-Blocking mode: Interrupt */ 01907 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 01908 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 01909 /* Non-Blocking mode: DMA */ 01910 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 01911 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 01912 /** 01913 * @} 01914 */ 01915 01916 /** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions 01917 * @brief Time Output Compare functions 01918 * @{ 01919 */ 01920 /* Timer Output Compare functions *********************************************/ 01921 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 01922 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 01923 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 01924 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 01925 /* Blocking mode: Polling */ 01926 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 01927 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 01928 /* Non-Blocking mode: Interrupt */ 01929 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01930 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01931 /* Non-Blocking mode: DMA */ 01932 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 01933 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 01934 /** 01935 * @} 01936 */ 01937 01938 /** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions 01939 * @brief Time PWM functions 01940 * @{ 01941 */ 01942 /* Timer PWM functions ********************************************************/ 01943 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 01944 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 01945 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 01946 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 01947 /* Blocking mode: Polling */ 01948 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 01949 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 01950 /* Non-Blocking mode: Interrupt */ 01951 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01952 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01953 /* Non-Blocking mode: DMA */ 01954 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 01955 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 01956 /** 01957 * @} 01958 */ 01959 01960 /** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions 01961 * @brief Time Input Capture functions 01962 * @{ 01963 */ 01964 /* Timer Input Capture functions **********************************************/ 01965 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 01966 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 01967 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 01968 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 01969 /* Blocking mode: Polling */ 01970 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 01971 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 01972 /* Non-Blocking mode: Interrupt */ 01973 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01974 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01975 /* Non-Blocking mode: DMA */ 01976 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 01977 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 01978 /** 01979 * @} 01980 */ 01981 01982 /** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions 01983 * @brief Time One Pulse functions 01984 * @{ 01985 */ 01986 /* Timer One Pulse functions **************************************************/ 01987 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 01988 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 01989 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 01990 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 01991 /* Blocking mode: Polling */ 01992 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 01993 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 01994 /* Non-Blocking mode: Interrupt */ 01995 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 01996 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 01997 /** 01998 * @} 01999 */ 02000 02001 /** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions 02002 * @brief Time Encoder functions 02003 * @{ 02004 */ 02005 /* Timer Encoder functions ****************************************************/ 02006 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); 02007 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 02008 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 02009 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 02010 /* Blocking mode: Polling */ 02011 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 02012 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 02013 /* Non-Blocking mode: Interrupt */ 02014 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 02015 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 02016 /* Non-Blocking mode: DMA */ 02017 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); 02018 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 02019 /** 02020 * @} 02021 */ 02022 02023 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 02024 * @brief IRQ handler management 02025 * @{ 02026 */ 02027 /* Interrupt Handler functions ***********************************************/ 02028 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 02029 /** 02030 * @} 02031 */ 02032 02033 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions 02034 * @brief Peripheral Control functions 02035 * @{ 02036 */ 02037 /* Control functions *********************************************************/ 02038 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 02039 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 02040 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); 02041 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); 02042 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); 02043 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); 02044 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 02045 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 02046 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 02047 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ 02048 uint32_t *BurstBuffer, uint32_t BurstLength); 02049 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 02050 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ 02051 uint32_t *BurstBuffer, uint32_t BurstLength); 02052 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 02053 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 02054 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 02055 /** 02056 * @} 02057 */ 02058 02059 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 02060 * @brief TIM Callbacks functions 02061 * @{ 02062 */ 02063 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 02064 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 02065 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 02066 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 02067 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 02068 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 02069 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 02070 02071 /* Callbacks Register/UnRegister functions ***********************************/ 02072 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 02073 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback); 02074 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 02075 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 02076 02077 /** 02078 * @} 02079 */ 02080 02081 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions 02082 * @brief Peripheral State functions 02083 * @{ 02084 */ 02085 /* Peripheral State functions ************************************************/ 02086 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); 02087 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); 02088 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); 02089 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); 02090 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); 02091 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); 02092 /** 02093 * @} 02094 */ 02095 02096 /** 02097 * @} 02098 */ 02099 /* End of exported functions -------------------------------------------------*/ 02100 02101 /* Private functions----------------------------------------------------------*/ 02102 /** @defgroup TIM_Private_Functions TIM Private Functions 02103 * @{ 02104 */ 02105 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); 02106 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 02107 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 02108 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 02109 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 02110 02111 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); 02112 void TIM_DMAError(DMA_HandleTypeDef *hdma); 02113 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 02114 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 02115 02116 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 02117 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 02118 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 02119 02120 /** 02121 * @} 02122 */ 02123 /* End of private functions --------------------------------------------------*/ 02124 02125 /** 02126 * @} 02127 */ 02128 02129 /** 02130 * @} 02131 */ 02132 02133 #ifdef __cplusplus 02134 } 02135 #endif 02136 02137 #endif /* STM32L4xx_HAL_TIM_H */ 02138 02139 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1