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STM32L486xx HAL User Manual
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Header file of TIM HAL Extended module. More...
#include "stm32l4xx_hal_def.h"Go to the source code of this file.
Data Structures | |
| struct | TIM_HallSensor_InitTypeDef |
| TIM Hall sensor Configuration Structure definition. More... | |
| struct | TIMEx_BreakInputConfigTypeDef |
| TIM Break/Break2 input configuration. More... | |
Defines | |
| #define | TIM_TIM1_ETR_ADC1_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ |
| #define | TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR1_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */ |
| #define | TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR1_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */ |
| #define | TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ |
| #define | TIM_TIM1_ETR_ADC3_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ |
| #define | TIM_TIM1_ETR_ADC3_AWD1 TIM1_OR1_ETR_ADC3_RMP_0 /* !< TIM1_ETR is connected to ADC3 AWD1 */ |
| #define | TIM_TIM1_ETR_ADC3_AWD2 TIM1_OR1_ETR_ADC3_RMP_1 /* !< TIM1_ETR is connected to ADC3 AWD2 */ |
| #define | TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */ |
| #define | TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 TI1 is connected to GPIO */ |
| #define | TIM_TIM1_TI1_COMP1 TIM1_OR1_TI1_RMP /* !< TIM1 TI1 is connected to COMP1 */ |
| #define | TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */ |
| #define | TIM_TIM1_ETR_COMP1 TIM1_OR2_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */ |
| #define | TIM_TIM1_ETR_COMP2 TIM1_OR2_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */ |
| #define | TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */ |
| #define | TIM_TIM2_ITR1_OTG_FS_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to OTG_FS SOF */ |
| #define | TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */ |
| #define | TIM_TIM2_ETR_LSE TIM2_OR1_ETR1_RMP /* !< TIM2_ETR is connected to LSE */ |
| #define | TIM_TIM2_ETR_COMP1 TIM2_OR2_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */ |
| #define | TIM_TIM2_ETR_COMP2 TIM2_OR2_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */ |
| #define | TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2 TI4 is connected to GPIO */ |
| #define | TIM_TIM2_TI4_COMP1 TIM2_OR1_TI4_RMP_0 /* !< TIM2 TI4 is connected to COMP1 output */ |
| #define | TIM_TIM2_TI4_COMP2 TIM2_OR1_TI4_RMP_1 /* !< TIM2 TI4 is connected to COMP2 output */ |
| #define | TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */ |
| #define | TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3 TI1 is connected to GPIO */ |
| #define | TIM_TIM3_TI1_COMP1 TIM3_OR1_TI1_RMP_0 /* !< TIM3 TI1 is connected to COMP1 output */ |
| #define | TIM_TIM3_TI1_COMP2 TIM3_OR1_TI1_RMP_1 /* !< TIM3 TI1 is connected to COMP2 output */ |
| #define | TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */ |
| #define | TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */ |
| #define | TIM_TIM3_ETR_COMP1 TIM3_OR2_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 output */ |
| #define | TIM_TIM8_ETR_ADC2_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ |
| #define | TIM_TIM8_ETR_ADC2_AWD1 TIM8_OR1_ETR_ADC2_RMP_0 /* !< TIM8_ETR is connected to ADC2 AWD1 */ |
| #define | TIM_TIM8_ETR_ADC2_AWD2 TIM8_OR1_ETR_ADC2_RMP_1 /* !< TIM8_ETR is connected to ADC2 AWD2 */ |
| #define | TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */ |
| #define | TIM_TIM8_ETR_ADC3_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ |
| #define | TIM_TIM8_ETR_ADC3_AWD1 TIM8_OR1_ETR_ADC3_RMP_0 /* !< TIM8_ETR is connected to ADC3 AWD1 */ |
| #define | TIM_TIM8_ETR_ADC3_AWD2 TIM8_OR1_ETR_ADC3_RMP_1 /* !< TIM8_ETR is connected to ADC3 AWD2 */ |
| #define | TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */ |
| #define | TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8 TI1 is connected to GPIO */ |
| #define | TIM_TIM8_TI1_COMP2 TIM8_OR1_TI1_RMP /* !< TIM8 TI1 is connected to COMP1 */ |
| #define | TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */ |
| #define | TIM_TIM8_ETR_COMP1 TIM8_OR2_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 output */ |
| #define | TIM_TIM8_ETR_COMP2 TIM8_OR2_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 output */ |
| #define | TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15 TI1 is connected to GPIO */ |
| #define | TIM_TIM15_TI1_LSE TIM15_OR1_TI1_RMP /* !< TIM15 TI1 is connected to LSE */ |
| #define | TIM_TIM15_ENCODERMODE_NONE 0x00000000U /* !< No redirection */ |
| #define | TIM_TIM15_ENCODERMODE_TIM2 TIM15_OR1_ENCODER_MODE_0 /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ |
| #define | TIM_TIM15_ENCODERMODE_TIM3 TIM15_OR1_ENCODER_MODE_1 /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ |
| #define | TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ |
| #define | TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */ |
| #define | TIM_TIM16_TI1_LSI TIM16_OR1_TI1_RMP_0 /* !< TIM16 TI1 is connected to LSI */ |
| #define | TIM_TIM16_TI1_LSE TIM16_OR1_TI1_RMP_1 /* !< TIM16 TI1 is connected to LSE */ |
| #define | TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */ |
| #define | TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */ |
| #define | TIM_TIM17_TI1_MSI TIM17_OR1_TI1_RMP_0 /* !< TIM17 TI1 is connected to MSI */ |
| #define | TIM_TIM17_TI1_HSE_32 TIM17_OR1_TI1_RMP_1 /* !< TIM17 TI1 is connected to HSE div 32 */ |
| #define | TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */ |
| #define | TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */ |
| #define | TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */ |
| #define | TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */ |
| #define | TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */ |
| #define | TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */ |
| #define | TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ |
| #define | TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */ |
| #define | TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */ |
| #define | TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */ |
| #define | TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */ |
| #define | IS_TIM_REMAP(__REMAP__) (((__REMAP__) <= (uint32_t)0x0001C01F)) |
| #define | IS_TIM_BREAKINPUT(__BREAKINPUT__) |
| #define | IS_TIM_BREAKINPUTSOURCE(__SOURCE__) |
| #define | IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) |
| #define | IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) |
Functions | |
| HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) |
| Initializes the TIM Hall Sensor Interface and initialize the associated handle. | |
| HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim) |
| DeInitializes the TIM Hall Sensor interface. | |
| __weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim) |
| Initializes the TIM Hall Sensor MSP. | |
| __weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim) |
| DeInitializes TIM Hall Sensor MSP. | |
| HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim) |
| Starts the TIM Hall Sensor Interface. | |
| HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim) |
| Stops the TIM Hall sensor Interface. | |
| HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim) |
| Starts the TIM Hall Sensor Interface in interrupt mode. | |
| HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim) |
| Stops the TIM Hall Sensor Interface in interrupt mode. | |
| HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) |
| Starts the TIM Hall Sensor Interface in DMA mode. | |
| HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim) |
| Stops the TIM Hall Sensor Interface in DMA mode. | |
| HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel) |
| Starts the TIM Output Compare signal generation on the complementary output. | |
| HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel) |
| Stops the TIM Output Compare signal generation on the complementary output. | |
| HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) |
| Starts the TIM Output Compare signal generation in interrupt mode on the complementary output. | |
| HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) |
| Stops the TIM Output Compare signal generation in interrupt mode on the complementary output. | |
| HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) |
| Starts the TIM Output Compare signal generation in DMA mode on the complementary output. | |
| HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel) |
| Stops the TIM Output Compare signal generation in DMA mode on the complementary output. | |
| HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel) |
| Starts the PWM signal generation on the complementary output. | |
| HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel) |
| Stops the PWM signal generation on the complementary output. | |
| HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) |
| Starts the PWM signal generation in interrupt mode on the complementary output. | |
| HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) |
| Stops the PWM signal generation in interrupt mode on the complementary output. | |
| HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) |
| Starts the TIM PWM signal generation in DMA mode on the complementary output. | |
| HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel) |
| Stops the TIM PWM signal generation in DMA mode on the complementary output. | |
| HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| Starts the TIM One Pulse signal generation on the complementary output. | |
| HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| Stops the TIM One Pulse signal generation on the complementary output. | |
| HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel. | |
| HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel. | |
| HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) |
| Configure the TIM commutation event sequence. | |
| HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) |
| Configure the TIM commutation event sequence with interrupt. | |
| HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) |
| Configure the TIM commutation event sequence with DMA. | |
| HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) |
| Configures the TIM in master mode. | |
| HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) |
| Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable). | |
| HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakInput (TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) |
| Configures the break input source. | |
| HAL_StatusTypeDef | HAL_TIMEx_GroupChannel5 (TIM_HandleTypeDef *htim, uint32_t Channels) |
| Group channel 5 and channel 1, 2 or 3. | |
| HAL_StatusTypeDef | HAL_TIMEx_RemapConfig (TIM_HandleTypeDef *htim, uint32_t Remap) |
| Configures the TIMx Remapping input capabilities. | |
| __weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim) |
| Hall commutation changed callback in non-blocking mode. | |
| __weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim) |
| Hall Break detection callback in non-blocking mode. | |
| __weak void | HAL_TIMEx_Break2Callback (TIM_HandleTypeDef *htim) |
| Hall Break2 detection callback in non blocking mode. | |
| HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim) |
| Return the TIM Hall Sensor interface handle state. | |
| void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma) |
| TIM DMA Commutation callback. | |
Header file of TIM HAL Extended module.
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Definition in file stm32l4xx_hal_tim_ex.h.
1.7.6.1