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STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_rcc_ex.h 00004 * @author MCD Application Team 00005 * @brief Header file of RCC HAL Extension module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32F4xx_HAL_RCC_EX_H 00038 #define __STM32F4xx_HAL_RCC_EX_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32f4xx_hal_def.h" 00046 00047 /** @addtogroup STM32F4xx_HAL_Driver 00048 * @{ 00049 */ 00050 00051 /** @addtogroup RCCEx 00052 * @{ 00053 */ 00054 00055 /* Exported types ------------------------------------------------------------*/ 00056 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 00057 * @{ 00058 */ 00059 00060 /** 00061 * @brief RCC PLL configuration structure definition 00062 */ 00063 typedef struct 00064 { 00065 uint32_t PLLState; /*!< The new state of the PLL. 00066 This parameter can be a value of @ref RCC_PLL_Config */ 00067 00068 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 00069 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 00070 00071 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 00072 This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ 00073 00074 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 00075 This parameter must be a number between Min_Data = 50 and Max_Data = 432 00076 except for STM32F411xE devices where the Min_Data = 192 */ 00077 00078 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). 00079 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 00080 00081 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks. 00082 This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ 00083 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 00084 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 00085 defined(STM32F413xx) || defined(STM32F423xx) 00086 uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. 00087 This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx 00088 and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. 00089 This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ 00090 #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 00091 }RCC_PLLInitTypeDef; 00092 00093 #if defined(STM32F446xx) 00094 /** 00095 * @brief PLLI2S Clock structure definition 00096 */ 00097 typedef struct 00098 { 00099 uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. 00100 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ 00101 00102 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 00103 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ 00104 00105 uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock. 00106 This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */ 00107 00108 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. 00109 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 00110 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 00111 00112 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 00113 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 00114 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 00115 }RCC_PLLI2SInitTypeDef; 00116 00117 /** 00118 * @brief PLLSAI Clock structure definition 00119 */ 00120 typedef struct 00121 { 00122 uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock. 00123 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ 00124 00125 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 00126 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ 00127 00128 uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks. 00129 This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ 00130 00131 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock. 00132 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 00133 This parameter will be used only when PLLSAI is selected as Clock Source SAI */ 00134 }RCC_PLLSAIInitTypeDef; 00135 00136 /** 00137 * @brief RCC extended clocks structure definition 00138 */ 00139 typedef struct 00140 { 00141 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 00142 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 00143 00144 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 00145 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 00146 00147 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. 00148 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ 00149 00150 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 00151 This parameter must be a number between Min_Data = 1 and Max_Data = 32 00152 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 00153 00154 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 00155 This parameter must be a number between Min_Data = 1 and Max_Data = 32 00156 This parameter will be used only when PLLSAI is selected as Clock Source SAI */ 00157 00158 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection. 00159 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 00160 00161 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection. 00162 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 00163 00164 uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. 00165 This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ 00166 00167 uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. 00168 This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ 00169 00170 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. 00171 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 00172 00173 uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. 00174 This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ 00175 00176 uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection. 00177 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ 00178 00179 uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. 00180 This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ 00181 00182 uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection. 00183 This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */ 00184 00185 uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 00186 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ 00187 00188 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 00189 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 00190 }RCC_PeriphCLKInitTypeDef; 00191 #endif /* STM32F446xx */ 00192 00193 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 00194 /** 00195 * @brief RCC extended clocks structure definition 00196 */ 00197 typedef struct 00198 { 00199 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 00200 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 00201 00202 uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection. 00203 This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */ 00204 00205 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. 00206 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 00207 00208 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. 00209 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 00210 00211 uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. 00212 This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ 00213 00214 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 00215 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 00216 }RCC_PeriphCLKInitTypeDef; 00217 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 00218 00219 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 00220 /** 00221 * @brief PLLI2S Clock structure definition 00222 */ 00223 typedef struct 00224 { 00225 uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. 00226 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ 00227 00228 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 00229 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ 00230 00231 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. 00232 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 00233 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 00234 00235 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 00236 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 00237 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 00238 }RCC_PLLI2SInitTypeDef; 00239 00240 /** 00241 * @brief RCC extended clocks structure definition 00242 */ 00243 typedef struct 00244 { 00245 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 00246 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 00247 00248 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 00249 This parameter will be used only when PLLI2S is selected as Clock Source I2S */ 00250 00251 #if defined(STM32F413xx) || defined(STM32F423xx) 00252 uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock. 00253 This parameter must be a number between Min_Data = 1 and Max_Data = 32 00254 This parameter will be used only when PLL is selected as Clock Source SAI */ 00255 00256 uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock. 00257 This parameter must be a number between Min_Data = 1 and Max_Data = 32 00258 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 00259 #endif /* STM32F413xx || STM32F423xx */ 00260 00261 uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. 00262 This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ 00263 00264 uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. 00265 This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ 00266 00267 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. 00268 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 00269 00270 uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. 00271 This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ 00272 00273 uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. 00274 This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ 00275 00276 uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 00277 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ 00278 00279 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection. 00280 This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ 00281 00282 uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection. 00283 This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ 00284 00285 #if defined(STM32F413xx) || defined(STM32F423xx) 00286 uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection. 00287 This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */ 00288 00289 uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection. 00290 This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */ 00291 00292 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. 00293 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 00294 00295 uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection 00296 This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */ 00297 00298 uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection 00299 This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */ 00300 #endif /* STM32F413xx || STM32F423xx */ 00301 00302 uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection. 00303 This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */ 00304 00305 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 00306 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 00307 }RCC_PeriphCLKInitTypeDef; 00308 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 00309 00310 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 00311 00312 /** 00313 * @brief PLLI2S Clock structure definition 00314 */ 00315 typedef struct 00316 { 00317 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 00318 This parameter must be a number between Min_Data = 50 and Max_Data = 432. 00319 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 00320 00321 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 00322 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 00323 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 00324 00325 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. 00326 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 00327 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 00328 }RCC_PLLI2SInitTypeDef; 00329 00330 /** 00331 * @brief PLLSAI Clock structure definition 00332 */ 00333 typedef struct 00334 { 00335 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 00336 This parameter must be a number between Min_Data = 50 and Max_Data = 432. 00337 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 00338 #if defined(STM32F469xx) || defined(STM32F479xx) 00339 uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks. 00340 This parameter is only available in STM32F469xx/STM32F479xx devices. 00341 This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ 00342 #endif /* STM32F469xx || STM32F479xx */ 00343 00344 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. 00345 This parameter must be a number between Min_Data = 2 and Max_Data = 15. 00346 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 00347 00348 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock 00349 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 00350 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ 00351 00352 }RCC_PLLSAIInitTypeDef; 00353 00354 /** 00355 * @brief RCC extended clocks structure definition 00356 */ 00357 typedef struct 00358 { 00359 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 00360 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 00361 00362 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 00363 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 00364 00365 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. 00366 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ 00367 00368 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 00369 This parameter must be a number between Min_Data = 1 and Max_Data = 32 00370 This parameter will be used only when PLLI2S is selected as Clock Source SAI */ 00371 00372 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. 00373 This parameter must be a number between Min_Data = 1 and Max_Data = 32 00374 This parameter will be used only when PLLSAI is selected as Clock Source SAI */ 00375 00376 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. 00377 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ 00378 00379 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. 00380 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 00381 00382 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. 00383 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 00384 #if defined(STM32F469xx) || defined(STM32F479xx) 00385 uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 00386 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ 00387 00388 uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. 00389 This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ 00390 #endif /* STM32F469xx || STM32F479xx */ 00391 }RCC_PeriphCLKInitTypeDef; 00392 00393 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 00394 00395 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ 00396 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 00397 /** 00398 * @brief PLLI2S Clock structure definition 00399 */ 00400 typedef struct 00401 { 00402 #if defined(STM32F411xE) 00403 uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock. 00404 This parameter must be a number between Min_Data = 2 and Max_Data = 62 */ 00405 #endif /* STM32F411xE */ 00406 00407 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. 00408 This parameter must be a number between Min_Data = 50 and Max_Data = 432 00409 Except for STM32F411xE devices where the Min_Data = 192. 00410 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 00411 00412 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. 00413 This parameter must be a number between Min_Data = 2 and Max_Data = 7. 00414 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 00415 00416 }RCC_PLLI2SInitTypeDef; 00417 00418 /** 00419 * @brief RCC extended clocks structure definition 00420 */ 00421 typedef struct 00422 { 00423 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 00424 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 00425 00426 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. 00427 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ 00428 00429 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. 00430 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 00431 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 00432 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. 00433 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ 00434 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ 00435 }RCC_PeriphCLKInitTypeDef; 00436 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ 00437 /** 00438 * @} 00439 */ 00440 00441 /* Exported constants --------------------------------------------------------*/ 00442 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 00443 * @{ 00444 */ 00445 00446 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection 00447 * @{ 00448 */ 00449 /* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */ 00450 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 00451 defined(STM32F413xx) || defined(STM32F423xx) 00452 #define RCC_PERIPHCLK_I2S_APB1 0x00000001U 00453 #define RCC_PERIPHCLK_I2S_APB2 0x00000002U 00454 #define RCC_PERIPHCLK_TIM 0x00000004U 00455 #define RCC_PERIPHCLK_RTC 0x00000008U 00456 #define RCC_PERIPHCLK_FMPI2C1 0x00000010U 00457 #define RCC_PERIPHCLK_CLK48 0x00000020U 00458 #define RCC_PERIPHCLK_SDIO 0x00000040U 00459 #define RCC_PERIPHCLK_PLLI2S 0x00000080U 00460 #define RCC_PERIPHCLK_DFSDM1 0x00000100U 00461 #define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U 00462 #endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */ 00463 #if defined(STM32F413xx) || defined(STM32F423xx) 00464 #define RCC_PERIPHCLK_DFSDM2 0x00000400U 00465 #define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U 00466 #define RCC_PERIPHCLK_LPTIM1 0x00001000U 00467 #define RCC_PERIPHCLK_SAIA 0x00002000U 00468 #define RCC_PERIPHCLK_SAIB 0x00004000U 00469 #endif /* STM32F413xx || STM32F423xx */ 00470 /*----------------------------------------------------------------------------*/ 00471 00472 /*------------------- Peripheral Clock source for STM32F410xx ----------------*/ 00473 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 00474 #define RCC_PERIPHCLK_I2S 0x00000001U 00475 #define RCC_PERIPHCLK_TIM 0x00000002U 00476 #define RCC_PERIPHCLK_RTC 0x00000004U 00477 #define RCC_PERIPHCLK_FMPI2C1 0x00000008U 00478 #define RCC_PERIPHCLK_LPTIM1 0x00000010U 00479 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 00480 /*----------------------------------------------------------------------------*/ 00481 00482 /*------------------- Peripheral Clock source for STM32F446xx ----------------*/ 00483 #if defined(STM32F446xx) 00484 #define RCC_PERIPHCLK_I2S_APB1 0x00000001U 00485 #define RCC_PERIPHCLK_I2S_APB2 0x00000002U 00486 #define RCC_PERIPHCLK_SAI1 0x00000004U 00487 #define RCC_PERIPHCLK_SAI2 0x00000008U 00488 #define RCC_PERIPHCLK_TIM 0x00000010U 00489 #define RCC_PERIPHCLK_RTC 0x00000020U 00490 #define RCC_PERIPHCLK_CEC 0x00000040U 00491 #define RCC_PERIPHCLK_FMPI2C1 0x00000080U 00492 #define RCC_PERIPHCLK_CLK48 0x00000100U 00493 #define RCC_PERIPHCLK_SDIO 0x00000200U 00494 #define RCC_PERIPHCLK_SPDIFRX 0x00000400U 00495 #define RCC_PERIPHCLK_PLLI2S 0x00000800U 00496 #endif /* STM32F446xx */ 00497 /*-----------------------------------------------------------------------------*/ 00498 00499 /*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/ 00500 #if defined(STM32F469xx) || defined(STM32F479xx) 00501 #define RCC_PERIPHCLK_I2S 0x00000001U 00502 #define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U 00503 #define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U 00504 #define RCC_PERIPHCLK_LTDC 0x00000008U 00505 #define RCC_PERIPHCLK_TIM 0x00000010U 00506 #define RCC_PERIPHCLK_RTC 0x00000020U 00507 #define RCC_PERIPHCLK_PLLI2S 0x00000040U 00508 #define RCC_PERIPHCLK_CLK48 0x00000080U 00509 #define RCC_PERIPHCLK_SDIO 0x00000100U 00510 #endif /* STM32F469xx || STM32F479xx */ 00511 /*----------------------------------------------------------------------------*/ 00512 00513 /*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/ 00514 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 00515 #define RCC_PERIPHCLK_I2S 0x00000001U 00516 #define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U 00517 #define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U 00518 #define RCC_PERIPHCLK_LTDC 0x00000008U 00519 #define RCC_PERIPHCLK_TIM 0x00000010U 00520 #define RCC_PERIPHCLK_RTC 0x00000020U 00521 #define RCC_PERIPHCLK_PLLI2S 0x00000040U 00522 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 00523 /*----------------------------------------------------------------------------*/ 00524 00525 /*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/ 00526 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ 00527 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 00528 #define RCC_PERIPHCLK_I2S 0x00000001U 00529 #define RCC_PERIPHCLK_RTC 0x00000002U 00530 #define RCC_PERIPHCLK_PLLI2S 0x00000004U 00531 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ 00532 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 00533 #define RCC_PERIPHCLK_TIM 0x00000008U 00534 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ 00535 /*----------------------------------------------------------------------------*/ 00536 /** 00537 * @} 00538 */ 00539 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 00540 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 00541 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \ 00542 defined(STM32F479xx) 00543 /** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source 00544 * @{ 00545 */ 00546 #define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U 00547 #define RCC_I2SCLKSOURCE_EXT 0x00000001U 00548 /** 00549 * @} 00550 */ 00551 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 00552 STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ 00553 00554 /** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR 00555 * @{ 00556 */ 00557 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ 00558 defined(STM32F469xx) || defined(STM32F479xx) 00559 #define RCC_PLLSAIDIVR_2 0x00000000U 00560 #define RCC_PLLSAIDIVR_4 0x00010000U 00561 #define RCC_PLLSAIDIVR_8 0x00020000U 00562 #define RCC_PLLSAIDIVR_16 0x00030000U 00563 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 00564 /** 00565 * @} 00566 */ 00567 00568 /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider 00569 * @{ 00570 */ 00571 #if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 00572 defined(STM32F412Rx) || defined(STM32F412Cx) 00573 #define RCC_PLLI2SP_DIV2 0x00000002U 00574 #define RCC_PLLI2SP_DIV4 0x00000004U 00575 #define RCC_PLLI2SP_DIV6 0x00000006U 00576 #define RCC_PLLI2SP_DIV8 0x00000008U 00577 #endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 00578 /** 00579 * @} 00580 */ 00581 00582 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider 00583 * @{ 00584 */ 00585 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 00586 #define RCC_PLLSAIP_DIV2 0x00000002U 00587 #define RCC_PLLSAIP_DIV4 0x00000004U 00588 #define RCC_PLLSAIP_DIV6 0x00000006U 00589 #define RCC_PLLSAIP_DIV8 0x00000008U 00590 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */ 00591 /** 00592 * @} 00593 */ 00594 00595 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 00596 /** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source 00597 * @{ 00598 */ 00599 #define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U 00600 #define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U 00601 #define RCC_SAIACLKSOURCE_EXT 0x00200000U 00602 /** 00603 * @} 00604 */ 00605 00606 /** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source 00607 * @{ 00608 */ 00609 #define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U 00610 #define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U 00611 #define RCC_SAIBCLKSOURCE_EXT 0x00800000U 00612 /** 00613 * @} 00614 */ 00615 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 00616 00617 #if defined(STM32F469xx) || defined(STM32F479xx) 00618 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source 00619 * @{ 00620 */ 00621 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U 00622 #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL) 00623 /** 00624 * @} 00625 */ 00626 00627 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source 00628 * @{ 00629 */ 00630 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U 00631 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL) 00632 /** 00633 * @} 00634 */ 00635 00636 /** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source 00637 * @{ 00638 */ 00639 #define RCC_DSICLKSOURCE_DSIPHY 0x00000000U 00640 #define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL) 00641 /** 00642 * @} 00643 */ 00644 #endif /* STM32F469xx || STM32F479xx */ 00645 00646 #if defined(STM32F446xx) 00647 /** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source 00648 * @{ 00649 */ 00650 #define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U 00651 #define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0) 00652 #define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1) 00653 #define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC) 00654 /** 00655 * @} 00656 */ 00657 00658 /** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source 00659 * @{ 00660 */ 00661 #define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U 00662 #define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0) 00663 #define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1) 00664 #define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC) 00665 /** 00666 * @} 00667 */ 00668 00669 /** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source 00670 * @{ 00671 */ 00672 #define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U 00673 #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) 00674 #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) 00675 #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) 00676 /** 00677 * @} 00678 */ 00679 00680 /** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source 00681 * @{ 00682 */ 00683 #define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U 00684 #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) 00685 #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) 00686 #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) 00687 /** 00688 * @} 00689 */ 00690 00691 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source 00692 * @{ 00693 */ 00694 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U 00695 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 00696 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 00697 /** 00698 * @} 00699 */ 00700 00701 /** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source 00702 * @{ 00703 */ 00704 #define RCC_CECCLKSOURCE_HSI 0x00000000U 00705 #define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL) 00706 /** 00707 * @} 00708 */ 00709 00710 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source 00711 * @{ 00712 */ 00713 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U 00714 #define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL) 00715 /** 00716 * @} 00717 */ 00718 00719 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source 00720 * @{ 00721 */ 00722 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U 00723 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) 00724 /** 00725 * @} 00726 */ 00727 00728 /** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source 00729 * @{ 00730 */ 00731 #define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U 00732 #define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL) 00733 /** 00734 * @} 00735 */ 00736 00737 #endif /* STM32F446xx */ 00738 00739 #if defined(STM32F413xx) || defined(STM32F423xx) 00740 /** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source 00741 * @{ 00742 */ 00743 #define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U 00744 #define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0) 00745 #define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1) 00746 #define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1) 00747 /** 00748 * @} 00749 */ 00750 00751 /** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source 00752 * @{ 00753 */ 00754 #define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U 00755 #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0) 00756 #define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1) 00757 #define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1) 00758 /** 00759 * @} 00760 */ 00761 00762 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source 00763 * @{ 00764 */ 00765 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U 00766 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) 00767 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) 00768 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) 00769 /** 00770 * @} 00771 */ 00772 00773 00774 /** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source 00775 * @{ 00776 */ 00777 #define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U 00778 #define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL) 00779 /** 00780 * @} 00781 */ 00782 00783 /** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source 00784 * @{ 00785 */ 00786 #define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U 00787 #define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) 00788 /** 00789 * @} 00790 */ 00791 00792 #endif /* STM32F413xx || STM32F423xx */ 00793 00794 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 00795 /** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source 00796 * @{ 00797 */ 00798 #define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U 00799 #define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC) 00800 /** 00801 * @} 00802 */ 00803 00804 /** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source 00805 * @{ 00806 */ 00807 #define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U 00808 #define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL) 00809 /** 00810 * @} 00811 */ 00812 00813 /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source 00814 * @{ 00815 */ 00816 #define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U 00817 #define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) 00818 /** 00819 * @} 00820 */ 00821 00822 /** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source 00823 * @{ 00824 */ 00825 #define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U 00826 #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) 00827 #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) 00828 #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) 00829 /** 00830 * @} 00831 */ 00832 00833 /** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source 00834 * @{ 00835 */ 00836 #define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U 00837 #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) 00838 #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) 00839 #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) 00840 /** 00841 * @} 00842 */ 00843 00844 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source 00845 * @{ 00846 */ 00847 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U 00848 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 00849 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 00850 /** 00851 * @} 00852 */ 00853 00854 /** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source 00855 * @{ 00856 */ 00857 #define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U 00858 #define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL) 00859 /** 00860 * @} 00861 */ 00862 00863 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source 00864 * @{ 00865 */ 00866 #define RCC_SDIOCLKSOURCE_CLK48 0x00000000U 00867 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) 00868 /** 00869 * @} 00870 */ 00871 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 00872 00873 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 00874 00875 /** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source 00876 * @{ 00877 */ 00878 #define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U 00879 #define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0) 00880 #define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1) 00881 /** 00882 * @} 00883 */ 00884 00885 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source 00886 * @{ 00887 */ 00888 #define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U 00889 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 00890 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 00891 /** 00892 * @} 00893 */ 00894 00895 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source 00896 * @{ 00897 */ 00898 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U 00899 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) 00900 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) 00901 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) 00902 /** 00903 * @} 00904 */ 00905 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 00906 00907 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 00908 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ 00909 defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 00910 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ 00911 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 00912 /** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection 00913 * @{ 00914 */ 00915 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) 00916 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) 00917 /** 00918 * @} 00919 */ 00920 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ 00921 STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ 00922 STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 00923 00924 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ 00925 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ 00926 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ 00927 defined(STM32F423xx) 00928 /** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection 00929 * @{ 00930 */ 00931 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) 00932 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) 00933 /** 00934 * @} 00935 */ 00936 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\ 00937 STM32F412Rx || STM32F412Cx */ 00938 00939 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 00940 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 00941 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 00942 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 00943 defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 00944 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source 00945 * @{ 00946 */ 00947 #define RCC_MCO2SOURCE_SYSCLK 0x00000000U 00948 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 00949 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 00950 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 00951 /** 00952 * @} 00953 */ 00954 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 00955 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 00956 STM32F412Rx || STM32F413xx | STM32F423xx */ 00957 00958 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 00959 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source 00960 * @{ 00961 */ 00962 #define RCC_MCO2SOURCE_SYSCLK 0x00000000U 00963 #define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0 00964 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 00965 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 00966 /** 00967 * @} 00968 */ 00969 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 00970 00971 /** 00972 * @} 00973 */ 00974 00975 /* Exported macro ------------------------------------------------------------*/ 00976 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 00977 * @{ 00978 */ 00979 /*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/ 00980 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 00981 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 00982 * @brief Enables or disables the AHB1 peripheral clock. 00983 * @note After reset, the peripheral clock (used for registers read/write access) 00984 * is disabled and the application software has to enable this clock before 00985 * using it. 00986 * @{ 00987 */ 00988 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 00989 __IO uint32_t tmpreg = 0x00U; \ 00990 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 00991 /* Delay after an RCC peripheral clock enabling */ \ 00992 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 00993 UNUSED(tmpreg); \ 00994 } while(0U) 00995 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 00996 __IO uint32_t tmpreg = 0x00U; \ 00997 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 00998 /* Delay after an RCC peripheral clock enabling */ \ 00999 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 01000 UNUSED(tmpreg); \ 01001 } while(0U) 01002 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 01003 __IO uint32_t tmpreg = 0x00U; \ 01004 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 01005 /* Delay after an RCC peripheral clock enabling */ \ 01006 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 01007 UNUSED(tmpreg); \ 01008 } while(0U) 01009 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 01010 __IO uint32_t tmpreg = 0x00U; \ 01011 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 01012 /* Delay after an RCC peripheral clock enabling */ \ 01013 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 01014 UNUSED(tmpreg); \ 01015 } while(0U) 01016 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 01017 __IO uint32_t tmpreg = 0x00U; \ 01018 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 01019 /* Delay after an RCC peripheral clock enabling */ \ 01020 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 01021 UNUSED(tmpreg); \ 01022 } while(0U) 01023 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 01024 __IO uint32_t tmpreg = 0x00U; \ 01025 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 01026 /* Delay after an RCC peripheral clock enabling */ \ 01027 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 01028 UNUSED(tmpreg); \ 01029 } while(0U) 01030 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 01031 __IO uint32_t tmpreg = 0x00U; \ 01032 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 01033 /* Delay after an RCC peripheral clock enabling */ \ 01034 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 01035 UNUSED(tmpreg); \ 01036 } while(0U) 01037 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 01038 __IO uint32_t tmpreg = 0x00U; \ 01039 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 01040 /* Delay after an RCC peripheral clock enabling */ \ 01041 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 01042 UNUSED(tmpreg); \ 01043 } while(0U) 01044 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ 01045 __IO uint32_t tmpreg = 0x00U; \ 01046 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ 01047 /* Delay after an RCC peripheral clock enabling */ \ 01048 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ 01049 UNUSED(tmpreg); \ 01050 } while(0U) 01051 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ 01052 __IO uint32_t tmpreg = 0x00U; \ 01053 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ 01054 /* Delay after an RCC peripheral clock enabling */ \ 01055 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ 01056 UNUSED(tmpreg); \ 01057 } while(0U) 01058 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 01059 __IO uint32_t tmpreg = 0x00U; \ 01060 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ 01061 /* Delay after an RCC peripheral clock enabling */ \ 01062 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ 01063 UNUSED(tmpreg); \ 01064 } while(0U) 01065 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ 01066 __IO uint32_t tmpreg = 0x00U; \ 01067 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 01068 /* Delay after an RCC peripheral clock enabling */ \ 01069 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 01070 UNUSED(tmpreg); \ 01071 } while(0U) 01072 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ 01073 __IO uint32_t tmpreg = 0x00U; \ 01074 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 01075 /* Delay after an RCC peripheral clock enabling */ \ 01076 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 01077 UNUSED(tmpreg); \ 01078 } while(0U) 01079 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ 01080 __IO uint32_t tmpreg = 0x00U; \ 01081 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 01082 /* Delay after an RCC peripheral clock enabling */ \ 01083 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 01084 UNUSED(tmpreg); \ 01085 } while(0U) 01086 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ 01087 __IO uint32_t tmpreg = 0x00U; \ 01088 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 01089 /* Delay after an RCC peripheral clock enabling */ \ 01090 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 01091 UNUSED(tmpreg); \ 01092 } while(0U) 01093 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 01094 __IO uint32_t tmpreg = 0x00U; \ 01095 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 01096 /* Delay after an RCC peripheral clock enabling */ \ 01097 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 01098 UNUSED(tmpreg); \ 01099 } while(0U) 01100 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ 01101 __IO uint32_t tmpreg = 0x00U; \ 01102 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 01103 /* Delay after an RCC peripheral clock enabling */ \ 01104 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 01105 UNUSED(tmpreg); \ 01106 } while(0U) 01107 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 01108 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 01109 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 01110 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 01111 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) 01112 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) 01113 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) 01114 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) 01115 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) 01116 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) 01117 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) 01118 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) 01119 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 01120 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 01121 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 01122 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 01123 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 01124 01125 /** 01126 * @brief Enable ETHERNET clock. 01127 */ 01128 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 01129 __HAL_RCC_ETHMAC_CLK_ENABLE(); \ 01130 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ 01131 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ 01132 } while(0U) 01133 /** 01134 * @brief Disable ETHERNET clock. 01135 */ 01136 #define __HAL_RCC_ETH_CLK_DISABLE() do { \ 01137 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ 01138 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ 01139 __HAL_RCC_ETHMAC_CLK_DISABLE(); \ 01140 } while(0U) 01141 /** 01142 * @} 01143 */ 01144 01145 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 01146 * @brief Get the enable or disable status of the AHB1 peripheral clock. 01147 * @note After reset, the peripheral clock (used for registers read/write access) 01148 * is disabled and the application software has to enable this clock before 01149 * using it. 01150 * @{ 01151 */ 01152 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 01153 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 01154 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 01155 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 01156 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) 01157 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) 01158 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) 01159 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) 01160 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) 01161 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) 01162 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) 01163 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) 01164 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) 01165 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 01166 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 01167 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 01168 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 01169 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ 01170 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ 01171 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) 01172 01173 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 01174 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 01175 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 01176 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 01177 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) 01178 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) 01179 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) 01180 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) 01181 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) 01182 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) 01183 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) 01184 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) 01185 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) 01186 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) 01187 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 01188 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 01189 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 01190 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ 01191 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ 01192 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) 01193 /** 01194 * @} 01195 */ 01196 01197 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 01198 * @brief Enable or disable the AHB2 peripheral clock. 01199 * @note After reset, the peripheral clock (used for registers read/write access) 01200 * is disabled and the application software has to enable this clock before 01201 * using it. 01202 * @{ 01203 */ 01204 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 01205 __IO uint32_t tmpreg = 0x00U; \ 01206 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 01207 /* Delay after an RCC peripheral clock enabling */ \ 01208 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 01209 UNUSED(tmpreg); \ 01210 } while(0U) 01211 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 01212 01213 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 01214 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ 01215 __IO uint32_t tmpreg = 0x00U; \ 01216 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 01217 /* Delay after an RCC peripheral clock enabling */ \ 01218 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 01219 UNUSED(tmpreg); \ 01220 } while(0U) 01221 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 01222 __IO uint32_t tmpreg = 0x00U; \ 01223 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 01224 /* Delay after an RCC peripheral clock enabling */ \ 01225 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 01226 UNUSED(tmpreg); \ 01227 } while(0U) 01228 01229 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) 01230 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) 01231 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 01232 01233 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 01234 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 01235 }while(0U) 01236 01237 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 01238 01239 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 01240 __IO uint32_t tmpreg = 0x00U; \ 01241 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 01242 /* Delay after an RCC peripheral clock enabling */ \ 01243 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 01244 UNUSED(tmpreg); \ 01245 } while(0U) 01246 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 01247 /** 01248 * @} 01249 */ 01250 01251 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 01252 * @brief Get the enable or disable status of the AHB1 peripheral clock. 01253 * @note After reset, the peripheral clock (used for registers read/write access) 01254 * is disabled and the application software has to enable this clock before 01255 * using it. 01256 * @{ 01257 */ 01258 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 01259 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 01260 01261 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 01262 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) 01263 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) 01264 01265 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) 01266 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) 01267 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 01268 01269 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 01270 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 01271 01272 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 01273 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 01274 /** 01275 * @} 01276 */ 01277 01278 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 01279 * @brief Enables or disables the AHB3 peripheral clock. 01280 * @note After reset, the peripheral clock (used for registers read/write access) 01281 * is disabled and the application software has to enable this clock before 01282 * using it. 01283 * @{ 01284 */ 01285 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 01286 __IO uint32_t tmpreg = 0x00U; \ 01287 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 01288 /* Delay after an RCC peripheral clock enabling */ \ 01289 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 01290 UNUSED(tmpreg); \ 01291 } while(0U) 01292 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) 01293 #if defined(STM32F469xx) || defined(STM32F479xx) 01294 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 01295 __IO uint32_t tmpreg = 0x00U; \ 01296 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 01297 /* Delay after an RCC peripheral clock enabling */ \ 01298 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 01299 UNUSED(tmpreg); \ 01300 } while(0U) 01301 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) 01302 #endif /* STM32F469xx || STM32F479xx */ 01303 /** 01304 * @} 01305 */ 01306 01307 01308 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 01309 * @brief Get the enable or disable status of the AHB3 peripheral clock. 01310 * @note After reset, the peripheral clock (used for registers read/write access) 01311 * is disabled and the application software has to enable this clock before 01312 * using it. 01313 * @{ 01314 */ 01315 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) 01316 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) 01317 #if defined(STM32F469xx) || defined(STM32F479xx) 01318 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 01319 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) 01320 #endif /* STM32F469xx || STM32F479xx */ 01321 /** 01322 * @} 01323 */ 01324 01325 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 01326 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 01327 * @note After reset, the peripheral clock (used for registers read/write access) 01328 * is disabled and the application software has to enable this clock before 01329 * using it. 01330 * @{ 01331 */ 01332 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 01333 __IO uint32_t tmpreg = 0x00U; \ 01334 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 01335 /* Delay after an RCC peripheral clock enabling */ \ 01336 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 01337 UNUSED(tmpreg); \ 01338 } while(0U) 01339 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 01340 __IO uint32_t tmpreg = 0x00U; \ 01341 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 01342 /* Delay after an RCC peripheral clock enabling */ \ 01343 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 01344 UNUSED(tmpreg); \ 01345 } while(0U) 01346 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 01347 __IO uint32_t tmpreg = 0x00U; \ 01348 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 01349 /* Delay after an RCC peripheral clock enabling */ \ 01350 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 01351 UNUSED(tmpreg); \ 01352 } while(0U) 01353 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 01354 __IO uint32_t tmpreg = 0x00U; \ 01355 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 01356 /* Delay after an RCC peripheral clock enabling */ \ 01357 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 01358 UNUSED(tmpreg); \ 01359 } while(0U) 01360 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 01361 __IO uint32_t tmpreg = 0x00U; \ 01362 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 01363 /* Delay after an RCC peripheral clock enabling */ \ 01364 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 01365 UNUSED(tmpreg); \ 01366 } while(0U) 01367 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 01368 __IO uint32_t tmpreg = 0x00U; \ 01369 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 01370 /* Delay after an RCC peripheral clock enabling */ \ 01371 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 01372 UNUSED(tmpreg); \ 01373 } while(0U) 01374 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 01375 __IO uint32_t tmpreg = 0x00U; \ 01376 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 01377 /* Delay after an RCC peripheral clock enabling */ \ 01378 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 01379 UNUSED(tmpreg); \ 01380 } while(0U) 01381 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 01382 __IO uint32_t tmpreg = 0x00U; \ 01383 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 01384 /* Delay after an RCC peripheral clock enabling */ \ 01385 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 01386 UNUSED(tmpreg); \ 01387 } while(0U) 01388 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 01389 __IO uint32_t tmpreg = 0x00U; \ 01390 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 01391 /* Delay after an RCC peripheral clock enabling */ \ 01392 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 01393 UNUSED(tmpreg); \ 01394 } while(0U) 01395 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 01396 __IO uint32_t tmpreg = 0x00U; \ 01397 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 01398 /* Delay after an RCC peripheral clock enabling */ \ 01399 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 01400 UNUSED(tmpreg); \ 01401 } while(0U) 01402 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 01403 __IO uint32_t tmpreg = 0x00U; \ 01404 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 01405 /* Delay after an RCC peripheral clock enabling */ \ 01406 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 01407 UNUSED(tmpreg); \ 01408 } while(0U) 01409 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 01410 __IO uint32_t tmpreg = 0x00U; \ 01411 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 01412 /* Delay after an RCC peripheral clock enabling */ \ 01413 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 01414 UNUSED(tmpreg); \ 01415 } while(0U) 01416 #define __HAL_RCC_UART7_CLK_ENABLE() do { \ 01417 __IO uint32_t tmpreg = 0x00U; \ 01418 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 01419 /* Delay after an RCC peripheral clock enabling */ \ 01420 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 01421 UNUSED(tmpreg); \ 01422 } while(0U) 01423 #define __HAL_RCC_UART8_CLK_ENABLE() do { \ 01424 __IO uint32_t tmpreg = 0x00U; \ 01425 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 01426 /* Delay after an RCC peripheral clock enabling */ \ 01427 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 01428 UNUSED(tmpreg); \ 01429 } while(0U) 01430 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 01431 __IO uint32_t tmpreg = 0x00U; \ 01432 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 01433 /* Delay after an RCC peripheral clock enabling */ \ 01434 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 01435 UNUSED(tmpreg); \ 01436 } while(0U) 01437 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 01438 __IO uint32_t tmpreg = 0x00U; \ 01439 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 01440 /* Delay after an RCC peripheral clock enabling */ \ 01441 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 01442 UNUSED(tmpreg); \ 01443 } while(0U) 01444 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 01445 __IO uint32_t tmpreg = 0x00U; \ 01446 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 01447 /* Delay after an RCC peripheral clock enabling */ \ 01448 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 01449 UNUSED(tmpreg); \ 01450 } while(0U) 01451 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 01452 __IO uint32_t tmpreg = 0x00U; \ 01453 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 01454 /* Delay after an RCC peripheral clock enabling */ \ 01455 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 01456 UNUSED(tmpreg); \ 01457 } while(0U) 01458 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 01459 __IO uint32_t tmpreg = 0x00U; \ 01460 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 01461 /* Delay after an RCC peripheral clock enabling */ \ 01462 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 01463 UNUSED(tmpreg); \ 01464 } while(0U) 01465 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 01466 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 01467 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 01468 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 01469 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 01470 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 01471 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 01472 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 01473 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 01474 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 01475 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 01476 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 01477 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 01478 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 01479 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 01480 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 01481 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) 01482 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) 01483 /** 01484 * @} 01485 */ 01486 01487 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 01488 * @brief Get the enable or disable status of the APB1 peripheral clock. 01489 * @note After reset, the peripheral clock (used for registers read/write access) 01490 * is disabled and the application software has to enable this clock before 01491 * using it. 01492 * @{ 01493 */ 01494 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 01495 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 01496 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 01497 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 01498 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 01499 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 01500 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 01501 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 01502 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 01503 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 01504 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 01505 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 01506 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 01507 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 01508 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 01509 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 01510 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) 01511 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 01512 01513 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 01514 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 01515 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 01516 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 01517 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 01518 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 01519 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 01520 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 01521 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 01522 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 01523 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 01524 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 01525 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 01526 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 01527 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 01528 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 01529 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) 01530 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) 01531 /** 01532 * @} 01533 */ 01534 01535 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 01536 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 01537 * @note After reset, the peripheral clock (used for registers read/write access) 01538 * is disabled and the application software has to enable this clock before 01539 * using it. 01540 * @{ 01541 */ 01542 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 01543 __IO uint32_t tmpreg = 0x00U; \ 01544 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 01545 /* Delay after an RCC peripheral clock enabling */ \ 01546 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 01547 UNUSED(tmpreg); \ 01548 } while(0U) 01549 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 01550 __IO uint32_t tmpreg = 0x00U; \ 01551 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 01552 /* Delay after an RCC peripheral clock enabling */ \ 01553 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 01554 UNUSED(tmpreg); \ 01555 } while(0U) 01556 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 01557 __IO uint32_t tmpreg = 0x00U; \ 01558 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 01559 /* Delay after an RCC peripheral clock enabling */ \ 01560 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 01561 UNUSED(tmpreg); \ 01562 } while(0U) 01563 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 01564 __IO uint32_t tmpreg = 0x00U; \ 01565 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 01566 /* Delay after an RCC peripheral clock enabling */ \ 01567 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 01568 UNUSED(tmpreg); \ 01569 } while(0U) 01570 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ 01571 __IO uint32_t tmpreg = 0x00U; \ 01572 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ 01573 /* Delay after an RCC peripheral clock enabling */ \ 01574 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ 01575 UNUSED(tmpreg); \ 01576 } while(0U) 01577 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 01578 __IO uint32_t tmpreg = 0x00U; \ 01579 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 01580 /* Delay after an RCC peripheral clock enabling */ \ 01581 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 01582 UNUSED(tmpreg); \ 01583 } while(0U) 01584 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 01585 __IO uint32_t tmpreg = 0x00U; \ 01586 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 01587 /* Delay after an RCC peripheral clock enabling */ \ 01588 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 01589 UNUSED(tmpreg); \ 01590 } while(0U) 01591 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 01592 __IO uint32_t tmpreg = 0x00U; \ 01593 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 01594 /* Delay after an RCC peripheral clock enabling */ \ 01595 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 01596 UNUSED(tmpreg); \ 01597 } while(0U) 01598 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 01599 __IO uint32_t tmpreg = 0x00U; \ 01600 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 01601 /* Delay after an RCC peripheral clock enabling */ \ 01602 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 01603 UNUSED(tmpreg); \ 01604 } while(0U) 01605 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 01606 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 01607 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 01608 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 01609 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 01610 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 01611 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 01612 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) 01613 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) 01614 01615 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 01616 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ 01617 __IO uint32_t tmpreg = 0x00U; \ 01618 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ 01619 /* Delay after an RCC peripheral clock enabling */ \ 01620 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ 01621 UNUSED(tmpreg); \ 01622 } while(0U) 01623 01624 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) 01625 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 01626 01627 #if defined(STM32F469xx) || defined(STM32F479xx) 01628 #define __HAL_RCC_DSI_CLK_ENABLE() do { \ 01629 __IO uint32_t tmpreg = 0x00U; \ 01630 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ 01631 /* Delay after an RCC peripheral clock enabling */ \ 01632 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ 01633 UNUSED(tmpreg); \ 01634 } while(0U) 01635 01636 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) 01637 #endif /* STM32F469xx || STM32F479xx */ 01638 /** 01639 * @} 01640 */ 01641 01642 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 01643 * @brief Get the enable or disable status of the APB2 peripheral clock. 01644 * @note After reset, the peripheral clock (used for registers read/write access) 01645 * is disabled and the application software has to enable this clock before 01646 * using it. 01647 * @{ 01648 */ 01649 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 01650 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 01651 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 01652 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 01653 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) 01654 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 01655 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 01656 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 01657 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET) 01658 01659 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 01660 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 01661 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET) 01662 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 01663 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 01664 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 01665 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 01666 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) 01667 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) 01668 01669 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 01670 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) 01671 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) 01672 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 01673 01674 #if defined(STM32F469xx) || defined(STM32F479xx) 01675 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) 01676 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) 01677 #endif /* STM32F469xx || STM32F479xx */ 01678 /** 01679 * @} 01680 */ 01681 01682 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 01683 * @brief Force or release AHB1 peripheral reset. 01684 * @{ 01685 */ 01686 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 01687 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 01688 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 01689 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 01690 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) 01691 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) 01692 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 01693 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) 01694 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) 01695 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) 01696 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 01697 01698 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 01699 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 01700 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 01701 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 01702 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) 01703 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) 01704 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 01705 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) 01706 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) 01707 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) 01708 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 01709 /** 01710 * @} 01711 */ 01712 01713 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 01714 * @brief Force or release AHB2 peripheral reset. 01715 * @{ 01716 */ 01717 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 01718 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 01719 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 01720 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 01721 01722 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 01723 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 01724 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 01725 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 01726 01727 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 01728 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) 01729 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) 01730 01731 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) 01732 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) 01733 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 01734 /** 01735 * @} 01736 */ 01737 01738 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 01739 * @brief Force or release AHB3 peripheral reset. 01740 * @{ 01741 */ 01742 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 01743 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 01744 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) 01745 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) 01746 01747 #if defined(STM32F469xx) || defined(STM32F479xx) 01748 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 01749 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) 01750 #endif /* STM32F469xx || STM32F479xx */ 01751 /** 01752 * @} 01753 */ 01754 01755 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 01756 * @brief Force or release APB1 peripheral reset. 01757 * @{ 01758 */ 01759 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 01760 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 01761 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 01762 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 01763 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 01764 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 01765 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 01766 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 01767 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 01768 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 01769 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 01770 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) 01771 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) 01772 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 01773 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 01774 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 01775 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 01776 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 01777 01778 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 01779 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 01780 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 01781 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 01782 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 01783 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 01784 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 01785 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 01786 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 01787 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 01788 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 01789 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 01790 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 01791 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 01792 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 01793 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 01794 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) 01795 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) 01796 /** 01797 * @} 01798 */ 01799 01800 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 01801 * @brief Force or release APB2 peripheral reset. 01802 * @{ 01803 */ 01804 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 01805 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 01806 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) 01807 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 01808 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 01809 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 01810 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 01811 01812 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 01813 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 01814 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 01815 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 01816 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 01817 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) 01818 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) 01819 01820 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 01821 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) 01822 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) 01823 #endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ 01824 01825 #if defined(STM32F469xx) || defined(STM32F479xx) 01826 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) 01827 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) 01828 #endif /* STM32F469xx || STM32F479xx */ 01829 /** 01830 * @} 01831 */ 01832 01833 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 01834 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 01835 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 01836 * power consumption. 01837 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 01838 * @note By default, all peripheral clocks are enabled during SLEEP mode. 01839 * @{ 01840 */ 01841 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 01842 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 01843 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 01844 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 01845 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) 01846 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 01847 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) 01848 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) 01849 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) 01850 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) 01851 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 01852 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 01853 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) 01854 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) 01855 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN)) 01856 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) 01857 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 01858 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 01859 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 01860 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 01861 01862 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 01863 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 01864 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 01865 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 01866 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) 01867 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 01868 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) 01869 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) 01870 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) 01871 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) 01872 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 01873 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 01874 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) 01875 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) 01876 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) 01877 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 01878 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 01879 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 01880 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 01881 /** 01882 * @} 01883 */ 01884 01885 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 01886 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 01887 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 01888 * power consumption. 01889 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 01890 * @note By default, all peripheral clocks are enabled during SLEEP mode. 01891 * @{ 01892 */ 01893 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 01894 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 01895 01896 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 01897 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 01898 01899 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 01900 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 01901 01902 #if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 01903 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 01904 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 01905 01906 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) 01907 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) 01908 #endif /* STM32F437xx || STM32F439xx || STM32F479xx */ 01909 /** 01910 * @} 01911 */ 01912 01913 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 01914 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 01915 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 01916 * power consumption. 01917 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 01918 * @note By default, all peripheral clocks are enabled during SLEEP mode. 01919 * @{ 01920 */ 01921 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 01922 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) 01923 01924 #if defined(STM32F469xx) || defined(STM32F479xx) 01925 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 01926 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) 01927 #endif /* STM32F469xx || STM32F479xx */ 01928 /** 01929 * @} 01930 */ 01931 01932 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 01933 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 01934 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 01935 * power consumption. 01936 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 01937 * @note By default, all peripheral clocks are enabled during SLEEP mode. 01938 * @{ 01939 */ 01940 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 01941 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 01942 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 01943 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 01944 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 01945 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 01946 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 01947 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 01948 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 01949 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 01950 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 01951 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) 01952 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) 01953 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 01954 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 01955 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 01956 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 01957 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 01958 01959 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 01960 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 01961 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 01962 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 01963 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 01964 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 01965 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 01966 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 01967 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 01968 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 01969 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 01970 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 01971 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 01972 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 01973 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 01974 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 01975 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) 01976 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) 01977 /** 01978 * @} 01979 */ 01980 01981 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 01982 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 01983 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 01984 * power consumption. 01985 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 01986 * @note By default, all peripheral clocks are enabled during SLEEP mode. 01987 * @{ 01988 */ 01989 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 01990 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 01991 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 01992 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 01993 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) 01994 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) 01995 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 01996 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 01997 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 01998 01999 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 02000 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 02001 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 02002 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 02003 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 02004 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 02005 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 02006 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) 02007 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) 02008 02009 #if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 02010 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) 02011 02012 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) 02013 #endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 02014 02015 #if defined(STM32F469xx) || defined(STM32F479xx) 02016 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) 02017 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) 02018 #endif /* STM32F469xx || STM32F479xx */ 02019 /** 02020 * @} 02021 */ 02022 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ 02023 /*----------------------------------------------------------------------------*/ 02024 02025 /*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/ 02026 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) 02027 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 02028 * @brief Enables or disables the AHB1 peripheral clock. 02029 * @note After reset, the peripheral clock (used for registers read/write access) 02030 * is disabled and the application software has to enable this clock before 02031 * using it. 02032 * @{ 02033 */ 02034 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 02035 __IO uint32_t tmpreg = 0x00U; \ 02036 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 02037 /* Delay after an RCC peripheral clock enabling */ \ 02038 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 02039 UNUSED(tmpreg); \ 02040 } while(0U) 02041 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 02042 __IO uint32_t tmpreg = 0x00U; \ 02043 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 02044 /* Delay after an RCC peripheral clock enabling */ \ 02045 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 02046 UNUSED(tmpreg); \ 02047 } while(0U) 02048 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 02049 __IO uint32_t tmpreg = 0x00U; \ 02050 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 02051 /* Delay after an RCC peripheral clock enabling */ \ 02052 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 02053 UNUSED(tmpreg); \ 02054 } while(0U) 02055 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 02056 __IO uint32_t tmpreg = 0x00U; \ 02057 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 02058 /* Delay after an RCC peripheral clock enabling */ \ 02059 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 02060 UNUSED(tmpreg); \ 02061 } while(0U) 02062 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 02063 __IO uint32_t tmpreg = 0x00U; \ 02064 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 02065 /* Delay after an RCC peripheral clock enabling */ \ 02066 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 02067 UNUSED(tmpreg); \ 02068 } while(0U) 02069 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 02070 __IO uint32_t tmpreg = 0x00U; \ 02071 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 02072 /* Delay after an RCC peripheral clock enabling */ \ 02073 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 02074 UNUSED(tmpreg); \ 02075 } while(0U) 02076 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 02077 __IO uint32_t tmpreg = 0x00U; \ 02078 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 02079 /* Delay after an RCC peripheral clock enabling */ \ 02080 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 02081 UNUSED(tmpreg); \ 02082 } while(0U) 02083 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 02084 __IO uint32_t tmpreg = 0x00U; \ 02085 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 02086 /* Delay after an RCC peripheral clock enabling */ \ 02087 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 02088 UNUSED(tmpreg); \ 02089 } while(0U) 02090 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 02091 __IO uint32_t tmpreg = 0x00U; \ 02092 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 02093 /* Delay after an RCC peripheral clock enabling */ \ 02094 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 02095 UNUSED(tmpreg); \ 02096 } while(0U) 02097 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ 02098 __IO uint32_t tmpreg = 0x00U; \ 02099 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 02100 /* Delay after an RCC peripheral clock enabling */ \ 02101 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 02102 UNUSED(tmpreg); \ 02103 } while(0U) 02104 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 02105 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 02106 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 02107 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 02108 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) 02109 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 02110 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 02111 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 02112 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 02113 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 02114 #if defined(STM32F407xx)|| defined(STM32F417xx) 02115 /** 02116 * @brief Enable ETHERNET clock. 02117 */ 02118 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ 02119 __IO uint32_t tmpreg = 0x00U; \ 02120 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 02121 /* Delay after an RCC peripheral clock enabling */ \ 02122 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ 02123 UNUSED(tmpreg); \ 02124 } while(0U) 02125 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ 02126 __IO uint32_t tmpreg = 0x00U; \ 02127 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 02128 /* Delay after an RCC peripheral clock enabling */ \ 02129 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ 02130 UNUSED(tmpreg); \ 02131 } while(0U) 02132 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ 02133 __IO uint32_t tmpreg = 0x00U; \ 02134 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 02135 /* Delay after an RCC peripheral clock enabling */ \ 02136 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ 02137 UNUSED(tmpreg); \ 02138 } while(0U) 02139 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ 02140 __IO uint32_t tmpreg = 0x00U; \ 02141 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 02142 /* Delay after an RCC peripheral clock enabling */ \ 02143 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ 02144 UNUSED(tmpreg); \ 02145 } while(0U) 02146 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 02147 __HAL_RCC_ETHMAC_CLK_ENABLE(); \ 02148 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ 02149 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ 02150 } while(0U) 02151 02152 /** 02153 * @brief Disable ETHERNET clock. 02154 */ 02155 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) 02156 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) 02157 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) 02158 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) 02159 #define __HAL_RCC_ETH_CLK_DISABLE() do { \ 02160 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ 02161 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ 02162 __HAL_RCC_ETHMAC_CLK_DISABLE(); \ 02163 } while(0U) 02164 #endif /* STM32F407xx || STM32F417xx */ 02165 /** 02166 * @} 02167 */ 02168 02169 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 02170 * @brief Get the enable or disable status of the AHB1 peripheral clock. 02171 * @note After reset, the peripheral clock (used for registers read/write access) 02172 * is disabled and the application software has to enable this clock before 02173 * using it. 02174 * @{ 02175 */ 02176 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 02177 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 02178 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 02179 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 02180 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 02181 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) 02182 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 02183 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 02184 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) 02185 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 02186 02187 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 02188 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 02189 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 02190 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 02191 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) 02192 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) 02193 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET) 02194 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 02195 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 02196 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 02197 #if defined(STM32F407xx)|| defined(STM32F417xx) 02198 /** 02199 * @brief Enable ETHERNET clock. 02200 */ 02201 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) 02202 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) 02203 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) 02204 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) 02205 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ 02206 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ 02207 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) 02208 /** 02209 * @brief Disable ETHERNET clock. 02210 */ 02211 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) 02212 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) 02213 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) 02214 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) 02215 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ 02216 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ 02217 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) 02218 #endif /* STM32F407xx || STM32F417xx */ 02219 /** 02220 * @} 02221 */ 02222 02223 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 02224 * @brief Enable or disable the AHB2 peripheral clock. 02225 * @note After reset, the peripheral clock (used for registers read/write access) 02226 * is disabled and the application software has to enable this clock before 02227 * using it. 02228 * @{ 02229 */ 02230 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 02231 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 02232 }while(0U) 02233 02234 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 02235 02236 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 02237 __IO uint32_t tmpreg = 0x00U; \ 02238 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 02239 /* Delay after an RCC peripheral clock enabling */ \ 02240 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 02241 UNUSED(tmpreg); \ 02242 } while(0U) 02243 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 02244 02245 #if defined(STM32F407xx)|| defined(STM32F417xx) 02246 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 02247 __IO uint32_t tmpreg = 0x00U; \ 02248 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 02249 /* Delay after an RCC peripheral clock enabling */ \ 02250 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 02251 UNUSED(tmpreg); \ 02252 } while(0U) 02253 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 02254 #endif /* STM32F407xx || STM32F417xx */ 02255 02256 #if defined(STM32F415xx) || defined(STM32F417xx) 02257 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ 02258 __IO uint32_t tmpreg = 0x00U; \ 02259 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 02260 /* Delay after an RCC peripheral clock enabling */ \ 02261 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ 02262 UNUSED(tmpreg); \ 02263 } while(0U) 02264 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 02265 __IO uint32_t tmpreg = 0x00U; \ 02266 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 02267 /* Delay after an RCC peripheral clock enabling */ \ 02268 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ 02269 UNUSED(tmpreg); \ 02270 } while(0U) 02271 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) 02272 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) 02273 #endif /* STM32F415xx || STM32F417xx */ 02274 /** 02275 * @} 02276 */ 02277 02278 02279 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 02280 * @brief Get the enable or disable status of the AHB2 peripheral clock. 02281 * @note After reset, the peripheral clock (used for registers read/write access) 02282 * is disabled and the application software has to enable this clock before 02283 * using it. 02284 * @{ 02285 */ 02286 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 02287 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 02288 02289 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 02290 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 02291 02292 #if defined(STM32F407xx)|| defined(STM32F417xx) 02293 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 02294 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 02295 #endif /* STM32F407xx || STM32F417xx */ 02296 02297 #if defined(STM32F415xx) || defined(STM32F417xx) 02298 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) 02299 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) 02300 02301 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) 02302 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) 02303 #endif /* STM32F415xx || STM32F417xx */ 02304 /** 02305 * @} 02306 */ 02307 02308 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 02309 * @brief Enables or disables the AHB3 peripheral clock. 02310 * @note After reset, the peripheral clock (used for registers read/write access) 02311 * is disabled and the application software has to enable this clock before 02312 * using it. 02313 * @{ 02314 */ 02315 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ 02316 __IO uint32_t tmpreg = 0x00U; \ 02317 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 02318 /* Delay after an RCC peripheral clock enabling */ \ 02319 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 02320 UNUSED(tmpreg); \ 02321 } while(0U) 02322 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) 02323 /** 02324 * @} 02325 */ 02326 02327 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 02328 * @brief Get the enable or disable status of the AHB3 peripheral clock. 02329 * @note After reset, the peripheral clock (used for registers read/write access) 02330 * is disabled and the application software has to enable this clock before 02331 * using it. 02332 * @{ 02333 */ 02334 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 02335 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) 02336 /** 02337 * @} 02338 */ 02339 02340 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 02341 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 02342 * @note After reset, the peripheral clock (used for registers read/write access) 02343 * is disabled and the application software has to enable this clock before 02344 * using it. 02345 * @{ 02346 */ 02347 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 02348 __IO uint32_t tmpreg = 0x00U; \ 02349 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 02350 /* Delay after an RCC peripheral clock enabling */ \ 02351 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 02352 UNUSED(tmpreg); \ 02353 } while(0U) 02354 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 02355 __IO uint32_t tmpreg = 0x00U; \ 02356 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 02357 /* Delay after an RCC peripheral clock enabling */ \ 02358 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 02359 UNUSED(tmpreg); \ 02360 } while(0U) 02361 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 02362 __IO uint32_t tmpreg = 0x00U; \ 02363 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 02364 /* Delay after an RCC peripheral clock enabling */ \ 02365 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 02366 UNUSED(tmpreg); \ 02367 } while(0U) 02368 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 02369 __IO uint32_t tmpreg = 0x00U; \ 02370 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 02371 /* Delay after an RCC peripheral clock enabling */ \ 02372 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 02373 UNUSED(tmpreg); \ 02374 } while(0U) 02375 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 02376 __IO uint32_t tmpreg = 0x00U; \ 02377 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 02378 /* Delay after an RCC peripheral clock enabling */ \ 02379 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 02380 UNUSED(tmpreg); \ 02381 } while(0U) 02382 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 02383 __IO uint32_t tmpreg = 0x00U; \ 02384 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 02385 /* Delay after an RCC peripheral clock enabling */ \ 02386 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 02387 UNUSED(tmpreg); \ 02388 } while(0U) 02389 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 02390 __IO uint32_t tmpreg = 0x00U; \ 02391 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 02392 /* Delay after an RCC peripheral clock enabling */ \ 02393 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 02394 UNUSED(tmpreg); \ 02395 } while(0U) 02396 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 02397 __IO uint32_t tmpreg = 0x00U; \ 02398 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 02399 /* Delay after an RCC peripheral clock enabling */ \ 02400 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 02401 UNUSED(tmpreg); \ 02402 } while(0U) 02403 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 02404 __IO uint32_t tmpreg = 0x00U; \ 02405 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 02406 /* Delay after an RCC peripheral clock enabling */ \ 02407 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 02408 UNUSED(tmpreg); \ 02409 } while(0U) 02410 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 02411 __IO uint32_t tmpreg = 0x00U; \ 02412 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 02413 /* Delay after an RCC peripheral clock enabling */ \ 02414 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 02415 UNUSED(tmpreg); \ 02416 } while(0U) 02417 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 02418 __IO uint32_t tmpreg = 0x00U; \ 02419 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 02420 /* Delay after an RCC peripheral clock enabling */ \ 02421 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 02422 UNUSED(tmpreg); \ 02423 } while(0U) 02424 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 02425 __IO uint32_t tmpreg = 0x00U; \ 02426 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 02427 /* Delay after an RCC peripheral clock enabling */ \ 02428 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 02429 UNUSED(tmpreg); \ 02430 } while(0U) 02431 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 02432 __IO uint32_t tmpreg = 0x00U; \ 02433 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 02434 /* Delay after an RCC peripheral clock enabling */ \ 02435 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 02436 UNUSED(tmpreg); \ 02437 } while(0U) 02438 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 02439 __IO uint32_t tmpreg = 0x00U; \ 02440 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 02441 /* Delay after an RCC peripheral clock enabling */ \ 02442 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 02443 UNUSED(tmpreg); \ 02444 } while(0U) 02445 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 02446 __IO uint32_t tmpreg = 0x00U; \ 02447 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 02448 /* Delay after an RCC peripheral clock enabling */ \ 02449 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 02450 UNUSED(tmpreg); \ 02451 } while(0U) 02452 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 02453 __IO uint32_t tmpreg = 0x00U; \ 02454 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 02455 /* Delay after an RCC peripheral clock enabling */ \ 02456 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 02457 UNUSED(tmpreg); \ 02458 } while(0U) 02459 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 02460 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 02461 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 02462 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 02463 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 02464 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 02465 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 02466 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 02467 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 02468 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 02469 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 02470 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 02471 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 02472 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 02473 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 02474 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 02475 /** 02476 * @} 02477 */ 02478 02479 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 02480 * @brief Get the enable or disable status of the APB1 peripheral clock. 02481 * @note After reset, the peripheral clock (used for registers read/write access) 02482 * is disabled and the application software has to enable this clock before 02483 * using it. 02484 * @{ 02485 */ 02486 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 02487 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 02488 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 02489 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 02490 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 02491 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 02492 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 02493 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 02494 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 02495 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 02496 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 02497 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 02498 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 02499 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 02500 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 02501 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 02502 02503 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 02504 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 02505 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 02506 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 02507 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 02508 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 02509 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 02510 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 02511 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 02512 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 02513 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 02514 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 02515 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 02516 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 02517 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 02518 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 02519 /** 02520 * @} 02521 */ 02522 02523 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 02524 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 02525 * @note After reset, the peripheral clock (used for registers read/write access) 02526 * is disabled and the application software has to enable this clock before 02527 * using it. 02528 * @{ 02529 */ 02530 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 02531 __IO uint32_t tmpreg = 0x00U; \ 02532 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 02533 /* Delay after an RCC peripheral clock enabling */ \ 02534 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 02535 UNUSED(tmpreg); \ 02536 } while(0U) 02537 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 02538 __IO uint32_t tmpreg = 0x00U; \ 02539 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 02540 /* Delay after an RCC peripheral clock enabling */ \ 02541 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 02542 UNUSED(tmpreg); \ 02543 } while(0U) 02544 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 02545 __IO uint32_t tmpreg = 0x00U; \ 02546 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 02547 /* Delay after an RCC peripheral clock enabling */ \ 02548 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 02549 UNUSED(tmpreg); \ 02550 } while(0U) 02551 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 02552 __IO uint32_t tmpreg = 0x00U; \ 02553 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 02554 /* Delay after an RCC peripheral clock enabling */ \ 02555 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 02556 UNUSED(tmpreg); \ 02557 } while(0U) 02558 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 02559 __IO uint32_t tmpreg = 0x00U; \ 02560 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 02561 /* Delay after an RCC peripheral clock enabling */ \ 02562 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 02563 UNUSED(tmpreg); \ 02564 } while(0U) 02565 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 02566 __IO uint32_t tmpreg = 0x00U; \ 02567 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 02568 /* Delay after an RCC peripheral clock enabling */ \ 02569 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 02570 UNUSED(tmpreg); \ 02571 } while(0U) 02572 02573 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 02574 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 02575 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 02576 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 02577 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 02578 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 02579 /** 02580 * @} 02581 */ 02582 02583 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 02584 * @brief Get the enable or disable status of the APB2 peripheral clock. 02585 * @note After reset, the peripheral clock (used for registers read/write access) 02586 * is disabled and the application software has to enable this clock before 02587 * using it. 02588 * @{ 02589 */ 02590 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 02591 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 02592 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 02593 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 02594 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 02595 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 02596 02597 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 02598 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 02599 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 02600 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 02601 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 02602 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 02603 /** 02604 * @} 02605 */ 02606 02607 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 02608 * @brief Force or release AHB1 peripheral reset. 02609 * @{ 02610 */ 02611 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 02612 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 02613 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 02614 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 02615 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) 02616 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) 02617 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 02618 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 02619 02620 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 02621 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 02622 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 02623 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 02624 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) 02625 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) 02626 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 02627 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 02628 /** 02629 * @} 02630 */ 02631 02632 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 02633 * @brief Force or release AHB2 peripheral reset. 02634 * @{ 02635 */ 02636 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 02637 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 02638 02639 #if defined(STM32F407xx)|| defined(STM32F417xx) 02640 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 02641 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 02642 #endif /* STM32F407xx || STM32F417xx */ 02643 02644 #if defined(STM32F415xx) || defined(STM32F417xx) 02645 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) 02646 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) 02647 02648 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) 02649 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) 02650 #endif /* STM32F415xx || STM32F417xx */ 02651 02652 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 02653 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 02654 02655 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 02656 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 02657 /** 02658 * @} 02659 */ 02660 02661 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 02662 * @brief Force or release AHB3 peripheral reset. 02663 * @{ 02664 */ 02665 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 02666 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 02667 02668 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) 02669 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) 02670 /** 02671 * @} 02672 */ 02673 02674 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 02675 * @brief Force or release APB1 peripheral reset. 02676 * @{ 02677 */ 02678 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 02679 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 02680 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 02681 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 02682 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 02683 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 02684 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 02685 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 02686 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 02687 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 02688 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 02689 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 02690 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 02691 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 02692 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 02693 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 02694 02695 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 02696 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 02697 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 02698 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 02699 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 02700 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 02701 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 02702 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 02703 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 02704 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 02705 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 02706 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 02707 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 02708 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 02709 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 02710 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 02711 /** 02712 * @} 02713 */ 02714 02715 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 02716 * @brief Force or release APB2 peripheral reset. 02717 * @{ 02718 */ 02719 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 02720 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 02721 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 02722 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 02723 02724 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 02725 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 02726 #define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 02727 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 02728 /** 02729 * @} 02730 */ 02731 02732 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 02733 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 02734 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02735 * power consumption. 02736 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02737 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02738 * @{ 02739 */ 02740 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 02741 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 02742 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 02743 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 02744 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) 02745 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 02746 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) 02747 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) 02748 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) 02749 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) 02750 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 02751 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 02752 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 02753 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 02754 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 02755 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 02756 02757 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 02758 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 02759 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 02760 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 02761 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) 02762 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 02763 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) 02764 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) 02765 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) 02766 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) 02767 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 02768 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 02769 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 02770 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 02771 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 02772 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 02773 /** 02774 * @} 02775 */ 02776 02777 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 02778 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 02779 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02780 * power consumption. 02781 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 02782 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02783 * @{ 02784 */ 02785 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 02786 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 02787 02788 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 02789 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 02790 02791 #if defined(STM32F407xx)|| defined(STM32F417xx) 02792 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 02793 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 02794 #endif /* STM32F407xx || STM32F417xx */ 02795 02796 #if defined(STM32F415xx) || defined(STM32F417xx) 02797 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) 02798 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) 02799 02800 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) 02801 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) 02802 #endif /* STM32F415xx || STM32F417xx */ 02803 /** 02804 * @} 02805 */ 02806 02807 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 02808 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 02809 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02810 * power consumption. 02811 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02812 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02813 * @{ 02814 */ 02815 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) 02816 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) 02817 /** 02818 * @} 02819 */ 02820 02821 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 02822 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 02823 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02824 * power consumption. 02825 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02826 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02827 * @{ 02828 */ 02829 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 02830 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 02831 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 02832 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 02833 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 02834 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 02835 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 02836 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 02837 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 02838 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 02839 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 02840 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 02841 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 02842 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 02843 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 02844 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 02845 02846 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 02847 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 02848 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 02849 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 02850 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 02851 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 02852 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 02853 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 02854 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 02855 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 02856 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 02857 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 02858 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 02859 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 02860 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 02861 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 02862 /** 02863 * @} 02864 */ 02865 02866 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 02867 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 02868 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02869 * power consumption. 02870 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02871 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02872 * @{ 02873 */ 02874 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 02875 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 02876 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 02877 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 02878 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 02879 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 02880 02881 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 02882 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 02883 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 02884 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 02885 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 02886 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 02887 /** 02888 * @} 02889 */ 02890 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ 02891 /*----------------------------------------------------------------------------*/ 02892 02893 /*------------------------- STM32F401xE/STM32F401xC --------------------------*/ 02894 #if defined(STM32F401xC) || defined(STM32F401xE) 02895 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 02896 * @brief Enable or disable the AHB1 peripheral clock. 02897 * @note After reset, the peripheral clock (used for registers read/write access) 02898 * is disabled and the application software has to enable this clock before 02899 * using it. 02900 * @{ 02901 */ 02902 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 02903 __IO uint32_t tmpreg = 0x00U; \ 02904 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 02905 /* Delay after an RCC peripheral clock enabling */ \ 02906 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 02907 UNUSED(tmpreg); \ 02908 } while(0U) 02909 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 02910 __IO uint32_t tmpreg = 0x00U; \ 02911 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 02912 /* Delay after an RCC peripheral clock enabling */ \ 02913 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 02914 UNUSED(tmpreg); \ 02915 } while(0U) 02916 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 02917 __IO uint32_t tmpreg = 0x00U; \ 02918 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 02919 /* Delay after an RCC peripheral clock enabling */ \ 02920 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 02921 UNUSED(tmpreg); \ 02922 } while(0U) 02923 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 02924 __IO uint32_t tmpreg = 0x00U; \ 02925 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 02926 /* Delay after an RCC peripheral clock enabling */ \ 02927 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 02928 UNUSED(tmpreg); \ 02929 } while(0U) 02930 02931 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 02932 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 02933 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 02934 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 02935 /** 02936 * @} 02937 */ 02938 02939 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 02940 * @brief Get the enable or disable status of the AHB1 peripheral clock. 02941 * @note After reset, the peripheral clock (used for registers read/write access) 02942 * is disabled and the application software has to enable this clock before 02943 * using it. 02944 * @{ 02945 */ 02946 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 02947 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 02948 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 02949 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 02950 02951 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 02952 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 02953 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 02954 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 02955 /** 02956 * @} 02957 */ 02958 02959 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 02960 * @brief Enable or disable the AHB2 peripheral clock. 02961 * @note After reset, the peripheral clock (used for registers read/write access) 02962 * is disabled and the application software has to enable this clock before 02963 * using it. 02964 * @{ 02965 */ 02966 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 02967 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 02968 }while(0U) 02969 02970 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 02971 /** 02972 * @} 02973 */ 02974 02975 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 02976 * @brief Get the enable or disable status of the AHB2 peripheral clock. 02977 * @note After reset, the peripheral clock (used for registers read/write access) 02978 * is disabled and the application software has to enable this clock before 02979 * using it. 02980 * @{ 02981 */ 02982 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 02983 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 02984 /** 02985 * @} 02986 */ 02987 02988 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 02989 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 02990 * @note After reset, the peripheral clock (used for registers read/write access) 02991 * is disabled and the application software has to enable this clock before 02992 * using it. 02993 * @{ 02994 */ 02995 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 02996 __IO uint32_t tmpreg = 0x00U; \ 02997 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 02998 /* Delay after an RCC peripheral clock enabling */ \ 02999 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 03000 UNUSED(tmpreg); \ 03001 } while(0U) 03002 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 03003 __IO uint32_t tmpreg = 0x00U; \ 03004 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 03005 /* Delay after an RCC peripheral clock enabling */ \ 03006 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 03007 UNUSED(tmpreg); \ 03008 } while(0U) 03009 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 03010 __IO uint32_t tmpreg = 0x00U; \ 03011 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 03012 /* Delay after an RCC peripheral clock enabling */ \ 03013 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 03014 UNUSED(tmpreg); \ 03015 } while(0U) 03016 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 03017 __IO uint32_t tmpreg = 0x00U; \ 03018 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 03019 /* Delay after an RCC peripheral clock enabling */ \ 03020 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 03021 UNUSED(tmpreg); \ 03022 } while(0U) 03023 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 03024 __IO uint32_t tmpreg = 0x00U; \ 03025 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 03026 /* Delay after an RCC peripheral clock enabling */ \ 03027 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 03028 UNUSED(tmpreg); \ 03029 } while(0U) 03030 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 03031 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 03032 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 03033 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 03034 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 03035 /** 03036 * @} 03037 */ 03038 03039 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 03040 * @brief Get the enable or disable status of the APB1 peripheral clock. 03041 * @note After reset, the peripheral clock (used for registers read/write access) 03042 * is disabled and the application software has to enable this clock before 03043 * using it. 03044 * @{ 03045 */ 03046 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 03047 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 03048 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 03049 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 03050 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 03051 03052 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 03053 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 03054 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 03055 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 03056 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 03057 /** 03058 * @} 03059 */ 03060 03061 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 03062 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 03063 * @note After reset, the peripheral clock (used for registers read/write access) 03064 * is disabled and the application software has to enable this clock before 03065 * using it. 03066 * @{ 03067 */ 03068 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 03069 __IO uint32_t tmpreg = 0x00U; \ 03070 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 03071 /* Delay after an RCC peripheral clock enabling */ \ 03072 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 03073 UNUSED(tmpreg); \ 03074 } while(0U) 03075 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 03076 __IO uint32_t tmpreg = 0x00U; \ 03077 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 03078 /* Delay after an RCC peripheral clock enabling */ \ 03079 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 03080 UNUSED(tmpreg); \ 03081 } while(0U) 03082 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 03083 __IO uint32_t tmpreg = 0x00U; \ 03084 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 03085 /* Delay after an RCC peripheral clock enabling */ \ 03086 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 03087 UNUSED(tmpreg); \ 03088 } while(0U) 03089 03090 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 03091 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 03092 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 03093 /** 03094 * @} 03095 */ 03096 03097 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 03098 * @brief Get the enable or disable status of the APB2 peripheral clock. 03099 * @note After reset, the peripheral clock (used for registers read/write access) 03100 * is disabled and the application software has to enable this clock before 03101 * using it. 03102 * @{ 03103 */ 03104 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 03105 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 03106 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 03107 03108 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 03109 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 03110 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 03111 /** 03112 * @} 03113 */ 03114 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 03115 * @brief Force or release AHB1 peripheral reset. 03116 * @{ 03117 */ 03118 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) 03119 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 03120 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 03121 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 03122 03123 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) 03124 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 03125 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 03126 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 03127 /** 03128 * @} 03129 */ 03130 03131 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 03132 * @brief Force or release AHB2 peripheral reset. 03133 * @{ 03134 */ 03135 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 03136 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 03137 03138 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 03139 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 03140 /** 03141 * @} 03142 */ 03143 03144 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 03145 * @brief Force or release APB1 peripheral reset. 03146 * @{ 03147 */ 03148 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) 03149 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 03150 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 03151 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 03152 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 03153 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 03154 03155 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) 03156 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 03157 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 03158 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 03159 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 03160 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 03161 /** 03162 * @} 03163 */ 03164 03165 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 03166 * @brief Force or release APB2 peripheral reset. 03167 * @{ 03168 */ 03169 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 03170 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 03171 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 03172 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 03173 03174 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) 03175 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 03176 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 03177 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 03178 /** 03179 * @} 03180 */ 03181 03182 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 03183 * @brief Force or release AHB3 peripheral reset. 03184 * @{ 03185 */ 03186 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 03187 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 03188 /** 03189 * @} 03190 */ 03191 03192 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 03193 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 03194 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03195 * power consumption. 03196 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 03197 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03198 * @{ 03199 */ 03200 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 03201 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 03202 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 03203 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 03204 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 03205 03206 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 03207 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 03208 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 03209 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 03210 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 03211 /** 03212 * @} 03213 */ 03214 03215 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 03216 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 03217 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03218 * power consumption. 03219 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 03220 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03221 * @{ 03222 */ 03223 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 03224 03225 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 03226 /** 03227 * @} 03228 */ 03229 03230 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 03231 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 03232 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03233 * power consumption. 03234 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 03235 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03236 * @{ 03237 */ 03238 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 03239 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 03240 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 03241 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 03242 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 03243 03244 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 03245 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 03246 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 03247 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 03248 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 03249 /** 03250 * @} 03251 */ 03252 03253 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 03254 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 03255 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03256 * power consumption. 03257 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 03258 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03259 * @{ 03260 */ 03261 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 03262 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 03263 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 03264 03265 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 03266 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 03267 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 03268 /** 03269 * @} 03270 */ 03271 #endif /* STM32F401xC || STM32F401xE*/ 03272 /*----------------------------------------------------------------------------*/ 03273 03274 /*-------------------------------- STM32F410xx -------------------------------*/ 03275 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 03276 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 03277 * @brief Enables or disables the AHB1 peripheral clock. 03278 * @note After reset, the peripheral clock (used for registers read/write access) 03279 * is disabled and the application software has to enable this clock before 03280 * using it. 03281 * @{ 03282 */ 03283 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 03284 __IO uint32_t tmpreg = 0x00U; \ 03285 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 03286 /* Delay after an RCC peripheral clock enabling */ \ 03287 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 03288 UNUSED(tmpreg); \ 03289 } while(0U) 03290 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 03291 __IO uint32_t tmpreg = 0x00U; \ 03292 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ 03293 /* Delay after an RCC peripheral clock enabling */ \ 03294 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ 03295 UNUSED(tmpreg); \ 03296 } while(0U) 03297 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 03298 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN)) 03299 /** 03300 * @} 03301 */ 03302 03303 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 03304 * @brief Get the enable or disable status of the AHB1 peripheral clock. 03305 * @note After reset, the peripheral clock (used for registers read/write access) 03306 * is disabled and the application software has to enable this clock before 03307 * using it. 03308 * @{ 03309 */ 03310 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 03311 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET) 03312 03313 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 03314 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET) 03315 /** 03316 * @} 03317 */ 03318 03319 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 03320 * @brief Enable or disable the High Speed APB (APB1) peripheral clock. 03321 * @{ 03322 */ 03323 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 03324 __IO uint32_t tmpreg = 0x00U; \ 03325 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 03326 /* Delay after an RCC peripheral clock enabling */ \ 03327 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 03328 UNUSED(tmpreg); \ 03329 } while(0U) 03330 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 03331 __IO uint32_t tmpreg = 0x00U; \ 03332 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 03333 /* Delay after an RCC peripheral clock enabling */ \ 03334 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 03335 UNUSED(tmpreg); \ 03336 } while(0U) 03337 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 03338 __IO uint32_t tmpreg = 0x00U; \ 03339 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 03340 /* Delay after an RCC peripheral clock enabling */ \ 03341 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 03342 UNUSED(tmpreg); \ 03343 } while(0U) 03344 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ 03345 __IO uint32_t tmpreg = 0x00U; \ 03346 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 03347 /* Delay after an RCC peripheral clock enabling */ \ 03348 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 03349 UNUSED(tmpreg); \ 03350 } while(0U) 03351 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 03352 __IO uint32_t tmpreg = 0x00U; \ 03353 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 03354 /* Delay after an RCC peripheral clock enabling */ \ 03355 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 03356 UNUSED(tmpreg); \ 03357 } while(0U) 03358 03359 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 03360 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) 03361 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) 03362 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) 03363 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 03364 /** 03365 * @} 03366 */ 03367 03368 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 03369 * @brief Get the enable or disable status of the APB1 peripheral clock. 03370 * @note After reset, the peripheral clock (used for registers read/write access) 03371 * is disabled and the application software has to enable this clock before 03372 * using it. 03373 * @{ 03374 */ 03375 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 03376 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) 03377 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 03378 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) 03379 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 03380 03381 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 03382 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) 03383 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 03384 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) 03385 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 03386 /** 03387 * @} 03388 */ 03389 03390 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 03391 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 03392 * @{ 03393 */ 03394 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 03395 __IO uint32_t tmpreg = 0x00U; \ 03396 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 03397 /* Delay after an RCC peripheral clock enabling */ \ 03398 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 03399 UNUSED(tmpreg); \ 03400 } while(0U) 03401 #define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ 03402 __IO uint32_t tmpreg = 0x00U; \ 03403 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 03404 /* Delay after an RCC peripheral clock enabling */ \ 03405 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 03406 UNUSED(tmpreg); \ 03407 } while(0U) 03408 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 03409 #define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) 03410 /** 03411 * @} 03412 */ 03413 03414 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 03415 * @brief Get the enable or disable status of the APB2 peripheral clock. 03416 * @note After reset, the peripheral clock (used for registers read/write access) 03417 * is disabled and the application software has to enable this clock before 03418 * using it. 03419 * @{ 03420 */ 03421 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 03422 #define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) 03423 03424 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 03425 #define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) 03426 /** 03427 * @} 03428 */ 03429 03430 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 03431 * @brief Force or release AHB1 peripheral reset. 03432 * @{ 03433 */ 03434 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 03435 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST)) 03436 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 03437 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST)) 03438 /** 03439 * @} 03440 */ 03441 03442 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 03443 * @brief Force or release AHB2 peripheral reset. 03444 * @{ 03445 */ 03446 #define __HAL_RCC_AHB2_FORCE_RESET() 03447 #define __HAL_RCC_AHB2_RELEASE_RESET() 03448 /** 03449 * @} 03450 */ 03451 03452 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 03453 * @brief Force or release AHB3 peripheral reset. 03454 * @{ 03455 */ 03456 #define __HAL_RCC_AHB3_FORCE_RESET() 03457 #define __HAL_RCC_AHB3_RELEASE_RESET() 03458 /** 03459 * @} 03460 */ 03461 03462 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 03463 * @brief Force or release APB1 peripheral reset. 03464 * @{ 03465 */ 03466 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 03467 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) 03468 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) 03469 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 03470 03471 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 03472 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) 03473 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) 03474 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 03475 /** 03476 * @} 03477 */ 03478 03479 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 03480 * @brief Force or release APB2 peripheral reset. 03481 * @{ 03482 */ 03483 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 03484 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 03485 /** 03486 * @} 03487 */ 03488 03489 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 03490 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 03491 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03492 * power consumption. 03493 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 03494 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03495 * @{ 03496 */ 03497 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN)) 03498 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 03499 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 03500 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 03501 03502 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN)) 03503 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 03504 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 03505 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 03506 /** 03507 * @} 03508 */ 03509 03510 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 03511 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 03512 * @{ 03513 */ 03514 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 03515 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) 03516 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) 03517 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) 03518 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 03519 03520 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 03521 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) 03522 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) 03523 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) 03524 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 03525 /** 03526 * @} 03527 */ 03528 03529 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 03530 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 03531 * @{ 03532 */ 03533 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 03534 #define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) 03535 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 03536 #define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) 03537 /** 03538 * @} 03539 */ 03540 03541 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 03542 /*----------------------------------------------------------------------------*/ 03543 03544 /*-------------------------------- STM32F411xx -------------------------------*/ 03545 #if defined(STM32F411xE) 03546 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 03547 * @brief Enables or disables the AHB1 peripheral clock. 03548 * @note After reset, the peripheral clock (used for registers read/write access) 03549 * is disabled and the application software has to enable this clock before 03550 * using it. 03551 * @{ 03552 */ 03553 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 03554 __IO uint32_t tmpreg = 0x00U; \ 03555 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 03556 /* Delay after an RCC peripheral clock enabling */ \ 03557 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 03558 UNUSED(tmpreg); \ 03559 } while(0U) 03560 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 03561 __IO uint32_t tmpreg = 0x00U; \ 03562 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 03563 /* Delay after an RCC peripheral clock enabling */ \ 03564 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 03565 UNUSED(tmpreg); \ 03566 } while(0U) 03567 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 03568 __IO uint32_t tmpreg = 0x00U; \ 03569 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 03570 /* Delay after an RCC peripheral clock enabling */ \ 03571 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 03572 UNUSED(tmpreg); \ 03573 } while(0U) 03574 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 03575 __IO uint32_t tmpreg = 0x00U; \ 03576 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 03577 /* Delay after an RCC peripheral clock enabling */ \ 03578 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 03579 UNUSED(tmpreg); \ 03580 } while(0U) 03581 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 03582 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 03583 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 03584 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 03585 /** 03586 * @} 03587 */ 03588 03589 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 03590 * @brief Get the enable or disable status of the AHB1 peripheral clock. 03591 * @note After reset, the peripheral clock (used for registers read/write access) 03592 * is disabled and the application software has to enable this clock before 03593 * using it. 03594 * @{ 03595 */ 03596 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 03597 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 03598 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 03599 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 03600 03601 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 03602 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 03603 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 03604 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 03605 /** 03606 * @} 03607 */ 03608 03609 /** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 03610 * @brief Enable or disable the AHB2 peripheral clock. 03611 * @note After reset, the peripheral clock (used for registers read/write access) 03612 * is disabled and the application software has to enable this clock before 03613 * using it. 03614 * @{ 03615 */ 03616 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 03617 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 03618 }while(0U) 03619 03620 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 03621 /** 03622 * @} 03623 */ 03624 03625 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 03626 * @brief Get the enable or disable status of the AHB2 peripheral clock. 03627 * @note After reset, the peripheral clock (used for registers read/write access) 03628 * is disabled and the application software has to enable this clock before 03629 * using it. 03630 * @{ 03631 */ 03632 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 03633 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 03634 /** 03635 * @} 03636 */ 03637 03638 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 03639 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 03640 * @note After reset, the peripheral clock (used for registers read/write access) 03641 * is disabled and the application software has to enable this clock before 03642 * using it. 03643 * @{ 03644 */ 03645 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 03646 __IO uint32_t tmpreg = 0x00U; \ 03647 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 03648 /* Delay after an RCC peripheral clock enabling */ \ 03649 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 03650 UNUSED(tmpreg); \ 03651 } while(0U) 03652 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 03653 __IO uint32_t tmpreg = 0x00U; \ 03654 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 03655 /* Delay after an RCC peripheral clock enabling */ \ 03656 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 03657 UNUSED(tmpreg); \ 03658 } while(0U) 03659 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 03660 __IO uint32_t tmpreg = 0x00U; \ 03661 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 03662 /* Delay after an RCC peripheral clock enabling */ \ 03663 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 03664 UNUSED(tmpreg); \ 03665 } while(0U) 03666 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 03667 __IO uint32_t tmpreg = 0x00U; \ 03668 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 03669 /* Delay after an RCC peripheral clock enabling */ \ 03670 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 03671 UNUSED(tmpreg); \ 03672 } while(0U) 03673 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 03674 __IO uint32_t tmpreg = 0x00U; \ 03675 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 03676 /* Delay after an RCC peripheral clock enabling */ \ 03677 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 03678 UNUSED(tmpreg); \ 03679 } while(0U) 03680 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 03681 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 03682 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 03683 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 03684 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 03685 /** 03686 * @} 03687 */ 03688 03689 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 03690 * @brief Get the enable or disable status of the APB1 peripheral clock. 03691 * @note After reset, the peripheral clock (used for registers read/write access) 03692 * is disabled and the application software has to enable this clock before 03693 * using it. 03694 * @{ 03695 */ 03696 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 03697 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 03698 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 03699 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 03700 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 03701 03702 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 03703 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 03704 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 03705 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 03706 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 03707 /** 03708 * @} 03709 */ 03710 03711 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 03712 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 03713 * @{ 03714 */ 03715 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 03716 __IO uint32_t tmpreg = 0x00U; \ 03717 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 03718 /* Delay after an RCC peripheral clock enabling */ \ 03719 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 03720 UNUSED(tmpreg); \ 03721 } while(0U) 03722 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 03723 __IO uint32_t tmpreg = 0x00U; \ 03724 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 03725 /* Delay after an RCC peripheral clock enabling */ \ 03726 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 03727 UNUSED(tmpreg); \ 03728 } while(0U) 03729 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 03730 __IO uint32_t tmpreg = 0x00U; \ 03731 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 03732 /* Delay after an RCC peripheral clock enabling */ \ 03733 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 03734 UNUSED(tmpreg); \ 03735 } while(0U) 03736 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 03737 __IO uint32_t tmpreg = 0x00U; \ 03738 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 03739 /* Delay after an RCC peripheral clock enabling */ \ 03740 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 03741 UNUSED(tmpreg); \ 03742 } while(0U) 03743 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 03744 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 03745 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 03746 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 03747 /** 03748 * @} 03749 */ 03750 03751 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 03752 * @brief Get the enable or disable status of the APB2 peripheral clock. 03753 * @note After reset, the peripheral clock (used for registers read/write access) 03754 * is disabled and the application software has to enable this clock before 03755 * using it. 03756 * @{ 03757 */ 03758 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 03759 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 03760 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 03761 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 03762 03763 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 03764 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 03765 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 03766 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 03767 /** 03768 * @} 03769 */ 03770 03771 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 03772 * @brief Force or release AHB1 peripheral reset. 03773 * @{ 03774 */ 03775 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 03776 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 03777 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 03778 03779 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 03780 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 03781 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 03782 /** 03783 * @} 03784 */ 03785 03786 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 03787 * @brief Force or release AHB2 peripheral reset. 03788 * @{ 03789 */ 03790 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 03791 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 03792 03793 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 03794 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 03795 /** 03796 * @} 03797 */ 03798 03799 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 03800 * @brief Force or release AHB3 peripheral reset. 03801 * @{ 03802 */ 03803 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 03804 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 03805 /** 03806 * @} 03807 */ 03808 03809 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 03810 * @brief Force or release APB1 peripheral reset. 03811 * @{ 03812 */ 03813 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 03814 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 03815 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 03816 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 03817 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 03818 03819 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 03820 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 03821 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 03822 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 03823 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 03824 /** 03825 * @} 03826 */ 03827 03828 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 03829 * @brief Force or release APB2 peripheral reset. 03830 * @{ 03831 */ 03832 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 03833 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 03834 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 03835 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 03836 03837 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 03838 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 03839 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 03840 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 03841 /** 03842 * @} 03843 */ 03844 03845 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 03846 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 03847 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03848 * power consumption. 03849 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 03850 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03851 * @{ 03852 */ 03853 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 03854 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 03855 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 03856 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 03857 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 03858 03859 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 03860 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 03861 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 03862 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 03863 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 03864 /** 03865 * @} 03866 */ 03867 03868 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 03869 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 03870 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 03871 * power consumption. 03872 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 03873 * @note By default, all peripheral clocks are enabled during SLEEP mode. 03874 * @{ 03875 */ 03876 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 03877 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 03878 /** 03879 * @} 03880 */ 03881 03882 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 03883 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 03884 * @{ 03885 */ 03886 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 03887 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 03888 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 03889 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 03890 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 03891 03892 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 03893 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 03894 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 03895 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 03896 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 03897 /** 03898 * @} 03899 */ 03900 03901 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 03902 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 03903 * @{ 03904 */ 03905 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 03906 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 03907 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 03908 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 03909 03910 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 03911 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 03912 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 03913 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 03914 /** 03915 * @} 03916 */ 03917 #endif /* STM32F411xE */ 03918 /*----------------------------------------------------------------------------*/ 03919 03920 /*---------------------------------- STM32F446xx -----------------------------*/ 03921 #if defined(STM32F446xx) 03922 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 03923 * @brief Enables or disables the AHB1 peripheral clock. 03924 * @note After reset, the peripheral clock (used for registers read/write access) 03925 * is disabled and the application software has to enable this clock before 03926 * using it. 03927 * @{ 03928 */ 03929 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 03930 __IO uint32_t tmpreg = 0x00U; \ 03931 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 03932 /* Delay after an RCC peripheral clock enabling */ \ 03933 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 03934 UNUSED(tmpreg); \ 03935 } while(0U) 03936 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ 03937 __IO uint32_t tmpreg = 0x00U; \ 03938 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 03939 /* Delay after an RCC peripheral clock enabling */ \ 03940 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 03941 UNUSED(tmpreg); \ 03942 } while(0U) 03943 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 03944 __IO uint32_t tmpreg = 0x00U; \ 03945 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 03946 /* Delay after an RCC peripheral clock enabling */ \ 03947 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 03948 UNUSED(tmpreg); \ 03949 } while(0U) 03950 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 03951 __IO uint32_t tmpreg = 0x00U; \ 03952 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 03953 /* Delay after an RCC peripheral clock enabling */ \ 03954 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 03955 UNUSED(tmpreg); \ 03956 } while(0U) 03957 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 03958 __IO uint32_t tmpreg = 0x00U; \ 03959 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 03960 /* Delay after an RCC peripheral clock enabling */ \ 03961 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 03962 UNUSED(tmpreg); \ 03963 } while(0U) 03964 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 03965 __IO uint32_t tmpreg = 0x00U; \ 03966 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 03967 /* Delay after an RCC peripheral clock enabling */ \ 03968 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 03969 UNUSED(tmpreg); \ 03970 } while(0U) 03971 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 03972 __IO uint32_t tmpreg = 0x00U; \ 03973 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 03974 /* Delay after an RCC peripheral clock enabling */ \ 03975 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 03976 UNUSED(tmpreg); \ 03977 } while(0U) 03978 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 03979 __IO uint32_t tmpreg = 0x00U; \ 03980 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 03981 /* Delay after an RCC peripheral clock enabling */ \ 03982 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 03983 UNUSED(tmpreg); \ 03984 } while(0U) 03985 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ 03986 __IO uint32_t tmpreg = 0x00U; \ 03987 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 03988 /* Delay after an RCC peripheral clock enabling */ \ 03989 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 03990 UNUSED(tmpreg); \ 03991 } while(0U) 03992 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 03993 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 03994 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 03995 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 03996 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 03997 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 03998 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 03999 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) 04000 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 04001 /** 04002 * @} 04003 */ 04004 04005 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 04006 * @brief Get the enable or disable status of the AHB1 peripheral clock. 04007 * @note After reset, the peripheral clock (used for registers read/write access) 04008 * is disabled and the application software has to enable this clock before 04009 * using it. 04010 * @{ 04011 */ 04012 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 04013 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 04014 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 04015 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 04016 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) 04017 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 04018 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) 04019 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET) 04020 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 04021 04022 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 04023 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 04024 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 04025 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 04026 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) 04027 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) 04028 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) 04029 #define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 04030 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 04031 /** 04032 * @} 04033 */ 04034 04035 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 04036 * @brief Enable or disable the AHB2 peripheral clock. 04037 * @note After reset, the peripheral clock (used for registers read/write access) 04038 * is disabled and the application software has to enable this clock before 04039 * using it. 04040 * @{ 04041 */ 04042 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ 04043 __IO uint32_t tmpreg = 0x00U; \ 04044 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 04045 /* Delay after an RCC peripheral clock enabling */ \ 04046 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ 04047 UNUSED(tmpreg); \ 04048 } while(0U) 04049 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) 04050 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 04051 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 04052 }while(0U) 04053 04054 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 04055 04056 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 04057 __IO uint32_t tmpreg = 0x00U; \ 04058 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 04059 /* Delay after an RCC peripheral clock enabling */ \ 04060 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 04061 UNUSED(tmpreg); \ 04062 } while(0U) 04063 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 04064 /** 04065 * @} 04066 */ 04067 04068 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 04069 * @brief Get the enable or disable status of the AHB2 peripheral clock. 04070 * @note After reset, the peripheral clock (used for registers read/write access) 04071 * is disabled and the application software has to enable this clock before 04072 * using it. 04073 * @{ 04074 */ 04075 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 04076 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 04077 04078 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 04079 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 04080 04081 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 04082 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 04083 /** 04084 * @} 04085 */ 04086 04087 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 04088 * @brief Enables or disables the AHB3 peripheral clock. 04089 * @note After reset, the peripheral clock (used for registers read/write access) 04090 * is disabled and the application software has to enable this clock before 04091 * using it. 04092 * @{ 04093 */ 04094 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 04095 __IO uint32_t tmpreg = 0x00U; \ 04096 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 04097 /* Delay after an RCC peripheral clock enabling */ \ 04098 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 04099 UNUSED(tmpreg); \ 04100 } while(0U) 04101 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 04102 __IO uint32_t tmpreg = 0x00U; \ 04103 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 04104 /* Delay after an RCC peripheral clock enabling */ \ 04105 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 04106 UNUSED(tmpreg); \ 04107 } while(0U) 04108 04109 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) 04110 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) 04111 /** 04112 * @} 04113 */ 04114 04115 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 04116 * @brief Get the enable or disable status of the AHB3 peripheral clock. 04117 * @note After reset, the peripheral clock (used for registers read/write access) 04118 * is disabled and the application software has to enable this clock before 04119 * using it. 04120 * @{ 04121 */ 04122 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) 04123 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 04124 04125 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) 04126 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) 04127 /** 04128 * @} 04129 */ 04130 04131 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 04132 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 04133 * @note After reset, the peripheral clock (used for registers read/write access) 04134 * is disabled and the application software has to enable this clock before 04135 * using it. 04136 * @{ 04137 */ 04138 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 04139 __IO uint32_t tmpreg = 0x00U; \ 04140 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 04141 /* Delay after an RCC peripheral clock enabling */ \ 04142 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 04143 UNUSED(tmpreg); \ 04144 } while(0U) 04145 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 04146 __IO uint32_t tmpreg = 0x00U; \ 04147 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 04148 /* Delay after an RCC peripheral clock enabling */ \ 04149 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 04150 UNUSED(tmpreg); \ 04151 } while(0U) 04152 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 04153 __IO uint32_t tmpreg = 0x00U; \ 04154 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 04155 /* Delay after an RCC peripheral clock enabling */ \ 04156 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 04157 UNUSED(tmpreg); \ 04158 } while(0U) 04159 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 04160 __IO uint32_t tmpreg = 0x00U; \ 04161 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 04162 /* Delay after an RCC peripheral clock enabling */ \ 04163 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 04164 UNUSED(tmpreg); \ 04165 } while(0U) 04166 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 04167 __IO uint32_t tmpreg = 0x00U; \ 04168 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 04169 /* Delay after an RCC peripheral clock enabling */ \ 04170 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 04171 UNUSED(tmpreg); \ 04172 } while(0U) 04173 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ 04174 __IO uint32_t tmpreg = 0x00U; \ 04175 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ 04176 /* Delay after an RCC peripheral clock enabling */ \ 04177 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ 04178 UNUSED(tmpreg); \ 04179 } while(0U) 04180 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 04181 __IO uint32_t tmpreg = 0x00U; \ 04182 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 04183 /* Delay after an RCC peripheral clock enabling */ \ 04184 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 04185 UNUSED(tmpreg); \ 04186 } while(0U) 04187 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 04188 __IO uint32_t tmpreg = 0x00U; \ 04189 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 04190 /* Delay after an RCC peripheral clock enabling */ \ 04191 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 04192 UNUSED(tmpreg); \ 04193 } while(0U) 04194 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 04195 __IO uint32_t tmpreg = 0x00U; \ 04196 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 04197 /* Delay after an RCC peripheral clock enabling */ \ 04198 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 04199 UNUSED(tmpreg); \ 04200 } while(0U) 04201 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ 04202 __IO uint32_t tmpreg = 0x00U; \ 04203 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 04204 /* Delay after an RCC peripheral clock enabling */ \ 04205 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 04206 UNUSED(tmpreg); \ 04207 } while(0U) 04208 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 04209 __IO uint32_t tmpreg = 0x00U; \ 04210 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 04211 /* Delay after an RCC peripheral clock enabling */ \ 04212 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 04213 UNUSED(tmpreg); \ 04214 } while(0U) 04215 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 04216 __IO uint32_t tmpreg = 0x00U; \ 04217 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 04218 /* Delay after an RCC peripheral clock enabling */ \ 04219 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 04220 UNUSED(tmpreg); \ 04221 } while(0U) 04222 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 04223 __IO uint32_t tmpreg = 0x00U; \ 04224 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 04225 /* Delay after an RCC peripheral clock enabling */ \ 04226 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 04227 UNUSED(tmpreg); \ 04228 } while(0U) 04229 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 04230 __IO uint32_t tmpreg = 0x00U; \ 04231 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 04232 /* Delay after an RCC peripheral clock enabling */ \ 04233 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 04234 UNUSED(tmpreg); \ 04235 } while(0U) 04236 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 04237 __IO uint32_t tmpreg = 0x00U; \ 04238 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 04239 /* Delay after an RCC peripheral clock enabling */ \ 04240 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 04241 UNUSED(tmpreg); \ 04242 } while(0U) 04243 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 04244 __IO uint32_t tmpreg = 0x00U; \ 04245 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 04246 /* Delay after an RCC peripheral clock enabling */ \ 04247 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 04248 UNUSED(tmpreg); \ 04249 } while(0U) 04250 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 04251 __IO uint32_t tmpreg = 0x00U; \ 04252 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 04253 /* Delay after an RCC peripheral clock enabling */ \ 04254 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 04255 UNUSED(tmpreg); \ 04256 } while(0U) 04257 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 04258 __IO uint32_t tmpreg = 0x00U; \ 04259 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 04260 /* Delay after an RCC peripheral clock enabling */ \ 04261 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 04262 UNUSED(tmpreg); \ 04263 } while(0U) 04264 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 04265 __IO uint32_t tmpreg = 0x00U; \ 04266 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 04267 /* Delay after an RCC peripheral clock enabling */ \ 04268 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 04269 UNUSED(tmpreg); \ 04270 } while(0U) 04271 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 04272 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 04273 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 04274 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 04275 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 04276 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 04277 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 04278 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 04279 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 04280 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 04281 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) 04282 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 04283 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 04284 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 04285 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) 04286 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 04287 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 04288 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) 04289 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 04290 /** 04291 * @} 04292 */ 04293 04294 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 04295 * @brief Get the enable or disable status of the APB1 peripheral clock. 04296 * @note After reset, the peripheral clock (used for registers read/write access) 04297 * is disabled and the application software has to enable this clock before 04298 * using it. 04299 * @{ 04300 */ 04301 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 04302 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 04303 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 04304 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 04305 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 04306 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 04307 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 04308 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 04309 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 04310 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 04311 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) 04312 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 04313 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 04314 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 04315 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) 04316 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 04317 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 04318 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) 04319 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 04320 04321 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 04322 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 04323 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 04324 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 04325 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 04326 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 04327 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 04328 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 04329 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 04330 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 04331 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) 04332 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 04333 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 04334 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 04335 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) 04336 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 04337 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 04338 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) 04339 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 04340 /** 04341 * @} 04342 */ 04343 04344 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 04345 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 04346 * @note After reset, the peripheral clock (used for registers read/write access) 04347 * is disabled and the application software has to enable this clock before 04348 * using it. 04349 * @{ 04350 */ 04351 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 04352 __IO uint32_t tmpreg = 0x00U; \ 04353 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 04354 /* Delay after an RCC peripheral clock enabling */ \ 04355 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 04356 UNUSED(tmpreg); \ 04357 } while(0U) 04358 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 04359 __IO uint32_t tmpreg = 0x00U; \ 04360 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 04361 /* Delay after an RCC peripheral clock enabling */ \ 04362 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 04363 UNUSED(tmpreg); \ 04364 } while(0U) 04365 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 04366 __IO uint32_t tmpreg = 0x00U; \ 04367 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 04368 /* Delay after an RCC peripheral clock enabling */ \ 04369 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 04370 UNUSED(tmpreg); \ 04371 } while(0U) 04372 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 04373 __IO uint32_t tmpreg = 0x00U; \ 04374 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 04375 /* Delay after an RCC peripheral clock enabling */ \ 04376 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 04377 UNUSED(tmpreg); \ 04378 } while(0U) 04379 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 04380 __IO uint32_t tmpreg = 0x00U; \ 04381 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ 04382 /* Delay after an RCC peripheral clock enabling */ \ 04383 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ 04384 UNUSED(tmpreg); \ 04385 } while(0U) 04386 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 04387 __IO uint32_t tmpreg = 0x00U; \ 04388 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 04389 /* Delay after an RCC peripheral clock enabling */ \ 04390 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 04391 UNUSED(tmpreg); \ 04392 } while(0U) 04393 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 04394 __IO uint32_t tmpreg = 0x00U; \ 04395 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 04396 /* Delay after an RCC peripheral clock enabling */ \ 04397 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 04398 UNUSED(tmpreg); \ 04399 } while(0U) 04400 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 04401 __IO uint32_t tmpreg = 0x00U; \ 04402 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 04403 /* Delay after an RCC peripheral clock enabling */ \ 04404 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 04405 UNUSED(tmpreg); \ 04406 } while(0U) 04407 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 04408 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 04409 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 04410 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 04411 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 04412 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 04413 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) 04414 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) 04415 /** 04416 * @} 04417 */ 04418 04419 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 04420 * @brief Get the enable or disable status of the APB2 peripheral clock. 04421 * @note After reset, the peripheral clock (used for registers read/write access) 04422 * is disabled and the application software has to enable this clock before 04423 * using it. 04424 * @{ 04425 */ 04426 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 04427 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 04428 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 04429 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 04430 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 04431 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 04432 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 04433 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) 04434 04435 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 04436 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 04437 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 04438 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 04439 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 04440 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 04441 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) 04442 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) 04443 /** 04444 * @} 04445 */ 04446 04447 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 04448 * @brief Force or release AHB1 peripheral reset. 04449 * @{ 04450 */ 04451 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 04452 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 04453 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 04454 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 04455 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 04456 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 04457 04458 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 04459 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 04460 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 04461 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 04462 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 04463 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 04464 /** 04465 * @} 04466 */ 04467 04468 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 04469 * @brief Force or release AHB2 peripheral reset. 04470 * @{ 04471 */ 04472 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 04473 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 04474 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 04475 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) 04476 04477 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 04478 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 04479 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 04480 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) 04481 /** 04482 * @} 04483 */ 04484 04485 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 04486 * @brief Force or release AHB3 peripheral reset. 04487 * @{ 04488 */ 04489 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 04490 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 04491 04492 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) 04493 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 04494 04495 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) 04496 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) 04497 /** 04498 * @} 04499 */ 04500 04501 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 04502 * @brief Force or release APB1 peripheral reset. 04503 * @{ 04504 */ 04505 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 04506 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 04507 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 04508 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 04509 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 04510 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) 04511 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 04512 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 04513 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 04514 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) 04515 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 04516 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 04517 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) 04518 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 04519 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 04520 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 04521 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 04522 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 04523 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 04524 04525 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 04526 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 04527 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 04528 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 04529 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 04530 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 04531 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 04532 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 04533 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 04534 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 04535 #define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) 04536 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 04537 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 04538 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 04539 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) 04540 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 04541 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 04542 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) 04543 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 04544 /** 04545 * @} 04546 */ 04547 04548 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 04549 * @brief Force or release APB2 peripheral reset. 04550 * @{ 04551 */ 04552 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 04553 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 04554 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) 04555 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 04556 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 04557 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 04558 04559 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 04560 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 04561 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 04562 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 04563 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) 04564 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) 04565 /** 04566 * @} 04567 */ 04568 04569 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 04570 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 04571 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 04572 * power consumption. 04573 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 04574 * @note By default, all peripheral clocks are enabled during SLEEP mode. 04575 * @{ 04576 */ 04577 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 04578 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 04579 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 04580 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 04581 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 04582 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 04583 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 04584 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 04585 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 04586 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 04587 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 04588 04589 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 04590 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 04591 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 04592 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 04593 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 04594 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 04595 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 04596 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 04597 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 04598 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 04599 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 04600 /** 04601 * @} 04602 */ 04603 04604 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 04605 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 04606 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 04607 * power consumption. 04608 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 04609 * @note By default, all peripheral clocks are enabled during SLEEP mode. 04610 * @{ 04611 */ 04612 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 04613 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 04614 04615 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 04616 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 04617 04618 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) 04619 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) 04620 /** 04621 * @} 04622 */ 04623 04624 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 04625 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 04626 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 04627 * power consumption. 04628 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 04629 * @note By default, all peripheral clocks are enabled during SLEEP mode. 04630 * @{ 04631 */ 04632 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) 04633 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 04634 04635 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) 04636 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) 04637 /** 04638 * @} 04639 */ 04640 04641 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 04642 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 04643 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 04644 * power consumption. 04645 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 04646 * @note By default, all peripheral clocks are enabled during SLEEP mode. 04647 * @{ 04648 */ 04649 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 04650 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 04651 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 04652 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 04653 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 04654 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) 04655 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 04656 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 04657 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 04658 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) 04659 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 04660 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 04661 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) 04662 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 04663 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 04664 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 04665 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 04666 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 04667 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 04668 04669 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 04670 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 04671 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 04672 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 04673 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 04674 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 04675 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 04676 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 04677 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 04678 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 04679 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) 04680 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 04681 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 04682 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 04683 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) 04684 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 04685 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 04686 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) 04687 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 04688 /** 04689 * @} 04690 */ 04691 04692 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 04693 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 04694 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 04695 * power consumption. 04696 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 04697 * @note By default, all peripheral clocks are enabled during SLEEP mode. 04698 * @{ 04699 */ 04700 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 04701 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 04702 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 04703 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) 04704 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) 04705 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 04706 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 04707 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 04708 04709 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 04710 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 04711 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 04712 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 04713 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 04714 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 04715 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) 04716 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) 04717 /** 04718 * @} 04719 */ 04720 04721 #endif /* STM32F446xx */ 04722 /*----------------------------------------------------------------------------*/ 04723 04724 /*-------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx-------*/ 04725 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 04726 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 04727 * @brief Enables or disables the AHB1 peripheral clock. 04728 * @note After reset, the peripheral clock (used for registers read/write access) 04729 * is disabled and the application software has to enable this clock before 04730 * using it. 04731 * @{ 04732 */ 04733 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 04734 __IO uint32_t tmpreg = 0x00U; \ 04735 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 04736 /* Delay after an RCC peripheral clock enabling */ \ 04737 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 04738 UNUSED(tmpreg); \ 04739 } while(0U) 04740 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 04741 __IO uint32_t tmpreg = 0x00U; \ 04742 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 04743 /* Delay after an RCC peripheral clock enabling */ \ 04744 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 04745 UNUSED(tmpreg); \ 04746 } while(0U) 04747 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 04748 __IO uint32_t tmpreg = 0x00U; \ 04749 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 04750 /* Delay after an RCC peripheral clock enabling */ \ 04751 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 04752 UNUSED(tmpreg); \ 04753 } while(0U) 04754 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 04755 __IO uint32_t tmpreg = 0x00U; \ 04756 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 04757 /* Delay after an RCC peripheral clock enabling */ \ 04758 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 04759 UNUSED(tmpreg); \ 04760 } while(0U) 04761 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 04762 __IO uint32_t tmpreg = 0x00U; \ 04763 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 04764 /* Delay after an RCC peripheral clock enabling */ \ 04765 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 04766 UNUSED(tmpreg); \ 04767 } while(0U) 04768 04769 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 04770 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 04771 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 04772 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 04773 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 04774 /** 04775 * @} 04776 */ 04777 04778 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 04779 * @brief Get the enable or disable status of the AHB1 peripheral clock. 04780 * @note After reset, the peripheral clock (used for registers read/write access) 04781 * is disabled and the application software has to enable this clock before 04782 * using it. 04783 * @{ 04784 */ 04785 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 04786 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 04787 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 04788 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 04789 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 04790 04791 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 04792 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 04793 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 04794 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 04795 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 04796 /** 04797 * @} 04798 */ 04799 04800 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 04801 * @brief Enable or disable the AHB2 peripheral clock. 04802 * @note After reset, the peripheral clock (used for registers read/write access) 04803 * is disabled and the application software has to enable this clock before 04804 * using it. 04805 * @{ 04806 */ 04807 #if defined(STM32F423xx) 04808 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 04809 __IO uint32_t tmpreg = 0x00U; \ 04810 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ 04811 /* Delay after an RCC peripheral clock enabling */ \ 04812 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ 04813 UNUSED(tmpreg); \ 04814 } while(0U) 04815 04816 #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) 04817 #endif /* STM32F423xx */ 04818 04819 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 04820 __IO uint32_t tmpreg = 0x00U; \ 04821 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 04822 /* Delay after an RCC peripheral clock enabling */ \ 04823 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 04824 UNUSED(tmpreg); \ 04825 } while(0U) 04826 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 04827 04828 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 04829 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 04830 }while(0U) 04831 04832 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 04833 /** 04834 * @} 04835 */ 04836 04837 /** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 04838 * @brief Get the enable or disable status of the AHB2 peripheral clock. 04839 * @note After reset, the peripheral clock (used for registers read/write access) 04840 * is disabled and the application software has to enable this clock before 04841 * using it. 04842 * @{ 04843 */ 04844 #if defined(STM32F423xx) 04845 #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) 04846 #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) 04847 #endif /* STM32F423xx */ 04848 04849 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) 04850 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 04851 04852 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 04853 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 04854 /** 04855 * @} 04856 */ 04857 04858 /** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 04859 * @brief Enables or disables the AHB3 peripheral clock. 04860 * @note After reset, the peripheral clock (used for registers read/write access) 04861 * is disabled and the application software has to enable this clock before 04862 * using it. 04863 * @{ 04864 */ 04865 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 04866 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ 04867 __IO uint32_t tmpreg = 0x00U; \ 04868 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 04869 /* Delay after an RCC peripheral clock enabling */ \ 04870 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 04871 UNUSED(tmpreg); \ 04872 } while(0U) 04873 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 04874 __IO uint32_t tmpreg = 0x00U; \ 04875 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 04876 /* Delay after an RCC peripheral clock enabling */ \ 04877 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 04878 UNUSED(tmpreg); \ 04879 } while(0U) 04880 04881 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) 04882 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) 04883 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 04884 /** 04885 * @} 04886 */ 04887 04888 /** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 04889 * @brief Get the enable or disable status of the AHB3 peripheral clock. 04890 * @note After reset, the peripheral clock (used for registers read/write access) 04891 * is disabled and the application software has to enable this clock before 04892 * using it. 04893 * @{ 04894 */ 04895 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 04896 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 04897 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 04898 04899 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) 04900 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) 04901 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 04902 04903 /** 04904 * @} 04905 */ 04906 04907 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 04908 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 04909 * @note After reset, the peripheral clock (used for registers read/write access) 04910 * is disabled and the application software has to enable this clock before 04911 * using it. 04912 * @{ 04913 */ 04914 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 04915 __IO uint32_t tmpreg = 0x00U; \ 04916 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 04917 /* Delay after an RCC peripheral clock enabling */ \ 04918 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 04919 UNUSED(tmpreg); \ 04920 } while(0U) 04921 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 04922 __IO uint32_t tmpreg = 0x00U; \ 04923 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 04924 /* Delay after an RCC peripheral clock enabling */ \ 04925 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 04926 UNUSED(tmpreg); \ 04927 } while(0U) 04928 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 04929 __IO uint32_t tmpreg = 0x00U; \ 04930 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 04931 /* Delay after an RCC peripheral clock enabling */ \ 04932 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 04933 UNUSED(tmpreg); \ 04934 } while(0U) 04935 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 04936 __IO uint32_t tmpreg = 0x00U; \ 04937 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 04938 /* Delay after an RCC peripheral clock enabling */ \ 04939 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 04940 UNUSED(tmpreg); \ 04941 } while(0U) 04942 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 04943 __IO uint32_t tmpreg = 0x00U; \ 04944 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 04945 /* Delay after an RCC peripheral clock enabling */ \ 04946 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 04947 UNUSED(tmpreg); \ 04948 } while(0U) 04949 #if defined(STM32F413xx) || defined(STM32F423xx) 04950 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 04951 __IO uint32_t tmpreg = 0x00U; \ 04952 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 04953 /* Delay after an RCC peripheral clock enabling */ \ 04954 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ 04955 UNUSED(tmpreg); \ 04956 } while(0U) 04957 #endif /* STM32F413xx || STM32F423xx */ 04958 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 04959 __IO uint32_t tmpreg = 0x00U; \ 04960 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 04961 /* Delay after an RCC peripheral clock enabling */ \ 04962 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ 04963 UNUSED(tmpreg); \ 04964 } while(0U) 04965 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 04966 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 04967 __IO uint32_t tmpreg = 0x00U; \ 04968 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 04969 /* Delay after an RCC peripheral clock enabling */ \ 04970 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 04971 UNUSED(tmpreg); \ 04972 } while(0U) 04973 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 04974 04975 #if defined(STM32F413xx) || defined(STM32F423xx) 04976 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 04977 __IO uint32_t tmpreg = 0x00U; \ 04978 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 04979 /* Delay after an RCC peripheral clock enabling */ \ 04980 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 04981 UNUSED(tmpreg); \ 04982 } while(0U) 04983 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 04984 __IO uint32_t tmpreg = 0x00U; \ 04985 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 04986 /* Delay after an RCC peripheral clock enabling */ \ 04987 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 04988 UNUSED(tmpreg); \ 04989 } while(0U) 04990 #endif /* STM32F413xx || STM32F423xx */ 04991 04992 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ 04993 __IO uint32_t tmpreg = 0x00U; \ 04994 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 04995 /* Delay after an RCC peripheral clock enabling */ \ 04996 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ 04997 UNUSED(tmpreg); \ 04998 } while(0U) 04999 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 05000 __IO uint32_t tmpreg = 0x00U; \ 05001 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 05002 /* Delay after an RCC peripheral clock enabling */ \ 05003 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 05004 UNUSED(tmpreg); \ 05005 } while(0U) 05006 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 05007 __IO uint32_t tmpreg = 0x00U; \ 05008 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 05009 /* Delay after an RCC peripheral clock enabling */ \ 05010 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 05011 UNUSED(tmpreg); \ 05012 } while(0U) 05013 #if defined(STM32F413xx) || defined(STM32F423xx) 05014 #define __HAL_RCC_CAN3_CLK_ENABLE() do { \ 05015 __IO uint32_t tmpreg = 0x00U; \ 05016 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ 05017 /* Delay after an RCC peripheral clock enabling */ \ 05018 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ 05019 UNUSED(tmpreg); \ 05020 } while(0U) 05021 #endif /* STM32F413xx || STM32F423xx */ 05022 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 05023 __IO uint32_t tmpreg = 0x00U; \ 05024 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 05025 /* Delay after an RCC peripheral clock enabling */ \ 05026 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 05027 UNUSED(tmpreg); \ 05028 } while(0U) 05029 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 05030 __IO uint32_t tmpreg = 0x00U; \ 05031 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 05032 /* Delay after an RCC peripheral clock enabling */ \ 05033 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 05034 UNUSED(tmpreg); \ 05035 } while(0U) 05036 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 05037 __IO uint32_t tmpreg = 0x00U; \ 05038 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 05039 /* Delay after an RCC peripheral clock enabling */ \ 05040 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 05041 UNUSED(tmpreg); \ 05042 } while(0U) 05043 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 05044 __IO uint32_t tmpreg = 0x00U; \ 05045 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 05046 /* Delay after an RCC peripheral clock enabling */ \ 05047 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 05048 UNUSED(tmpreg); \ 05049 } while(0U) 05050 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 05051 __IO uint32_t tmpreg = 0x00U; \ 05052 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 05053 /* Delay after an RCC peripheral clock enabling */ \ 05054 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 05055 UNUSED(tmpreg); \ 05056 } while(0U) 05057 #if defined(STM32F413xx) || defined(STM32F423xx) 05058 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 05059 __IO uint32_t tmpreg = 0x00U; \ 05060 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 05061 /* Delay after an RCC peripheral clock enabling */ \ 05062 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 05063 UNUSED(tmpreg); \ 05064 } while(0U) 05065 #define __HAL_RCC_UART7_CLK_ENABLE() do { \ 05066 __IO uint32_t tmpreg = 0x00U; \ 05067 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 05068 /* Delay after an RCC peripheral clock enabling */ \ 05069 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ 05070 UNUSED(tmpreg); \ 05071 } while(0U) 05072 #define __HAL_RCC_UART8_CLK_ENABLE() do { \ 05073 __IO uint32_t tmpreg = 0x00U; \ 05074 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 05075 /* Delay after an RCC peripheral clock enabling */ \ 05076 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ 05077 UNUSED(tmpreg); \ 05078 } while(0U) 05079 #endif /* STM32F413xx || STM32F423xx */ 05080 05081 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 05082 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 05083 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 05084 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 05085 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 05086 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 05087 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 05088 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 05089 #if defined(STM32F413xx) || defined(STM32F423xx) 05090 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) 05091 #endif /* STM32F413xx || STM32F423xx */ 05092 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) 05093 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 05094 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 05095 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 05096 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 05097 #if defined(STM32F413xx) || defined(STM32F423xx) 05098 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 05099 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 05100 #endif /* STM32F413xx || STM32F423xx */ 05101 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 05102 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) 05103 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 05104 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 05105 #if defined(STM32F413xx) || defined(STM32F423xx) 05106 #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) 05107 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 05108 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) 05109 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) 05110 #endif /* STM32F413xx || STM32F423xx */ 05111 05112 /** 05113 * @} 05114 */ 05115 05116 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 05117 * @brief Get the enable or disable status of the APB1 peripheral clock. 05118 * @note After reset, the peripheral clock (used for registers read/write access) 05119 * is disabled and the application software has to enable this clock before 05120 * using it. 05121 * @{ 05122 */ 05123 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 05124 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 05125 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 05126 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 05127 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 05128 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 05129 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 05130 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 05131 #if defined(STM32F413xx) || defined(STM32F423xx) 05132 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 05133 #endif /* STM32F413xx || STM32F423xx */ 05134 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) 05135 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 05136 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 05137 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 05138 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */ 05139 #if defined(STM32F413xx) || defined(STM32F423xx) 05140 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 05141 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 05142 #endif /* STM32F413xx || STM32F423xx */ 05143 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 05144 #define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) 05145 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET) 05146 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 05147 #if defined(STM32F413xx) || defined(STM32F423xx) 05148 #define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) 05149 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 05150 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) 05151 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 05152 #endif /* STM32F413xx || STM32F423xx */ 05153 05154 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 05155 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 05156 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 05157 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 05158 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 05159 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 05160 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 05161 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 05162 #if defined(STM32F413xx) || defined(STM32F423xx) 05163 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 05164 #endif /* STM32F413xx || STM32F423xx */ 05165 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) 05166 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 05167 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 05168 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 05169 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */ 05170 #if defined(STM32F413xx) || defined(STM32F423xx) 05171 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 05172 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 05173 #endif /* STM32F413xx || STM32F423xx */ 05174 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 05175 #define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) 05176 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 05177 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 05178 #if defined(STM32F413xx) || defined(STM32F423xx) 05179 #define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) 05180 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 05181 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) 05182 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) 05183 #endif /* STM32F413xx || STM32F423xx */ 05184 /** 05185 * @} 05186 */ 05187 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 05188 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 05189 * @note After reset, the peripheral clock (used for registers read/write access) 05190 * is disabled and the application software has to enable this clock before 05191 * using it. 05192 * @{ 05193 */ 05194 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 05195 __IO uint32_t tmpreg = 0x00U; \ 05196 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 05197 /* Delay after an RCC peripheral clock enabling */ \ 05198 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 05199 UNUSED(tmpreg); \ 05200 } while(0U) 05201 #if defined(STM32F413xx) || defined(STM32F423xx) 05202 #define __HAL_RCC_UART9_CLK_ENABLE() do { \ 05203 __IO uint32_t tmpreg = 0x00U; \ 05204 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ 05205 /* Delay after an RCC peripheral clock enabling */ \ 05206 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ 05207 UNUSED(tmpreg); \ 05208 } while(0U) 05209 #define __HAL_RCC_UART10_CLK_ENABLE() do { \ 05210 __IO uint32_t tmpreg = 0x00U; \ 05211 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ 05212 /* Delay after an RCC peripheral clock enabling */ \ 05213 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ 05214 UNUSED(tmpreg); \ 05215 } while(0U) 05216 #endif /* STM32F413xx || STM32F423xx */ 05217 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 05218 __IO uint32_t tmpreg = 0x00U; \ 05219 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 05220 /* Delay after an RCC peripheral clock enabling */ \ 05221 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 05222 UNUSED(tmpreg); \ 05223 } while(0U) 05224 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 05225 __IO uint32_t tmpreg = 0x00U; \ 05226 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 05227 /* Delay after an RCC peripheral clock enabling */ \ 05228 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 05229 UNUSED(tmpreg); \ 05230 } while(0U) 05231 #define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ 05232 __IO uint32_t tmpreg = 0x00U; \ 05233 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 05234 /* Delay after an RCC peripheral clock enabling */ \ 05235 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ 05236 UNUSED(tmpreg); \ 05237 } while(0U) 05238 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 05239 __IO uint32_t tmpreg = 0x00U; \ 05240 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 05241 /* Delay after an RCC peripheral clock enabling */ \ 05242 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 05243 UNUSED(tmpreg); \ 05244 } while(0U) 05245 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 05246 __IO uint32_t tmpreg = 0x00U; \ 05247 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 05248 /* Delay after an RCC peripheral clock enabling */ \ 05249 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 05250 UNUSED(tmpreg); \ 05251 } while(0U) 05252 #if defined(STM32F413xx) || defined(STM32F423xx) 05253 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 05254 __IO uint32_t tmpreg = 0x00U; \ 05255 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 05256 /* Delay after an RCC peripheral clock enabling */ \ 05257 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 05258 UNUSED(tmpreg); \ 05259 } while(0U) 05260 #endif /* STM32F413xx || STM32F423xx */ 05261 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ 05262 __IO uint32_t tmpreg = 0x00U; \ 05263 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 05264 /* Delay after an RCC peripheral clock enabling */ \ 05265 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ 05266 UNUSED(tmpreg); \ 05267 } while(0U) 05268 #if defined(STM32F413xx) || defined(STM32F423xx) 05269 #define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \ 05270 __IO uint32_t tmpreg = 0x00U; \ 05271 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ 05272 /* Delay after an RCC peripheral clock enabling */ \ 05273 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ 05274 UNUSED(tmpreg); \ 05275 } while(0U) 05276 #endif /* STM32F413xx || STM32F423xx */ 05277 05278 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 05279 #if defined(STM32F413xx) || defined(STM32F423xx) 05280 #define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN)) 05281 #define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN)) 05282 #endif /* STM32F413xx || STM32F423xx */ 05283 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 05284 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) 05285 #define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) 05286 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 05287 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) 05288 #if defined(STM32F413xx) || defined(STM32F423xx) 05289 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) 05290 #endif /* STM32F413xx || STM32F423xx */ 05291 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) 05292 #if defined(STM32F413xx) || defined(STM32F423xx) 05293 #define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN)) 05294 #endif /* STM32F413xx || STM32F423xx */ 05295 /** 05296 * @} 05297 */ 05298 05299 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 05300 * @brief Get the enable or disable status of the APB2 peripheral clock. 05301 * @note After reset, the peripheral clock (used for registers read/write access) 05302 * is disabled and the application software has to enable this clock before 05303 * using it. 05304 * @{ 05305 */ 05306 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 05307 #if defined(STM32F413xx) || defined(STM32F423xx) 05308 #define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET) 05309 #define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET) 05310 #endif /* STM32F413xx || STM32F423xx */ 05311 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 05312 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 05313 #define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) 05314 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 05315 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 05316 #if defined(STM32F413xx) || defined(STM32F423xx) 05317 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 05318 #endif /* STM32F413xx || STM32F423xx */ 05319 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) 05320 #if defined(STM32F413xx) || defined(STM32F423xx) 05321 #define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET) 05322 #endif /* STM32F413xx || STM32F423xx */ 05323 05324 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 05325 #if defined(STM32F413xx) || defined(STM32F423xx) 05326 #define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET) 05327 #define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET) 05328 #endif /* STM32F413xx || STM32F423xx */ 05329 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 05330 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 05331 #define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) 05332 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 05333 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) 05334 #if defined(STM32F413xx) || defined(STM32F423xx) 05335 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) 05336 #endif /* STM32F413xx || STM32F423xx */ 05337 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) 05338 #if defined(STM32F413xx) || defined(STM32F423xx) 05339 #define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET) 05340 #endif /* STM32F413xx || STM32F423xx */ 05341 /** 05342 * @} 05343 */ 05344 05345 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 05346 * @brief Force or release AHB1 peripheral reset. 05347 * @{ 05348 */ 05349 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 05350 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 05351 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 05352 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 05353 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 05354 05355 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 05356 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 05357 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 05358 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 05359 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 05360 /** 05361 * @} 05362 */ 05363 05364 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 05365 * @brief Force or release AHB2 peripheral reset. 05366 * @{ 05367 */ 05368 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 05369 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 05370 05371 #if defined(STM32F423xx) 05372 #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) 05373 #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) 05374 #endif /* STM32F423xx */ 05375 05376 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 05377 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 05378 05379 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 05380 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 05381 /** 05382 * @} 05383 */ 05384 05385 /** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 05386 * @brief Force or release AHB3 peripheral reset. 05387 * @{ 05388 */ 05389 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 05390 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 05391 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 05392 05393 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) 05394 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) 05395 05396 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) 05397 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) 05398 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 05399 #if defined(STM32F412Cx) 05400 #define __HAL_RCC_AHB3_FORCE_RESET() 05401 #define __HAL_RCC_AHB3_RELEASE_RESET() 05402 05403 #define __HAL_RCC_FSMC_FORCE_RESET() 05404 #define __HAL_RCC_QSPI_FORCE_RESET() 05405 05406 #define __HAL_RCC_FSMC_RELEASE_RESET() 05407 #define __HAL_RCC_QSPI_RELEASE_RESET() 05408 #endif /* STM32F412Cx */ 05409 /** 05410 * @} 05411 */ 05412 05413 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 05414 * @brief Force or release APB1 peripheral reset. 05415 * @{ 05416 */ 05417 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 05418 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 05419 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 05420 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 05421 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 05422 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 05423 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 05424 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 05425 #if defined(STM32F413xx) || defined(STM32F423xx) 05426 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) 05427 #endif /* STM32F413xx || STM32F423xx */ 05428 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 05429 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 05430 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 05431 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 05432 #if defined(STM32F413xx) || defined(STM32F423xx) 05433 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 05434 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 05435 #endif /* STM32F413xx || STM32F423xx */ 05436 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 05437 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) 05438 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 05439 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 05440 #if defined(STM32F413xx) || defined(STM32F423xx) 05441 #define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) 05442 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 05443 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) 05444 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) 05445 #endif /* STM32F413xx || STM32F423xx */ 05446 05447 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 05448 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 05449 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 05450 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 05451 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 05452 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 05453 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 05454 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 05455 #if defined(STM32F413xx) || defined(STM32F423xx) 05456 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) 05457 #endif /* STM32F413xx || STM32F423xx */ 05458 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 05459 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 05460 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 05461 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 05462 #if defined(STM32F413xx) || defined(STM32F423xx) 05463 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 05464 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 05465 #endif /* STM32F413xx || STM32F423xx */ 05466 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 05467 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) 05468 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 05469 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 05470 #if defined(STM32F413xx) || defined(STM32F423xx) 05471 #define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) 05472 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 05473 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) 05474 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) 05475 #endif /* STM32F413xx || STM32F423xx */ 05476 /** 05477 * @} 05478 */ 05479 05480 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 05481 * @brief Force or release APB2 peripheral reset. 05482 * @{ 05483 */ 05484 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 05485 #if defined(STM32F413xx) || defined(STM32F423xx) 05486 #define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST)) 05487 #define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART10RST)) 05488 #endif /* STM32F413xx || STM32F423xx */ 05489 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 05490 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) 05491 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 05492 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) 05493 #if defined(STM32F413xx) || defined(STM32F423xx) 05494 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 05495 #endif /* STM32F413xx || STM32F423xx */ 05496 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) 05497 #if defined(STM32F413xx) || defined(STM32F423xx) 05498 #define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM2RST)) 05499 #endif /* STM32F413xx || STM32F423xx */ 05500 05501 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 05502 #if defined(STM32F413xx) || defined(STM32F423xx) 05503 #define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST)) 05504 #define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST)) 05505 #endif /* STM32F413xx || STM32F423xx */ 05506 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 05507 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) 05508 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 05509 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) 05510 #if defined(STM32F413xx) || defined(STM32F423xx) 05511 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) 05512 #endif /* STM32F413xx || STM32F423xx */ 05513 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) 05514 #if defined(STM32F413xx) || defined(STM32F423xx) 05515 #define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST)) 05516 #endif /* STM32F413xx || STM32F423xx */ 05517 /** 05518 * @} 05519 */ 05520 05521 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 05522 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 05523 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05524 * power consumption. 05525 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 05526 * @note By default, all peripheral clocks are enabled during SLEEP mode. 05527 * @{ 05528 */ 05529 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 05530 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 05531 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 05532 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 05533 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 05534 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 05535 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 05536 #if defined(STM32F413xx) || defined(STM32F423xx) 05537 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 05538 #endif /* STM32F413xx || STM32F423xx */ 05539 05540 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 05541 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 05542 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 05543 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 05544 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 05545 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 05546 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 05547 #if defined(STM32F413xx) || defined(STM32F423xx) 05548 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 05549 #endif /* STM32F413xx || STM32F423xx */ 05550 /** 05551 * @} 05552 */ 05553 05554 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 05555 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 05556 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05557 * power consumption. 05558 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 05559 * @note By default, all peripheral clocks are enabled during SLEEP mode. 05560 * @{ 05561 */ 05562 #if defined(STM32F423xx) 05563 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) 05564 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) 05565 #endif /* STM32F423xx */ 05566 05567 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 05568 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 05569 05570 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 05571 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 05572 /** 05573 * @} 05574 */ 05575 05576 /** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 05577 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 05578 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05579 * power consumption. 05580 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 05581 * @note By default, all peripheral clocks are enabled during SLEEP mode. 05582 * @{ 05583 */ 05584 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 05585 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) 05586 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) 05587 05588 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) 05589 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) 05590 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 05591 05592 /** 05593 * @} 05594 */ 05595 05596 /** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 05597 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 05598 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05599 * power consumption. 05600 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 05601 * @note By default, all peripheral clocks are enabled during SLEEP mode. 05602 * @{ 05603 */ 05604 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 05605 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 05606 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 05607 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 05608 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 05609 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 05610 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 05611 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 05612 #if defined(STM32F413xx) || defined(STM32F423xx) 05613 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) 05614 #endif /* STM32F413xx || STM32F423xx */ 05615 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) 05616 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 05617 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 05618 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 05619 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 05620 #if defined(STM32F413xx) || defined(STM32F423xx) 05621 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 05622 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 05623 #endif /* STM32F413xx || STM32F423xx */ 05624 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 05625 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) 05626 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 05627 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 05628 #if defined(STM32F413xx) || defined(STM32F423xx) 05629 #define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) 05630 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 05631 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) 05632 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) 05633 #endif /* STM32F413xx || STM32F423xx */ 05634 05635 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 05636 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 05637 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 05638 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 05639 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 05640 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 05641 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 05642 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 05643 #if defined(STM32F413xx) || defined(STM32F423xx) 05644 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) 05645 #endif /* STM32F413xx || STM32F423xx */ 05646 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) 05647 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 05648 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 05649 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 05650 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 05651 #if defined(STM32F413xx) || defined(STM32F423xx) 05652 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 05653 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 05654 #endif /* STM32F413xx || STM32F423xx */ 05655 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 05656 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) 05657 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 05658 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 05659 #if defined(STM32F413xx) || defined(STM32F423xx) 05660 #define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) 05661 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 05662 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) 05663 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) 05664 #endif /* STM32F413xx || STM32F423xx */ 05665 /** 05666 * @} 05667 */ 05668 05669 /** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 05670 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 05671 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 05672 * power consumption. 05673 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 05674 * @note By default, all peripheral clocks are enabled during SLEEP mode. 05675 * @{ 05676 */ 05677 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 05678 #if defined(STM32F413xx) || defined(STM32F423xx) 05679 #define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART9LPEN)) 05680 #define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART10LPEN)) 05681 #endif /* STM32F413xx || STM32F423xx */ 05682 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 05683 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) 05684 #define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) 05685 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 05686 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) 05687 #if defined(STM32F413xx) || defined(STM32F423xx) 05688 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) 05689 #endif /* STM32F413xx || STM32F423xx */ 05690 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) 05691 #if defined(STM32F413xx) || defined(STM32F423xx) 05692 #define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM2LPEN)) 05693 #endif /* STM32F413xx || STM32F423xx */ 05694 05695 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 05696 #if defined(STM32F413xx) || defined(STM32F423xx) 05697 #define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN)) 05698 #define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN)) 05699 #endif /* STM32F413xx || STM32F423xx */ 05700 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 05701 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) 05702 #define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) 05703 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 05704 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) 05705 #if defined(STM32F413xx) || defined(STM32F423xx) 05706 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) 05707 #endif /* STM32F413xx || STM32F423xx */ 05708 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) 05709 #if defined(STM32F413xx) || defined(STM32F423xx) 05710 #define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN)) 05711 #endif /* STM32F413xx || STM32F423xx */ 05712 /** 05713 * @} 05714 */ 05715 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 05716 /*----------------------------------------------------------------------------*/ 05717 05718 /*------------------------------- PLL Configuration --------------------------*/ 05719 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\ 05720 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 05721 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 05722 /** @brief Macro to configure the main PLL clock source, multiplication and division factors. 05723 * @note This function must be used only when the main PLL is disabled. 05724 * @param __RCC_PLLSource__ specifies the PLL entry clock source. 05725 * This parameter can be one of the following values: 05726 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 05727 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 05728 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. 05729 * @param __PLLM__ specifies the division factor for PLL VCO input clock 05730 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 05731 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 05732 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 05733 * of 2 MHz to limit PLL jitter. 05734 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock 05735 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 05736 * @note You have to set the PLLN parameter correctly to ensure that the VCO 05737 * output frequency is between 100 and 432 MHz. 05738 * 05739 * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) 05740 * This parameter must be a number in the range {2, 4, 6, or 8}. 05741 * 05742 * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks 05743 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 05744 * @note If the USB OTG FS is used in your application, you have to set the 05745 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 05746 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work 05747 * correctly. 05748 * 05749 * @param __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. 05750 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 05751 * @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/ 05752 STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. 05753 * 05754 */ 05755 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ 05756 (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ 05757 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 05758 ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ 05759 ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ 05760 ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) 05761 #else 05762 /** @brief Macro to configure the main PLL clock source, multiplication and division factors. 05763 * @note This function must be used only when the main PLL is disabled. 05764 * @param __RCC_PLLSource__ specifies the PLL entry clock source. 05765 * This parameter can be one of the following values: 05766 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 05767 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 05768 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. 05769 * @param __PLLM__ specifies the division factor for PLL VCO input clock 05770 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 05771 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 05772 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 05773 * of 2 MHz to limit PLL jitter. 05774 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock 05775 * This parameter must be a number between Min_Data = 50 and Max_Data = 432 05776 * Except for STM32F411xE devices where Min_Data = 192. 05777 * @note You have to set the PLLN parameter correctly to ensure that the VCO 05778 * output frequency is between 100 and 432 MHz, Except for STM32F411xE devices 05779 * where frequency is between 192 and 432 MHz. 05780 * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) 05781 * This parameter must be a number in the range {2, 4, 6, or 8}. 05782 * 05783 * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks 05784 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 05785 * @note If the USB OTG FS is used in your application, you have to set the 05786 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 05787 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work 05788 * correctly. 05789 * 05790 */ 05791 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ 05792 (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \ 05793 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 05794 ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ 05795 ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) 05796 #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 05797 /*----------------------------------------------------------------------------*/ 05798 05799 /*----------------------------PLLI2S Configuration ---------------------------*/ 05800 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 05801 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 05802 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 05803 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 05804 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 05805 05806 /** @brief Macros to enable or disable the PLLI2S. 05807 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. 05808 */ 05809 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) 05810 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) 05811 05812 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 05813 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 05814 STM32F412Rx || STM32F412Cx */ 05815 #if defined(STM32F446xx) 05816 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 05817 * @note This macro must be used only when the PLLI2S is disabled. 05818 * @note PLLI2S clock source is common with the main PLL (configured in 05819 * HAL_RCC_ClockConfig() API). 05820 * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock 05821 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 05822 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input 05823 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 05824 * of 1 MHz to limit PLLI2S jitter. 05825 * 05826 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 05827 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 05828 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 05829 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 05830 * 05831 * @param __PLLI2SP__ specifies division factor for SPDIFRX Clock. 05832 * This parameter must be a number in the range {2, 4, 6, or 8}. 05833 * @note the PLLI2SP parameter is only available with STM32F446xx Devices 05834 * 05835 * @param __PLLI2SR__ specifies the division factor for I2S clock 05836 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 05837 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 05838 * on the I2S clock frequency. 05839 * 05840 * @param __PLLI2SQ__ specifies the division factor for SAI clock 05841 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 05842 */ 05843 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ 05844 (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ 05845 ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 05846 ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ 05847 ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ 05848 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 05849 #elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 05850 defined(STM32F413xx) || defined(STM32F423xx) 05851 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 05852 * @note This macro must be used only when the PLLI2S is disabled. 05853 * @note PLLI2S clock source is common with the main PLL (configured in 05854 * HAL_RCC_ClockConfig() API). 05855 * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock 05856 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 05857 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input 05858 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 05859 * of 1 MHz to limit PLLI2S jitter. 05860 * 05861 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 05862 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 05863 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 05864 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 05865 * 05866 * @param __PLLI2SR__ specifies the division factor for I2S clock 05867 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 05868 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 05869 * on the I2S clock frequency. 05870 * 05871 * @param __PLLI2SQ__ specifies the division factor for SAI clock 05872 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 05873 */ 05874 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ 05875 (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ 05876 ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 05877 ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ 05878 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 05879 #else 05880 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 05881 * @note This macro must be used only when the PLLI2S is disabled. 05882 * @note PLLI2S clock source is common with the main PLL (configured in 05883 * HAL_RCC_ClockConfig() API). 05884 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 05885 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 05886 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 05887 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 05888 * 05889 * @param __PLLI2SR__ specifies the division factor for I2S clock 05890 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 05891 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 05892 * on the I2S clock frequency. 05893 * 05894 */ 05895 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \ 05896 (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 05897 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 05898 #endif /* STM32F446xx */ 05899 05900 #if defined(STM32F411xE) 05901 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 05902 * @note This macro must be used only when the PLLI2S is disabled. 05903 * @note This macro must be used only when the PLLI2S is disabled. 05904 * @note PLLI2S clock source is common with the main PLL (configured in 05905 * HAL_RCC_ClockConfig() API). 05906 * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock 05907 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 05908 * @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices 05909 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input 05910 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 05911 * of 2 MHz to limit PLLI2S jitter. 05912 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 05913 * This parameter must be a number between Min_Data = 192 and Max_Data = 432. 05914 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 05915 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. 05916 * @param __PLLI2SR__ specifies the division factor for I2S clock 05917 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 05918 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 05919 * on the I2S clock frequency. 05920 */ 05921 #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ 05922 ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ 05923 ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) 05924 #endif /* STM32F411xE */ 05925 05926 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 05927 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors. 05928 * @note This macro must be used only when the PLLI2S is disabled. 05929 * @note PLLI2S clock source is common with the main PLL (configured in 05930 * HAL_RCC_ClockConfig() API) 05931 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. 05932 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 05933 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 05934 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 05935 * @param __PLLI2SQ__ specifies the division factor for SAI1 clock. 05936 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 05937 * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx 05938 * Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro 05939 * @param __PLLI2SR__ specifies the division factor for I2S clock 05940 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 05941 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 05942 * on the I2S clock frequency. 05943 */ 05944 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) |\ 05945 ((__PLLI2SQ__) << 24U) |\ 05946 ((__PLLI2SR__) << 28U)) 05947 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 05948 /*----------------------------------------------------------------------------*/ 05949 05950 /*------------------------------ PLLSAI Configuration ------------------------*/ 05951 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 05952 /** @brief Macros to Enable or Disable the PLLISAI. 05953 * @note The PLLSAI is only available with STM32F429x/439x Devices. 05954 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. 05955 */ 05956 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE) 05957 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE) 05958 05959 #if defined(STM32F446xx) 05960 /** @brief Macro to configure the PLLSAI clock multiplication and division factors. 05961 * 05962 * @param __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock 05963 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 05964 * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input 05965 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 05966 * of 1 MHz to limit PLLI2S jitter. 05967 * @note The PLLSAIM parameter is only used with STM32F446xx Devices 05968 * 05969 * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. 05970 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 05971 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO 05972 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 05973 * 05974 * @param __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks. 05975 * This parameter must be a number in the range {2, 4, 6, or 8}. 05976 * @note the PLLSAIP parameter is only available with STM32F446xx Devices 05977 * 05978 * @param __PLLSAIQ__ specifies the division factor for SAI clock 05979 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 05980 * 05981 * @param __PLLSAIR__ specifies the division factor for LTDC clock 05982 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 05983 * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices 05984 */ 05985 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ 05986 (RCC->PLLSAICFGR = ((__PLLSAIM__) | \ 05987 ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ 05988 ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \ 05989 ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))) 05990 #endif /* STM32F446xx */ 05991 05992 #if defined(STM32F469xx) || defined(STM32F479xx) 05993 /** @brief Macro to configure the PLLSAI clock multiplication and division factors. 05994 * 05995 * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. 05996 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 05997 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO 05998 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 05999 * 06000 * @param __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks. 06001 * This parameter must be a number in the range {2, 4, 6, or 8}. 06002 * 06003 * @param __PLLSAIQ__ specifies the division factor for SAI clock 06004 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 06005 * 06006 * @param __PLLSAIR__ specifies the division factor for LTDC clock 06007 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 06008 */ 06009 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ 06010 (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ 06011 ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ 06012 ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ 06013 ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) 06014 #endif /* STM32F469xx || STM32F479xx */ 06015 06016 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 06017 /** @brief Macro to configure the PLLSAI clock multiplication and division factors. 06018 * 06019 * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. 06020 * This parameter must be a number between Min_Data = 50 and Max_Data = 432. 06021 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO 06022 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. 06023 * 06024 * @param __PLLSAIQ__ specifies the division factor for SAI clock 06025 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 06026 * 06027 * @param __PLLSAIR__ specifies the division factor for LTDC clock 06028 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 06029 * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices 06030 */ 06031 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \ 06032 (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ 06033 ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) | \ 06034 ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) 06035 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 06036 06037 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 06038 /*----------------------------------------------------------------------------*/ 06039 06040 /*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/ 06041 #if defined(STM32F413xx) || defined(STM32F423xx) 06042 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. 06043 * @note This function must be called before enabling the PLLI2S. 06044 * @param __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock. 06045 * This parameter must be a number between 1 and 32. 06046 * SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__ 06047 */ 06048 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U)) 06049 06050 /** @brief Macro to configure the SAI clock Divider coming from PLL. 06051 * @param __PLLDivR__ specifies the PLL division factor for SAI1 clock. 06052 * This parameter must be a number between 1 and 32. 06053 * SAI1 clock frequency = f(PLLR) / __PLLDivR__ 06054 */ 06055 #define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U)) 06056 #endif /* STM32F413xx || STM32F423xx */ 06057 06058 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ 06059 defined(STM32F469xx) || defined(STM32F479xx) 06060 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. 06061 * @note This function must be called before enabling the PLLI2S. 06062 * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock. 06063 * This parameter must be a number between 1 and 32. 06064 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ 06065 */ 06066 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U)) 06067 06068 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI. 06069 * @note This function must be called before enabling the PLLSAI. 06070 * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . 06071 * This parameter must be a number between Min_Data = 1 and Max_Data = 32. 06072 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ 06073 */ 06074 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U)) 06075 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 06076 06077 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 06078 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. 06079 * 06080 * @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices. 06081 * @note This function must be called before enabling the PLLSAI. 06082 * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . 06083 * This parameter must be a number between Min_Data = 2 and Max_Data = 16. 06084 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ 06085 */ 06086 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__))) 06087 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 06088 /*----------------------------------------------------------------------------*/ 06089 06090 /*------------------------- Peripheral Clock selection -----------------------*/ 06091 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ 06092 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 06093 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\ 06094 defined(STM32F479xx) 06095 /** @brief Macro to configure the I2S clock source (I2SCLK). 06096 * @note This function must be called before enabling the I2S APB clock. 06097 * @param __SOURCE__ specifies the I2S clock source. 06098 * This parameter can be one of the following values: 06099 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. 06100 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin 06101 * used as I2S clock source. 06102 */ 06103 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__)) 06104 06105 06106 /** @brief Macro to get the I2S clock source (I2SCLK). 06107 * @retval The clock source can be one of the following values: 06108 * @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. 06109 * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin 06110 * used as I2S clock source 06111 */ 06112 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) 06113 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */ 06114 06115 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 06116 06117 /** @brief Macro to configure SAI1BlockA clock source selection. 06118 * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. 06119 * @note This function must be called before enabling PLLSAI, PLLI2S and 06120 * the SAI clock. 06121 * @param __SOURCE__ specifies the SAI Block A clock source. 06122 * This parameter can be one of the following values: 06123 * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 06124 * as SAI1 Block A clock. 06125 * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 06126 * as SAI1 Block A clock. 06127 * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin 06128 * used as SAI1 Block A clock. 06129 */ 06130 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) 06131 06132 /** @brief Macro to configure SAI1BlockB clock source selection. 06133 * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. 06134 * @note This function must be called before enabling PLLSAI, PLLI2S and 06135 * the SAI clock. 06136 * @param __SOURCE__ specifies the SAI Block B clock source. 06137 * This parameter can be one of the following values: 06138 * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 06139 * as SAI1 Block B clock. 06140 * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 06141 * as SAI1 Block B clock. 06142 * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin 06143 * used as SAI1 Block B clock. 06144 */ 06145 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) 06146 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 06147 06148 #if defined(STM32F446xx) 06149 /** @brief Macro to configure SAI1 clock source selection. 06150 * @note This configuration is only available with STM32F446xx Devices. 06151 * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and 06152 * the SAI clock. 06153 * @param __SOURCE__ specifies the SAI1 clock source. 06154 * This parameter can be one of the following values: 06155 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 06156 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. 06157 * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. 06158 * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. 06159 */ 06160 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__))) 06161 06162 /** @brief Macro to Get SAI1 clock source selection. 06163 * @note This configuration is only available with STM32F446xx Devices. 06164 * @retval The clock source can be one of the following values: 06165 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 06166 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. 06167 * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. 06168 * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. 06169 */ 06170 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC)) 06171 06172 /** @brief Macro to configure SAI2 clock source selection. 06173 * @note This configuration is only available with STM32F446xx Devices. 06174 * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and 06175 * the SAI clock. 06176 * @param __SOURCE__ specifies the SAI2 clock source. 06177 * This parameter can be one of the following values: 06178 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 06179 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. 06180 * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. 06181 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. 06182 */ 06183 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__))) 06184 06185 /** @brief Macro to Get SAI2 clock source selection. 06186 * @note This configuration is only available with STM32F446xx Devices. 06187 * @retval The clock source can be one of the following values: 06188 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 06189 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. 06190 * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. 06191 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. 06192 */ 06193 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC)) 06194 06195 /** @brief Macro to configure I2S APB1 clock source selection. 06196 * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. 06197 * @param __SOURCE__ specifies the I2S APB1 clock source. 06198 * This parameter can be one of the following values: 06199 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 06200 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. 06201 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. 06202 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06203 */ 06204 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) 06205 06206 /** @brief Macro to Get I2S APB1 clock source selection. 06207 * @retval The clock source can be one of the following values: 06208 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 06209 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. 06210 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. 06211 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06212 */ 06213 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) 06214 06215 /** @brief Macro to configure I2S APB2 clock source selection. 06216 * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. 06217 * @param __SOURCE__ specifies the SAI Block A clock source. 06218 * This parameter can be one of the following values: 06219 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 06220 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. 06221 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. 06222 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06223 */ 06224 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) 06225 06226 /** @brief Macro to Get I2S APB2 clock source selection. 06227 * @retval The clock source can be one of the following values: 06228 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 06229 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. 06230 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. 06231 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06232 */ 06233 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) 06234 06235 /** @brief Macro to configure the CEC clock. 06236 * @param __SOURCE__ specifies the CEC clock source. 06237 * This parameter can be one of the following values: 06238 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock 06239 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 06240 */ 06241 #define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__))) 06242 06243 /** @brief Macro to Get the CEC clock. 06244 * @retval The clock source can be one of the following values: 06245 * @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock 06246 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock 06247 */ 06248 #define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)) 06249 06250 /** @brief Macro to configure the FMPI2C1 clock. 06251 * @param __SOURCE__ specifies the FMPI2C1 clock source. 06252 * This parameter can be one of the following values: 06253 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 06254 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 06255 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 06256 */ 06257 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) 06258 06259 /** @brief Macro to Get the FMPI2C1 clock. 06260 * @retval The clock source can be one of the following values: 06261 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 06262 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 06263 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 06264 */ 06265 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) 06266 06267 /** @brief Macro to configure the CLK48 clock. 06268 * @param __SOURCE__ specifies the CLK48 clock source. 06269 * This parameter can be one of the following values: 06270 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 06271 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 06272 */ 06273 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) 06274 06275 /** @brief Macro to Get the CLK48 clock. 06276 * @retval The clock source can be one of the following values: 06277 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 06278 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 06279 */ 06280 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) 06281 06282 /** @brief Macro to configure the SDIO clock. 06283 * @param __SOURCE__ specifies the SDIO clock source. 06284 * This parameter can be one of the following values: 06285 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 06286 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 06287 */ 06288 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) 06289 06290 /** @brief Macro to Get the SDIO clock. 06291 * @retval The clock source can be one of the following values: 06292 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 06293 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 06294 */ 06295 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) 06296 06297 /** @brief Macro to configure the SPDIFRX clock. 06298 * @param __SOURCE__ specifies the SPDIFRX clock source. 06299 * This parameter can be one of the following values: 06300 * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. 06301 * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 06302 */ 06303 #define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__))) 06304 06305 /** @brief Macro to Get the SPDIFRX clock. 06306 * @retval The clock source can be one of the following values: 06307 * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. 06308 * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 06309 */ 06310 #define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL)) 06311 #endif /* STM32F446xx */ 06312 06313 #if defined(STM32F469xx) || defined(STM32F479xx) 06314 06315 /** @brief Macro to configure the CLK48 clock. 06316 * @param __SOURCE__ specifies the CLK48 clock source. 06317 * This parameter can be one of the following values: 06318 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 06319 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 06320 */ 06321 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__))) 06322 06323 /** @brief Macro to Get the CLK48 clock. 06324 * @retval The clock source can be one of the following values: 06325 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 06326 * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 06327 */ 06328 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL)) 06329 06330 /** @brief Macro to configure the SDIO clock. 06331 * @param __SOURCE__ specifies the SDIO clock source. 06332 * This parameter can be one of the following values: 06333 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 06334 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 06335 */ 06336 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__))) 06337 06338 /** @brief Macro to Get the SDIO clock. 06339 * @retval The clock source can be one of the following values: 06340 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 06341 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 06342 */ 06343 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL)) 06344 06345 /** @brief Macro to configure the DSI clock. 06346 * @param __SOURCE__ specifies the DSI clock source. 06347 * This parameter can be one of the following values: 06348 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 06349 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 06350 */ 06351 #define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__))) 06352 06353 /** @brief Macro to Get the DSI clock. 06354 * @retval The clock source can be one of the following values: 06355 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 06356 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 06357 */ 06358 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL)) 06359 06360 #endif /* STM32F469xx || STM32F479xx */ 06361 06362 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 06363 defined(STM32F413xx) || defined(STM32F423xx) 06364 /** @brief Macro to configure the DFSDM1 clock. 06365 * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. 06366 * This parameter can be one of the following values: 06367 * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 06368 * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock. 06369 * @retval None 06370 */ 06371 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__)) 06372 06373 /** @brief Macro to get the DFSDM1 clock source. 06374 * @retval The clock source can be one of the following values: 06375 * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 06376 * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock. 06377 */ 06378 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) 06379 06380 /** @brief Macro to configure DFSDM1 Audio clock source selection. 06381 * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ 06382 STM32F413xx/STM32F423xx Devices. 06383 * @param __SOURCE__ specifies the DFSDM1 Audio clock source. 06384 * This parameter can be one of the following values: 06385 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 06386 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 06387 */ 06388 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__))) 06389 06390 /** @brief Macro to Get DFSDM1 Audio clock source selection. 06391 * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ 06392 STM32F413xx/STM32F423xx Devices. 06393 * @retval The clock source can be one of the following values: 06394 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 06395 * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 06396 */ 06397 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL)) 06398 06399 #if defined(STM32F413xx) || defined(STM32F423xx) 06400 /** @brief Macro to configure the DFSDM2 clock. 06401 * @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source. 06402 * This parameter can be one of the following values: 06403 * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 06404 * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock. 06405 * @retval None 06406 */ 06407 #define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__)) 06408 06409 /** @brief Macro to get the DFSDM2 clock source. 06410 * @retval The clock source can be one of the following values: 06411 * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 06412 * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock. 06413 */ 06414 #define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) 06415 06416 /** @brief Macro to configure DFSDM1 Audio clock source selection. 06417 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 06418 * @param __SOURCE__ specifies the DFSDM2 Audio clock source. 06419 * This parameter can be one of the following values: 06420 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 06421 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 06422 */ 06423 #define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__))) 06424 06425 /** @brief Macro to Get DFSDM2 Audio clock source selection. 06426 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 06427 * @retval The clock source can be one of the following values: 06428 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock 06429 * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock 06430 */ 06431 #define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL)) 06432 06433 /** @brief Macro to configure SAI1BlockA clock source selection. 06434 * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. 06435 * @note This function must be called before enabling PLLSAI, PLLI2S and 06436 * the SAI clock. 06437 * @param __SOURCE__ specifies the SAI Block A clock source. 06438 * This parameter can be one of the following values: 06439 * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 06440 * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. 06441 * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 06442 * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06443 */ 06444 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) 06445 06446 /** @brief Macro to Get SAI1 BlockA clock source selection. 06447 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 06448 * @retval The clock source can be one of the following values: 06449 * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 06450 * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. 06451 * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 06452 * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06453 */ 06454 #define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC)) 06455 06456 /** @brief Macro to configure SAI1 BlockB clock source selection. 06457 * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. 06458 * @note This function must be called before enabling PLLSAI, PLLI2S and 06459 * the SAI clock. 06460 * @param __SOURCE__ specifies the SAI Block B clock source. 06461 * This parameter can be one of the following values: 06462 * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 06463 * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. 06464 * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 06465 * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06466 */ 06467 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) 06468 06469 /** @brief Macro to Get SAI1 BlockB clock source selection. 06470 * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. 06471 * @retval The clock source can be one of the following values: 06472 * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. 06473 * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. 06474 * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. 06475 * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06476 */ 06477 #define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC)) 06478 06479 /** @brief Macro to configure the LPTIM1 clock. 06480 * @param __SOURCE__ specifies the LPTIM1 clock source. 06481 * This parameter can be one of the following values: 06482 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock 06483 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 06484 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 06485 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 06486 */ 06487 #define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) 06488 06489 /** @brief Macro to Get the LPTIM1 clock. 06490 * @retval The clock source can be one of the following values: 06491 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock 06492 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 06493 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 06494 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 06495 */ 06496 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) 06497 #endif /* STM32F413xx || STM32F423xx */ 06498 06499 /** @brief Macro to configure I2S APB1 clock source selection. 06500 * @param __SOURCE__ specifies the I2S APB1 clock source. 06501 * This parameter can be one of the following values: 06502 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 06503 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 06504 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 06505 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06506 */ 06507 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) 06508 06509 /** @brief Macro to Get I2S APB1 clock source selection. 06510 * @retval The clock source can be one of the following values: 06511 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 06512 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 06513 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 06514 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06515 */ 06516 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) 06517 06518 /** @brief Macro to configure I2S APB2 clock source selection. 06519 * @param __SOURCE__ specifies the I2S APB2 clock source. 06520 * This parameter can be one of the following values: 06521 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 06522 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 06523 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 06524 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06525 */ 06526 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) 06527 06528 /** @brief Macro to Get I2S APB2 clock source selection. 06529 * @retval The clock source can be one of the following values: 06530 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. 06531 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 06532 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. 06533 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06534 */ 06535 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) 06536 06537 /** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK). 06538 * @note This macro must be called before enabling the I2S APB clock. 06539 * @param __SOURCE__ specifies the I2S clock source. 06540 * This parameter can be one of the following values: 06541 * @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. 06542 * @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin 06543 * used as I2S clock source. 06544 */ 06545 #define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__)) 06546 06547 /** @brief Macro to configure the FMPI2C1 clock. 06548 * @param __SOURCE__ specifies the FMPI2C1 clock source. 06549 * This parameter can be one of the following values: 06550 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 06551 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 06552 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 06553 */ 06554 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) 06555 06556 /** @brief Macro to Get the FMPI2C1 clock. 06557 * @retval The clock source can be one of the following values: 06558 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 06559 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 06560 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 06561 */ 06562 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) 06563 06564 /** @brief Macro to configure the CLK48 clock. 06565 * @param __SOURCE__ specifies the CLK48 clock source. 06566 * This parameter can be one of the following values: 06567 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 06568 * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock. 06569 */ 06570 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) 06571 06572 /** @brief Macro to Get the CLK48 clock. 06573 * @retval The clock source can be one of the following values: 06574 * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 06575 * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock 06576 */ 06577 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) 06578 06579 /** @brief Macro to configure the SDIO clock. 06580 * @param __SOURCE__ specifies the SDIO clock source. 06581 * This parameter can be one of the following values: 06582 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 06583 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 06584 */ 06585 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) 06586 06587 /** @brief Macro to Get the SDIO clock. 06588 * @retval The clock source can be one of the following values: 06589 * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 06590 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 06591 */ 06592 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) 06593 06594 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 06595 06596 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 06597 /** @brief Macro to configure I2S clock source selection. 06598 * @param __SOURCE__ specifies the I2S clock source. 06599 * This parameter can be one of the following values: 06600 * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. 06601 * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 06602 * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. 06603 */ 06604 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__))) 06605 06606 /** @brief Macro to Get I2S clock source selection. 06607 * @retval The clock source can be one of the following values: 06608 * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. 06609 * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. 06610 * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. 06611 */ 06612 #define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC)) 06613 06614 /** @brief Macro to configure the FMPI2C1 clock. 06615 * @param __SOURCE__ specifies the FMPI2C1 clock source. 06616 * This parameter can be one of the following values: 06617 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 06618 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 06619 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 06620 */ 06621 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) 06622 06623 /** @brief Macro to Get the FMPI2C1 clock. 06624 * @retval The clock source can be one of the following values: 06625 * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock 06626 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock 06627 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock 06628 */ 06629 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) 06630 06631 /** @brief Macro to configure the LPTIM1 clock. 06632 * @param __SOURCE__ specifies the LPTIM1 clock source. 06633 * This parameter can be one of the following values: 06634 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock 06635 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 06636 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 06637 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 06638 */ 06639 #define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) 06640 06641 /** @brief Macro to Get the LPTIM1 clock. 06642 * @retval The clock source can be one of the following values: 06643 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock 06644 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock 06645 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock 06646 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock 06647 */ 06648 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) 06649 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 06650 06651 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 06652 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ 06653 defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 06654 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ 06655 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 06656 /** @brief Macro to configure the Timers clocks prescalers 06657 * @note This feature is only available with STM32F429x/439x Devices. 06658 * @param __PRESC__ specifies the Timers clocks prescalers selection 06659 * This parameter can be one of the following values: 06660 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is 06661 * equal to HPRE if PPREx is corresponding to division by 1 or 2, 06662 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to 06663 * division by 4 or more. 06664 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 06665 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, 06666 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding 06667 * to division by 8 or more. 06668 */ 06669 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__)) 06670 06671 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\ 06672 STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx ||\ 06673 STM32F423xx */ 06674 06675 /*----------------------------------------------------------------------------*/ 06676 06677 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 06678 /** @brief Enable PLLSAI_RDY interrupt. 06679 */ 06680 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) 06681 06682 /** @brief Disable PLLSAI_RDY interrupt. 06683 */ 06684 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) 06685 06686 /** @brief Clear the PLLSAI RDY interrupt pending bits. 06687 */ 06688 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) 06689 06690 /** @brief Check the PLLSAI RDY interrupt has occurred or not. 06691 * @retval The new state (TRUE or FALSE). 06692 */ 06693 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) 06694 06695 /** @brief Check PLLSAI RDY flag is set or not. 06696 * @retval The new state (TRUE or FALSE). 06697 */ 06698 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) 06699 06700 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 06701 06702 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 06703 /** @brief Macros to enable or disable the RCC MCO1 feature. 06704 */ 06705 #define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE) 06706 #define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE) 06707 06708 /** @brief Macros to enable or disable the RCC MCO2 feature. 06709 */ 06710 #define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE) 06711 #define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE) 06712 06713 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 06714 06715 /** 06716 * @} 06717 */ 06718 06719 /* Exported functions --------------------------------------------------------*/ 06720 /** @addtogroup RCCEx_Exported_Functions 06721 * @{ 06722 */ 06723 06724 /** @addtogroup RCCEx_Exported_Functions_Group1 06725 * @{ 06726 */ 06727 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 06728 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 06729 06730 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 06731 06732 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ 06733 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ 06734 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ 06735 defined(STM32F423xx) 06736 void HAL_RCCEx_SelectLSEMode(uint8_t Mode); 06737 #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 06738 #if defined(RCC_PLLI2S_SUPPORT) 06739 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); 06740 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); 06741 #endif /* RCC_PLLI2S_SUPPORT */ 06742 #if defined(RCC_PLLSAI_SUPPORT) 06743 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); 06744 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); 06745 #endif /* RCC_PLLSAI_SUPPORT */ 06746 /** 06747 * @} 06748 */ 06749 06750 /** 06751 * @} 06752 */ 06753 /* Private types -------------------------------------------------------------*/ 06754 /* Private variables ---------------------------------------------------------*/ 06755 /* Private constants ---------------------------------------------------------*/ 06756 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants 06757 * @{ 06758 */ 06759 06760 /** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion 06761 * @brief RCC registers bit address in the alias region 06762 * @{ 06763 */ 06764 /* --- CR Register ---*/ 06765 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 06766 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 06767 /* Alias word address of PLLSAION bit */ 06768 #define RCC_PLLSAION_BIT_NUMBER 0x1CU 06769 #define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U)) 06770 06771 #define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ 06772 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 06773 06774 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 06775 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 06776 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 06777 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 06778 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 06779 /* Alias word address of PLLI2SON bit */ 06780 #define RCC_PLLI2SON_BIT_NUMBER 0x1AU 06781 #define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U)) 06782 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 06783 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 06784 STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 06785 06786 /* --- DCKCFGR Register ---*/ 06787 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 06788 defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\ 06789 defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ 06790 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ 06791 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 06792 /* Alias word address of TIMPRE bit */ 06793 #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU) 06794 #define RCC_TIMPRE_BIT_NUMBER 0x18U 06795 #define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U)) 06796 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\ 06797 STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ 06798 STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 06799 06800 /* --- CFGR Register ---*/ 06801 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U) 06802 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 06803 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 06804 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 06805 defined(STM32F469xx) || defined(STM32F479xx) 06806 /* Alias word address of I2SSRC bit */ 06807 #define RCC_I2SSRC_BIT_NUMBER 0x17U 06808 #define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U)) 06809 06810 #define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ 06811 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 06812 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ 06813 06814 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 06815 defined(STM32F413xx) || defined(STM32F423xx) 06816 /* --- PLLI2SCFGR Register ---*/ 06817 #define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U) 06818 /* Alias word address of PLLI2SSRC bit */ 06819 #define RCC_PLLI2SSRC_BIT_NUMBER 0x16U 06820 #define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U)) 06821 06822 #define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ 06823 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx | STM32F423xx */ 06824 06825 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 06826 /* Alias word address of MCO1EN bit */ 06827 #define RCC_MCO1EN_BIT_NUMBER 0x8U 06828 #define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U)) 06829 06830 /* Alias word address of MCO2EN bit */ 06831 #define RCC_MCO2EN_BIT_NUMBER 0x9U 06832 #define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U)) 06833 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 06834 06835 #define PLL_TIMEOUT_VALUE 2U /* 2 ms */ 06836 /** 06837 * @} 06838 */ 06839 06840 /** 06841 * @} 06842 */ 06843 06844 /* Private macros ------------------------------------------------------------*/ 06845 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros 06846 * @{ 06847 */ 06848 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters 06849 * @{ 06850 */ 06851 #if defined(STM32F411xE) 06852 #define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U)) 06853 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U)) 06854 #else /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || 06855 STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410Tx || STM32F410Cx || 06856 STM32F410Rx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Cx || STM32F412Rx || 06857 STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ 06858 #define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) 06859 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) 06860 #endif /* STM32F411xE */ 06861 06862 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 06863 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU)) 06864 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 06865 06866 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) 06867 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U)) 06868 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ 06869 06870 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 06871 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU)) 06872 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ 06873 06874 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 06875 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU)) 06876 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 06877 06878 #if defined(STM32F446xx) 06879 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU)) 06880 #endif /* STM32F446xx */ 06881 06882 #if defined(STM32F469xx) || defined(STM32F479xx) 06883 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU)) 06884 #endif /* STM32F469xx || STM32F479xx */ 06885 06886 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) 06887 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU)) 06888 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ 06889 06890 #if defined(STM32F413xx) || defined(STM32F423xx) 06891 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU)) 06892 #endif /* STM32F413xx || STM32F423xx */ 06893 06894 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 06895 06896 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ 06897 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 06898 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 06899 06900 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) 06901 06902 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 06903 06904 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 06905 06906 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 06907 06908 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 06909 06910 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ 06911 ((VALUE) == RCC_PLLSAIDIVR_4) ||\ 06912 ((VALUE) == RCC_PLLSAIDIVR_8) ||\ 06913 ((VALUE) == RCC_PLLSAIDIVR_16)) 06914 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 06915 06916 #if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 06917 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 06918 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U)) 06919 06920 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ 06921 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 06922 #endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 06923 06924 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 06925 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 06926 06927 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ 06928 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 06929 06930 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ 06931 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ 06932 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) 06933 06934 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ 06935 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ 06936 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ 06937 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) 06938 06939 #define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) ||\ 06940 ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) ||\ 06941 ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC)) 06942 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 06943 06944 #if defined(STM32F446xx) 06945 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 06946 06947 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ 06948 ((VALUE) == RCC_PLLI2SP_DIV4) ||\ 06949 ((VALUE) == RCC_PLLI2SP_DIV6) ||\ 06950 ((VALUE) == RCC_PLLI2SP_DIV8)) 06951 06952 #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U) 06953 06954 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ 06955 ((VALUE) == RCC_PLLSAIP_DIV4) ||\ 06956 ((VALUE) == RCC_PLLSAIP_DIV6) ||\ 06957 ((VALUE) == RCC_PLLSAIP_DIV8)) 06958 06959 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\ 06960 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\ 06961 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) ||\ 06962 ((SOURCE) == RCC_SAI1CLKSOURCE_EXT)) 06963 06964 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\ 06965 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\ 06966 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) ||\ 06967 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) 06968 06969 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ 06970 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ 06971 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ 06972 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) 06973 06974 #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ 06975 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ 06976 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ 06977 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) 06978 06979 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ 06980 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ 06981 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) 06982 06983 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) ||\ 06984 ((SOURCE) == RCC_CECCLKSOURCE_LSE)) 06985 06986 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ 06987 ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) 06988 06989 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ 06990 ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) 06991 06992 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\ 06993 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) 06994 #endif /* STM32F446xx */ 06995 06996 #if defined(STM32F469xx) || defined(STM32F479xx) 06997 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 06998 06999 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ 07000 ((VALUE) == RCC_PLLSAIP_DIV4) ||\ 07001 ((VALUE) == RCC_PLLSAIP_DIV6) ||\ 07002 ((VALUE) == RCC_PLLSAIP_DIV8)) 07003 07004 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ 07005 ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) 07006 07007 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ 07008 ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) 07009 07010 #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ 07011 ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) 07012 07013 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ 07014 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 07015 #endif /* STM32F469xx || STM32F479xx */ 07016 07017 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 07018 defined(STM32F413xx) || defined(STM32F423xx) 07019 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 07020 07021 #define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) 07022 07023 #define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \ 07024 ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT)) 07025 07026 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ 07027 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ 07028 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ 07029 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) 07030 07031 #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ 07032 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ 07033 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ 07034 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) 07035 07036 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ 07037 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ 07038 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) 07039 07040 #define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ 07041 ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ)) 07042 07043 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ 07044 ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) 07045 07046 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ 07047 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) 07048 07049 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) || \ 07050 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2)) 07051 07052 #if defined(STM32F413xx) || defined(STM32F423xx) 07053 #define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) || \ 07054 ((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK)) 07055 07056 #define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) || \ 07057 ((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2)) 07058 07059 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ 07060 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ 07061 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ 07062 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) 07063 07064 #define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) ||\ 07065 ((SOURCE) == RCC_SAIACLKSOURCE_EXT) ||\ 07066 ((SOURCE) == RCC_SAIACLKSOURCE_PLLR) ||\ 07067 ((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC)) 07068 07069 #define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) ||\ 07070 ((SOURCE) == RCC_SAIBCLKSOURCE_EXT) ||\ 07071 ((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) ||\ 07072 ((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC)) 07073 07074 #define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 07075 07076 #define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) 07077 07078 #endif /* STM32F413xx || STM32F423xx */ 07079 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 07080 07081 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ 07082 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 07083 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ 07084 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 07085 defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 07086 07087 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ 07088 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) 07089 07090 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 07091 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \ 07092 STM32F412Rx */ 07093 07094 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 07095 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \ 07096 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) 07097 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 07098 /** 07099 * @} 07100 */ 07101 07102 /** 07103 * @} 07104 */ 07105 07106 /** 07107 * @} 07108 */ 07109 07110 /** 07111 * @} 07112 */ 07113 #ifdef __cplusplus 07114 } 07115 #endif 07116 07117 #endif /* __STM32F4xx_HAL_RCC_EX_H */ 07118 07119 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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