STM32F439xx HAL User Manual
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Enable or disable the High Speed APB (APB2) peripheral clock. More...
Defines | |
#define | __HAL_RCC_TIM8_CLK_ENABLE() |
#define | __HAL_RCC_ADC2_CLK_ENABLE() |
#define | __HAL_RCC_ADC3_CLK_ENABLE() |
#define | __HAL_RCC_SPI5_CLK_ENABLE() |
#define | __HAL_RCC_SPI6_CLK_ENABLE() |
#define | __HAL_RCC_SAI1_CLK_ENABLE() |
#define | __HAL_RCC_SDIO_CLK_ENABLE() |
#define | __HAL_RCC_SPI4_CLK_ENABLE() |
#define | __HAL_RCC_TIM10_CLK_ENABLE() |
#define | __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) |
#define | __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) |
#define | __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) |
#define | __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) |
#define | __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) |
#define | __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) |
#define | __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) |
#define | __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) |
#define | __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) |
#define | __HAL_RCC_LTDC_CLK_ENABLE() |
#define | __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) |
Enable or disable the High Speed APB (APB2) peripheral clock.
#define __HAL_RCC_ADC2_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) |
Definition at line 1609 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_ADC2_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1549 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_ADC3_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) |
Definition at line 1610 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_ADC3_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1556 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_LTDC_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) |
Definition at line 1624 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_LTDC_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1616 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_SAI1_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) |
Definition at line 1613 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_SAI1_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1577 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_SDIO_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) |
Definition at line 1605 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_SDIO_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1584 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_SPI4_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) |
Definition at line 1606 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_SPI4_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1591 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_SPI5_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) |
Definition at line 1611 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_SPI5_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1563 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_SPI6_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) |
Definition at line 1612 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_SPI6_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1570 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM10_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) |
Definition at line 1607 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM10_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1598 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM8_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) |
Definition at line 1608 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM8_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1542 of file stm32f4xx_hal_rcc_ex.h.