STM32F439xx HAL User Manual
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Enable or disable the Low Speed APB (APB1) peripheral clock. More...
Defines | |
#define | __HAL_RCC_TIM6_CLK_ENABLE() |
#define | __HAL_RCC_TIM7_CLK_ENABLE() |
#define | __HAL_RCC_TIM12_CLK_ENABLE() |
#define | __HAL_RCC_TIM13_CLK_ENABLE() |
#define | __HAL_RCC_TIM14_CLK_ENABLE() |
#define | __HAL_RCC_TIM14_CLK_ENABLE() |
#define | __HAL_RCC_USART3_CLK_ENABLE() |
#define | __HAL_RCC_UART4_CLK_ENABLE() |
#define | __HAL_RCC_UART5_CLK_ENABLE() |
#define | __HAL_RCC_CAN1_CLK_ENABLE() |
#define | __HAL_RCC_CAN2_CLK_ENABLE() |
#define | __HAL_RCC_DAC_CLK_ENABLE() |
#define | __HAL_RCC_UART7_CLK_ENABLE() |
#define | __HAL_RCC_UART8_CLK_ENABLE() |
#define | __HAL_RCC_TIM2_CLK_ENABLE() |
#define | __HAL_RCC_TIM3_CLK_ENABLE() |
#define | __HAL_RCC_TIM4_CLK_ENABLE() |
#define | __HAL_RCC_SPI3_CLK_ENABLE() |
#define | __HAL_RCC_I2C3_CLK_ENABLE() |
#define | __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) |
#define | __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) |
#define | __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) |
#define | __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) |
#define | __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) |
#define | __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
#define | __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) |
#define | __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) |
#define | __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) |
#define | __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) |
#define | __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
#define | __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) |
#define | __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) |
#define | __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) |
#define | __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) |
#define | __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) |
#define | __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) |
#define | __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) |
Enable or disable the Low Speed APB (APB1) peripheral clock.
#define __HAL_RCC_CAN1_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) |
Definition at line 1478 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_CAN1_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1395 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_CAN2_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) |
Definition at line 1479 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_CAN2_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1402 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_DAC_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) |
Definition at line 1480 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_DAC_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1409 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_I2C3_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) |
Definition at line 1469 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_I2C3_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1458 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_SPI3_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) |
Definition at line 1468 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_SPI3_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1451 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM12_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) |
Definition at line 1472 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM12_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1346 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM13_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) |
Definition at line 1473 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM13_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1353 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM14_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) |
Definition at line 1474 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM14_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1367 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM14_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1367 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM2_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) |
Definition at line 1465 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM2_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1430 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM3_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) |
Definition at line 1466 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM3_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1437 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM4_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) |
Definition at line 1467 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM4_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1444 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM6_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
Definition at line 1470 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM6_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1332 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM7_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) |
Definition at line 1471 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_TIM7_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1339 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_UART4_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) |
Definition at line 1476 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_UART4_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1381 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_UART5_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) |
Definition at line 1477 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_UART5_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1388 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_UART7_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) |
Definition at line 1481 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_UART7_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1416 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_UART8_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) |
Definition at line 1482 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_UART8_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1423 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_USART3_CLK_DISABLE | ( | ) | (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
Definition at line 1475 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_USART3_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 1374 of file stm32f4xx_hal_rcc_ex.h.