STM32F439xx HAL User Manual
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Modules | |
AHB1 Peripheral Clock Enable Disable | |
Enables or disables the AHB1 peripheral clock. | |
AHB1 Peripheral Clock Enable Disable Status | |
Get the enable or disable status of the AHB1 peripheral clock. | |
AHB2 Peripheral Clock Enable Disable | |
Enable or disable the AHB2 peripheral clock. | |
AHB2 Peripheral Clock Enable Disable Status | |
Get the enable or disable status of the AHB1 peripheral clock. | |
AHB3 Peripheral Clock Enable Disable | |
Enables or disables the AHB3 peripheral clock. | |
AHB3 Peripheral Clock Enable Disable Status | |
Get the enable or disable status of the AHB3 peripheral clock. | |
APB1 Peripheral Clock Enable Disable | |
Enable or disable the Low Speed APB (APB1) peripheral clock. | |
APB1 Peripheral Clock Enable Disable Status | |
Get the enable or disable status of the APB1 peripheral clock. | |
APB2 Peripheral Clock Enable Disable | |
Enable or disable the High Speed APB (APB2) peripheral clock. | |
APB2 Peripheral Clock Enable Disable Status | |
Get the enable or disable status of the APB2 peripheral clock. | |
AHB1 Force Release Reset | |
Force or release AHB1 peripheral reset. | |
AHB2 Force Release Reset | |
Force or release AHB2 peripheral reset. | |
AHB3 Force Release Reset | |
Force or release AHB3 peripheral reset. | |
APB1 Force Release Reset | |
Force or release APB1 peripheral reset. | |
APB2 Force Release Reset | |
Force or release APB2 peripheral reset. | |
AHB1 Peripheral Low Power Enable Disable | |
Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. | |
AHB2 Peripheral Low Power Enable Disable | |
Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. | |
AHB3 Peripheral Low Power Enable Disable | |
Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. | |
APB1 Peripheral Low Power Enable Disable | |
Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. | |
APB2 Peripheral Low Power Enable Disable | |
Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. | |
Defines | |
#define | __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) |
Macro to configure the main PLL clock source, multiplication and division factors. | |
#define | __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) |
Macros to enable or disable the PLLI2S. | |
#define | __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) |
#define | __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) |
Macro to configure the PLLI2S clock multiplication and division factors . | |
#define | __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) |
Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors. | |
#define | __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE) |
Macros to Enable or Disable the PLLISAI. | |
#define | __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE) |
#define | __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) |
Macro to configure the PLLSAI clock multiplication and division factors. | |
#define | __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U)) |
Macro to configure the SAI clock Divider coming from PLLI2S. | |
#define | __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U)) |
Macro to configure the SAI clock Divider coming from PLLSAI. | |
#define | __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__))) |
Macro to configure the LTDC clock Divider coming from PLLSAI. | |
#define | __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__)) |
Macro to configure the I2S clock source (I2SCLK). | |
#define | __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) |
Macro to get the I2S clock source (I2SCLK). | |
#define | __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) |
Macro to configure SAI1BlockA clock source selection. | |
#define | __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) |
Macro to configure SAI1BlockB clock source selection. | |
#define | __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__)) |
Macro to configure the Timers clocks prescalers. | |
#define | __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) |
Enable PLLSAI_RDY interrupt. | |
#define | __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) |
Disable PLLSAI_RDY interrupt. | |
#define | __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) |
Clear the PLLSAI RDY interrupt pending bits. | |
#define | __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) |
Check the PLLSAI RDY interrupt has occurred or not. | |
#define | __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) |
Check PLLSAI RDY flag is set or not. |
#define __HAL_RCC_GET_I2S_SOURCE | ( | ) | ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) |
Macro to get the I2S clock source (I2SCLK).
The | clock source can be one of the following values:
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Definition at line 6112 of file stm32f4xx_hal_rcc_ex.h.
Referenced by HAL_RCCEx_GetPeriphCLKFreq().
#define __HAL_RCC_I2S_CONFIG | ( | __SOURCE__ | ) | (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__)) |
Macro to configure the I2S clock source (I2SCLK).
__SOURCE__ | specifies the I2S clock source. This parameter can be one of the following values:
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Definition at line 6103 of file stm32f4xx_hal_rcc_ex.h.
Referenced by SAI_GetInputClock().
#define __HAL_RCC_PLL_CONFIG | ( | __RCC_PLLSource__, | |
__PLLM__, | |||
__PLLN__, | |||
__PLLP__, | |||
__PLLQ__ | |||
) |
(RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \ ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))
Macro to configure the main PLL clock source, multiplication and division factors.
__RCC_PLLSource__ | specifies the PLL entry clock source. This parameter can be one of the following values:
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__PLLM__ | specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63. |
__PLLN__ | specifies the multiplication factor for PLL VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432 Except for STM32F411xE devices where Min_Data = 192. |
__PLLP__ | specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}. |
__PLLQ__ | specifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
Definition at line 5791 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_PLLI2S_CONFIG | ( | __PLLI2SN__, | |
__PLLI2SR__ | |||
) |
(RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
Macro to configure the PLLI2S clock multiplication and division factors .
__PLLI2SN__ | specifies the multiplication factor for PLLI2S VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
__PLLI2SR__ | specifies the division factor for I2S clock This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
Definition at line 5895 of file stm32f4xx_hal_rcc_ex.h.
Referenced by HAL_RCCEx_EnablePLLI2S(), and HAL_RCCEx_PeriphCLKConfig().
#define __HAL_RCC_PLLI2S_DISABLE | ( | ) | (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) |
Definition at line 5810 of file stm32f4xx_hal_rcc_ex.h.
Referenced by HAL_RCCEx_DisablePLLI2S(), HAL_RCCEx_EnablePLLI2S(), and HAL_RCCEx_PeriphCLKConfig().
#define __HAL_RCC_PLLI2S_ENABLE | ( | ) | (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) |
Macros to enable or disable the PLLI2S.
Definition at line 5809 of file stm32f4xx_hal_rcc_ex.h.
Referenced by HAL_RCCEx_EnablePLLI2S(), and HAL_RCCEx_PeriphCLKConfig().
#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG | ( | __PLLI2SDivQ__ | ) | (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U)) |
Macro to configure the SAI clock Divider coming from PLLI2S.
__PLLI2SDivQ__ | specifies the PLLI2S division factor for SAI1 clock. This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ |
Definition at line 6066 of file stm32f4xx_hal_rcc_ex.h.
Referenced by HAL_RCCEx_PeriphCLKConfig().
#define __HAL_RCC_PLLI2S_SAICLK_CONFIG | ( | __PLLI2SN__, | |
__PLLI2SQ__, | |||
__PLLI2SR__ | |||
) |
(RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) |\ ((__PLLI2SQ__) << 24U) |\ ((__PLLI2SR__) << 28U))
Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
__PLLI2SN__ | specifies the multiplication factor for PLLI2S VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
__PLLI2SQ__ | specifies the division factor for SAI1 clock. This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
__PLLI2SR__ | specifies the division factor for I2S clock This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
Definition at line 5944 of file stm32f4xx_hal_rcc_ex.h.
Referenced by HAL_RCCEx_EnablePLLI2S(), and HAL_RCCEx_PeriphCLKConfig().
#define __HAL_RCC_PLLSAI_CLEAR_IT | ( | ) | (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) |
Clear the PLLSAI RDY interrupt pending bits.
Definition at line 6688 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_PLLSAI_CONFIG | ( | __PLLSAIN__, | |
__PLLSAIQ__, | |||
__PLLSAIR__ | |||
) |
(RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) | \ ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
Macro to configure the PLLSAI clock multiplication and division factors.
__PLLSAIN__ | specifies the multiplication factor for PLLSAI VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432. |
__PLLSAIQ__ | specifies the division factor for SAI clock This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
__PLLSAIR__ | specifies the division factor for LTDC clock This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
Definition at line 6031 of file stm32f4xx_hal_rcc_ex.h.
Referenced by HAL_RCCEx_EnablePLLSAI(), and HAL_RCCEx_PeriphCLKConfig().
#define __HAL_RCC_PLLSAI_DISABLE | ( | ) | (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE) |
Definition at line 5957 of file stm32f4xx_hal_rcc_ex.h.
Referenced by HAL_RCCEx_DisablePLLSAI(), HAL_RCCEx_EnablePLLSAI(), and HAL_RCCEx_PeriphCLKConfig().
#define __HAL_RCC_PLLSAI_DISABLE_IT | ( | ) | (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) |
Disable PLLSAI_RDY interrupt.
Definition at line 6684 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_PLLSAI_ENABLE | ( | ) | (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE) |
Macros to Enable or Disable the PLLISAI.
Definition at line 5956 of file stm32f4xx_hal_rcc_ex.h.
Referenced by HAL_RCCEx_EnablePLLSAI(), and HAL_RCCEx_PeriphCLKConfig().
#define __HAL_RCC_PLLSAI_ENABLE_IT | ( | ) | (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) |
Enable PLLSAI_RDY interrupt.
Definition at line 6680 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_PLLSAI_GET_FLAG | ( | ) | ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) |
Check PLLSAI RDY flag is set or not.
The | new state (TRUE or FALSE). |
Definition at line 6698 of file stm32f4xx_hal_rcc_ex.h.
Referenced by HAL_RCCEx_DisablePLLSAI(), HAL_RCCEx_EnablePLLSAI(), and HAL_RCCEx_PeriphCLKConfig().
#define __HAL_RCC_PLLSAI_GET_IT | ( | ) | ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) |
Check the PLLSAI RDY interrupt has occurred or not.
The | new state (TRUE or FALSE). |
Definition at line 6693 of file stm32f4xx_hal_rcc_ex.h.
#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG | ( | __PLLSAIDivQ__ | ) | (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U)) |
Macro to configure the SAI clock Divider coming from PLLSAI.
__PLLSAIDivQ__ | specifies the PLLSAI division factor for SAI1 clock . This parameter must be a number between Min_Data = 1 and Max_Data = 32. SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ |
Definition at line 6074 of file stm32f4xx_hal_rcc_ex.h.
Referenced by HAL_RCCEx_PeriphCLKConfig().
#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG | ( | __PLLSAIDivR__ | ) | (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__))) |
Macro to configure the LTDC clock Divider coming from PLLSAI.
__PLLSAIDivR__ | specifies the PLLSAI division factor for LTDC clock . This parameter must be a number between Min_Data = 2 and Max_Data = 16. LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ |
Definition at line 6086 of file stm32f4xx_hal_rcc_ex.h.
Referenced by HAL_RCCEx_PeriphCLKConfig().
#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG | ( | __SOURCE__ | ) | (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) |
Macro to configure SAI1BlockA clock source selection.
__SOURCE__ | specifies the SAI Block A clock source. This parameter can be one of the following values:
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Definition at line 6130 of file stm32f4xx_hal_rcc_ex.h.
Referenced by SAI_GetInputClock().
#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG | ( | __SOURCE__ | ) | (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) |
Macro to configure SAI1BlockB clock source selection.
__SOURCE__ | specifies the SAI Block B clock source. This parameter can be one of the following values:
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Definition at line 6145 of file stm32f4xx_hal_rcc_ex.h.
Referenced by SAI_GetInputClock().
#define __HAL_RCC_TIMCLKPRESCALER | ( | __PRESC__ | ) | (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__)) |
Macro to configure the Timers clocks prescalers.
__PRESC__ | specifies the Timers clocks prescalers selection This parameter can be one of the following values:
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Definition at line 6669 of file stm32f4xx_hal_rcc_ex.h.
Referenced by HAL_RCCEx_PeriphCLKConfig().