STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_tim_ex.c 00004 * @author MCD Application Team 00005 * @brief TIM HAL module driver. 00006 * This file provides firmware functions to manage the following 00007 * functionalities of the Timer Extended peripheral: 00008 * + Time Hall Sensor Interface Initialization 00009 * + Time Hall Sensor Interface Start 00010 * + Time Complementary signal break and dead time configuration 00011 * + Time Master and Slave synchronization configuration 00012 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) 00013 * + Time OCRef clear configuration 00014 * + Timer remapping capabilities configuration 00015 @verbatim 00016 ============================================================================== 00017 ##### TIMER Extended features ##### 00018 ============================================================================== 00019 [..] 00020 The Timer Extended features include: 00021 (#) Complementary outputs with programmable dead-time for : 00022 (++) Output Compare 00023 (++) PWM generation (Edge and Center-aligned Mode) 00024 (++) One-pulse mode output 00025 (#) Synchronization circuit to control the timer with external signals and to 00026 interconnect several timers together. 00027 (#) Break input to put the timer output signals in reset state or in a known state. 00028 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for 00029 positioning purposes 00030 00031 ##### How to use this driver ##### 00032 ============================================================================== 00033 [..] 00034 (#) Initialize the TIM low level resources by implementing the following functions 00035 depending on the selected feature: 00036 (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() 00037 00038 (#) Initialize the TIM low level resources : 00039 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); 00040 (##) TIM pins configuration 00041 (+++) Enable the clock for the TIM GPIOs using the following function: 00042 __HAL_RCC_GPIOx_CLK_ENABLE(); 00043 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); 00044 00045 (#) The external Clock can be configured, if needed (the default clock is the 00046 internal clock from the APBx), using the following function: 00047 HAL_TIM_ConfigClockSource, the clock configuration should be done before 00048 any start function. 00049 00050 (#) Configure the TIM in the desired functioning mode using one of the 00051 initialization function of this driver: 00052 (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutationEvent(): to use the 00053 Timer Hall Sensor Interface and the commutation event with the corresponding 00054 Interrupt and DMA request if needed (Note that One Timer is used to interface 00055 with the Hall sensor Interface and another Timer should be used to use 00056 the commutation event). 00057 00058 (#) Activate the TIM peripheral using one of the start functions: 00059 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() 00060 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() 00061 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() 00062 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). 00063 00064 @endverbatim 00065 ****************************************************************************** 00066 * @attention 00067 * 00068 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00069 * 00070 * Redistribution and use in source and binary forms, with or without modification, 00071 * are permitted provided that the following conditions are met: 00072 * 1. Redistributions of source code must retain the above copyright notice, 00073 * this list of conditions and the following disclaimer. 00074 * 2. Redistributions in binary form must reproduce the above copyright notice, 00075 * this list of conditions and the following disclaimer in the documentation 00076 * and/or other materials provided with the distribution. 00077 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00078 * may be used to endorse or promote products derived from this software 00079 * without specific prior written permission. 00080 * 00081 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00082 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00083 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00084 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00085 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00086 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00087 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00088 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00089 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00090 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00091 * 00092 ****************************************************************************** 00093 */ 00094 00095 /* Includes ------------------------------------------------------------------*/ 00096 #include "stm32l4xx_hal.h" 00097 00098 /** @addtogroup STM32L4xx_HAL_Driver 00099 * @{ 00100 */ 00101 00102 /** @defgroup TIMEx TIMEx 00103 * @brief TIM Extended HAL module driver 00104 * @{ 00105 */ 00106 00107 #ifdef HAL_TIM_MODULE_ENABLED 00108 00109 /* Private typedef -----------------------------------------------------------*/ 00110 /* Private define ------------------------------------------------------------*/ 00111 /* Private macro -------------------------------------------------------------*/ 00112 /* Private variables ---------------------------------------------------------*/ 00113 /* Private function prototypes -----------------------------------------------*/ 00114 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); 00115 00116 /* Exported functions --------------------------------------------------------*/ 00117 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions 00118 * @{ 00119 */ 00120 00121 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions 00122 * @brief Timer Hall Sensor functions 00123 * 00124 @verbatim 00125 ============================================================================== 00126 ##### Timer Hall Sensor functions ##### 00127 ============================================================================== 00128 [..] 00129 This section provides functions allowing to: 00130 (+) Initialize and configure TIM HAL Sensor. 00131 (+) De-initialize TIM HAL Sensor. 00132 (+) Start the Hall Sensor Interface. 00133 (+) Stop the Hall Sensor Interface. 00134 (+) Start the Hall Sensor Interface and enable interrupts. 00135 (+) Stop the Hall Sensor Interface and disable interrupts. 00136 (+) Start the Hall Sensor Interface and enable DMA transfers. 00137 (+) Stop the Hall Sensor Interface and disable DMA transfers. 00138 00139 @endverbatim 00140 * @{ 00141 */ 00142 /** 00143 * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. 00144 * @param htim TIM Hall Sensor Interface handle 00145 * @param sConfig TIM Hall Sensor configuration structure 00146 * @retval HAL status 00147 */ 00148 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) 00149 { 00150 TIM_OC_InitTypeDef OC_Config; 00151 00152 /* Check the TIM handle allocation */ 00153 if (htim == NULL) 00154 { 00155 return HAL_ERROR; 00156 } 00157 00158 /* Check the parameters */ 00159 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); 00160 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); 00161 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 00162 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); 00163 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); 00164 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); 00165 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); 00166 00167 if (htim->State == HAL_TIM_STATE_RESET) 00168 { 00169 /* Allocate lock resource and initialize it */ 00170 htim->Lock = HAL_UNLOCKED; 00171 00172 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 00173 /* Reset interrupt callbacks to legacy week callbacks */ 00174 TIM_ResetCallback(htim); 00175 00176 if (htim->HallSensor_MspInitCallback == NULL) 00177 { 00178 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; 00179 } 00180 /* Init the low level hardware : GPIO, CLOCK, NVIC */ 00181 htim->HallSensor_MspInitCallback(htim); 00182 #else 00183 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ 00184 HAL_TIMEx_HallSensor_MspInit(htim); 00185 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 00186 } 00187 00188 /* Set the TIM state */ 00189 htim->State = HAL_TIM_STATE_BUSY; 00190 00191 /* Configure the Time base in the Encoder Mode */ 00192 TIM_Base_SetConfig(htim->Instance, &htim->Init); 00193 00194 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ 00195 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); 00196 00197 /* Reset the IC1PSC Bits */ 00198 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; 00199 /* Set the IC1PSC value */ 00200 htim->Instance->CCMR1 |= sConfig->IC1Prescaler; 00201 00202 /* Enable the Hall sensor interface (XOR function of the three inputs) */ 00203 htim->Instance->CR2 |= TIM_CR2_TI1S; 00204 00205 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ 00206 htim->Instance->SMCR &= ~TIM_SMCR_TS; 00207 htim->Instance->SMCR |= TIM_TS_TI1F_ED; 00208 00209 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ 00210 htim->Instance->SMCR &= ~TIM_SMCR_SMS; 00211 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; 00212 00213 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ 00214 OC_Config.OCFastMode = TIM_OCFAST_DISABLE; 00215 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; 00216 OC_Config.OCMode = TIM_OCMODE_PWM2; 00217 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; 00218 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; 00219 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; 00220 OC_Config.Pulse = sConfig->Commutation_Delay; 00221 00222 TIM_OC2_SetConfig(htim->Instance, &OC_Config); 00223 00224 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 00225 register to 101 */ 00226 htim->Instance->CR2 &= ~TIM_CR2_MMS; 00227 htim->Instance->CR2 |= TIM_TRGO_OC2REF; 00228 00229 /* Initialize the TIM state*/ 00230 htim->State = HAL_TIM_STATE_READY; 00231 00232 return HAL_OK; 00233 } 00234 00235 /** 00236 * @brief DeInitializes the TIM Hall Sensor interface 00237 * @param htim TIM Hall Sensor Interface handle 00238 * @retval HAL status 00239 */ 00240 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) 00241 { 00242 /* Check the parameters */ 00243 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00244 00245 htim->State = HAL_TIM_STATE_BUSY; 00246 00247 /* Disable the TIM Peripheral Clock */ 00248 __HAL_TIM_DISABLE(htim); 00249 00250 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 00251 if (htim->HallSensor_MspDeInitCallback == NULL) 00252 { 00253 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; 00254 } 00255 /* DeInit the low level hardware */ 00256 htim->HallSensor_MspDeInitCallback(htim); 00257 #else 00258 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ 00259 HAL_TIMEx_HallSensor_MspDeInit(htim); 00260 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 00261 00262 /* Change TIM state */ 00263 htim->State = HAL_TIM_STATE_RESET; 00264 00265 /* Release Lock */ 00266 __HAL_UNLOCK(htim); 00267 00268 return HAL_OK; 00269 } 00270 00271 /** 00272 * @brief Initializes the TIM Hall Sensor MSP. 00273 * @param htim TIM Hall Sensor Interface handle 00274 * @retval None 00275 */ 00276 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) 00277 { 00278 /* Prevent unused argument(s) compilation warning */ 00279 UNUSED(htim); 00280 00281 /* NOTE : This function should not be modified, when the callback is needed, 00282 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file 00283 */ 00284 } 00285 00286 /** 00287 * @brief DeInitializes TIM Hall Sensor MSP. 00288 * @param htim TIM Hall Sensor Interface handle 00289 * @retval None 00290 */ 00291 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) 00292 { 00293 /* Prevent unused argument(s) compilation warning */ 00294 UNUSED(htim); 00295 00296 /* NOTE : This function should not be modified, when the callback is needed, 00297 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file 00298 */ 00299 } 00300 00301 /** 00302 * @brief Starts the TIM Hall Sensor Interface. 00303 * @param htim TIM Hall Sensor Interface handle 00304 * @retval HAL status 00305 */ 00306 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) 00307 { 00308 /* Check the parameters */ 00309 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); 00310 00311 /* Enable the Input Capture channel 1 00312 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ 00313 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 00314 00315 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 00316 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 00317 { 00318 __HAL_TIM_ENABLE(htim); 00319 } 00320 00321 /* Return function status */ 00322 return HAL_OK; 00323 } 00324 00325 /** 00326 * @brief Stops the TIM Hall sensor Interface. 00327 * @param htim TIM Hall Sensor Interface handle 00328 * @retval HAL status 00329 */ 00330 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) 00331 { 00332 /* Check the parameters */ 00333 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); 00334 00335 /* Disable the Input Capture channels 1, 2 and 3 00336 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ 00337 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 00338 00339 /* Disable the Peripheral */ 00340 __HAL_TIM_DISABLE(htim); 00341 00342 /* Return function status */ 00343 return HAL_OK; 00344 } 00345 00346 /** 00347 * @brief Starts the TIM Hall Sensor Interface in interrupt mode. 00348 * @param htim TIM Hall Sensor Interface handle 00349 * @retval HAL status 00350 */ 00351 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) 00352 { 00353 /* Check the parameters */ 00354 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); 00355 00356 /* Enable the capture compare Interrupts 1 event */ 00357 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 00358 00359 /* Enable the Input Capture channel 1 00360 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ 00361 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 00362 00363 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 00364 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 00365 { 00366 __HAL_TIM_ENABLE(htim); 00367 } 00368 00369 /* Return function status */ 00370 return HAL_OK; 00371 } 00372 00373 /** 00374 * @brief Stops the TIM Hall Sensor Interface in interrupt mode. 00375 * @param htim TIM Hall Sensor Interface handle 00376 * @retval HAL status 00377 */ 00378 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) 00379 { 00380 /* Check the parameters */ 00381 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); 00382 00383 /* Disable the Input Capture channel 1 00384 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ 00385 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 00386 00387 /* Disable the capture compare Interrupts event */ 00388 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 00389 00390 /* Disable the Peripheral */ 00391 __HAL_TIM_DISABLE(htim); 00392 00393 /* Return function status */ 00394 return HAL_OK; 00395 } 00396 00397 /** 00398 * @brief Starts the TIM Hall Sensor Interface in DMA mode. 00399 * @param htim TIM Hall Sensor Interface handle 00400 * @param pData The destination Buffer address. 00401 * @param Length The length of data to be transferred from TIM peripheral to memory. 00402 * @retval HAL status 00403 */ 00404 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) 00405 { 00406 /* Check the parameters */ 00407 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); 00408 00409 if ((htim->State == HAL_TIM_STATE_BUSY)) 00410 { 00411 return HAL_BUSY; 00412 } 00413 else if ((htim->State == HAL_TIM_STATE_READY)) 00414 { 00415 if (((uint32_t)pData == 0U) && (Length > 0U)) 00416 { 00417 return HAL_ERROR; 00418 } 00419 else 00420 { 00421 htim->State = HAL_TIM_STATE_BUSY; 00422 } 00423 } 00424 else 00425 { 00426 /* nothing to do */ 00427 } 00428 /* Enable the Input Capture channel 1 00429 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ 00430 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 00431 00432 /* Set the DMA Input Capture 1 Callback */ 00433 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; 00434 /* Set the DMA error callback */ 00435 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 00436 00437 /* Enable the DMA channel for Capture 1*/ 00438 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) 00439 { 00440 return HAL_ERROR; 00441 } 00442 /* Enable the capture compare 1 Interrupt */ 00443 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 00444 00445 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 00446 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 00447 { 00448 __HAL_TIM_ENABLE(htim); 00449 } 00450 00451 /* Return function status */ 00452 return HAL_OK; 00453 } 00454 00455 /** 00456 * @brief Stops the TIM Hall Sensor Interface in DMA mode. 00457 * @param htim TIM Hall Sensor Interface handle 00458 * @retval HAL status 00459 */ 00460 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) 00461 { 00462 /* Check the parameters */ 00463 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); 00464 00465 /* Disable the Input Capture channel 1 00466 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ 00467 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 00468 00469 00470 /* Disable the capture compare Interrupts 1 event */ 00471 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 00472 00473 /* Disable the Peripheral */ 00474 __HAL_TIM_DISABLE(htim); 00475 00476 /* Return function status */ 00477 return HAL_OK; 00478 } 00479 00480 /** 00481 * @} 00482 */ 00483 00484 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions 00485 * @brief Timer Complementary Output Compare functions 00486 * 00487 @verbatim 00488 ============================================================================== 00489 ##### Timer Complementary Output Compare functions ##### 00490 ============================================================================== 00491 [..] 00492 This section provides functions allowing to: 00493 (+) Start the Complementary Output Compare/PWM. 00494 (+) Stop the Complementary Output Compare/PWM. 00495 (+) Start the Complementary Output Compare/PWM and enable interrupts. 00496 (+) Stop the Complementary Output Compare/PWM and disable interrupts. 00497 (+) Start the Complementary Output Compare/PWM and enable DMA transfers. 00498 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. 00499 00500 @endverbatim 00501 * @{ 00502 */ 00503 00504 /** 00505 * @brief Starts the TIM Output Compare signal generation on the complementary 00506 * output. 00507 * @param htim TIM Output Compare handle 00508 * @param Channel TIM Channel to be enabled 00509 * This parameter can be one of the following values: 00510 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00511 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00512 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00513 * @retval HAL status 00514 */ 00515 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) 00516 { 00517 /* Check the parameters */ 00518 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 00519 00520 /* Enable the Capture compare channel N */ 00521 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); 00522 00523 /* Enable the Main Output */ 00524 __HAL_TIM_MOE_ENABLE(htim); 00525 00526 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 00527 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 00528 { 00529 __HAL_TIM_ENABLE(htim); 00530 } 00531 00532 /* Return function status */ 00533 return HAL_OK; 00534 } 00535 00536 /** 00537 * @brief Stops the TIM Output Compare signal generation on the complementary 00538 * output. 00539 * @param htim TIM handle 00540 * @param Channel TIM Channel to be disabled 00541 * This parameter can be one of the following values: 00542 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00543 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00544 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00545 * @retval HAL status 00546 */ 00547 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) 00548 { 00549 /* Check the parameters */ 00550 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 00551 00552 /* Disable the Capture compare channel N */ 00553 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); 00554 00555 /* Disable the Main Output */ 00556 __HAL_TIM_MOE_DISABLE(htim); 00557 00558 /* Disable the Peripheral */ 00559 __HAL_TIM_DISABLE(htim); 00560 00561 /* Return function status */ 00562 return HAL_OK; 00563 } 00564 00565 /** 00566 * @brief Starts the TIM Output Compare signal generation in interrupt mode 00567 * on the complementary output. 00568 * @param htim TIM OC handle 00569 * @param Channel TIM Channel to be enabled 00570 * This parameter can be one of the following values: 00571 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00572 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00573 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00574 * @retval HAL status 00575 */ 00576 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 00577 { 00578 /* Check the parameters */ 00579 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 00580 00581 switch (Channel) 00582 { 00583 case TIM_CHANNEL_1: 00584 { 00585 /* Enable the TIM Output Compare interrupt */ 00586 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 00587 break; 00588 } 00589 00590 case TIM_CHANNEL_2: 00591 { 00592 /* Enable the TIM Output Compare interrupt */ 00593 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 00594 break; 00595 } 00596 00597 case TIM_CHANNEL_3: 00598 { 00599 /* Enable the TIM Output Compare interrupt */ 00600 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 00601 break; 00602 } 00603 00604 00605 default: 00606 break; 00607 } 00608 00609 /* Enable the TIM Break interrupt */ 00610 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); 00611 00612 /* Enable the Capture compare channel N */ 00613 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); 00614 00615 /* Enable the Main Output */ 00616 __HAL_TIM_MOE_ENABLE(htim); 00617 00618 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 00619 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 00620 { 00621 __HAL_TIM_ENABLE(htim); 00622 } 00623 00624 /* Return function status */ 00625 return HAL_OK; 00626 } 00627 00628 /** 00629 * @brief Stops the TIM Output Compare signal generation in interrupt mode 00630 * on the complementary output. 00631 * @param htim TIM Output Compare handle 00632 * @param Channel TIM Channel to be disabled 00633 * This parameter can be one of the following values: 00634 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00635 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00636 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00637 * @retval HAL status 00638 */ 00639 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 00640 { 00641 uint32_t tmpccer; 00642 /* Check the parameters */ 00643 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 00644 00645 switch (Channel) 00646 { 00647 case TIM_CHANNEL_1: 00648 { 00649 /* Disable the TIM Output Compare interrupt */ 00650 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 00651 break; 00652 } 00653 00654 case TIM_CHANNEL_2: 00655 { 00656 /* Disable the TIM Output Compare interrupt */ 00657 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 00658 break; 00659 } 00660 00661 case TIM_CHANNEL_3: 00662 { 00663 /* Disable the TIM Output Compare interrupt */ 00664 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); 00665 break; 00666 } 00667 00668 default: 00669 break; 00670 } 00671 00672 /* Disable the Capture compare channel N */ 00673 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); 00674 00675 /* Disable the TIM Break interrupt (only if no more channel is active) */ 00676 tmpccer = htim->Instance->CCER; 00677 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) 00678 { 00679 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); 00680 } 00681 00682 /* Disable the Main Output */ 00683 __HAL_TIM_MOE_DISABLE(htim); 00684 00685 /* Disable the Peripheral */ 00686 __HAL_TIM_DISABLE(htim); 00687 00688 /* Return function status */ 00689 return HAL_OK; 00690 } 00691 00692 /** 00693 * @brief Starts the TIM Output Compare signal generation in DMA mode 00694 * on the complementary output. 00695 * @param htim TIM Output Compare handle 00696 * @param Channel TIM Channel to be enabled 00697 * This parameter can be one of the following values: 00698 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00699 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00700 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00701 * @param pData The source Buffer address. 00702 * @param Length The length of data to be transferred from memory to TIM peripheral 00703 * @retval HAL status 00704 */ 00705 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) 00706 { 00707 /* Check the parameters */ 00708 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 00709 00710 if ((htim->State == HAL_TIM_STATE_BUSY)) 00711 { 00712 return HAL_BUSY; 00713 } 00714 else if ((htim->State == HAL_TIM_STATE_READY)) 00715 { 00716 if (((uint32_t)pData == 0U) && (Length > 0U)) 00717 { 00718 return HAL_ERROR; 00719 } 00720 else 00721 { 00722 htim->State = HAL_TIM_STATE_BUSY; 00723 } 00724 } 00725 else 00726 { 00727 /* nothing to do */ 00728 } 00729 00730 switch (Channel) 00731 { 00732 case TIM_CHANNEL_1: 00733 { 00734 /* Set the DMA Period elapsed callback */ 00735 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; 00736 00737 /* Set the DMA error callback */ 00738 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 00739 00740 /* Enable the DMA channel */ 00741 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) 00742 { 00743 return HAL_ERROR; 00744 } 00745 /* Enable the TIM Output Compare DMA request */ 00746 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 00747 break; 00748 } 00749 00750 case TIM_CHANNEL_2: 00751 { 00752 /* Set the DMA Period elapsed callback */ 00753 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; 00754 00755 /* Set the DMA error callback */ 00756 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 00757 00758 /* Enable the DMA channel */ 00759 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) 00760 { 00761 return HAL_ERROR; 00762 } 00763 /* Enable the TIM Output Compare DMA request */ 00764 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 00765 break; 00766 } 00767 00768 case TIM_CHANNEL_3: 00769 { 00770 /* Set the DMA Period elapsed callback */ 00771 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; 00772 00773 /* Set the DMA error callback */ 00774 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 00775 00776 /* Enable the DMA channel */ 00777 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) 00778 { 00779 return HAL_ERROR; 00780 } 00781 /* Enable the TIM Output Compare DMA request */ 00782 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); 00783 break; 00784 } 00785 00786 default: 00787 break; 00788 } 00789 00790 /* Enable the Capture compare channel N */ 00791 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); 00792 00793 /* Enable the Main Output */ 00794 __HAL_TIM_MOE_ENABLE(htim); 00795 00796 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 00797 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 00798 { 00799 __HAL_TIM_ENABLE(htim); 00800 } 00801 00802 /* Return function status */ 00803 return HAL_OK; 00804 } 00805 00806 /** 00807 * @brief Stops the TIM Output Compare signal generation in DMA mode 00808 * on the complementary output. 00809 * @param htim TIM Output Compare handle 00810 * @param Channel TIM Channel to be disabled 00811 * This parameter can be one of the following values: 00812 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00813 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00814 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00815 * @retval HAL status 00816 */ 00817 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) 00818 { 00819 /* Check the parameters */ 00820 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 00821 00822 switch (Channel) 00823 { 00824 case TIM_CHANNEL_1: 00825 { 00826 /* Disable the TIM Output Compare DMA request */ 00827 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 00828 break; 00829 } 00830 00831 case TIM_CHANNEL_2: 00832 { 00833 /* Disable the TIM Output Compare DMA request */ 00834 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 00835 break; 00836 } 00837 00838 case TIM_CHANNEL_3: 00839 { 00840 /* Disable the TIM Output Compare DMA request */ 00841 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); 00842 break; 00843 } 00844 00845 default: 00846 break; 00847 } 00848 00849 /* Disable the Capture compare channel N */ 00850 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); 00851 00852 /* Disable the Main Output */ 00853 __HAL_TIM_MOE_DISABLE(htim); 00854 00855 /* Disable the Peripheral */ 00856 __HAL_TIM_DISABLE(htim); 00857 00858 /* Change the htim state */ 00859 htim->State = HAL_TIM_STATE_READY; 00860 00861 /* Return function status */ 00862 return HAL_OK; 00863 } 00864 00865 /** 00866 * @} 00867 */ 00868 00869 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions 00870 * @brief Timer Complementary PWM functions 00871 * 00872 @verbatim 00873 ============================================================================== 00874 ##### Timer Complementary PWM functions ##### 00875 ============================================================================== 00876 [..] 00877 This section provides functions allowing to: 00878 (+) Start the Complementary PWM. 00879 (+) Stop the Complementary PWM. 00880 (+) Start the Complementary PWM and enable interrupts. 00881 (+) Stop the Complementary PWM and disable interrupts. 00882 (+) Start the Complementary PWM and enable DMA transfers. 00883 (+) Stop the Complementary PWM and disable DMA transfers. 00884 (+) Start the Complementary Input Capture measurement. 00885 (+) Stop the Complementary Input Capture. 00886 (+) Start the Complementary Input Capture and enable interrupts. 00887 (+) Stop the Complementary Input Capture and disable interrupts. 00888 (+) Start the Complementary Input Capture and enable DMA transfers. 00889 (+) Stop the Complementary Input Capture and disable DMA transfers. 00890 (+) Start the Complementary One Pulse generation. 00891 (+) Stop the Complementary One Pulse. 00892 (+) Start the Complementary One Pulse and enable interrupts. 00893 (+) Stop the Complementary One Pulse and disable interrupts. 00894 00895 @endverbatim 00896 * @{ 00897 */ 00898 00899 /** 00900 * @brief Starts the PWM signal generation on the complementary output. 00901 * @param htim TIM handle 00902 * @param Channel TIM Channel to be enabled 00903 * This parameter can be one of the following values: 00904 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00905 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00906 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00907 * @retval HAL status 00908 */ 00909 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) 00910 { 00911 /* Check the parameters */ 00912 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 00913 00914 /* Enable the complementary PWM output */ 00915 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); 00916 00917 /* Enable the Main Output */ 00918 __HAL_TIM_MOE_ENABLE(htim); 00919 00920 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 00921 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 00922 { 00923 __HAL_TIM_ENABLE(htim); 00924 } 00925 00926 /* Return function status */ 00927 return HAL_OK; 00928 } 00929 00930 /** 00931 * @brief Stops the PWM signal generation on the complementary output. 00932 * @param htim TIM handle 00933 * @param Channel TIM Channel to be disabled 00934 * This parameter can be one of the following values: 00935 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00936 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00937 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00938 * @retval HAL status 00939 */ 00940 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) 00941 { 00942 /* Check the parameters */ 00943 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 00944 00945 /* Disable the complementary PWM output */ 00946 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); 00947 00948 /* Disable the Main Output */ 00949 __HAL_TIM_MOE_DISABLE(htim); 00950 00951 /* Disable the Peripheral */ 00952 __HAL_TIM_DISABLE(htim); 00953 00954 /* Return function status */ 00955 return HAL_OK; 00956 } 00957 00958 /** 00959 * @brief Starts the PWM signal generation in interrupt mode on the 00960 * complementary output. 00961 * @param htim TIM handle 00962 * @param Channel TIM Channel to be disabled 00963 * This parameter can be one of the following values: 00964 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00965 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00966 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00967 * @retval HAL status 00968 */ 00969 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 00970 { 00971 /* Check the parameters */ 00972 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 00973 00974 switch (Channel) 00975 { 00976 case TIM_CHANNEL_1: 00977 { 00978 /* Enable the TIM Capture/Compare 1 interrupt */ 00979 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 00980 break; 00981 } 00982 00983 case TIM_CHANNEL_2: 00984 { 00985 /* Enable the TIM Capture/Compare 2 interrupt */ 00986 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 00987 break; 00988 } 00989 00990 case TIM_CHANNEL_3: 00991 { 00992 /* Enable the TIM Capture/Compare 3 interrupt */ 00993 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 00994 break; 00995 } 00996 00997 default: 00998 break; 00999 } 01000 01001 /* Enable the TIM Break interrupt */ 01002 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); 01003 01004 /* Enable the complementary PWM output */ 01005 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); 01006 01007 /* Enable the Main Output */ 01008 __HAL_TIM_MOE_ENABLE(htim); 01009 01010 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 01011 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 01012 { 01013 __HAL_TIM_ENABLE(htim); 01014 } 01015 01016 /* Return function status */ 01017 return HAL_OK; 01018 } 01019 01020 /** 01021 * @brief Stops the PWM signal generation in interrupt mode on the 01022 * complementary output. 01023 * @param htim TIM handle 01024 * @param Channel TIM Channel to be disabled 01025 * This parameter can be one of the following values: 01026 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01027 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01028 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01029 * @retval HAL status 01030 */ 01031 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 01032 { 01033 uint32_t tmpccer; 01034 01035 /* Check the parameters */ 01036 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 01037 01038 switch (Channel) 01039 { 01040 case TIM_CHANNEL_1: 01041 { 01042 /* Disable the TIM Capture/Compare 1 interrupt */ 01043 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 01044 break; 01045 } 01046 01047 case TIM_CHANNEL_2: 01048 { 01049 /* Disable the TIM Capture/Compare 2 interrupt */ 01050 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 01051 break; 01052 } 01053 01054 case TIM_CHANNEL_3: 01055 { 01056 /* Disable the TIM Capture/Compare 3 interrupt */ 01057 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); 01058 break; 01059 } 01060 01061 default: 01062 break; 01063 } 01064 01065 /* Disable the complementary PWM output */ 01066 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); 01067 01068 /* Disable the TIM Break interrupt (only if no more channel is active) */ 01069 tmpccer = htim->Instance->CCER; 01070 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) 01071 { 01072 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); 01073 } 01074 01075 /* Disable the Main Output */ 01076 __HAL_TIM_MOE_DISABLE(htim); 01077 01078 /* Disable the Peripheral */ 01079 __HAL_TIM_DISABLE(htim); 01080 01081 /* Return function status */ 01082 return HAL_OK; 01083 } 01084 01085 /** 01086 * @brief Starts the TIM PWM signal generation in DMA mode on the 01087 * complementary output 01088 * @param htim TIM handle 01089 * @param Channel TIM Channel to be enabled 01090 * This parameter can be one of the following values: 01091 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01092 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01093 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01094 * @param pData The source Buffer address. 01095 * @param Length The length of data to be transferred from memory to TIM peripheral 01096 * @retval HAL status 01097 */ 01098 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) 01099 { 01100 /* Check the parameters */ 01101 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 01102 01103 if ((htim->State == HAL_TIM_STATE_BUSY)) 01104 { 01105 return HAL_BUSY; 01106 } 01107 else if ((htim->State == HAL_TIM_STATE_READY)) 01108 { 01109 if (((uint32_t)pData == 0U) && (Length > 0U)) 01110 { 01111 return HAL_ERROR; 01112 } 01113 else 01114 { 01115 htim->State = HAL_TIM_STATE_BUSY; 01116 } 01117 } 01118 else 01119 { 01120 /* nothing to do */ 01121 } 01122 switch (Channel) 01123 { 01124 case TIM_CHANNEL_1: 01125 { 01126 /* Set the DMA Period elapsed callback */ 01127 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; 01128 01129 /* Set the DMA error callback */ 01130 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 01131 01132 /* Enable the DMA channel */ 01133 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) 01134 { 01135 return HAL_ERROR; 01136 } 01137 /* Enable the TIM Capture/Compare 1 DMA request */ 01138 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 01139 break; 01140 } 01141 01142 case TIM_CHANNEL_2: 01143 { 01144 /* Set the DMA Period elapsed callback */ 01145 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; 01146 01147 /* Set the DMA error callback */ 01148 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 01149 01150 /* Enable the DMA channel */ 01151 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) 01152 { 01153 return HAL_ERROR; 01154 } 01155 /* Enable the TIM Capture/Compare 2 DMA request */ 01156 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 01157 break; 01158 } 01159 01160 case TIM_CHANNEL_3: 01161 { 01162 /* Set the DMA Period elapsed callback */ 01163 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; 01164 01165 /* Set the DMA error callback */ 01166 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 01167 01168 /* Enable the DMA channel */ 01169 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) 01170 { 01171 return HAL_ERROR; 01172 } 01173 /* Enable the TIM Capture/Compare 3 DMA request */ 01174 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); 01175 break; 01176 } 01177 01178 default: 01179 break; 01180 } 01181 01182 /* Enable the complementary PWM output */ 01183 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); 01184 01185 /* Enable the Main Output */ 01186 __HAL_TIM_MOE_ENABLE(htim); 01187 01188 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 01189 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 01190 { 01191 __HAL_TIM_ENABLE(htim); 01192 } 01193 01194 /* Return function status */ 01195 return HAL_OK; 01196 } 01197 01198 /** 01199 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary 01200 * output 01201 * @param htim TIM handle 01202 * @param Channel TIM Channel to be disabled 01203 * This parameter can be one of the following values: 01204 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01205 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01206 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01207 * @retval HAL status 01208 */ 01209 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) 01210 { 01211 /* Check the parameters */ 01212 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 01213 01214 switch (Channel) 01215 { 01216 case TIM_CHANNEL_1: 01217 { 01218 /* Disable the TIM Capture/Compare 1 DMA request */ 01219 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 01220 break; 01221 } 01222 01223 case TIM_CHANNEL_2: 01224 { 01225 /* Disable the TIM Capture/Compare 2 DMA request */ 01226 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 01227 break; 01228 } 01229 01230 case TIM_CHANNEL_3: 01231 { 01232 /* Disable the TIM Capture/Compare 3 DMA request */ 01233 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); 01234 break; 01235 } 01236 01237 default: 01238 break; 01239 } 01240 01241 /* Disable the complementary PWM output */ 01242 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); 01243 01244 /* Disable the Main Output */ 01245 __HAL_TIM_MOE_DISABLE(htim); 01246 01247 /* Disable the Peripheral */ 01248 __HAL_TIM_DISABLE(htim); 01249 01250 /* Change the htim state */ 01251 htim->State = HAL_TIM_STATE_READY; 01252 01253 /* Return function status */ 01254 return HAL_OK; 01255 } 01256 01257 /** 01258 * @} 01259 */ 01260 01261 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions 01262 * @brief Timer Complementary One Pulse functions 01263 * 01264 @verbatim 01265 ============================================================================== 01266 ##### Timer Complementary One Pulse functions ##### 01267 ============================================================================== 01268 [..] 01269 This section provides functions allowing to: 01270 (+) Start the Complementary One Pulse generation. 01271 (+) Stop the Complementary One Pulse. 01272 (+) Start the Complementary One Pulse and enable interrupts. 01273 (+) Stop the Complementary One Pulse and disable interrupts. 01274 01275 @endverbatim 01276 * @{ 01277 */ 01278 01279 /** 01280 * @brief Starts the TIM One Pulse signal generation on the complementary 01281 * output. 01282 * @param htim TIM One Pulse handle 01283 * @param OutputChannel TIM Channel to be enabled 01284 * This parameter can be one of the following values: 01285 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01286 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01287 * @retval HAL status 01288 */ 01289 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) 01290 { 01291 /* Check the parameters */ 01292 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); 01293 01294 /* Enable the complementary One Pulse output */ 01295 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); 01296 01297 /* Enable the Main Output */ 01298 __HAL_TIM_MOE_ENABLE(htim); 01299 01300 /* Return function status */ 01301 return HAL_OK; 01302 } 01303 01304 /** 01305 * @brief Stops the TIM One Pulse signal generation on the complementary 01306 * output. 01307 * @param htim TIM One Pulse handle 01308 * @param OutputChannel TIM Channel to be disabled 01309 * This parameter can be one of the following values: 01310 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01311 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01312 * @retval HAL status 01313 */ 01314 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) 01315 { 01316 01317 /* Check the parameters */ 01318 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); 01319 01320 /* Disable the complementary One Pulse output */ 01321 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); 01322 01323 /* Disable the Main Output */ 01324 __HAL_TIM_MOE_DISABLE(htim); 01325 01326 /* Disable the Peripheral */ 01327 __HAL_TIM_DISABLE(htim); 01328 01329 /* Return function status */ 01330 return HAL_OK; 01331 } 01332 01333 /** 01334 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the 01335 * complementary channel. 01336 * @param htim TIM One Pulse handle 01337 * @param OutputChannel TIM Channel to be enabled 01338 * This parameter can be one of the following values: 01339 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01340 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01341 * @retval HAL status 01342 */ 01343 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) 01344 { 01345 /* Check the parameters */ 01346 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); 01347 01348 /* Enable the TIM Capture/Compare 1 interrupt */ 01349 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 01350 01351 /* Enable the TIM Capture/Compare 2 interrupt */ 01352 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 01353 01354 /* Enable the complementary One Pulse output */ 01355 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); 01356 01357 /* Enable the Main Output */ 01358 __HAL_TIM_MOE_ENABLE(htim); 01359 01360 /* Return function status */ 01361 return HAL_OK; 01362 } 01363 01364 /** 01365 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the 01366 * complementary channel. 01367 * @param htim TIM One Pulse handle 01368 * @param OutputChannel TIM Channel to be disabled 01369 * This parameter can be one of the following values: 01370 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01371 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01372 * @retval HAL status 01373 */ 01374 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) 01375 { 01376 /* Check the parameters */ 01377 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); 01378 01379 /* Disable the TIM Capture/Compare 1 interrupt */ 01380 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 01381 01382 /* Disable the TIM Capture/Compare 2 interrupt */ 01383 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 01384 01385 /* Disable the complementary One Pulse output */ 01386 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); 01387 01388 /* Disable the Main Output */ 01389 __HAL_TIM_MOE_DISABLE(htim); 01390 01391 /* Disable the Peripheral */ 01392 __HAL_TIM_DISABLE(htim); 01393 01394 /* Return function status */ 01395 return HAL_OK; 01396 } 01397 01398 /** 01399 * @} 01400 */ 01401 01402 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions 01403 * @brief Peripheral Control functions 01404 * 01405 @verbatim 01406 ============================================================================== 01407 ##### Peripheral Control functions ##### 01408 ============================================================================== 01409 [..] 01410 This section provides functions allowing to: 01411 (+) Configure the commutation event in case of use of the Hall sensor interface. 01412 (+) Configure Output channels for OC and PWM mode. 01413 01414 (+) Configure Complementary channels, break features and dead time. 01415 (+) Configure Master synchronization. 01416 (+) Configure timer remapping capabilities. 01417 (+) Enable or disable channel grouping. 01418 01419 @endverbatim 01420 * @{ 01421 */ 01422 01423 /** 01424 * @brief Configure the TIM commutation event sequence. 01425 * @note This function is mandatory to use the commutation event in order to 01426 * update the configuration at each commutation detection on the TRGI input of the Timer, 01427 * the typical use of this feature is with the use of another Timer(interface Timer) 01428 * configured in Hall sensor interface, this interface Timer will generate the 01429 * commutation at its TRGO output (connected to Timer used in this function) each time 01430 * the TI1 of the Interface Timer detect a commutation at its input TI1. 01431 * @param htim TIM handle 01432 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor 01433 * This parameter can be one of the following values: 01434 * @arg TIM_TS_ITR0: Internal trigger 0 selected 01435 * @arg TIM_TS_ITR1: Internal trigger 1 selected 01436 * @arg TIM_TS_ITR2: Internal trigger 2 selected 01437 * @arg TIM_TS_ITR3: Internal trigger 3 selected 01438 * @arg TIM_TS_NONE: No trigger is needed 01439 * @param CommutationSource the Commutation Event source 01440 * This parameter can be one of the following values: 01441 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer 01442 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit 01443 * @retval HAL status 01444 */ 01445 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) 01446 { 01447 /* Check the parameters */ 01448 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); 01449 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); 01450 01451 __HAL_LOCK(htim); 01452 01453 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || 01454 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) 01455 { 01456 /* Select the Input trigger */ 01457 htim->Instance->SMCR &= ~TIM_SMCR_TS; 01458 htim->Instance->SMCR |= InputTrigger; 01459 } 01460 01461 /* Select the Capture Compare preload feature */ 01462 htim->Instance->CR2 |= TIM_CR2_CCPC; 01463 /* Select the Commutation event source */ 01464 htim->Instance->CR2 &= ~TIM_CR2_CCUS; 01465 htim->Instance->CR2 |= CommutationSource; 01466 01467 __HAL_UNLOCK(htim); 01468 01469 return HAL_OK; 01470 } 01471 01472 /** 01473 * @brief Configure the TIM commutation event sequence with interrupt. 01474 * @note This function is mandatory to use the commutation event in order to 01475 * update the configuration at each commutation detection on the TRGI input of the Timer, 01476 * the typical use of this feature is with the use of another Timer(interface Timer) 01477 * configured in Hall sensor interface, this interface Timer will generate the 01478 * commutation at its TRGO output (connected to Timer used in this function) each time 01479 * the TI1 of the Interface Timer detect a commutation at its input TI1. 01480 * @param htim TIM handle 01481 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor 01482 * This parameter can be one of the following values: 01483 * @arg TIM_TS_ITR0: Internal trigger 0 selected 01484 * @arg TIM_TS_ITR1: Internal trigger 1 selected 01485 * @arg TIM_TS_ITR2: Internal trigger 2 selected 01486 * @arg TIM_TS_ITR3: Internal trigger 3 selected 01487 * @arg TIM_TS_NONE: No trigger is needed 01488 * @param CommutationSource the Commutation Event source 01489 * This parameter can be one of the following values: 01490 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer 01491 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit 01492 * @retval HAL status 01493 */ 01494 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) 01495 { 01496 /* Check the parameters */ 01497 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); 01498 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); 01499 01500 __HAL_LOCK(htim); 01501 01502 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || 01503 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) 01504 { 01505 /* Select the Input trigger */ 01506 htim->Instance->SMCR &= ~TIM_SMCR_TS; 01507 htim->Instance->SMCR |= InputTrigger; 01508 } 01509 01510 /* Select the Capture Compare preload feature */ 01511 htim->Instance->CR2 |= TIM_CR2_CCPC; 01512 /* Select the Commutation event source */ 01513 htim->Instance->CR2 &= ~TIM_CR2_CCUS; 01514 htim->Instance->CR2 |= CommutationSource; 01515 01516 /* Enable the Commutation Interrupt Request */ 01517 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); 01518 01519 __HAL_UNLOCK(htim); 01520 01521 return HAL_OK; 01522 } 01523 01524 /** 01525 * @brief Configure the TIM commutation event sequence with DMA. 01526 * @note This function is mandatory to use the commutation event in order to 01527 * update the configuration at each commutation detection on the TRGI input of the Timer, 01528 * the typical use of this feature is with the use of another Timer(interface Timer) 01529 * configured in Hall sensor interface, this interface Timer will generate the 01530 * commutation at its TRGO output (connected to Timer used in this function) each time 01531 * the TI1 of the Interface Timer detect a commutation at its input TI1. 01532 * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set 01533 * @param htim TIM handle 01534 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor 01535 * This parameter can be one of the following values: 01536 * @arg TIM_TS_ITR0: Internal trigger 0 selected 01537 * @arg TIM_TS_ITR1: Internal trigger 1 selected 01538 * @arg TIM_TS_ITR2: Internal trigger 2 selected 01539 * @arg TIM_TS_ITR3: Internal trigger 3 selected 01540 * @arg TIM_TS_NONE: No trigger is needed 01541 * @param CommutationSource the Commutation Event source 01542 * This parameter can be one of the following values: 01543 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer 01544 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit 01545 * @retval HAL status 01546 */ 01547 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) 01548 { 01549 /* Check the parameters */ 01550 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); 01551 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); 01552 01553 __HAL_LOCK(htim); 01554 01555 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || 01556 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) 01557 { 01558 /* Select the Input trigger */ 01559 htim->Instance->SMCR &= ~TIM_SMCR_TS; 01560 htim->Instance->SMCR |= InputTrigger; 01561 } 01562 01563 /* Select the Capture Compare preload feature */ 01564 htim->Instance->CR2 |= TIM_CR2_CCPC; 01565 /* Select the Commutation event source */ 01566 htim->Instance->CR2 &= ~TIM_CR2_CCUS; 01567 htim->Instance->CR2 |= CommutationSource; 01568 01569 /* Enable the Commutation DMA Request */ 01570 /* Set the DMA Commutation Callback */ 01571 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; 01572 /* Set the DMA error callback */ 01573 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; 01574 01575 /* Enable the Commutation DMA Request */ 01576 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); 01577 01578 __HAL_UNLOCK(htim); 01579 01580 return HAL_OK; 01581 } 01582 01583 /** 01584 * @brief Configures the TIM in master mode. 01585 * @param htim TIM handle. 01586 * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that 01587 * contains the selected trigger output (TRGO) and the Master/Slave 01588 * mode. 01589 * @retval HAL status 01590 */ 01591 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, 01592 TIM_MasterConfigTypeDef *sMasterConfig) 01593 { 01594 uint32_t tmpcr2; 01595 uint32_t tmpsmcr; 01596 01597 /* Check the parameters */ 01598 assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); 01599 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); 01600 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); 01601 01602 /* Check input state */ 01603 __HAL_LOCK(htim); 01604 01605 /* Change the handler state */ 01606 htim->State = HAL_TIM_STATE_BUSY; 01607 01608 /* Get the TIMx CR2 register value */ 01609 tmpcr2 = htim->Instance->CR2; 01610 01611 /* Get the TIMx SMCR register value */ 01612 tmpsmcr = htim->Instance->SMCR; 01613 01614 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ 01615 if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 01616 { 01617 /* Check the parameters */ 01618 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); 01619 01620 /* Clear the MMS2 bits */ 01621 tmpcr2 &= ~TIM_CR2_MMS2; 01622 /* Select the TRGO2 source*/ 01623 tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 01624 } 01625 01626 /* Reset the MMS Bits */ 01627 tmpcr2 &= ~TIM_CR2_MMS; 01628 /* Select the TRGO source */ 01629 tmpcr2 |= sMasterConfig->MasterOutputTrigger; 01630 01631 /* Reset the MSM Bit */ 01632 tmpsmcr &= ~TIM_SMCR_MSM; 01633 /* Set master mode */ 01634 tmpsmcr |= sMasterConfig->MasterSlaveMode; 01635 01636 /* Update TIMx CR2 */ 01637 htim->Instance->CR2 = tmpcr2; 01638 01639 /* Update TIMx SMCR */ 01640 htim->Instance->SMCR = tmpsmcr; 01641 01642 /* Change the htim state */ 01643 htim->State = HAL_TIM_STATE_READY; 01644 01645 __HAL_UNLOCK(htim); 01646 01647 return HAL_OK; 01648 } 01649 01650 /** 01651 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State 01652 * and the AOE(automatic output enable). 01653 * @param htim TIM handle 01654 * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that 01655 * contains the BDTR Register configuration information for the TIM peripheral. 01656 * @retval HAL status 01657 */ 01658 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, 01659 TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) 01660 { 01661 /* Keep this variable initialized to 0 as it is used to configure BDTR register */ 01662 uint32_t tmpbdtr = 0U; 01663 01664 /* Check the parameters */ 01665 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); 01666 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); 01667 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); 01668 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); 01669 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); 01670 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); 01671 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); 01672 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); 01673 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); 01674 01675 /* Check input state */ 01676 __HAL_LOCK(htim); 01677 01678 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, 01679 the OSSI State, the dead time value and the Automatic Output Enable Bit */ 01680 01681 /* Set the BDTR bits */ 01682 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); 01683 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); 01684 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 01685 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 01686 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 01687 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 01688 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 01689 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 01690 01691 if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) 01692 { 01693 /* Check the parameters */ 01694 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); 01695 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); 01696 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); 01697 01698 /* Set the BREAK2 input related BDTR bits */ 01699 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); 01700 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); 01701 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); 01702 } 01703 01704 /* Set TIMx_BDTR */ 01705 htim->Instance->BDTR = tmpbdtr; 01706 01707 __HAL_UNLOCK(htim); 01708 01709 return HAL_OK; 01710 } 01711 01712 /** 01713 * @brief Configures the break input source. 01714 * @param htim TIM handle. 01715 * @param BreakInput Break input to configure 01716 * This parameter can be one of the following values: 01717 * @arg TIM_BREAKINPUT_BRK: Timer break input 01718 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input 01719 * @param sBreakInputConfig Break input source configuration 01720 * @retval HAL status 01721 */ 01722 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, 01723 uint32_t BreakInput, 01724 TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) 01725 01726 { 01727 uint32_t tmporx; 01728 uint32_t bkin_enable_mask = 0U; 01729 uint32_t bkin_polarity_mask = 0U; 01730 uint32_t bkin_enable_bitpos = 0U; 01731 uint32_t bkin_polarity_bitpos = 0U; 01732 01733 /* Check the parameters */ 01734 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); 01735 assert_param(IS_TIM_BREAKINPUT(BreakInput)); 01736 assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); 01737 assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); 01738 #if defined(DFSDM1_Channel0) 01739 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) 01740 { 01741 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); 01742 } 01743 #else 01744 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); 01745 #endif /* DFSDM1_Channel0 */ 01746 01747 /* Check input state */ 01748 __HAL_LOCK(htim); 01749 01750 switch (sBreakInputConfig->Source) 01751 { 01752 case TIM_BREAKINPUTSOURCE_BKIN: 01753 { 01754 bkin_enable_mask = TIM1_OR2_BKINE; 01755 bkin_enable_bitpos = TIM1_OR2_BKINE_Pos; 01756 bkin_polarity_mask = TIM1_OR2_BKINP; 01757 bkin_polarity_bitpos = TIM1_OR2_BKINP_Pos; 01758 break; 01759 } 01760 case TIM_BREAKINPUTSOURCE_COMP1: 01761 { 01762 bkin_enable_mask = TIM1_OR2_BKCMP1E; 01763 bkin_enable_bitpos = TIM1_OR2_BKCMP1E_Pos; 01764 bkin_polarity_mask = TIM1_OR2_BKCMP1P; 01765 bkin_polarity_bitpos = TIM1_OR2_BKCMP1P_Pos; 01766 break; 01767 } 01768 case TIM_BREAKINPUTSOURCE_COMP2: 01769 { 01770 bkin_enable_mask = TIM1_OR2_BKCMP2E; 01771 bkin_enable_bitpos = TIM1_OR2_BKCMP2E_Pos; 01772 bkin_polarity_mask = TIM1_OR2_BKCMP2P; 01773 bkin_polarity_bitpos = TIM1_OR2_BKCMP2P_Pos; 01774 break; 01775 } 01776 #if defined(DFSDM1_Channel0) 01777 case TIM_BREAKINPUTSOURCE_DFSDM1: 01778 { 01779 bkin_enable_mask = TIM1_OR2_BKDF1BK0E; 01780 bkin_enable_bitpos = 8U; 01781 break; 01782 } 01783 #endif /* DFSDM1_Channel0 */ 01784 01785 default: 01786 break; 01787 } 01788 01789 switch (BreakInput) 01790 { 01791 case TIM_BREAKINPUT_BRK: 01792 { 01793 /* Get the TIMx_OR2 register value */ 01794 tmporx = htim->Instance->OR2; 01795 01796 /* Enable the break input */ 01797 tmporx &= ~bkin_enable_mask; 01798 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; 01799 01800 /* Set the break input polarity */ 01801 #if defined(DFSDM1_Channel0) 01802 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) 01803 #endif /* DFSDM1_Channel0 */ 01804 { 01805 tmporx &= ~bkin_polarity_mask; 01806 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; 01807 } 01808 01809 /* Set TIMx_OR2 */ 01810 htim->Instance->OR2 = tmporx; 01811 break; 01812 } 01813 case TIM_BREAKINPUT_BRK2: 01814 { 01815 /* Get the TIMx_OR3 register value */ 01816 tmporx = htim->Instance->OR3; 01817 01818 /* Enable the break input */ 01819 tmporx &= ~bkin_enable_mask; 01820 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; 01821 01822 /* Set the break input polarity */ 01823 #if defined(DFSDM1_Channel0) 01824 if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) 01825 #endif /* DFSDM1_Channel0 */ 01826 { 01827 tmporx &= ~bkin_polarity_mask; 01828 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; 01829 } 01830 01831 /* Set TIMx_OR3 */ 01832 htim->Instance->OR3 = tmporx; 01833 break; 01834 } 01835 default: 01836 break; 01837 } 01838 01839 __HAL_UNLOCK(htim); 01840 01841 return HAL_OK; 01842 } 01843 01844 /** 01845 * @brief Configures the TIMx Remapping input capabilities. 01846 * @param htim TIM handle. 01847 * @param Remap specifies the TIM remapping source. 01848 @if STM32L486xx 01849 * For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4): 01850 * 01851 * field1 can have the following values: 01852 * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog) 01853 * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 01854 * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 01855 * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 01856 * 01857 * field2 can have the following values: 01858 * @arg TIM_TIM1_ETR_ADC3_NONE: TIM1_ETR is not connected to any ADC3 AWD (analog watchdog) 01859 * @arg TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1 01860 * @arg TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2 01861 * @arg TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3 01862 * 01863 * field3 can have the following values: 01864 * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO 01865 * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output 01866 * 01867 * field4 can have the following values: 01868 * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output 01869 * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output 01870 * @note When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant 01871 @endif 01872 @if STM32L443xx 01873 * For TIM1, the parameter is a combination of 3 fields (field1 | field2 | field3): 01874 * 01875 * field1 can have the following values: 01876 * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog) 01877 * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 01878 * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 01879 * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 01880 * 01881 * field2 can have the following values: 01882 * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO 01883 * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output 01884 * 01885 * field3 can have the following values: 01886 * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output 01887 * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output 01888 * 01889 * @note When field3 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 values is not significant 01890 * 01891 @endif 01892 @if STM32L486xx 01893 * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3): 01894 * 01895 * field1 can have the following values: 01896 * @arg TIM_TIM2_ITR1_TIM8_TRGO: TIM2_ITR1 is connected to TIM8_TRGO 01897 * @arg TIM_TIM2_ITR1_OTG_FS_SOF: TIM2_ITR1 is connected to OTG_FS SOF 01898 * 01899 * field2 can have the following values: 01900 * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO 01901 * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE 01902 * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output 01903 * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output 01904 * 01905 * field3 can have the following values: 01906 * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO 01907 * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output 01908 * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output 01909 * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output 01910 @endif 01911 @if STM32L443xx 01912 * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3): 01913 * 01914 * field1 can have the following values: 01915 * @arg TIM_TIM2_ITR1_NONE: No internal trigger on TIM2_ITR1 01916 * @arg TIM_TIM2_ITR1_USB_SOF: TIM2_ITR1 is connected to USB SOF 01917 * 01918 * field2 can have the following values: 01919 * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO 01920 * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE 01921 * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output 01922 * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output 01923 * 01924 * field3 can have the following values: 01925 * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO 01926 * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output 01927 * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output 01928 * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output 01929 * 01930 @endif 01931 @if STM32L486xx 01932 * For TIM3, the parameter is a combination 2 fields(field1 | field2): 01933 * 01934 * field1 can have the following values: 01935 * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO 01936 * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output 01937 * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output 01938 * @arg TIM_TIM3_TI1_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output 01939 * 01940 * field2 can have the following values: 01941 * @arg TIM_TIM3_ETR_GPIO: TIM3_ETR is connected to GPIO 01942 * @arg TIM_TIM3_ETR_COMP1: TIM3_ETR is connected to COMP1 output 01943 * 01944 @endif 01945 @if STM32L486xx 01946 * For TIM8, the parameter is a combination of 3 fields (field1 | field2 | field3): 01947 * 01948 * field1 can have the following values: 01949 * @arg TIM_TIM8_ETR_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD (analog watchdog) 01950 * @arg TIM_TIM8_ETR_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1 01951 * @arg TIM_TIM8_ETR_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2 01952 * @arg TIM_TIM8_ETR_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3 01953 * 01954 * field2 can have the following values: 01955 * @arg TIM_TIM8_ETR_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD (analog watchdog) 01956 * @arg TIM_TIM8_ETR_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1 01957 * @arg TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2 01958 * @arg TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3 01959 * 01960 * field3 can have the following values: 01961 * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO 01962 * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output 01963 * 01964 * field4 can have the following values: 01965 * @arg TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output 01966 * @arg TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output 01967 * @note When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant 01968 * 01969 @endif 01970 * For TIM15, the parameter is a combination of 3 fields (field1 | field2): 01971 * 01972 * field1 can have the following values: 01973 * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO 01974 * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE 01975 * 01976 * field2 can have the following values: 01977 * @arg TIM_TIM15_ENCODERMODE_NONE: No redirection 01978 * @arg TIM_TIM15_ENCODERMODE_TIM2: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively 01979 * @arg TIM_TIM15_ENCODERMODE_TIM3: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively 01980 * @arg TIM_TIM15_ENCODERMODE_TIM4: TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively 01981 * 01982 @if STM32L486xx 01983 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO 01984 * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI 01985 * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE 01986 * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt 01987 * 01988 @endif 01989 @if STM32L443xx 01990 * For TIM16, the parameter can have the following values: 01991 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO 01992 * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI 01993 * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE 01994 * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt 01995 * @arg TIM_TIM16_TI1_MSI: TIM16 TI1 is connected to MSI (contraints: MSI clock < 1/4 TIM APB clock) 01996 * @arg TIM_TIM16_TI1_HSE_32: TIM16 TI1 is connected to HSE div 32 (note that HSE div 32 must be selected as RTC clock source) 01997 * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO 01998 * 01999 @endif 02000 @if STM32L486xx 02001 * For TIM17, the parameter can have the following values: 02002 * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO 02003 * @arg TIM_TIM17_TI1_MSI: TIM17 TI1 is connected to MSI (contraints: MSI clock < 1/4 TIM APB clock) 02004 * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32 02005 * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO 02006 @endif 02007 * 02008 * @retval HAL status 02009 */ 02010 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) 02011 { 02012 uint32_t tmpor1 = 0U; 02013 uint32_t tmpor2 = 0U; 02014 02015 __HAL_LOCK(htim); 02016 02017 /* Check parameters */ 02018 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); 02019 assert_param(IS_TIM_REMAP(Remap)); 02020 02021 /* Set ETR_SEL bit field (if required) */ 02022 if (IS_TIM_ETRSEL_INSTANCE(htim->Instance)) 02023 { 02024 tmpor2 = htim->Instance->OR2; 02025 tmpor2 &= ~TIM1_OR2_ETRSEL_Msk; 02026 tmpor2 |= (Remap & TIM1_OR2_ETRSEL_Msk); 02027 02028 /* Set TIMx_OR2 */ 02029 htim->Instance->OR2 = tmpor2; 02030 } 02031 02032 /* Set other remapping capabilities */ 02033 tmpor1 = Remap; 02034 tmpor1 &= ~TIM1_OR2_ETRSEL_Msk; 02035 02036 /* Set TIMx_OR1 */ 02037 htim->Instance->OR1 = tmpor1; 02038 02039 __HAL_UNLOCK(htim); 02040 02041 return HAL_OK; 02042 } 02043 02044 /** 02045 * @brief Group channel 5 and channel 1, 2 or 3 02046 * @param htim TIM handle. 02047 * @param Channels specifies the reference signal(s) the OC5REF is combined with. 02048 * This parameter can be any combination of the following values: 02049 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC 02050 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF 02051 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF 02052 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF 02053 * @retval HAL status 02054 */ 02055 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) 02056 { 02057 /* Check parameters */ 02058 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); 02059 assert_param(IS_TIM_GROUPCH5(Channels)); 02060 02061 /* Process Locked */ 02062 __HAL_LOCK(htim); 02063 02064 htim->State = HAL_TIM_STATE_BUSY; 02065 02066 /* Clear GC5Cx bit fields */ 02067 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); 02068 02069 /* Set GC5Cx bit fields */ 02070 htim->Instance->CCR5 |= Channels; 02071 02072 /* Change the htim state */ 02073 htim->State = HAL_TIM_STATE_READY; 02074 02075 __HAL_UNLOCK(htim); 02076 02077 return HAL_OK; 02078 } 02079 02080 /** 02081 * @} 02082 */ 02083 02084 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions 02085 * @brief Extended Callbacks functions 02086 * 02087 @verbatim 02088 ============================================================================== 02089 ##### Extended Callbacks functions ##### 02090 ============================================================================== 02091 [..] 02092 This section provides Extended TIM callback functions: 02093 (+) Timer Commutation callback 02094 (+) Timer Break callback 02095 02096 @endverbatim 02097 * @{ 02098 */ 02099 02100 /** 02101 * @brief Hall commutation changed callback in non-blocking mode 02102 * @param htim TIM handle 02103 * @retval None 02104 */ 02105 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) 02106 { 02107 /* Prevent unused argument(s) compilation warning */ 02108 UNUSED(htim); 02109 02110 /* NOTE : This function should not be modified, when the callback is needed, 02111 the HAL_TIMEx_CommutationCallback could be implemented in the user file 02112 */ 02113 } 02114 02115 /** 02116 * @brief Hall Break detection callback in non-blocking mode 02117 * @param htim TIM handle 02118 * @retval None 02119 */ 02120 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) 02121 { 02122 /* Prevent unused argument(s) compilation warning */ 02123 UNUSED(htim); 02124 02125 /* NOTE : This function should not be modified, when the callback is needed, 02126 the HAL_TIMEx_BreakCallback could be implemented in the user file 02127 */ 02128 } 02129 02130 /** 02131 * @brief Hall Break2 detection callback in non blocking mode 02132 * @param htim: TIM handle 02133 * @retval None 02134 */ 02135 __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) 02136 { 02137 /* Prevent unused argument(s) compilation warning */ 02138 UNUSED(htim); 02139 02140 /* NOTE : This function Should not be modified, when the callback is needed, 02141 the HAL_TIMEx_Break2Callback could be implemented in the user file 02142 */ 02143 } 02144 /** 02145 * @} 02146 */ 02147 02148 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions 02149 * @brief Extended Peripheral State functions 02150 * 02151 @verbatim 02152 ============================================================================== 02153 ##### Extended Peripheral State functions ##### 02154 ============================================================================== 02155 [..] 02156 This subsection permits to get in run-time the status of the peripheral 02157 and the data flow. 02158 02159 @endverbatim 02160 * @{ 02161 */ 02162 02163 /** 02164 * @brief Return the TIM Hall Sensor interface handle state. 02165 * @param htim TIM Hall Sensor handle 02166 * @retval HAL state 02167 */ 02168 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) 02169 { 02170 return htim->State; 02171 } 02172 02173 /** 02174 * @} 02175 */ 02176 02177 /** 02178 * @} 02179 */ 02180 02181 /* Private functions ---------------------------------------------------------*/ 02182 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions 02183 * @{ 02184 */ 02185 02186 /** 02187 * @brief TIM DMA Commutation callback. 02188 * @param hdma pointer to DMA handle. 02189 * @retval None 02190 */ 02191 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) 02192 { 02193 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 02194 02195 /* Change the htim state */ 02196 htim->State = HAL_TIM_STATE_READY; 02197 02198 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 02199 htim->CommutationCallback(htim); 02200 #else 02201 HAL_TIMEx_CommutationCallback(htim); 02202 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 02203 } 02204 02205 /** 02206 * @brief Enables or disables the TIM Capture Compare Channel xN. 02207 * @param TIMx to select the TIM peripheral 02208 * @param Channel specifies the TIM Channel 02209 * This parameter can be one of the following values: 02210 * @arg TIM_CHANNEL_1: TIM Channel 1 02211 * @arg TIM_CHANNEL_2: TIM Channel 2 02212 * @arg TIM_CHANNEL_3: TIM Channel 3 02213 * @param ChannelNState specifies the TIM Channel CCxNE bit new state. 02214 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. 02215 * @retval None 02216 */ 02217 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) 02218 { 02219 uint32_t tmp; 02220 02221 tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 02222 02223 /* Reset the CCxNE Bit */ 02224 TIMx->CCER &= ~tmp; 02225 02226 /* Set or reset the CCxNE Bit */ 02227 TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 02228 } 02229 /** 02230 * @} 02231 */ 02232 02233 #endif /* HAL_TIM_MODULE_ENABLED */ 02234 /** 02235 * @} 02236 */ 02237 02238 /** 02239 * @} 02240 */ 02241 02242 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/