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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_rcc_ex.c 00004 * @author MCD Application Team 00005 * @brief Extended RCC HAL module driver. 00006 * This file provides firmware functions to manage the following 00007 * functionalities RCC extended peripheral: 00008 * + Extended Peripheral Control functions 00009 * + Extended Clock management functions 00010 * + Extended Clock Recovery System Control functions 00011 * 00012 ****************************************************************************** 00013 * @attention 00014 * 00015 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00016 * 00017 * Redistribution and use in source and binary forms, with or without modification, 00018 * are permitted provided that the following conditions are met: 00019 * 1. Redistributions of source code must retain the above copyright notice, 00020 * this list of conditions and the following disclaimer. 00021 * 2. Redistributions in binary form must reproduce the above copyright notice, 00022 * this list of conditions and the following disclaimer in the documentation 00023 * and/or other materials provided with the distribution. 00024 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00025 * may be used to endorse or promote products derived from this software 00026 * without specific prior written permission. 00027 * 00028 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00029 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00030 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00031 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00032 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00033 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00034 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00035 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00036 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00037 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00038 * 00039 ****************************************************************************** 00040 */ 00041 00042 /* Includes ------------------------------------------------------------------*/ 00043 #include "stm32l4xx_hal.h" 00044 00045 /** @addtogroup STM32L4xx_HAL_Driver 00046 * @{ 00047 */ 00048 00049 /** @defgroup RCCEx RCCEx 00050 * @brief RCC Extended HAL module driver 00051 * @{ 00052 */ 00053 00054 #ifdef HAL_RCC_MODULE_ENABLED 00055 00056 /* Private typedef -----------------------------------------------------------*/ 00057 /* Private defines -----------------------------------------------------------*/ 00058 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants 00059 * @{ 00060 */ 00061 #define PLLSAI1_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 00062 #define PLLSAI2_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 00063 #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 00064 00065 #define DIVIDER_P_UPDATE 0U 00066 #define DIVIDER_Q_UPDATE 1U 00067 #define DIVIDER_R_UPDATE 2U 00068 00069 #define __LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() 00070 #define LSCO_GPIO_PORT GPIOA 00071 #define LSCO_PIN GPIO_PIN_2 00072 /** 00073 * @} 00074 */ 00075 00076 /* Private macros ------------------------------------------------------------*/ 00077 /* Private variables ---------------------------------------------------------*/ 00078 /* Private function prototypes -----------------------------------------------*/ 00079 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions 00080 * @{ 00081 */ 00082 static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider); 00083 00084 #if defined(RCC_PLLSAI2_SUPPORT) 00085 00086 static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider); 00087 00088 #endif /* RCC_PLLSAI2_SUPPORT */ 00089 00090 /** 00091 * @} 00092 */ 00093 00094 /* Exported functions --------------------------------------------------------*/ 00095 00096 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions 00097 * @{ 00098 */ 00099 00100 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions 00101 * @brief Extended Peripheral Control functions 00102 * 00103 @verbatim 00104 =============================================================================== 00105 ##### Extended Peripheral Control functions ##### 00106 =============================================================================== 00107 [..] 00108 This subsection provides a set of functions allowing to control the RCC Clocks 00109 frequencies. 00110 [..] 00111 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to 00112 select the RTC clock source; in this case the Backup domain will be reset in 00113 order to modify the RTC Clock source, as consequence RTC registers (including 00114 the backup registers) are set to their reset values. 00115 00116 @endverbatim 00117 * @{ 00118 */ 00119 /** 00120 * @brief Initialize the RCC extended peripherals clocks according to the specified 00121 * parameters in the RCC_PeriphCLKInitTypeDef. 00122 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that 00123 * contains a field PeriphClockSelection which can be a combination of the following values: 00124 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock 00125 * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock 00126 @if STM32L462xx 00127 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM1) 00128 @endif 00129 @if STM32L486xx 00130 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM1) 00131 @endif 00132 @if STM32L4A6xx 00133 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM1) 00134 @endif 00135 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock 00136 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock 00137 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock 00138 @if STM32L462xx 00139 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) 00140 @endif 00141 @if STM32L4A6xx 00142 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) 00143 @endif 00144 @if STM32L4S9xx 00145 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) 00146 @endif 00147 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock 00148 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock 00149 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock 00150 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock 00151 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock 00152 @if STM32L486xx 00153 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) 00154 @endif 00155 @if STM32L4A6xx 00156 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) 00157 @endif 00158 @if STM32L4S9xx 00159 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) 00160 @endif 00161 * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock 00162 @if STM32L443xx 00163 * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) 00164 @endif 00165 @if STM32L486xx 00166 * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) 00167 @endif 00168 @if STM32L4A6xx 00169 * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) 00170 @endif 00171 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock 00172 * @arg @ref RCC_PERIPHCLK_USART2 USART1 peripheral clock 00173 * @arg @ref RCC_PERIPHCLK_USART3 USART1 peripheral clock 00174 @if STM32L462xx 00175 * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) 00176 @endif 00177 @if STM32L486xx 00178 * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) 00179 * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) 00180 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) 00181 @endif 00182 @if STM32L4A6xx 00183 * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) 00184 * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) 00185 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) 00186 @endif 00187 @if STM32L4S9xx 00188 * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) 00189 * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) 00190 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) 00191 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral kernel clock (only for devices with DFSDM1) 00192 * @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO DFSDM1 peripheral audio clock (only for devices with DFSDM1) 00193 * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (only for devices with LTDC) 00194 * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock (only for devices with DSI) 00195 * @arg @ref RCC_PERIPHCLK_OSPI OctoSPI peripheral clock (only for devices with OctoSPI) 00196 @endif 00197 * 00198 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select 00199 * the RTC clock source: in this case the access to Backup domain is enabled. 00200 * 00201 * @retval HAL status 00202 */ 00203 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) 00204 { 00205 uint32_t tmpregister = 0; 00206 uint32_t tickstart = 0U; 00207 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 00208 HAL_StatusTypeDef status = HAL_OK; /* Final status */ 00209 00210 /* Check the parameters */ 00211 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); 00212 00213 /*-------------------------- SAI1 clock source configuration ---------------------*/ 00214 if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) 00215 { 00216 /* Check the parameters */ 00217 assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection)); 00218 00219 switch(PeriphClkInit->Sai1ClockSelection) 00220 { 00221 case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ 00222 /* Enable SAI Clock output generated form System PLL . */ 00223 #if defined(RCC_PLLSAI2_SUPPORT) 00224 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); 00225 #else 00226 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK); 00227 #endif /* RCC_PLLSAI2_SUPPORT */ 00228 /* SAI1 clock source config set later after clock selection check */ 00229 break; 00230 00231 case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/ 00232 /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */ 00233 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE); 00234 /* SAI1 clock source config set later after clock selection check */ 00235 break; 00236 00237 #if defined(RCC_PLLSAI2_SUPPORT) 00238 00239 case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/ 00240 /* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */ 00241 ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE); 00242 /* SAI1 clock source config set later after clock selection check */ 00243 break; 00244 00245 #endif /* RCC_PLLSAI2_SUPPORT */ 00246 00247 case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/ 00248 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00249 case RCC_SAI1CLKSOURCE_HSI: /* HSI is used as source of SAI1 clock*/ 00250 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00251 /* SAI1 clock source config set later after clock selection check */ 00252 break; 00253 00254 default: 00255 ret = HAL_ERROR; 00256 break; 00257 } 00258 00259 if(ret == HAL_OK) 00260 { 00261 /* Set the source of SAI1 clock*/ 00262 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 00263 } 00264 else 00265 { 00266 /* set overall return value */ 00267 status = ret; 00268 } 00269 } 00270 00271 #if defined(SAI2) 00272 00273 /*-------------------------- SAI2 clock source configuration ---------------------*/ 00274 if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2)) 00275 { 00276 /* Check the parameters */ 00277 assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection)); 00278 00279 switch(PeriphClkInit->Sai2ClockSelection) 00280 { 00281 case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ 00282 /* Enable SAI Clock output generated form System PLL . */ 00283 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); 00284 /* SAI2 clock source config set later after clock selection check */ 00285 break; 00286 00287 case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/ 00288 /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */ 00289 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE); 00290 /* SAI2 clock source config set later after clock selection check */ 00291 break; 00292 00293 case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/ 00294 /* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */ 00295 ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE); 00296 /* SAI2 clock source config set later after clock selection check */ 00297 break; 00298 00299 case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/ 00300 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00301 case RCC_SAI2CLKSOURCE_HSI: /* HSI is used as source of SAI2 clock*/ 00302 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00303 /* SAI2 clock source config set later after clock selection check */ 00304 break; 00305 00306 default: 00307 ret = HAL_ERROR; 00308 break; 00309 } 00310 00311 if(ret == HAL_OK) 00312 { 00313 /* Set the source of SAI2 clock*/ 00314 __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); 00315 } 00316 else 00317 { 00318 /* set overall return value */ 00319 status = ret; 00320 } 00321 } 00322 #endif /* SAI2 */ 00323 00324 /*-------------------------- RTC clock source configuration ----------------------*/ 00325 if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 00326 { 00327 FlagStatus pwrclkchanged = RESET; 00328 00329 /* Check for RTC Parameters used to output RTCCLK */ 00330 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); 00331 00332 /* Enable Power Clock */ 00333 if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 00334 { 00335 __HAL_RCC_PWR_CLK_ENABLE(); 00336 pwrclkchanged = SET; 00337 } 00338 00339 /* Enable write access to Backup domain */ 00340 SET_BIT(PWR->CR1, PWR_CR1_DBP); 00341 00342 /* Wait for Backup domain Write protection disable */ 00343 tickstart = HAL_GetTick(); 00344 00345 while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == RESET) 00346 { 00347 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 00348 { 00349 ret = HAL_TIMEOUT; 00350 break; 00351 } 00352 } 00353 00354 if(ret == HAL_OK) 00355 { 00356 /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ 00357 tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); 00358 00359 if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) 00360 { 00361 /* Store the content of BDCR register before the reset of Backup Domain */ 00362 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); 00363 /* RTC Clock selection can be changed only if the Backup Domain is reset */ 00364 __HAL_RCC_BACKUPRESET_FORCE(); 00365 __HAL_RCC_BACKUPRESET_RELEASE(); 00366 /* Restore the Content of BDCR register */ 00367 RCC->BDCR = tmpregister; 00368 } 00369 00370 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ 00371 if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) 00372 { 00373 /* Get Start Tick*/ 00374 tickstart = HAL_GetTick(); 00375 00376 /* Wait till LSE is ready */ 00377 while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET) 00378 { 00379 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 00380 { 00381 ret = HAL_TIMEOUT; 00382 break; 00383 } 00384 } 00385 } 00386 00387 if(ret == HAL_OK) 00388 { 00389 /* Apply new RTC clock source selection */ 00390 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 00391 } 00392 else 00393 { 00394 /* set overall return value */ 00395 status = ret; 00396 } 00397 } 00398 else 00399 { 00400 /* set overall return value */ 00401 status = ret; 00402 } 00403 00404 /* Restore clock configuration if changed */ 00405 if(pwrclkchanged == SET) 00406 { 00407 __HAL_RCC_PWR_CLK_DISABLE(); 00408 } 00409 } 00410 00411 /*-------------------------- USART1 clock source configuration -------------------*/ 00412 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 00413 { 00414 /* Check the parameters */ 00415 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); 00416 00417 /* Configure the USART1 clock source */ 00418 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 00419 } 00420 00421 /*-------------------------- USART2 clock source configuration -------------------*/ 00422 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) 00423 { 00424 /* Check the parameters */ 00425 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); 00426 00427 /* Configure the USART2 clock source */ 00428 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); 00429 } 00430 00431 #if defined(USART3) 00432 00433 /*-------------------------- USART3 clock source configuration -------------------*/ 00434 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) 00435 { 00436 /* Check the parameters */ 00437 assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); 00438 00439 /* Configure the USART3 clock source */ 00440 __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); 00441 } 00442 00443 #endif /* USART3 */ 00444 00445 #if defined(UART4) 00446 00447 /*-------------------------- UART4 clock source configuration --------------------*/ 00448 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) 00449 { 00450 /* Check the parameters */ 00451 assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); 00452 00453 /* Configure the UART4 clock source */ 00454 __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); 00455 } 00456 00457 #endif /* UART4 */ 00458 00459 #if defined(UART5) 00460 00461 /*-------------------------- UART5 clock source configuration --------------------*/ 00462 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) 00463 { 00464 /* Check the parameters */ 00465 assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); 00466 00467 /* Configure the UART5 clock source */ 00468 __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); 00469 } 00470 00471 #endif /* UART5 */ 00472 00473 /*-------------------------- LPUART1 clock source configuration ------------------*/ 00474 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 00475 { 00476 /* Check the parameters */ 00477 assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); 00478 00479 /* Configure the LPUAR1 clock source */ 00480 __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 00481 } 00482 00483 /*-------------------------- LPTIM1 clock source configuration -------------------*/ 00484 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) 00485 { 00486 assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); 00487 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 00488 } 00489 00490 /*-------------------------- LPTIM2 clock source configuration -------------------*/ 00491 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) 00492 { 00493 assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection)); 00494 __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 00495 } 00496 00497 /*-------------------------- I2C1 clock source configuration ---------------------*/ 00498 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 00499 { 00500 /* Check the parameters */ 00501 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); 00502 00503 /* Configure the I2C1 clock source */ 00504 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 00505 } 00506 00507 #if defined(I2C2) 00508 00509 /*-------------------------- I2C2 clock source configuration ---------------------*/ 00510 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) 00511 { 00512 /* Check the parameters */ 00513 assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); 00514 00515 /* Configure the I2C2 clock source */ 00516 __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); 00517 } 00518 00519 #endif /* I2C2 */ 00520 00521 /*-------------------------- I2C3 clock source configuration ---------------------*/ 00522 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) 00523 { 00524 /* Check the parameters */ 00525 assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); 00526 00527 /* Configure the I2C3 clock source */ 00528 __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); 00529 } 00530 00531 #if defined(I2C4) 00532 00533 /*-------------------------- I2C4 clock source configuration ---------------------*/ 00534 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 00535 { 00536 /* Check the parameters */ 00537 assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); 00538 00539 /* Configure the I2C4 clock source */ 00540 __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 00541 } 00542 00543 #endif /* I2C4 */ 00544 00545 #if defined(USB_OTG_FS) || defined(USB) 00546 00547 /*-------------------------- USB clock source configuration ----------------------*/ 00548 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) 00549 { 00550 assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); 00551 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 00552 00553 if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) 00554 { 00555 /* Enable PLL48M1CLK output */ 00556 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 00557 } 00558 else 00559 { 00560 if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) 00561 { 00562 /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ 00563 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); 00564 00565 if(ret != HAL_OK) 00566 { 00567 /* set overall return value */ 00568 status = ret; 00569 } 00570 } 00571 } 00572 } 00573 00574 #endif /* USB_OTG_FS || USB */ 00575 00576 #if defined(SDMMC1) 00577 00578 /*-------------------------- SDMMC1 clock source configuration -------------------*/ 00579 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1)) 00580 { 00581 assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); 00582 __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); 00583 00584 if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */ 00585 { 00586 /* Enable PLL48M1CLK output */ 00587 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 00588 } 00589 #if defined(RCC_CCIPR2_SDMMCSEL) 00590 else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLP) /* PLL "P" ? */ 00591 { 00592 /* Enable PLLSAI3CLK output */ 00593 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); 00594 } 00595 #endif 00596 else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1) 00597 { 00598 /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ 00599 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); 00600 00601 if(ret != HAL_OK) 00602 { 00603 /* set overall return value */ 00604 status = ret; 00605 } 00606 } 00607 } 00608 00609 #endif /* SDMMC1 */ 00610 00611 /*-------------------------- RNG clock source configuration ----------------------*/ 00612 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) 00613 { 00614 assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); 00615 __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 00616 00617 if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) 00618 { 00619 /* Enable PLL48M1CLK output */ 00620 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 00621 } 00622 else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1) 00623 { 00624 /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ 00625 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); 00626 00627 if(ret != HAL_OK) 00628 { 00629 /* set overall return value */ 00630 status = ret; 00631 } 00632 } 00633 } 00634 00635 /*-------------------------- ADC clock source configuration ----------------------*/ 00636 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 00637 { 00638 /* Check the parameters */ 00639 assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); 00640 00641 /* Configure the ADC interface clock source */ 00642 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 00643 00644 if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) 00645 { 00646 /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */ 00647 ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE); 00648 00649 if(ret != HAL_OK) 00650 { 00651 /* set overall return value */ 00652 status = ret; 00653 } 00654 } 00655 00656 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 00657 00658 else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2) 00659 { 00660 /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */ 00661 ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE); 00662 00663 if(ret != HAL_OK) 00664 { 00665 /* set overall return value */ 00666 status = ret; 00667 } 00668 } 00669 00670 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 00671 00672 } 00673 00674 #if defined(SWPMI1) 00675 00676 /*-------------------------- SWPMI1 clock source configuration -------------------*/ 00677 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 00678 { 00679 /* Check the parameters */ 00680 assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); 00681 00682 /* Configure the SWPMI1 clock source */ 00683 __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 00684 } 00685 00686 #endif /* SWPMI1 */ 00687 00688 #if defined(DFSDM1_Filter0) 00689 00690 /*-------------------------- DFSDM1 clock source configuration -------------------*/ 00691 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 00692 { 00693 /* Check the parameters */ 00694 assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); 00695 00696 /* Configure the DFSDM1 interface clock source */ 00697 __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 00698 } 00699 00700 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00701 /*-------------------------- DFSDM1 audio clock source configuration -------------*/ 00702 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) 00703 { 00704 /* Check the parameters */ 00705 assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); 00706 00707 /* Configure the DFSDM1 interface audio clock source */ 00708 __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); 00709 } 00710 00711 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00712 00713 #endif /* DFSDM1_Filter0 */ 00714 00715 #if defined(LTDC) 00716 00717 /*-------------------------- LTDC clock source configuration --------------------*/ 00718 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) 00719 { 00720 /* Check the parameters */ 00721 assert_param(IS_RCC_LTDCCLKSOURCE(PeriphClkInit->LtdcClockSelection)); 00722 00723 /* Disable the PLLSAI2 */ 00724 __HAL_RCC_PLLSAI2_DISABLE(); 00725 00726 /* Get Start Tick*/ 00727 tickstart = HAL_GetTick(); 00728 00729 /* Wait till PLLSAI2 is ready */ 00730 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) 00731 { 00732 if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) 00733 { 00734 ret = HAL_TIMEOUT; 00735 break; 00736 } 00737 } 00738 00739 if(ret == HAL_OK) 00740 { 00741 /* Configure the LTDC clock source */ 00742 __HAL_RCC_LTDC_CONFIG(PeriphClkInit->LtdcClockSelection); 00743 00744 /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */ 00745 ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE); 00746 } 00747 00748 if(ret != HAL_OK) 00749 { 00750 /* set overall return value */ 00751 status = ret; 00752 } 00753 } 00754 00755 #endif /* LTDC */ 00756 00757 #if defined(DSI) 00758 00759 /*-------------------------- DSI clock source configuration ---------------------*/ 00760 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) 00761 { 00762 /* Check the parameters */ 00763 assert_param(IS_RCC_DSICLKSOURCE(PeriphClkInit->DsiClockSelection)); 00764 00765 /* Configure the DSI clock source */ 00766 __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection); 00767 00768 if(PeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLLSAI2) 00769 { 00770 /* PLLSAI2 input clock, parameters M, N & Q configuration and clock output (PLLSAI2ClockOut) */ 00771 ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_Q_UPDATE); 00772 00773 if(ret != HAL_OK) 00774 { 00775 /* set overall return value */ 00776 status = ret; 00777 } 00778 } 00779 } 00780 00781 #endif /* DSI */ 00782 00783 #if defined(OCTOSPI1) || defined(OCTOSPI2) 00784 00785 /*-------------------------- OctoSPIx clock source configuration ----------------*/ 00786 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) 00787 { 00788 /* Check the parameters */ 00789 assert_param(IS_RCC_OSPICLKSOURCE(PeriphClkInit->OspiClockSelection)); 00790 00791 /* Configure the OctoSPI clock source */ 00792 __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); 00793 00794 if(PeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL) 00795 { 00796 /* Enable PLL48M1CLK output */ 00797 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 00798 } 00799 } 00800 00801 #endif /* OCTOSPI1 || OCTOSPI2 */ 00802 00803 return status; 00804 } 00805 00806 /** 00807 * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. 00808 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that 00809 * returns the configuration information for the Extended Peripherals 00810 * clocks(SAI1, SAI2, LPTIM1, LPTIM2, I2C1, I2C2, I2C3, I2C4, LPUART, 00811 * USART1, USART2, USART3, UART4, UART5, RTC, ADCx, DFSDMx, SWPMI1, USB, SDMMC1 and RNG). 00812 * @retval None 00813 */ 00814 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) 00815 { 00816 /* Set all possible values for the extended clock type parameter------------*/ 00817 00818 #if defined(STM32L431xx) 00819 00820 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 00821 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 00822 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | \ 00823 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \ 00824 RCC_PERIPHCLK_RTC ; 00825 00826 #elif defined(STM32L432xx) || defined(STM32L442xx) 00827 00828 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ 00829 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | \ 00830 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \ 00831 RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \ 00832 RCC_PERIPHCLK_RTC ; 00833 00834 #elif defined(STM32L433xx) || defined(STM32L443xx) 00835 00836 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ 00837 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 00838 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \ 00839 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \ 00840 RCC_PERIPHCLK_RTC ; 00841 00842 #elif defined(STM32L451xx) 00843 00844 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ 00845 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ 00846 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | \ 00847 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ 00848 RCC_PERIPHCLK_RTC ; 00849 00850 #elif defined(STM32L452xx) || defined(STM32L462xx) 00851 00852 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ 00853 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ 00854 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \ 00855 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ 00856 RCC_PERIPHCLK_RTC ; 00857 00858 #elif defined(STM32L471xx) 00859 00860 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 00861 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 00862 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ 00863 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ 00864 RCC_PERIPHCLK_RTC ; 00865 00866 #elif defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 00867 00868 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 00869 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ 00870 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ 00871 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ 00872 RCC_PERIPHCLK_RTC ; 00873 00874 #elif defined(STM32L496xx) || defined(STM32L4A6xx) 00875 00876 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 00877 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ 00878 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ 00879 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ 00880 RCC_PERIPHCLK_RTC ; 00881 00882 #elif defined(STM32L4R5xx) || defined(STM32L4S5xx) 00883 00884 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 00885 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ 00886 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ 00887 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ 00888 RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI; 00889 00890 #elif defined(STM32L4R7xx) || defined(STM32L4S7xx) 00891 00892 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 00893 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ 00894 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ 00895 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ 00896 RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC; 00897 00898 #elif defined(STM32L4R9xx) || defined(STM32L4S9xx) 00899 00900 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ 00901 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ 00902 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ 00903 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ 00904 RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_DSI; 00905 00906 #endif /* STM32L431xx */ 00907 00908 /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/ 00909 00910 PeriphClkInit->PLLSAI1.PLLSAI1Source = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_PLLSRC_Pos; 00911 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 00912 PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U; 00913 #else 00914 PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U; 00915 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 00916 PeriphClkInit->PLLSAI1.PLLSAI1N = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; 00917 PeriphClkInit->PLLSAI1.PLLSAI1P = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos) << 4U) + 7U; 00918 PeriphClkInit->PLLSAI1.PLLSAI1Q = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) * 2U; 00919 PeriphClkInit->PLLSAI1.PLLSAI1R = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) * 2U; 00920 00921 #if defined(RCC_PLLSAI2_SUPPORT) 00922 00923 /* Get the PLLSAI2 Clock configuration -----------------------------------------------*/ 00924 00925 PeriphClkInit->PLLSAI2.PLLSAI2Source = PeriphClkInit->PLLSAI1.PLLSAI1Source; 00926 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 00927 PeriphClkInit->PLLSAI2.PLLSAI2M = (READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U; 00928 #else 00929 PeriphClkInit->PLLSAI2.PLLSAI2M = PeriphClkInit->PLLSAI1.PLLSAI1M; 00930 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 00931 PeriphClkInit->PLLSAI2.PLLSAI2N = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; 00932 PeriphClkInit->PLLSAI2.PLLSAI2P = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) >> RCC_PLLSAI2CFGR_PLLSAI2P_Pos) << 4U) + 7U; 00933 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 00934 PeriphClkInit->PLLSAI2.PLLSAI2Q = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) * 2U; 00935 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 00936 PeriphClkInit->PLLSAI2.PLLSAI2R = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)>> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) * 2U; 00937 00938 #endif /* RCC_PLLSAI2_SUPPORT */ 00939 00940 /* Get the USART1 clock source ---------------------------------------------*/ 00941 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); 00942 /* Get the USART2 clock source ---------------------------------------------*/ 00943 PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); 00944 00945 #if defined(USART3) 00946 /* Get the USART3 clock source ---------------------------------------------*/ 00947 PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); 00948 #endif /* USART3 */ 00949 00950 #if defined(UART4) 00951 /* Get the UART4 clock source ----------------------------------------------*/ 00952 PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); 00953 #endif /* UART4 */ 00954 00955 #if defined(UART5) 00956 /* Get the UART5 clock source ----------------------------------------------*/ 00957 PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); 00958 #endif /* UART5 */ 00959 00960 /* Get the LPUART1 clock source --------------------------------------------*/ 00961 PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); 00962 00963 /* Get the I2C1 clock source -----------------------------------------------*/ 00964 PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); 00965 00966 #if defined(I2C2) 00967 /* Get the I2C2 clock source ----------------------------------------------*/ 00968 PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); 00969 #endif /* I2C2 */ 00970 00971 /* Get the I2C3 clock source -----------------------------------------------*/ 00972 PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); 00973 00974 #if defined(I2C4) 00975 /* Get the I2C4 clock source -----------------------------------------------*/ 00976 PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); 00977 #endif /* I2C4 */ 00978 00979 /* Get the LPTIM1 clock source ---------------------------------------------*/ 00980 PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); 00981 00982 /* Get the LPTIM2 clock source ---------------------------------------------*/ 00983 PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); 00984 00985 /* Get the SAI1 clock source -----------------------------------------------*/ 00986 PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); 00987 00988 #if defined(SAI2) 00989 /* Get the SAI2 clock source -----------------------------------------------*/ 00990 PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); 00991 #endif /* SAI2 */ 00992 00993 /* Get the RTC clock source ------------------------------------------------*/ 00994 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); 00995 00996 #if defined(USB_OTG_FS) || defined(USB) 00997 /* Get the USB clock source ------------------------------------------------*/ 00998 PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); 00999 #endif /* USB_OTG_FS || USB */ 01000 01001 #if defined(SDMMC1) 01002 /* Get the SDMMC1 clock source ---------------------------------------------*/ 01003 PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); 01004 #endif /* SDMMC1 */ 01005 01006 /* Get the RNG clock source ------------------------------------------------*/ 01007 PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); 01008 01009 /* Get the ADC clock source ------------------------------------------------*/ 01010 PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); 01011 01012 #if defined(SWPMI1) 01013 /* Get the SWPMI1 clock source ---------------------------------------------*/ 01014 PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE(); 01015 #endif /* SWPMI1 */ 01016 01017 #if defined(DFSDM1_Filter0) 01018 /* Get the DFSDM1 clock source ---------------------------------------------*/ 01019 PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); 01020 01021 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01022 /* Get the DFSDM1 audio clock source ---------------------------------------*/ 01023 PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); 01024 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01025 #endif /* DFSDM1_Filter0 */ 01026 01027 #if defined(LTDC) 01028 /* Get the LTDC clock source -----------------------------------------------*/ 01029 PeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE(); 01030 #endif /* LTDC */ 01031 01032 #if defined(DSI) 01033 /* Get the DSI clock source ------------------------------------------------*/ 01034 PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE(); 01035 #endif /* DSI */ 01036 01037 #if defined(OCTOSPI1) || defined(OCTOSPI2) 01038 /* Get the OctoSPIclock source --------------------------------------------*/ 01039 PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE(); 01040 #endif /* OCTOSPI1 || OCTOSPI2 */ 01041 } 01042 01043 /** 01044 * @brief Return the peripheral clock frequency for peripherals with clock source from PLLSAIs 01045 * @note Return 0 if peripheral clock identifier not managed by this API 01046 * @param PeriphClk Peripheral clock identifier 01047 * This parameter can be one of the following values: 01048 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock 01049 * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock 01050 @if STM32L462xx 01051 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM) 01052 @endif 01053 @if STM32L486xx 01054 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM) 01055 @endif 01056 @if STM32L4A6xx 01057 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM) 01058 @endif 01059 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock 01060 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock 01061 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock 01062 @if STM32L462xx 01063 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) 01064 @endif 01065 @if STM32L4A6xx 01066 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) 01067 @endif 01068 @if STM32L4S9xx 01069 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) 01070 @endif 01071 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock 01072 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock 01073 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock 01074 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock 01075 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock 01076 @if STM32L486xx 01077 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) 01078 @endif 01079 @if STM32L4A6xx 01080 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) 01081 @endif 01082 @if STM32L4S9xx 01083 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) 01084 @endif 01085 * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock 01086 @if STM32L443xx 01087 * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) 01088 @endif 01089 @if STM32L486xx 01090 * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) 01091 @endif 01092 @if STM32L4A6xx 01093 * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) 01094 @endif 01095 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock 01096 * @arg @ref RCC_PERIPHCLK_USART2 USART1 peripheral clock 01097 * @arg @ref RCC_PERIPHCLK_USART3 USART1 peripheral clock 01098 @if STM32L462xx 01099 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) 01100 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) 01101 @endif 01102 @if STM32L486xx 01103 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) 01104 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5) 01105 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) 01106 @endif 01107 @if STM32L4A6xx 01108 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) 01109 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5) 01110 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) 01111 @endif 01112 @if STM32L4S9xx 01113 * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) 01114 * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) 01115 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) 01116 * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral kernel clock (only for devices with DFSDM1) 01117 * @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO DFSDM1 peripheral audio clock (only for devices with DFSDM1) 01118 * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (only for devices with LTDC) 01119 * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock (only for devices with DSI) 01120 * @arg @ref RCC_PERIPHCLK_OSPI OctoSPI peripheral clock (only for devices with OctoSPI) 01121 @endif 01122 * @retval Frequency in Hz 01123 */ 01124 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) 01125 { 01126 uint32_t frequency = 0U; 01127 uint32_t srcclk = 0U; 01128 uint32_t pllvco = 0U, plln = 0U, pllp = 0U; 01129 01130 /* Check the parameters */ 01131 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); 01132 01133 if(PeriphClk == RCC_PERIPHCLK_RTC) 01134 { 01135 /* Get the current RTC source */ 01136 srcclk = __HAL_RCC_GET_RTC_SOURCE(); 01137 01138 /* Check if LSE is ready and if RTC clock selection is LSE */ 01139 if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) 01140 { 01141 frequency = LSE_VALUE; 01142 } 01143 /* Check if LSI is ready and if RTC clock selection is LSI */ 01144 else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 01145 { 01146 frequency = LSI_VALUE; 01147 } 01148 /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ 01149 else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 01150 { 01151 frequency = HSE_VALUE / 32U; 01152 } 01153 /* Clock not enabled for RTC*/ 01154 else 01155 { 01156 frequency = 0U; 01157 } 01158 } 01159 else 01160 { 01161 /* Other external peripheral clock source than RTC */ 01162 01163 /* Compute PLL clock input */ 01164 if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI) /* MSI ? */ 01165 { 01166 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) 01167 { 01168 /*MSI frequency range in HZ*/ 01169 pllvco = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; 01170 } 01171 else 01172 { 01173 pllvco = 0U; 01174 } 01175 } 01176 else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) /* HSI ? */ 01177 { 01178 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01179 { 01180 pllvco = HSI_VALUE; 01181 } 01182 else 01183 { 01184 pllvco = 0U; 01185 } 01186 } 01187 else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) /* HSE ? */ 01188 { 01189 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 01190 { 01191 pllvco = HSE_VALUE; 01192 } 01193 else 01194 { 01195 pllvco = 0U; 01196 } 01197 } 01198 else /* No source */ 01199 { 01200 pllvco = 0U; 01201 } 01202 01203 switch(PeriphClk) 01204 { 01205 #if defined(SAI2) 01206 01207 case RCC_PERIPHCLK_SAI1: 01208 case RCC_PERIPHCLK_SAI2: 01209 01210 if(PeriphClk == RCC_PERIPHCLK_SAI1) 01211 { 01212 srcclk = __HAL_RCC_GET_SAI1_SOURCE(); 01213 01214 if(srcclk == RCC_SAI1CLKSOURCE_PIN) 01215 { 01216 frequency = EXTERNAL_SAI1_CLOCK_VALUE; 01217 } 01218 /* Else, PLL clock output to check below */ 01219 } 01220 else /* RCC_PERIPHCLK_SAI2 */ 01221 { 01222 srcclk = __HAL_RCC_GET_SAI2_SOURCE(); 01223 01224 if(srcclk == RCC_SAI2CLKSOURCE_PIN) 01225 { 01226 frequency = EXTERNAL_SAI2_CLOCK_VALUE; 01227 } 01228 /* Else, PLL clock output to check below */ 01229 } 01230 01231 #else 01232 01233 case RCC_PERIPHCLK_SAI1: 01234 01235 if(PeriphClk == RCC_PERIPHCLK_SAI1) 01236 { 01237 srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL); 01238 01239 if(srcclk == RCC_SAI1CLKSOURCE_PIN) 01240 { 01241 frequency = EXTERNAL_SAI1_CLOCK_VALUE; 01242 } 01243 /* Else, PLL clock output to check below */ 01244 } 01245 01246 #endif /* SAI2 */ 01247 01248 if(frequency == 0U) 01249 { 01250 #if defined(SAI2) 01251 if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL)) 01252 { 01253 if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != RESET) 01254 { 01255 /* f(PLL Source) / PLLM */ 01256 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01257 /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ 01258 plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; 01259 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 01260 pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; 01261 #endif 01262 if(pllp == 0U) 01263 { 01264 if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) 01265 { 01266 pllp = 17U; 01267 } 01268 else 01269 { 01270 pllp = 7U; 01271 } 01272 } 01273 frequency = (pllvco * plln) / pllp; 01274 } 01275 } 01276 else if(srcclk == 0U) /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */ 01277 { 01278 if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET) 01279 { 01280 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 01281 /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ 01282 /* f(PLLSAI1 Source) / PLLSAI1M */ 01283 pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); 01284 #else 01285 /* f(PLL Source) / PLLM */ 01286 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01287 #endif 01288 /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ 01289 plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; 01290 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 01291 pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; 01292 #endif 01293 if(pllp == 0U) 01294 { 01295 if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET) 01296 { 01297 pllp = 17U; 01298 } 01299 else 01300 { 01301 pllp = 7U; 01302 } 01303 } 01304 frequency = (pllvco * plln) / pllp; 01305 } 01306 } 01307 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01308 else if((srcclk == RCC_SAI1CLKSOURCE_HSI) || (srcclk == RCC_SAI2CLKSOURCE_HSI)) 01309 { 01310 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01311 { 01312 frequency = HSI_VALUE; 01313 } 01314 } 01315 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01316 01317 #else 01318 if(srcclk == RCC_SAI1CLKSOURCE_PLL) 01319 { 01320 if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != RESET) 01321 { 01322 /* f(PLL Source) / PLLM */ 01323 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01324 /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */ 01325 plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; 01326 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 01327 pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; 01328 #endif 01329 if(pllp == 0U) 01330 { 01331 if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) 01332 { 01333 pllp = 17U; 01334 } 01335 else 01336 { 01337 pllp = 7U; 01338 } 01339 } 01340 01341 frequency = (pllvco * plln) / pllp; 01342 } 01343 else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01344 { 01345 /* HSI automatically selected as clock source if PLLs not enabled */ 01346 frequency = HSI_VALUE; 01347 } 01348 else 01349 { 01350 /* No clock source */ 01351 frequency = 0U; 01352 } 01353 } 01354 else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1) 01355 { 01356 if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET) 01357 { 01358 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 01359 /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ 01360 /* f(PLLSAI1 Source) / PLLSAI1M */ 01361 pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); 01362 #else 01363 /* f(PLL Source) / PLLM */ 01364 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01365 #endif 01366 /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ 01367 plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; 01368 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 01369 pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; 01370 #endif 01371 if(pllp == 0U) 01372 { 01373 if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET) 01374 { 01375 pllp = 17U; 01376 } 01377 else 01378 { 01379 pllp = 7U; 01380 } 01381 } 01382 01383 frequency = (pllvco * plln) / pllp; 01384 } 01385 else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 01386 { 01387 /* HSI automatically selected as clock source if PLLs not enabled */ 01388 frequency = HSI_VALUE; 01389 } 01390 else 01391 { 01392 /* No clock source */ 01393 frequency = 0U; 01394 } 01395 } 01396 #endif /* SAI2 */ 01397 01398 #if defined(RCC_PLLSAI2_SUPPORT) 01399 01400 else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2)) 01401 { 01402 if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != RESET) 01403 { 01404 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 01405 /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */ 01406 /* f(PLLSAI2 Source) / PLLSAI2M */ 01407 pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); 01408 #else 01409 /* f(PLL Source) / PLLM */ 01410 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01411 #endif 01412 /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */ 01413 plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; 01414 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 01415 pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos; 01416 #endif 01417 if(pllp == 0U) 01418 { 01419 if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != RESET) 01420 { 01421 pllp = 17U; 01422 } 01423 else 01424 { 01425 pllp = 7U; 01426 } 01427 } 01428 frequency = (pllvco * plln) / pllp; 01429 } 01430 } 01431 01432 #endif /* RCC_PLLSAI2_SUPPORT */ 01433 01434 else 01435 { 01436 /* No clock source */ 01437 frequency = 0U; 01438 } 01439 } 01440 break; 01441 01442 #if defined(USB_OTG_FS) || defined(USB) 01443 01444 case RCC_PERIPHCLK_USB: 01445 01446 #endif /* USB_OTG_FS || USB */ 01447 01448 case RCC_PERIPHCLK_RNG: 01449 01450 #if defined(SDMMC1) && !defined(RCC_CCIPR2_SDMMCSEL) 01451 01452 case RCC_PERIPHCLK_SDMMC1: 01453 01454 #endif /* SDMMC1 && !RCC_CCIPR2_SDMMCSEL */ 01455 01456 srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); 01457 01458 if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */ 01459 { 01460 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) 01461 { 01462 /*MSI frequency range in HZ*/ 01463 frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; 01464 } 01465 else 01466 { 01467 frequency = 0U; 01468 } 01469 } 01470 else if(srcclk == RCC_CCIPR_CLK48SEL_1) /* PLL ? */ 01471 { 01472 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) 01473 { 01474 /* f(PLL Source) / PLLM */ 01475 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01476 /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ 01477 plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; 01478 frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); 01479 } 01480 else 01481 { 01482 frequency = 0U; 01483 } 01484 } 01485 else if(srcclk == RCC_CCIPR_CLK48SEL_0) /* PLLSAI1 ? */ 01486 { 01487 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) 01488 { 01489 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 01490 /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ 01491 /* f(PLLSAI1 Source) / PLLSAI1M */ 01492 pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); 01493 #else 01494 /* f(PLL Source) / PLLM */ 01495 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01496 #endif 01497 /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ 01498 plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; 01499 frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U); 01500 } 01501 else 01502 { 01503 frequency = 0U; 01504 } 01505 } 01506 #if defined(RCC_HSI48_SUPPORT) 01507 else if((srcclk == 0U) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))) /* HSI48 ? */ 01508 { 01509 frequency = HSI48_VALUE; 01510 } 01511 else /* No clock source */ 01512 { 01513 frequency = 0U; 01514 } 01515 #else 01516 else /* No clock source */ 01517 { 01518 frequency = 0U; 01519 } 01520 #endif /* RCC_HSI48_SUPPORT */ 01521 break; 01522 01523 #if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL) 01524 01525 case RCC_PERIPHCLK_SDMMC1: 01526 01527 if(HAL_IS_BIT_SET(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL)) /* PLL "P" ? */ 01528 { 01529 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)) 01530 { 01531 /* f(PLL Source) / PLLM */ 01532 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01533 /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ 01534 plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; 01535 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 01536 pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; 01537 #endif 01538 if(pllp == 0U) 01539 { 01540 if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) 01541 { 01542 pllp = 17U; 01543 } 01544 else 01545 { 01546 pllp = 7U; 01547 } 01548 } 01549 frequency = (pllvco * plln) / pllp; 01550 } 01551 else 01552 { 01553 frequency = 0U; 01554 } 01555 } 01556 else /* 48MHz from PLL "Q" or MSI or PLLSAI1Q or HSI48 */ 01557 { 01558 srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); 01559 01560 if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */ 01561 { 01562 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) 01563 { 01564 /*MSI frequency range in HZ*/ 01565 frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; 01566 } 01567 else 01568 { 01569 frequency = 0U; 01570 } 01571 } 01572 else if(srcclk == RCC_CCIPR_CLK48SEL_1) /* PLL "Q" ? */ 01573 { 01574 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) 01575 { 01576 /* f(PLL Source) / PLLM */ 01577 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01578 /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ 01579 plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; 01580 frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); 01581 } 01582 else 01583 { 01584 frequency = 0U; 01585 } 01586 } 01587 else if(srcclk == RCC_CCIPR_CLK48SEL_0) /* PLLSAI1 ? */ 01588 { 01589 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) 01590 { 01591 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 01592 /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ 01593 /* f(PLLSAI1 Source) / PLLSAI1M */ 01594 pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); 01595 #else 01596 /* f(PLL Source) / PLLM */ 01597 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01598 #endif 01599 /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ 01600 plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; 01601 frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U); 01602 } 01603 else 01604 { 01605 frequency = 0U; 01606 } 01607 } 01608 else if((srcclk == 0U) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))) /* HSI48 ? */ 01609 { 01610 frequency = HSI48_VALUE; 01611 } 01612 else /* No clock source */ 01613 { 01614 frequency = 0U; 01615 } 01616 } 01617 break; 01618 01619 #endif /* SDMMC1 && RCC_CCIPR2_SDMMCSEL */ 01620 01621 case RCC_PERIPHCLK_USART1: 01622 /* Get the current USART1 source */ 01623 srcclk = __HAL_RCC_GET_USART1_SOURCE(); 01624 01625 if(srcclk == RCC_USART1CLKSOURCE_PCLK2) 01626 { 01627 frequency = HAL_RCC_GetPCLK2Freq(); 01628 } 01629 else if(srcclk == RCC_USART1CLKSOURCE_SYSCLK) 01630 { 01631 frequency = HAL_RCC_GetSysClockFreq(); 01632 } 01633 else if((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) 01634 { 01635 frequency = HSI_VALUE; 01636 } 01637 else if((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) 01638 { 01639 frequency = LSE_VALUE; 01640 } 01641 /* Clock not enabled for USART1 */ 01642 else 01643 { 01644 frequency = 0U; 01645 } 01646 break; 01647 01648 case RCC_PERIPHCLK_USART2: 01649 /* Get the current USART2 source */ 01650 srcclk = __HAL_RCC_GET_USART2_SOURCE(); 01651 01652 if(srcclk == RCC_USART2CLKSOURCE_PCLK1) 01653 { 01654 frequency = HAL_RCC_GetPCLK1Freq(); 01655 } 01656 else if(srcclk == RCC_USART2CLKSOURCE_SYSCLK) 01657 { 01658 frequency = HAL_RCC_GetSysClockFreq(); 01659 } 01660 else if((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) 01661 { 01662 frequency = HSI_VALUE; 01663 } 01664 else if((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) 01665 { 01666 frequency = LSE_VALUE; 01667 } 01668 /* Clock not enabled for USART2 */ 01669 else 01670 { 01671 frequency = 0U; 01672 } 01673 break; 01674 01675 #if defined(USART3) 01676 01677 case RCC_PERIPHCLK_USART3: 01678 /* Get the current USART3 source */ 01679 srcclk = __HAL_RCC_GET_USART3_SOURCE(); 01680 01681 if(srcclk == RCC_USART3CLKSOURCE_PCLK1) 01682 { 01683 frequency = HAL_RCC_GetPCLK1Freq(); 01684 } 01685 else if(srcclk == RCC_USART3CLKSOURCE_SYSCLK) 01686 { 01687 frequency = HAL_RCC_GetSysClockFreq(); 01688 } 01689 else if((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) 01690 { 01691 frequency = HSI_VALUE; 01692 } 01693 else if((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) 01694 { 01695 frequency = LSE_VALUE; 01696 } 01697 /* Clock not enabled for USART3 */ 01698 else 01699 { 01700 frequency = 0U; 01701 } 01702 break; 01703 01704 #endif /* USART3 */ 01705 01706 #if defined(UART4) 01707 01708 case RCC_PERIPHCLK_UART4: 01709 /* Get the current UART4 source */ 01710 srcclk = __HAL_RCC_GET_UART4_SOURCE(); 01711 01712 if(srcclk == RCC_UART4CLKSOURCE_PCLK1) 01713 { 01714 frequency = HAL_RCC_GetPCLK1Freq(); 01715 } 01716 else if(srcclk == RCC_UART4CLKSOURCE_SYSCLK) 01717 { 01718 frequency = HAL_RCC_GetSysClockFreq(); 01719 } 01720 else if((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) 01721 { 01722 frequency = HSI_VALUE; 01723 } 01724 else if((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) 01725 { 01726 frequency = LSE_VALUE; 01727 } 01728 /* Clock not enabled for UART4 */ 01729 else 01730 { 01731 frequency = 0U; 01732 } 01733 break; 01734 01735 #endif /* UART4 */ 01736 01737 #if defined(UART5) 01738 01739 case RCC_PERIPHCLK_UART5: 01740 /* Get the current UART5 source */ 01741 srcclk = __HAL_RCC_GET_UART5_SOURCE(); 01742 01743 if(srcclk == RCC_UART5CLKSOURCE_PCLK1) 01744 { 01745 frequency = HAL_RCC_GetPCLK1Freq(); 01746 } 01747 else if(srcclk == RCC_UART5CLKSOURCE_SYSCLK) 01748 { 01749 frequency = HAL_RCC_GetSysClockFreq(); 01750 } 01751 else if((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) 01752 { 01753 frequency = HSI_VALUE; 01754 } 01755 else if((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) 01756 { 01757 frequency = LSE_VALUE; 01758 } 01759 /* Clock not enabled for UART5 */ 01760 else 01761 { 01762 frequency = 0U; 01763 } 01764 break; 01765 01766 #endif /* UART5 */ 01767 01768 case RCC_PERIPHCLK_LPUART1: 01769 /* Get the current LPUART1 source */ 01770 srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); 01771 01772 if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1) 01773 { 01774 frequency = HAL_RCC_GetPCLK1Freq(); 01775 } 01776 else if(srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) 01777 { 01778 frequency = HAL_RCC_GetSysClockFreq(); 01779 } 01780 else if((srcclk == RCC_LPUART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) 01781 { 01782 frequency = HSI_VALUE; 01783 } 01784 else if((srcclk == RCC_LPUART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) 01785 { 01786 frequency = LSE_VALUE; 01787 } 01788 /* Clock not enabled for LPUART1 */ 01789 else 01790 { 01791 frequency = 0U; 01792 } 01793 break; 01794 01795 case RCC_PERIPHCLK_ADC: 01796 01797 srcclk = __HAL_RCC_GET_ADC_SOURCE(); 01798 01799 if(srcclk == RCC_ADCCLKSOURCE_SYSCLK) 01800 { 01801 frequency = HAL_RCC_GetSysClockFreq(); 01802 } 01803 else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI1) 01804 { 01805 if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != RESET) 01806 { 01807 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 01808 /* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */ 01809 /* f(PLLSAI1 Source) / PLLSAI1M */ 01810 pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); 01811 #else 01812 /* f(PLL Source) / PLLM */ 01813 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01814 #endif 01815 /* f(PLLADC1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1R */ 01816 plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; 01817 frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U); 01818 } 01819 } 01820 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 01821 else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI2) 01822 { 01823 if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != RESET) 01824 { 01825 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 01826 /* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */ 01827 /* f(PLLSAI2 Source) / PLLSAI2M */ 01828 pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); 01829 #else 01830 /* f(PLL Source) / PLLM */ 01831 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 01832 #endif 01833 /* f(PLLADC2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2R */ 01834 plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; 01835 frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) << 1U); 01836 } 01837 } 01838 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 01839 /* Clock not enabled for ADC */ 01840 else 01841 { 01842 frequency = 0U; 01843 } 01844 break; 01845 01846 #if defined(DFSDM1_Filter0) 01847 01848 case RCC_PERIPHCLK_DFSDM1: 01849 /* Get the current DFSDM1 source */ 01850 srcclk = __HAL_RCC_GET_DFSDM1_SOURCE(); 01851 01852 if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2) 01853 { 01854 frequency = HAL_RCC_GetPCLK2Freq(); 01855 } 01856 else 01857 { 01858 frequency = HAL_RCC_GetSysClockFreq(); 01859 } 01860 break; 01861 01862 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01863 01864 case RCC_PERIPHCLK_DFSDM1AUDIO: 01865 /* Get the current DFSDM1 audio source */ 01866 srcclk = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); 01867 01868 if(srcclk == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) 01869 { 01870 frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); 01871 } 01872 else if((srcclk == RCC_DFSDM1AUDIOCLKSOURCE_MSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))) 01873 { 01874 /*MSI frequency range in HZ*/ 01875 frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; 01876 } 01877 else if((srcclk == RCC_DFSDM1AUDIOCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) 01878 { 01879 frequency = HSI_VALUE; 01880 } 01881 /* Clock not enabled for DFSDM1 audio source */ 01882 else 01883 { 01884 frequency = 0U; 01885 } 01886 break; 01887 01888 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01889 01890 #endif /* DFSDM1_Filter0 */ 01891 01892 case RCC_PERIPHCLK_I2C1: 01893 /* Get the current I2C1 source */ 01894 srcclk = __HAL_RCC_GET_I2C1_SOURCE(); 01895 01896 if(srcclk == RCC_I2C1CLKSOURCE_PCLK1) 01897 { 01898 frequency = HAL_RCC_GetPCLK1Freq(); 01899 } 01900 else if(srcclk == RCC_I2C1CLKSOURCE_SYSCLK) 01901 { 01902 frequency = HAL_RCC_GetSysClockFreq(); 01903 } 01904 else if((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) 01905 { 01906 frequency = HSI_VALUE; 01907 } 01908 /* Clock not enabled for I2C1 */ 01909 else 01910 { 01911 frequency = 0U; 01912 } 01913 break; 01914 01915 #if defined(I2C2) 01916 01917 case RCC_PERIPHCLK_I2C2: 01918 /* Get the current I2C2 source */ 01919 srcclk = __HAL_RCC_GET_I2C2_SOURCE(); 01920 01921 if(srcclk == RCC_I2C2CLKSOURCE_PCLK1) 01922 { 01923 frequency = HAL_RCC_GetPCLK1Freq(); 01924 } 01925 else if(srcclk == RCC_I2C2CLKSOURCE_SYSCLK) 01926 { 01927 frequency = HAL_RCC_GetSysClockFreq(); 01928 } 01929 else if((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) 01930 { 01931 frequency = HSI_VALUE; 01932 } 01933 /* Clock not enabled for I2C2 */ 01934 else 01935 { 01936 frequency = 0U; 01937 } 01938 break; 01939 01940 #endif /* I2C2 */ 01941 01942 case RCC_PERIPHCLK_I2C3: 01943 /* Get the current I2C3 source */ 01944 srcclk = __HAL_RCC_GET_I2C3_SOURCE(); 01945 01946 if(srcclk == RCC_I2C3CLKSOURCE_PCLK1) 01947 { 01948 frequency = HAL_RCC_GetPCLK1Freq(); 01949 } 01950 else if(srcclk == RCC_I2C3CLKSOURCE_SYSCLK) 01951 { 01952 frequency = HAL_RCC_GetSysClockFreq(); 01953 } 01954 else if((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) 01955 { 01956 frequency = HSI_VALUE; 01957 } 01958 /* Clock not enabled for I2C3 */ 01959 else 01960 { 01961 frequency = 0U; 01962 } 01963 break; 01964 01965 #if defined(I2C4) 01966 01967 case RCC_PERIPHCLK_I2C4: 01968 /* Get the current I2C4 source */ 01969 srcclk = __HAL_RCC_GET_I2C4_SOURCE(); 01970 01971 if(srcclk == RCC_I2C4CLKSOURCE_PCLK1) 01972 { 01973 frequency = HAL_RCC_GetPCLK1Freq(); 01974 } 01975 else if(srcclk == RCC_I2C4CLKSOURCE_SYSCLK) 01976 { 01977 frequency = HAL_RCC_GetSysClockFreq(); 01978 } 01979 else if((srcclk == RCC_I2C4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) 01980 { 01981 frequency = HSI_VALUE; 01982 } 01983 /* Clock not enabled for I2C4 */ 01984 else 01985 { 01986 frequency = 0U; 01987 } 01988 break; 01989 01990 #endif /* I2C4 */ 01991 01992 case RCC_PERIPHCLK_LPTIM1: 01993 /* Get the current LPTIM1 source */ 01994 srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); 01995 01996 if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK1) 01997 { 01998 frequency = HAL_RCC_GetPCLK1Freq(); 01999 } 02000 else if((srcclk == RCC_LPTIM1CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 02001 { 02002 frequency = LSI_VALUE; 02003 } 02004 else if((srcclk == RCC_LPTIM1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) 02005 { 02006 frequency = HSI_VALUE; 02007 } 02008 else if ((srcclk == RCC_LPTIM1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) 02009 { 02010 frequency = LSE_VALUE; 02011 } 02012 /* Clock not enabled for LPTIM1 */ 02013 else 02014 { 02015 frequency = 0U; 02016 } 02017 break; 02018 02019 case RCC_PERIPHCLK_LPTIM2: 02020 /* Get the current LPTIM2 source */ 02021 srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); 02022 02023 if(srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) 02024 { 02025 frequency = HAL_RCC_GetPCLK1Freq(); 02026 } 02027 else if((srcclk == RCC_LPTIM2CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 02028 { 02029 frequency = LSI_VALUE; 02030 } 02031 else if((srcclk == RCC_LPTIM2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) 02032 { 02033 frequency = HSI_VALUE; 02034 } 02035 else if ((srcclk == RCC_LPTIM2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) 02036 { 02037 frequency = LSE_VALUE; 02038 } 02039 /* Clock not enabled for LPTIM2 */ 02040 else 02041 { 02042 frequency = 0U; 02043 } 02044 break; 02045 02046 #if defined(SWPMI1) 02047 02048 case RCC_PERIPHCLK_SWPMI1: 02049 /* Get the current SWPMI1 source */ 02050 srcclk = __HAL_RCC_GET_SWPMI1_SOURCE(); 02051 02052 if(srcclk == RCC_SWPMI1CLKSOURCE_PCLK1) 02053 { 02054 frequency = HAL_RCC_GetPCLK1Freq(); 02055 } 02056 else if((srcclk == RCC_SWPMI1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) 02057 { 02058 frequency = HSI_VALUE; 02059 } 02060 /* Clock not enabled for SWPMI1 */ 02061 else 02062 { 02063 frequency = 0U; 02064 } 02065 break; 02066 02067 #endif /* SWPMI1 */ 02068 02069 #if defined(OCTOSPI1) || defined(OCTOSPI2) 02070 02071 case RCC_PERIPHCLK_OSPI: 02072 /* Get the current OctoSPI clock source */ 02073 srcclk = __HAL_RCC_GET_OSPI_SOURCE(); 02074 02075 if(srcclk == RCC_OSPICLKSOURCE_SYSCLK) 02076 { 02077 frequency = HAL_RCC_GetSysClockFreq(); 02078 } 02079 else if((srcclk == RCC_OSPICLKSOURCE_MSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))) 02080 { 02081 /*MSI frequency range in HZ*/ 02082 frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; 02083 } 02084 else if(srcclk == RCC_OSPICLKSOURCE_PLL) 02085 { 02086 if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) 02087 { 02088 /* f(PLL Source) / PLLM */ 02089 pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); 02090 /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ 02091 plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; 02092 frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); 02093 } 02094 else 02095 { 02096 frequency = 0U; 02097 } 02098 } 02099 /* Clock not enabled for OctoSPI */ 02100 else 02101 { 02102 frequency = 0U; 02103 } 02104 break; 02105 02106 #endif /* OCTOSPI1 || OCTOSPI2 */ 02107 02108 default: 02109 break; 02110 } 02111 } 02112 02113 return(frequency); 02114 } 02115 02116 /** 02117 * @} 02118 */ 02119 02120 /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions 02121 * @brief Extended Clock management functions 02122 * 02123 @verbatim 02124 =============================================================================== 02125 ##### Extended clock management functions ##### 02126 =============================================================================== 02127 [..] 02128 This subsection provides a set of functions allowing to control the 02129 activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI2, LSE CSS, 02130 Low speed clock output and clock after wake-up from STOP mode. 02131 @endverbatim 02132 * @{ 02133 */ 02134 02135 /** 02136 * @brief Enable PLLSAI1. 02137 * @param PLLSAI1Init pointer to an RCC_PLLSAI1InitTypeDef structure that 02138 * contains the configuration information for the PLLSAI1 02139 * @retval HAL status 02140 */ 02141 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) 02142 { 02143 uint32_t tickstart = 0U; 02144 HAL_StatusTypeDef status = HAL_OK; 02145 02146 /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */ 02147 assert_param(IS_RCC_PLLSAI1SOURCE(PLLSAI1Init->PLLSAI1Source)); 02148 assert_param(IS_RCC_PLLSAI1M_VALUE(PLLSAI1Init->PLLSAI1M)); 02149 assert_param(IS_RCC_PLLSAI1N_VALUE(PLLSAI1Init->PLLSAI1N)); 02150 assert_param(IS_RCC_PLLSAI1P_VALUE(PLLSAI1Init->PLLSAI1P)); 02151 assert_param(IS_RCC_PLLSAI1Q_VALUE(PLLSAI1Init->PLLSAI1Q)); 02152 assert_param(IS_RCC_PLLSAI1R_VALUE(PLLSAI1Init->PLLSAI1R)); 02153 assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1Init->PLLSAI1ClockOut)); 02154 02155 /* Disable the PLLSAI1 */ 02156 __HAL_RCC_PLLSAI1_DISABLE(); 02157 02158 /* Get Start Tick*/ 02159 tickstart = HAL_GetTick(); 02160 02161 /* Wait till PLLSAI1 is ready to be updated */ 02162 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET) 02163 { 02164 if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 02165 { 02166 status = HAL_TIMEOUT; 02167 break; 02168 } 02169 } 02170 02171 if(status == HAL_OK) 02172 { 02173 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 02174 /* Configure the PLLSAI1 Multiplication factor N */ 02175 /* Configure the PLLSAI1 Division factors M, P, Q and R */ 02176 __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1M, PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R); 02177 #else 02178 /* Configure the PLLSAI1 Multiplication factor N */ 02179 /* Configure the PLLSAI1 Division factors P, Q and R */ 02180 __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R); 02181 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 02182 /* Configure the PLLSAI1 Clock output(s) */ 02183 __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1Init->PLLSAI1ClockOut); 02184 02185 /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ 02186 __HAL_RCC_PLLSAI1_ENABLE(); 02187 02188 /* Get Start Tick*/ 02189 tickstart = HAL_GetTick(); 02190 02191 /* Wait till PLLSAI1 is ready */ 02192 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) 02193 { 02194 if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 02195 { 02196 status = HAL_TIMEOUT; 02197 break; 02198 } 02199 } 02200 } 02201 02202 return status; 02203 } 02204 02205 /** 02206 * @brief Disable PLLSAI1. 02207 * @retval HAL status 02208 */ 02209 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void) 02210 { 02211 uint32_t tickstart = 0U; 02212 HAL_StatusTypeDef status = HAL_OK; 02213 02214 /* Disable the PLLSAI1 */ 02215 __HAL_RCC_PLLSAI1_DISABLE(); 02216 02217 /* Get Start Tick*/ 02218 tickstart = HAL_GetTick(); 02219 02220 /* Wait till PLLSAI1 is ready */ 02221 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET) 02222 { 02223 if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 02224 { 02225 status = HAL_TIMEOUT; 02226 break; 02227 } 02228 } 02229 02230 /* Disable the PLLSAI1 Clock outputs */ 02231 __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1CFGR_PLLSAI1PEN|RCC_PLLSAI1CFGR_PLLSAI1QEN|RCC_PLLSAI1CFGR_PLLSAI1REN); 02232 02233 /* Reset PLL source to save power if no PLLs on */ 02234 if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) 02235 #if defined(RCC_PLLSAI2_SUPPORT) 02236 && 02237 (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) 02238 #endif /* RCC_PLLSAI2_SUPPORT */ 02239 ) 02240 { 02241 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); 02242 } 02243 02244 return status; 02245 } 02246 02247 #if defined(RCC_PLLSAI2_SUPPORT) 02248 02249 /** 02250 * @brief Enable PLLSAI2. 02251 * @param PLLSAI2Init pointer to an RCC_PLLSAI2InitTypeDef structure that 02252 * contains the configuration information for the PLLSAI2 02253 * @retval HAL status 02254 */ 02255 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) 02256 { 02257 uint32_t tickstart = 0U; 02258 HAL_StatusTypeDef status = HAL_OK; 02259 02260 /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */ 02261 assert_param(IS_RCC_PLLSAI2SOURCE(PLLSAI2Init->PLLSAI2Source)); 02262 assert_param(IS_RCC_PLLSAI2M_VALUE(PLLSAI2Init->PLLSAI2M)); 02263 assert_param(IS_RCC_PLLSAI2N_VALUE(PLLSAI2Init->PLLSAI2N)); 02264 assert_param(IS_RCC_PLLSAI2P_VALUE(PLLSAI2Init->PLLSAI2P)); 02265 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 02266 assert_param(IS_RCC_PLLSAI2Q_VALUE(PLLSAI2Init->PLLSAI2Q)); 02267 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 02268 assert_param(IS_RCC_PLLSAI2R_VALUE(PLLSAI2Init->PLLSAI2R)); 02269 assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PLLSAI2Init->PLLSAI2ClockOut)); 02270 02271 /* Disable the PLLSAI2 */ 02272 __HAL_RCC_PLLSAI2_DISABLE(); 02273 02274 /* Get Start Tick*/ 02275 tickstart = HAL_GetTick(); 02276 02277 /* Wait till PLLSAI2 is ready to be updated */ 02278 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) 02279 { 02280 if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) 02281 { 02282 status = HAL_TIMEOUT; 02283 break; 02284 } 02285 } 02286 02287 if(status == HAL_OK) 02288 { 02289 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) 02290 /* Configure the PLLSAI2 Multiplication factor N */ 02291 /* Configure the PLLSAI2 Division factors M, P, Q and R */ 02292 __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R); 02293 #elif defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 02294 /* Configure the PLLSAI2 Multiplication factor N */ 02295 /* Configure the PLLSAI2 Division factors M, P and R */ 02296 __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R); 02297 #elif defined(RCC_PLLSAI2Q_DIV_SUPPORT) 02298 /* Configure the PLLSAI2 Multiplication factor N */ 02299 /* Configure the PLLSAI2 Division factors P, Q and R */ 02300 __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R); 02301 #else 02302 /* Configure the PLLSAI2 Multiplication factor N */ 02303 /* Configure the PLLSAI2 Division factors P and R */ 02304 __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R); 02305 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ 02306 /* Configure the PLLSAI2 Clock output(s) */ 02307 __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PLLSAI2Init->PLLSAI2ClockOut); 02308 02309 /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/ 02310 __HAL_RCC_PLLSAI2_ENABLE(); 02311 02312 /* Get Start Tick*/ 02313 tickstart = HAL_GetTick(); 02314 02315 /* Wait till PLLSAI2 is ready */ 02316 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) 02317 { 02318 if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) 02319 { 02320 status = HAL_TIMEOUT; 02321 break; 02322 } 02323 } 02324 } 02325 02326 return status; 02327 } 02328 02329 /** 02330 * @brief Disable PLLISAI2. 02331 * @retval HAL status 02332 */ 02333 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) 02334 { 02335 uint32_t tickstart = 0U; 02336 HAL_StatusTypeDef status = HAL_OK; 02337 02338 /* Disable the PLLSAI2 */ 02339 __HAL_RCC_PLLSAI2_DISABLE(); 02340 02341 /* Get Start Tick*/ 02342 tickstart = HAL_GetTick(); 02343 02344 /* Wait till PLLSAI2 is ready */ 02345 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) 02346 { 02347 if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) 02348 { 02349 status = HAL_TIMEOUT; 02350 break; 02351 } 02352 } 02353 02354 /* Disable the PLLSAI2 Clock outputs */ 02355 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 02356 __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2QEN|RCC_PLLSAI2CFGR_PLLSAI2REN); 02357 #else 02358 __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2REN); 02359 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ 02360 02361 /* Reset PLL source to save power if no PLLs on */ 02362 if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) 02363 && 02364 (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) 02365 ) 02366 { 02367 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); 02368 } 02369 02370 return status; 02371 } 02372 02373 #endif /* RCC_PLLSAI2_SUPPORT */ 02374 02375 /** 02376 * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock. 02377 * @param WakeUpClk Wakeup clock 02378 * This parameter can be one of the following values: 02379 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection 02380 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection 02381 * @note This function shall not be called after the Clock Security System on HSE has been 02382 * enabled. 02383 * @retval None 02384 */ 02385 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) 02386 { 02387 assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); 02388 02389 __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); 02390 } 02391 02392 /** 02393 * @brief Configure the MSI range after standby mode. 02394 * @note After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). 02395 * @param MSIRange MSI range 02396 * This parameter can be one of the following values: 02397 * @arg @ref RCC_MSIRANGE_4 Range 4 around 1 MHz 02398 * @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz 02399 * @arg @ref RCC_MSIRANGE_6 Range 6 around 4 MHz (reset value) 02400 * @arg @ref RCC_MSIRANGE_7 Range 7 around 8 MHz 02401 * @retval None 02402 */ 02403 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange) 02404 { 02405 assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange)); 02406 02407 __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange); 02408 } 02409 02410 /** 02411 * @brief Enable the LSE Clock Security System. 02412 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled 02413 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC 02414 * clock with HAL_RCCEx_PeriphCLKConfig(). 02415 * @retval None 02416 */ 02417 void HAL_RCCEx_EnableLSECSS(void) 02418 { 02419 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; 02420 } 02421 02422 /** 02423 * @brief Disable the LSE Clock Security System. 02424 * @note LSE Clock Security System can only be disabled after a LSE failure detection. 02425 * @retval None 02426 */ 02427 void HAL_RCCEx_DisableLSECSS(void) 02428 { 02429 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; 02430 02431 /* Disable LSE CSS IT if any */ 02432 __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); 02433 } 02434 02435 /** 02436 * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. 02437 * @note LSE Clock Security System Interrupt is mapped on RTC EXTI line 19 02438 * @retval None 02439 */ 02440 void HAL_RCCEx_EnableLSECSS_IT(void) 02441 { 02442 /* Enable LSE CSS */ 02443 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; 02444 02445 /* Enable LSE CSS IT */ 02446 __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); 02447 02448 /* Enable IT on EXTI Line 19 */ 02449 __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); 02450 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); 02451 } 02452 02453 /** 02454 * @brief Handle the RCC LSE Clock Security System interrupt request. 02455 * @retval None 02456 */ 02457 void HAL_RCCEx_LSECSS_IRQHandler(void) 02458 { 02459 /* Check RCC LSE CSSF flag */ 02460 if(__HAL_RCC_GET_IT(RCC_IT_LSECSS)) 02461 { 02462 /* RCC LSE Clock Security System interrupt user callback */ 02463 HAL_RCCEx_LSECSS_Callback(); 02464 02465 /* Clear RCC LSE CSS pending bit */ 02466 __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); 02467 } 02468 } 02469 02470 /** 02471 * @brief RCCEx LSE Clock Security System interrupt callback. 02472 * @retval none 02473 */ 02474 __weak void HAL_RCCEx_LSECSS_Callback(void) 02475 { 02476 /* NOTE : This function should not be modified, when the callback is needed, 02477 the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file 02478 */ 02479 } 02480 02481 /** 02482 * @brief Select the Low Speed clock source to output on LSCO pin (PA2). 02483 * @param LSCOSource specifies the Low Speed clock source to output. 02484 * This parameter can be one of the following values: 02485 * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source 02486 * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source 02487 * @retval None 02488 */ 02489 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) 02490 { 02491 GPIO_InitTypeDef GPIO_InitStruct; 02492 FlagStatus pwrclkchanged = RESET; 02493 FlagStatus backupchanged = RESET; 02494 02495 /* Check the parameters */ 02496 assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); 02497 02498 /* LSCO Pin Clock Enable */ 02499 __LSCO_CLK_ENABLE(); 02500 02501 /* Configue the LSCO pin in analog mode */ 02502 GPIO_InitStruct.Pin = LSCO_PIN; 02503 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 02504 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 02505 GPIO_InitStruct.Pull = GPIO_NOPULL; 02506 HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct); 02507 02508 /* Update LSCOSEL clock source in Backup Domain control register */ 02509 if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 02510 { 02511 __HAL_RCC_PWR_CLK_ENABLE(); 02512 pwrclkchanged = SET; 02513 } 02514 if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 02515 { 02516 HAL_PWR_EnableBkUpAccess(); 02517 backupchanged = SET; 02518 } 02519 02520 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN); 02521 02522 if(backupchanged == SET) 02523 { 02524 HAL_PWR_DisableBkUpAccess(); 02525 } 02526 if(pwrclkchanged == SET) 02527 { 02528 __HAL_RCC_PWR_CLK_DISABLE(); 02529 } 02530 } 02531 02532 /** 02533 * @brief Disable the Low Speed clock output. 02534 * @retval None 02535 */ 02536 void HAL_RCCEx_DisableLSCO(void) 02537 { 02538 FlagStatus pwrclkchanged = RESET; 02539 FlagStatus backupchanged = RESET; 02540 02541 /* Update LSCOEN bit in Backup Domain control register */ 02542 if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 02543 { 02544 __HAL_RCC_PWR_CLK_ENABLE(); 02545 pwrclkchanged = SET; 02546 } 02547 if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 02548 { 02549 /* Enable access to the backup domain */ 02550 HAL_PWR_EnableBkUpAccess(); 02551 backupchanged = SET; 02552 } 02553 02554 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); 02555 02556 /* Restore previous configuration */ 02557 if(backupchanged == SET) 02558 { 02559 /* Disable access to the backup domain */ 02560 HAL_PWR_DisableBkUpAccess(); 02561 } 02562 if(pwrclkchanged == SET) 02563 { 02564 __HAL_RCC_PWR_CLK_DISABLE(); 02565 } 02566 } 02567 02568 /** 02569 * @brief Enable the PLL-mode of the MSI. 02570 * @note Prior to enable the PLL-mode of the MSI for automatic hardware 02571 * calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig(). 02572 * @retval None 02573 */ 02574 void HAL_RCCEx_EnableMSIPLLMode(void) 02575 { 02576 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ; 02577 } 02578 02579 /** 02580 * @brief Disable the PLL-mode of the MSI. 02581 * @note PLL-mode of the MSI is automatically reset when LSE oscillator is disabled. 02582 * @retval None 02583 */ 02584 void HAL_RCCEx_DisableMSIPLLMode(void) 02585 { 02586 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN) ; 02587 } 02588 02589 /** 02590 * @} 02591 */ 02592 02593 #if defined(CRS) 02594 02595 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions 02596 * @brief Extended Clock Recovery System Control functions 02597 * 02598 @verbatim 02599 =============================================================================== 02600 ##### Extended Clock Recovery System Control functions ##### 02601 =============================================================================== 02602 [..] 02603 For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows: 02604 02605 (#) In System clock config, HSI48 needs to be enabled 02606 02607 (#) Enable CRS clock in IP MSP init which will use CRS functions 02608 02609 (#) Call CRS functions as follows: 02610 (##) Prepare synchronization configuration necessary for HSI48 calibration 02611 (+++) Default values can be set for frequency Error Measurement (reload and error limit) 02612 and also HSI48 oscillator smooth trimming. 02613 (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate 02614 directly reload value with target and sychronization frequencies values 02615 (##) Call function HAL_RCCEx_CRSConfig which 02616 (+++) Resets CRS registers to their default values. 02617 (+++) Configures CRS registers with synchronization configuration 02618 (+++) Enables automatic calibration and frequency error counter feature 02619 Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the 02620 periodic USB SOF will not be generated by the host. No SYNC signal will therefore be 02621 provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock 02622 precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs 02623 should be used as SYNC signal. 02624 02625 (##) A polling function is provided to wait for complete synchronization 02626 (+++) Call function HAL_RCCEx_CRSWaitSynchronization() 02627 (+++) According to CRS status, user can decide to adjust again the calibration or continue 02628 application if synchronization is OK 02629 02630 (#) User can retrieve information related to synchronization in calling function 02631 HAL_RCCEx_CRSGetSynchronizationInfo() 02632 02633 (#) Regarding synchronization status and synchronization information, user can try a new calibration 02634 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. 02635 Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), 02636 it means that the actual frequency is lower than the target (and so, that the TRIM value should be 02637 incremented), while when it is detected during the upcounting phase it means that the actual frequency 02638 is higher (and that the TRIM value should be decremented). 02639 02640 (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go 02641 through CRS Handler (CRS_IRQn/CRS_IRQHandler) 02642 (++) Call function HAL_RCCEx_CRSConfig() 02643 (++) Enable CRS_IRQn (thanks to NVIC functions) 02644 (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) 02645 (++) Implement CRS status management in the following user callbacks called from 02646 HAL_RCCEx_CRS_IRQHandler(): 02647 (+++) HAL_RCCEx_CRS_SyncOkCallback() 02648 (+++) HAL_RCCEx_CRS_SyncWarnCallback() 02649 (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() 02650 (+++) HAL_RCCEx_CRS_ErrorCallback() 02651 02652 (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). 02653 This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) 02654 02655 @endverbatim 02656 * @{ 02657 */ 02658 02659 /** 02660 * @brief Start automatic synchronization for polling mode 02661 * @param pInit Pointer on RCC_CRSInitTypeDef structure 02662 * @retval None 02663 */ 02664 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) 02665 { 02666 uint32_t value = 0; 02667 02668 /* Check the parameters */ 02669 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); 02670 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); 02671 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); 02672 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); 02673 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); 02674 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); 02675 02676 /* CONFIGURATION */ 02677 02678 /* Before configuration, reset CRS registers to their default values*/ 02679 __HAL_RCC_CRS_FORCE_RESET(); 02680 __HAL_RCC_CRS_RELEASE_RESET(); 02681 02682 /* Set the SYNCDIV[2:0] bits according to Prescaler value */ 02683 /* Set the SYNCSRC[1:0] bits according to Source value */ 02684 /* Set the SYNCSPOL bit according to Polarity value */ 02685 value = (pInit->Prescaler | pInit->Source | pInit->Polarity); 02686 /* Set the RELOAD[15:0] bits according to ReloadValue value */ 02687 value |= pInit->ReloadValue; 02688 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ 02689 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); 02690 WRITE_REG(CRS->CFGR, value); 02691 02692 /* Adjust HSI48 oscillator smooth trimming */ 02693 /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ 02694 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); 02695 02696 /* START AUTOMATIC SYNCHRONIZATION*/ 02697 02698 /* Enable Automatic trimming & Frequency error counter */ 02699 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); 02700 } 02701 02702 /** 02703 * @brief Generate the software synchronization event 02704 * @retval None 02705 */ 02706 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) 02707 { 02708 SET_BIT(CRS->CR, CRS_CR_SWSYNC); 02709 } 02710 02711 /** 02712 * @brief Return synchronization info 02713 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure 02714 * @retval None 02715 */ 02716 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) 02717 { 02718 /* Check the parameter */ 02719 assert_param(pSynchroInfo != NULL); 02720 02721 /* Get the reload value */ 02722 pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); 02723 02724 /* Get HSI48 oscillator smooth trimming */ 02725 pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); 02726 02727 /* Get Frequency error capture */ 02728 pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); 02729 02730 /* Get Frequency error direction */ 02731 pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); 02732 } 02733 02734 /** 02735 * @brief Wait for CRS Synchronization status. 02736 * @param Timeout Duration of the timeout 02737 * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization 02738 * frequency. 02739 * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. 02740 * @retval Combination of Synchronization status 02741 * This parameter can be a combination of the following values: 02742 * @arg @ref RCC_CRS_TIMEOUT 02743 * @arg @ref RCC_CRS_SYNCOK 02744 * @arg @ref RCC_CRS_SYNCWARN 02745 * @arg @ref RCC_CRS_SYNCERR 02746 * @arg @ref RCC_CRS_SYNCMISS 02747 * @arg @ref RCC_CRS_TRIMOVF 02748 */ 02749 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) 02750 { 02751 uint32_t crsstatus = RCC_CRS_NONE; 02752 uint32_t tickstart = 0U; 02753 02754 /* Get timeout */ 02755 tickstart = HAL_GetTick(); 02756 02757 /* Wait for CRS flag or timeout detection */ 02758 do 02759 { 02760 if(Timeout != HAL_MAX_DELAY) 02761 { 02762 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) 02763 { 02764 crsstatus = RCC_CRS_TIMEOUT; 02765 } 02766 } 02767 /* Check CRS SYNCOK flag */ 02768 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) 02769 { 02770 /* CRS SYNC event OK */ 02771 crsstatus |= RCC_CRS_SYNCOK; 02772 02773 /* Clear CRS SYNC event OK bit */ 02774 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); 02775 } 02776 02777 /* Check CRS SYNCWARN flag */ 02778 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) 02779 { 02780 /* CRS SYNC warning */ 02781 crsstatus |= RCC_CRS_SYNCWARN; 02782 02783 /* Clear CRS SYNCWARN bit */ 02784 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); 02785 } 02786 02787 /* Check CRS TRIM overflow flag */ 02788 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) 02789 { 02790 /* CRS SYNC Error */ 02791 crsstatus |= RCC_CRS_TRIMOVF; 02792 02793 /* Clear CRS Error bit */ 02794 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); 02795 } 02796 02797 /* Check CRS Error flag */ 02798 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) 02799 { 02800 /* CRS SYNC Error */ 02801 crsstatus |= RCC_CRS_SYNCERR; 02802 02803 /* Clear CRS Error bit */ 02804 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); 02805 } 02806 02807 /* Check CRS SYNC Missed flag */ 02808 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) 02809 { 02810 /* CRS SYNC Missed */ 02811 crsstatus |= RCC_CRS_SYNCMISS; 02812 02813 /* Clear CRS SYNC Missed bit */ 02814 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); 02815 } 02816 02817 /* Check CRS Expected SYNC flag */ 02818 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) 02819 { 02820 /* frequency error counter reached a zero value */ 02821 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); 02822 } 02823 } while(RCC_CRS_NONE == crsstatus); 02824 02825 return crsstatus; 02826 } 02827 02828 /** 02829 * @brief Handle the Clock Recovery System interrupt request. 02830 * @retval None 02831 */ 02832 void HAL_RCCEx_CRS_IRQHandler(void) 02833 { 02834 uint32_t crserror = RCC_CRS_NONE; 02835 /* Get current IT flags and IT sources values */ 02836 uint32_t itflags = READ_REG(CRS->ISR); 02837 uint32_t itsources = READ_REG(CRS->CR); 02838 02839 /* Check CRS SYNCOK flag */ 02840 if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET)) 02841 { 02842 /* Clear CRS SYNC event OK flag */ 02843 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); 02844 02845 /* user callback */ 02846 HAL_RCCEx_CRS_SyncOkCallback(); 02847 } 02848 /* Check CRS SYNCWARN flag */ 02849 else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET)) 02850 { 02851 /* Clear CRS SYNCWARN flag */ 02852 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); 02853 02854 /* user callback */ 02855 HAL_RCCEx_CRS_SyncWarnCallback(); 02856 } 02857 /* Check CRS Expected SYNC flag */ 02858 else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET)) 02859 { 02860 /* frequency error counter reached a zero value */ 02861 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); 02862 02863 /* user callback */ 02864 HAL_RCCEx_CRS_ExpectedSyncCallback(); 02865 } 02866 /* Check CRS Error flags */ 02867 else 02868 { 02869 if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET)) 02870 { 02871 if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET) 02872 { 02873 crserror |= RCC_CRS_SYNCERR; 02874 } 02875 if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET) 02876 { 02877 crserror |= RCC_CRS_SYNCMISS; 02878 } 02879 if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET) 02880 { 02881 crserror |= RCC_CRS_TRIMOVF; 02882 } 02883 02884 /* Clear CRS Error flags */ 02885 WRITE_REG(CRS->ICR, CRS_ICR_ERRC); 02886 02887 /* user error callback */ 02888 HAL_RCCEx_CRS_ErrorCallback(crserror); 02889 } 02890 } 02891 } 02892 02893 /** 02894 * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. 02895 * @retval none 02896 */ 02897 __weak void HAL_RCCEx_CRS_SyncOkCallback(void) 02898 { 02899 /* NOTE : This function should not be modified, when the callback is needed, 02900 the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file 02901 */ 02902 } 02903 02904 /** 02905 * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. 02906 * @retval none 02907 */ 02908 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void) 02909 { 02910 /* NOTE : This function should not be modified, when the callback is needed, 02911 the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file 02912 */ 02913 } 02914 02915 /** 02916 * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. 02917 * @retval none 02918 */ 02919 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) 02920 { 02921 /* NOTE : This function should not be modified, when the callback is needed, 02922 the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file 02923 */ 02924 } 02925 02926 /** 02927 * @brief RCCEx Clock Recovery System Error interrupt callback. 02928 * @param Error Combination of Error status. 02929 * This parameter can be a combination of the following values: 02930 * @arg @ref RCC_CRS_SYNCERR 02931 * @arg @ref RCC_CRS_SYNCMISS 02932 * @arg @ref RCC_CRS_TRIMOVF 02933 * @retval none 02934 */ 02935 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) 02936 { 02937 /* Prevent unused argument(s) compilation warning */ 02938 UNUSED(Error); 02939 02940 /* NOTE : This function should not be modified, when the callback is needed, 02941 the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file 02942 */ 02943 } 02944 02945 /** 02946 * @} 02947 */ 02948 02949 #endif /* CRS */ 02950 02951 /** 02952 * @} 02953 */ 02954 02955 /** @addtogroup RCCEx_Private_Functions 02956 * @{ 02957 */ 02958 02959 /** 02960 * @brief Configure the parameters N & P & optionally M of PLLSAI1 and enable PLLSAI1 output clock(s). 02961 * @param PllSai1 pointer to an RCC_PLLSAI1InitTypeDef structure that 02962 * contains the configuration parameters N & P & optionally M as well as PLLSAI1 output clock(s) 02963 * @param Divider divider parameter to be updated 02964 * 02965 * @note PLLSAI1 is temporary disable to apply new parameters 02966 * 02967 * @retval HAL status 02968 */ 02969 static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider) 02970 { 02971 uint32_t tickstart = 0U; 02972 HAL_StatusTypeDef status = HAL_OK; 02973 02974 /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */ 02975 /* P, Q and R dividers are verified in each specific divider case below */ 02976 assert_param(IS_RCC_PLLSAI1SOURCE(PllSai1->PLLSAI1Source)); 02977 assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M)); 02978 assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N)); 02979 assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut)); 02980 02981 /* Check that PLLSAI1 clock source and divider M can be applied */ 02982 if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) 02983 { 02984 /* PLL clock source and divider M already set, check that no request for change */ 02985 if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source) 02986 || 02987 (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE) 02988 #if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 02989 || 02990 (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M) 02991 #endif 02992 ) 02993 { 02994 status = HAL_ERROR; 02995 } 02996 } 02997 else 02998 { 02999 /* Check PLLSAI1 clock source availability */ 03000 switch(PllSai1->PLLSAI1Source) 03001 { 03002 case RCC_PLLSOURCE_MSI: 03003 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY)) 03004 { 03005 status = HAL_ERROR; 03006 } 03007 break; 03008 case RCC_PLLSOURCE_HSI: 03009 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY)) 03010 { 03011 status = HAL_ERROR; 03012 } 03013 break; 03014 case RCC_PLLSOURCE_HSE: 03015 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY) && HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) 03016 { 03017 status = HAL_ERROR; 03018 } 03019 break; 03020 default: 03021 status = HAL_ERROR; 03022 break; 03023 } 03024 03025 if(status == HAL_OK) 03026 { 03027 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 03028 /* Set PLLSAI1 clock source */ 03029 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source); 03030 #else 03031 /* Set PLLSAI1 clock source and divider M */ 03032 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos); 03033 #endif 03034 } 03035 } 03036 03037 if(status == HAL_OK) 03038 { 03039 /* Disable the PLLSAI1 */ 03040 __HAL_RCC_PLLSAI1_DISABLE(); 03041 03042 /* Get Start Tick*/ 03043 tickstart = HAL_GetTick(); 03044 03045 /* Wait till PLLSAI1 is ready to be updated */ 03046 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET) 03047 { 03048 if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 03049 { 03050 status = HAL_TIMEOUT; 03051 break; 03052 } 03053 } 03054 03055 if(status == HAL_OK) 03056 { 03057 if(Divider == DIVIDER_P_UPDATE) 03058 { 03059 assert_param(IS_RCC_PLLSAI1P_VALUE(PllSai1->PLLSAI1P)); 03060 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 03061 03062 /* Configure the PLLSAI1 Division factor M, P and Multiplication factor N*/ 03063 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 03064 MODIFY_REG(RCC->PLLSAI1CFGR, 03065 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV | RCC_PLLSAI1CFGR_PLLSAI1M, 03066 (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | 03067 (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) | 03068 ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); 03069 #else 03070 MODIFY_REG(RCC->PLLSAI1CFGR, 03071 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1M, 03072 (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | 03073 ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | 03074 ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); 03075 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 03076 03077 #else 03078 /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/ 03079 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 03080 MODIFY_REG(RCC->PLLSAI1CFGR, 03081 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, 03082 (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | 03083 (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)); 03084 #else 03085 MODIFY_REG(RCC->PLLSAI1CFGR, 03086 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, 03087 (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | 03088 ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)); 03089 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 03090 03091 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 03092 } 03093 else if(Divider == DIVIDER_Q_UPDATE) 03094 { 03095 assert_param(IS_RCC_PLLSAI1Q_VALUE(PllSai1->PLLSAI1Q)); 03096 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 03097 /* Configure the PLLSAI1 Division factor M, Q and Multiplication factor N*/ 03098 MODIFY_REG(RCC->PLLSAI1CFGR, 03099 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1M, 03100 (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | 03101 (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | 03102 ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); 03103 #else 03104 /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/ 03105 MODIFY_REG(RCC->PLLSAI1CFGR, 03106 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, 03107 (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | 03108 (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)); 03109 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 03110 } 03111 else 03112 { 03113 assert_param(IS_RCC_PLLSAI1R_VALUE(PllSai1->PLLSAI1R)); 03114 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 03115 /* Configure the PLLSAI1 Division factor M, R and Multiplication factor N*/ 03116 MODIFY_REG(RCC->PLLSAI1CFGR, 03117 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1M, 03118 (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | 03119 (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | 03120 ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); 03121 #else 03122 /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/ 03123 MODIFY_REG(RCC->PLLSAI1CFGR, 03124 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, 03125 (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | 03126 (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)); 03127 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 03128 } 03129 03130 /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ 03131 __HAL_RCC_PLLSAI1_ENABLE(); 03132 03133 /* Get Start Tick*/ 03134 tickstart = HAL_GetTick(); 03135 03136 /* Wait till PLLSAI1 is ready */ 03137 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) 03138 { 03139 if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 03140 { 03141 status = HAL_TIMEOUT; 03142 break; 03143 } 03144 } 03145 03146 if(status == HAL_OK) 03147 { 03148 /* Configure the PLLSAI1 Clock output(s) */ 03149 __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut); 03150 } 03151 } 03152 } 03153 03154 return status; 03155 } 03156 03157 #if defined(RCC_PLLSAI2_SUPPORT) 03158 03159 /** 03160 * @brief Configure the parameters N & P & optionally M of PLLSAI2 and enable PLLSAI2 output clock(s). 03161 * @param PllSai2 pointer to an RCC_PLLSAI2InitTypeDef structure that 03162 * contains the configuration parameters N & P & optionally M as well as PLLSAI2 output clock(s) 03163 * @param Divider divider parameter to be updated 03164 * 03165 * @note PLLSAI2 is temporary disable to apply new parameters 03166 * 03167 * @retval HAL status 03168 */ 03169 static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider) 03170 { 03171 uint32_t tickstart = 0U; 03172 HAL_StatusTypeDef status = HAL_OK; 03173 03174 /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */ 03175 /* P, Q and R dividers are verified in each specific divider case below */ 03176 assert_param(IS_RCC_PLLSAI2SOURCE(PllSai2->PLLSAI2Source)); 03177 assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M)); 03178 assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N)); 03179 assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut)); 03180 03181 /* Check that PLLSAI2 clock source and divider M can be applied */ 03182 if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) 03183 { 03184 /* PLL clock source and divider M already set, check that no request for change */ 03185 if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source) 03186 || 03187 (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE) 03188 #if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 03189 || 03190 (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M) 03191 #endif 03192 ) 03193 { 03194 status = HAL_ERROR; 03195 } 03196 } 03197 else 03198 { 03199 /* Check PLLSAI2 clock source availability */ 03200 switch(PllSai2->PLLSAI2Source) 03201 { 03202 case RCC_PLLSOURCE_MSI: 03203 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY)) 03204 { 03205 status = HAL_ERROR; 03206 } 03207 break; 03208 case RCC_PLLSOURCE_HSI: 03209 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY)) 03210 { 03211 status = HAL_ERROR; 03212 } 03213 break; 03214 case RCC_PLLSOURCE_HSE: 03215 if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY) && HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) 03216 { 03217 status = HAL_ERROR; 03218 } 03219 break; 03220 default: 03221 status = HAL_ERROR; 03222 break; 03223 } 03224 03225 if(status == HAL_OK) 03226 { 03227 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 03228 /* Set PLLSAI2 clock source */ 03229 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source); 03230 #else 03231 /* Set PLLSAI2 clock source and divider M */ 03232 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos); 03233 #endif 03234 } 03235 } 03236 03237 if(status == HAL_OK) 03238 { 03239 /* Disable the PLLSAI2 */ 03240 __HAL_RCC_PLLSAI2_DISABLE(); 03241 03242 /* Get Start Tick*/ 03243 tickstart = HAL_GetTick(); 03244 03245 /* Wait till PLLSAI2 is ready to be updated */ 03246 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) 03247 { 03248 if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) 03249 { 03250 status = HAL_TIMEOUT; 03251 break; 03252 } 03253 } 03254 03255 if(status == HAL_OK) 03256 { 03257 if(Divider == DIVIDER_P_UPDATE) 03258 { 03259 assert_param(IS_RCC_PLLSAI2P_VALUE(PllSai2->PLLSAI2P)); 03260 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 03261 03262 /* Configure the PLLSAI2 Division factor M, P and Multiplication factor N*/ 03263 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 03264 MODIFY_REG(RCC->PLLSAI2CFGR, 03265 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV | RCC_PLLSAI2CFGR_PLLSAI2M, 03266 (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | 03267 (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | 03268 ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); 03269 #else 03270 MODIFY_REG(RCC->PLLSAI2CFGR, 03271 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2M, 03272 (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | 03273 ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | 03274 ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); 03275 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ 03276 03277 #else 03278 /* Configure the PLLSAI2 Division factor P and Multiplication factor N*/ 03279 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 03280 MODIFY_REG(RCC->PLLSAI2CFGR, 03281 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, 03282 (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | 03283 (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)); 03284 #else 03285 MODIFY_REG(RCC->PLLSAI2CFGR, 03286 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, 03287 (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | 03288 ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)); 03289 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ 03290 03291 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 03292 } 03293 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 03294 else if(Divider == DIVIDER_Q_UPDATE) 03295 { 03296 assert_param(IS_RCC_PLLSAI2Q_VALUE(PllSai2->PLLSAI2Q)); 03297 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 03298 /* Configure the PLLSAI2 Division factor M, Q and Multiplication factor N*/ 03299 MODIFY_REG(RCC->PLLSAI2CFGR, 03300 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2M, 03301 (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | 03302 (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | 03303 ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); 03304 #else 03305 /* Configure the PLLSAI2 Division factor Q and Multiplication factor N*/ 03306 MODIFY_REG(RCC->PLLSAI2CFGR, 03307 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, 03308 (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | 03309 (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos)); 03310 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 03311 } 03312 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 03313 else 03314 { 03315 assert_param(IS_RCC_PLLSAI2R_VALUE(PllSai2->PLLSAI2R)); 03316 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 03317 /* Configure the PLLSAI2 Division factor M, R and Multiplication factor N*/ 03318 MODIFY_REG(RCC->PLLSAI2CFGR, 03319 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2M, 03320 (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | 03321 (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | 03322 ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); 03323 #else 03324 /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/ 03325 MODIFY_REG(RCC->PLLSAI2CFGR, 03326 RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, 03327 (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | 03328 (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)); 03329 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 03330 } 03331 03332 /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/ 03333 __HAL_RCC_PLLSAI2_ENABLE(); 03334 03335 /* Get Start Tick*/ 03336 tickstart = HAL_GetTick(); 03337 03338 /* Wait till PLLSAI2 is ready */ 03339 while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) 03340 { 03341 if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) 03342 { 03343 status = HAL_TIMEOUT; 03344 break; 03345 } 03346 } 03347 03348 if(status == HAL_OK) 03349 { 03350 /* Configure the PLLSAI2 Clock output(s) */ 03351 __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut); 03352 } 03353 } 03354 } 03355 03356 return status; 03357 } 03358 03359 #endif /* RCC_PLLSAI2_SUPPORT */ 03360 03361 /** 03362 * @} 03363 */ 03364 03365 /** 03366 * @} 03367 */ 03368 03369 #endif /* HAL_RCC_MODULE_ENABLED */ 03370 /** 03371 * @} 03372 */ 03373 03374 /** 03375 * @} 03376 */ 03377 03378 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 03379
1.7.6.1