Modules
	Flags Interrupts Management
	macros to manage the specified RCC Flags and interrupts.
Defines
#define	__HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__)
	Macro to configure the PLLSAI1 clock multiplication and division factors.
#define	__HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
	Macro to configure the PLLSAI1 clock multiplication factor N.
#define	__HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)
	Macro to configure the PLLSAI1 clock division factor P.
#define	__HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
	Macro to configure the PLLSAI1 clock division factor Q.
#define	__HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
	Macro to configure the PLLSAI1 clock division factor R.
#define	__HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
	Macros to enable or disable the PLLSAI1.
#define	__HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
#define	__HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
	Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
#define	__HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
#define	__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
	Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
#define	__HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__)
	Macro to configure the PLLSAI2 clock multiplication and division factors.
#define	__HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
	Macro to configure the PLLSAI2 clock multiplication factor N.
#define	__HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)
	Macro to configure the PLLSAI2 clock division factor P.
#define	__HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
	Macro to configure the PLLSAI2 clock division factor R.
#define	__HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
	Macros to enable or disable the PLLSAI2.
#define	__HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
#define	__HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
	Macros to enable or disable each clock output (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK).
#define	__HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
#define	__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
	Macro to get clock output enable status (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK).
#define	__HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))
	Macro to configure the SAI1 clock source.
#define	__HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))
	Macro to get the SAI1 clock source.
#define	__HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__))
	Macro to configure the SAI2 clock source.
#define	__HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL))
	Macro to get the SAI2 clock source.
#define	__HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))
	Macro to configure the I2C1 clock (I2C1CLK).
#define	__HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))
	Macro to get the I2C1 clock source.
#define	__HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))
	Macro to configure the I2C2 clock (I2C2CLK).
#define	__HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))
	Macro to get the I2C2 clock source.
#define	__HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))
	Macro to configure the I2C3 clock (I2C3CLK).
#define	__HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))
	Macro to get the I2C3 clock source.
#define	__HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))
	Macro to configure the USART1 clock (USART1CLK).
#define	__HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))
	Macro to get the USART1 clock source.
#define	__HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))
	Macro to configure the USART2 clock (USART2CLK).
#define	__HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))
	Macro to get the USART2 clock source.
#define	__HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))
	Macro to configure the USART3 clock (USART3CLK).
#define	__HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))
	Macro to get the USART3 clock source.
#define	__HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))
	Macro to configure the UART4 clock (UART4CLK).
#define	__HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))
	Macro to get the UART4 clock source.
#define	__HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__))
	Macro to configure the UART5 clock (UART5CLK).
#define	__HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))
	Macro to get the UART5 clock source.
#define	__HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))
	Macro to configure the LPUART1 clock (LPUART1CLK).
#define	__HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))
	Macro to get the LPUART1 clock source.
#define	__HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))
	Macro to configure the LPTIM1 clock (LPTIM1CLK).
#define	__HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))
	Macro to get the LPTIM1 clock source.
#define	__HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__))
	Macro to configure the LPTIM2 clock (LPTIM2CLK).
#define	__HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))
	Macro to get the LPTIM2 clock source.
#define	__HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__))
	Macro to configure the SDMMC1 clock.
#define	__HAL_RCC_GET_SDMMC1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
	Macro to get the SDMMC1 clock.
#define	__HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))
	Macro to configure the RNG clock.
#define	__HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
	Macro to get the RNG clock.
#define	__HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))
	Macro to configure the USB clock (USBCLK).
#define	__HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
	Macro to get the USB clock source.
#define	__HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__))
	Macro to configure the ADC interface clock.
#define	__HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))
	Macro to get the ADC clock source.
#define	__HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__))
	Macro to configure the SWPMI1 clock.
#define	__HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL))
	Macro to get the SWPMI1 clock source.
#define	__HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__))
	Macro to configure the DFSDM1 clock.
#define	__HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL))
	Macro to get the DFSDM1 clock source.

Define Documentation

#define __HAL_RCC_ADC_CONFIG ( __ADC_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__))

Macro to configure the ADC interface clock.

Parameters:

__ADC_CLKSOURCE__

specifies the ADC digital interface clock source. This parameter can be one of the following values:

RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock

Return values:

None

Definition at line 1851 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_DFSDM1_CONFIG ( __DFSDM1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__))

Macro to configure the DFSDM1 clock.

Parameters:

__DFSDM1_CLKSOURCE__

specifies the DFSDM1 clock source. This parameter can be one of the following values:

RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock
RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock

Return values:

None

Definition at line 1898 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_ADC_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))

Macro to get the ADC clock source.

Return values:

The

clock source can be one of the following values:

RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock

Definition at line 1863 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_DFSDM1_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL))

Macro to get the DFSDM1 clock source.

Return values:

The	clock source can be one of the following values: RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock

Definition at line 1910 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_I2C1_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))

Macro to get the I2C1 clock source.

Return values:

The	clock source can be one of the following values: RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock

Definition at line 1427 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_I2C2_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))

Macro to get the I2C2 clock source.

Return values:

The	clock source can be one of the following values: RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock

Definition at line 1449 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_I2C3_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))

Macro to get the I2C3 clock source.

Return values:

The	clock source can be one of the following values: RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock

Definition at line 1471 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_LPTIM1_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))

Macro to get the LPTIM1 clock source.

Return values:

The	clock source can be one of the following values: RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock

Definition at line 1662 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_LPTIM2_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))

Macro to get the LPTIM2 clock source.

Return values:

The	clock source can be one of the following values: RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPUART1 clock RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock

Definition at line 1684 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_LPUART1_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))

Macro to get the LPUART1 clock source.

Return values:

The	clock source can be one of the following values: RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock

Definition at line 1640 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG ( __PLLSAI1_CLOCKOUT__ ) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))

Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).

Parameters:

__PLLSAI1_CLOCKOUT__

specifies the PLLSAI1 clock to be output. This parameter can be one of the following values:

RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface in case.
RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.

Return values:

SET / RESET

Definition at line 1076 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG ( __PLLSAI2_CLOCKOUT__ ) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))

Macro to get clock output enable status (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK).

Parameters:

__PLLSAI2_CLOCKOUT__

specifies the PLLSAI2 clock to be output. This parameter can be one of the following values:

RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface in case.
RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.

Return values:

SET / RESET

Definition at line 1317 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_RNG_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))

Macro to get the RNG clock.

Return values:

The

clock source can be one of the following values:

RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock
RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock

Definition at line 1800 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SAI1_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))

Macro to get the SAI1 clock source.

Return values:

The

clock source can be one of the following values:

RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)

Note:: Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 clock source when PLLs are disabled for devices without PLLSAI2.

Definition at line 1366 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SAI2_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL))

Macro to get the SAI2 clock source.

Return values:

The

clock source can be one of the following values:

RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)

Definition at line 1404 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_SDMMC1_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))

Macro to get the SDMMC1 clock.

Return values:

The

clock source can be one of the following values:

RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock

Definition at line 1762 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_GET_SWPMI1_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL))

Macro to get the SWPMI1 clock source.

Return values:

The	clock source can be one of the following values: RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock

Definition at line 1882 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_UART4_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))

Macro to get the UART4 clock source.

Return values:

The	clock source can be one of the following values: RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock

Definition at line 1590 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_UART5_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))

Macro to get the UART5 clock source.

Return values:

The	clock source can be one of the following values: RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock

Definition at line 1616 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USART1_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))

Macro to get the USART1 clock source.

Return values:

The	clock source can be one of the following values: RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock

Definition at line 1518 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USART2_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))

Macro to get the USART2 clock source.

Return values:

The	clock source can be one of the following values: RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock

Definition at line 1540 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USART3_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))

Macro to get the USART3 clock source.

Return values:

The	clock source can be one of the following values: RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock

Definition at line 1564 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USB_SOURCE ( ) (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))

Macro to get the USB clock source.

Return values:

The

clock source can be one of the following values:

RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
RCC_USBCLKSOURCE_MSI MSI selected as USB clock
RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock

Definition at line 1836 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_I2C1_CONFIG ( __I2C1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))

Macro to configure the I2C1 clock (I2C1CLK).

Parameters:

__I2C1_CLKSOURCE__

specifies the I2C1 clock source. This parameter can be one of the following values:

RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock

Return values:

None

Definition at line 1418 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C2_CONFIG ( __I2C2_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))

Macro to configure the I2C2 clock (I2C2CLK).

Parameters:

__I2C2_CLKSOURCE__

specifies the I2C2 clock source. This parameter can be one of the following values:

RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock

Return values:

None

Definition at line 1440 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_I2C3_CONFIG ( __I2C3_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))

Macro to configure the I2C3 clock (I2C3CLK).

Parameters:

__I2C3_CLKSOURCE__

specifies the I2C3 clock source. This parameter can be one of the following values:

RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock

Return values:

None

Definition at line 1462 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPTIM1_CONFIG ( __LPTIM1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))

Macro to configure the LPTIM1 clock (LPTIM1CLK).

Parameters:

__LPTIM1_CLKSOURCE__

specifies the LPTIM1 clock source. This parameter can be one of the following values:

RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock
RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock

Return values:

None

Definition at line 1652 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPTIM2_CONFIG ( __LPTIM2_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__))

Macro to configure the LPTIM2 clock (LPTIM2CLK).

Parameters:

__LPTIM2_CLKSOURCE__

specifies the LPTIM2 clock source. This parameter can be one of the following values:

RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock
RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock
RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock
RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock

Return values:

None

Definition at line 1674 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_LPUART1_CONFIG ( __LPUART1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))

Macro to configure the LPUART1 clock (LPUART1CLK).

Parameters:

__LPUART1_CLKSOURCE__

specifies the LPUART1 clock source. This parameter can be one of the following values:

RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock

Return values:

None

Definition at line 1630 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PLLSAI1_CONFIG	(	__PLLSAI1N__,
		__PLLSAI1P__,
		__PLLSAI1Q__,
		__PLLSAI1R__
	)

Value:

WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
                   (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \
                   ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \
                   ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos))

Macro to configure the PLLSAI1 clock multiplication and division factors.

Note:: This function must be used only when the PLLSAI1 is disabled.; PLLSAI1 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)

Parameters:

__PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. This parameter must be a number between 8 and 86.

Note:: You have to set the PLLSAI1N parameter correctly to ensure that the VCO output frequency is between 64 and 344 MHz. PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N

Parameters:

__PLLSAI1P__	specifies the division factor for SAI clock. This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx else (2 to 31). SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
__PLLSAI1Q__	specifies the division factor for USB/RNG/SDMMC1 clock. This parameter must be in the range (2, 4, 6 or 8). USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
__PLLSAI1R__	specifies the division factor for SAR ADC clock. This parameter must be in the range (2, 4, 6 or 8). ADC clock frequency = f(PLLSAI1) / PLLSAI1R

Return values:

None

Definition at line 935 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1().

#define __HAL_RCC_PLLSAI1_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)

Definition at line 1045 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_DisablePLLSAI1(), HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_Config().

#define __HAL_RCC_PLLSAI1_DIVP_CONFIG ( __PLLSAI1P__ ) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)

Macro to configure the PLLSAI1 clock division factor P.

Note:: This function must be used only when the PLLSAI1 is disabled.; PLLSAI1 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)

Parameters:

__PLLSAI1P__ specifies the division factor for SAI clock. This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx else (2 to 31). Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P

Return values:

None

Definition at line 1002 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1_DIVQ_CONFIG ( __PLLSAI1Q__ ) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)

Macro to configure the PLLSAI1 clock division factor Q.

Note:: This function must be used only when the PLLSAI1 is disabled.; PLLSAI1 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)

Parameters:

__PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. This parameter must be in the range (2, 4, 6 or 8). Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q

Return values:

None

Definition at line 1019 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1_DIVR_CONFIG ( __PLLSAI1R__ ) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)

Macro to configure the PLLSAI1 clock division factor R.

Note:: This function must be used only when the PLLSAI1 is disabled.; PLLSAI1 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)

Parameters:

__PLLSAI1R__ specifies the division factor for ADC clock. This parameter must be in the range (2, 4, 6 or 8) Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R

Return values:

None

Definition at line 1034 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)

Macros to enable or disable the PLLSAI1.

Note:: The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.

Return values:

None

Definition at line 1043 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_Config().

#define __HAL_RCC_PLLSAI1_MULN_CONFIG ( __PLLSAI1N__ ) MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)

Macro to configure the PLLSAI1 clock multiplication factor N.

Note:: This function must be used only when the PLLSAI1 is disabled.; PLLSAI1 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)

Parameters:

__PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. This parameter must be a number between 8 and 86.

Note:: You have to set the PLLSAI1N parameter correctly to ensure that the VCO output frequency is between 64 and 344 MHz. Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N

Return values:

None

Definition at line 960 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI1CLKOUT_DISABLE ( __PLLSAI1_CLOCKOUT__ ) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))

Definition at line 1063 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_DisablePLLSAI1().

#define __HAL_RCC_PLLSAI1CLKOUT_ENABLE ( __PLLSAI1_CLOCKOUT__ ) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))

Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).

Note:: Enabling and disabling those clocks can be done without the need to stop the PLL. This is mainly used to save Power.

Parameters:

__PLLSAI1_CLOCKOUT__

specifies the PLLSAI1 clock to be output. This parameter can be one or a combination of the following values:

RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface in case.
RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.

Return values:

None

Definition at line 1061 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI1(), and RCCEx_PLLSAI1_Config().

#define __HAL_RCC_PLLSAI2_CONFIG	(	__PLLSAI2N__,
		__PLLSAI2P__,
		__PLLSAI2R__
	)

Value:

WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
                    (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \
                    ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos))

Macro to configure the PLLSAI2 clock multiplication and division factors.

Note:: This function must be used only when the PLLSAI2 is disabled.; PLLSAI2 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)

Parameters:

__PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. This parameter must be a number between 8 and 86.

Note:: You have to set the PLLSAI2N parameter correctly to ensure that the VCO output frequency is between 64 and 344 MHz.

Parameters:

__PLLSAI2P__	specifies the division factor for SAI clock. This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx else (2 to 31). SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P
__PLLSAI2R__	specifies the division factor for SAR ADC clock. This parameter must be in the range (2, 4, 6 or 8).

Return values:

None

Definition at line 1162 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI2().

#define __HAL_RCC_PLLSAI2_DISABLE ( ) CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)

Definition at line 1266 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_DisablePLLSAI2(), HAL_RCCEx_EnablePLLSAI2(), HAL_RCCEx_PeriphCLKConfig(), and RCCEx_PLLSAI2_Config().

#define __HAL_RCC_PLLSAI2_DIVP_CONFIG ( __PLLSAI2P__ ) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)

Macro to configure the PLLSAI2 clock division factor P.

Note:: This function must be used only when the PLLSAI2 is disabled.; PLLSAI2 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)

Parameters:

__PLLSAI2P__ specifies the division factor. This parameter must be a number in the range (7 or 17). Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__

Return values:

None

Definition at line 1221 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI2_DIVR_CONFIG ( __PLLSAI2R__ ) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)

Macro to configure the PLLSAI2 clock division factor R.

Note:: This function must be used only when the PLLSAI2 is disabled.; PLLSAI2 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)

Parameters:

__PLLSAI2R__ specifies the division factor. This parameter must be in the range (2, 4, 6 or 8). Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__

Return values:

None

Definition at line 1255 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI2_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)

Macros to enable or disable the PLLSAI2.

Note:: The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes.

Return values:

None

Definition at line 1264 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI2(), and RCCEx_PLLSAI2_Config().

#define __HAL_RCC_PLLSAI2_MULN_CONFIG ( __PLLSAI2N__ ) MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)

Macro to configure the PLLSAI2 clock multiplication factor N.

Note:: This function must be used only when the PLLSAI2 is disabled.; PLLSAI2 clock source is common with the main PLL (configured through __HAL_RCC_PLL_CONFIG() macro)

Parameters:

__PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. This parameter must be a number between 8 and 86.

Note:: You have to set the PLLSAI2N parameter correctly to ensure that the VCO output frequency is between 64 and 344 MHz. PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N

Return values:

None

Definition at line 1187 of file stm32l4xx_hal_rcc_ex.h.

#define __HAL_RCC_PLLSAI2CLKOUT_DISABLE ( __PLLSAI2_CLOCKOUT__ ) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))

Definition at line 1294 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_DisablePLLSAI2().

#define __HAL_RCC_PLLSAI2CLKOUT_ENABLE ( __PLLSAI2_CLOCKOUT__ ) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))

Macros to enable or disable each clock output (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK).

Note:: Enabling and disabling those clocks can be done without the need to stop the PLL. This is mainly used to save Power.

Parameters:

__PLLSAI2_CLOCKOUT__

specifies the PLLSAI2 clock to be output. This parameter can be one or a combination of the following values:

RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface in case.
RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.

Return values:

None

Definition at line 1292 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_EnablePLLSAI2(), and RCCEx_PLLSAI2_Config().

#define __HAL_RCC_RNG_CONFIG ( __RNG_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))

Macro to configure the RNG clock.

Note:: USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.

Parameters:

__RNG_CLKSOURCE__

specifies the RNG clock source. This parameter can be one of the following values:

RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock
RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock

Return values:

None

Definition at line 1785 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI1_CONFIG ( __SAI1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))

Macro to configure the SAI1 clock source.

Parameters:

__SAI1_CLKSOURCE__

defines the SAI1 clock source. This clock is derived from the PLLSAI1, system PLL or external clock (through a dedicated pin). This parameter can be one of the following values:

RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)

Return values:

None

Definition at line 1346 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SAI2_CONFIG ( __SAI2_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__))

Macro to configure the SAI2 clock source.

Parameters:

__SAI2_CLKSOURCE__

defines the SAI2 clock source. This clock is derived from the PLLSAI2, system PLL or external clock (through a dedicated pin). This parameter can be one of the following values:

RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)

Return values:

None

Definition at line 1390 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SDMMC1_CONFIG ( __SDMMC1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__))

Macro to configure the SDMMC1 clock.

Note:: USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.

Parameters:

__SDMMC1_CLKSOURCE__

specifies the SDMMC1 clock source. This parameter can be one of the following values:

RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock
RCC_SDMMC1CLKSOURCE_PLL PLL "Q" Clock selected as SDMMC1 clock

Return values:

None

Definition at line 1734 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_SWPMI1_CONFIG ( __SWPMI1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__))

Macro to configure the SWPMI1 clock.

Parameters:

__SWPMI1_CLKSOURCE__

specifies the SWPMI1 clock source. This parameter can be one of the following values:

RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock
RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock

Return values:

None

Definition at line 1874 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_UART4_CONFIG ( __UART4_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))

Macro to configure the UART4 clock (UART4CLK).

Parameters:

__UART4_CLKSOURCE__

specifies the UART4 clock source. This parameter can be one of the following values:

RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock

Return values:

None

Definition at line 1580 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_UART5_CONFIG ( __UART5_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__))

Macro to configure the UART5 clock (UART5CLK).

Parameters:

__UART5_CLKSOURCE__

specifies the UART5 clock source. This parameter can be one of the following values:

RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock

Return values:

None

Definition at line 1606 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART1_CONFIG ( __USART1_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))

Macro to configure the USART1 clock (USART1CLK).

Parameters:

__USART1_CLKSOURCE__

specifies the USART1 clock source. This parameter can be one of the following values:

RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock

Return values:

None

Definition at line 1508 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART2_CONFIG ( __USART2_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))

Macro to configure the USART2 clock (USART2CLK).

Parameters:

__USART2_CLKSOURCE__

specifies the USART2 clock source. This parameter can be one of the following values:

RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock

Return values:

None

Definition at line 1530 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USART3_CONFIG ( __USART3_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))

Macro to configure the USART3 clock (USART3CLK).

Parameters:

__USART3_CLKSOURCE__

specifies the USART3 clock source. This parameter can be one of the following values:

RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock

Return values:

None

Definition at line 1554 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_USB_CONFIG ( __USB_CLKSOURCE__ ) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))

Macro to configure the USB clock (USBCLK).

Note:: USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.

Parameters:

__USB_CLKSOURCE__

specifies the USB clock source. This parameter can be one of the following values:

RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
RCC_USBCLKSOURCE_MSI MSI selected as USB clock
RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock

Return values:

None

Definition at line 1821 of file stm32l4xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Modules

Defines

Define Documentation