Defines
#define	ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
#define	ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
#define	ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
#define	ADC_SQR1_REGOFFSET (0x00000000U)
#define	ADC_SQR2_REGOFFSET (0x00000100U)
#define	ADC_SQR3_REGOFFSET (0x00000200U)
#define	ADC_SQR4_REGOFFSET (0x00000300U)
#define	ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET \| ADC_SQR2_REGOFFSET \| ADC_SQR3_REGOFFSET \| ADC_SQR4_REGOFFSET)
#define	ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define	ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */
#define	ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */
#define	ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */
#define	ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */
#define	ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */
#define	ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */
#define	ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
#define	ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
#define	ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
#define	ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */
#define	ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */
#define	ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */
#define	ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
#define	ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
#define	ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */
#define	ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */
#define	ADC_JDR1_REGOFFSET (0x00000000U)
#define	ADC_JDR2_REGOFFSET (0x00000100U)
#define	ADC_JDR3_REGOFFSET (0x00000200U)
#define	ADC_JDR4_REGOFFSET (0x00000300U)
#define	ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET \| ADC_JDR2_REGOFFSET \| ADC_JDR3_REGOFFSET \| ADC_JDR4_REGOFFSET)
#define	ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define	ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
#define	ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
#define	ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
#define	ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
#define	ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define	ADC_REG_TRIG_SOURCE_MASK
#define	ADC_REG_TRIG_EDGE_MASK
#define	ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */
#define	ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */
#define	ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define	ADC_INJ_TRIG_SOURCE_MASK
#define	ADC_INJ_TRIG_EDGE_MASK
#define	ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */
#define	ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */
#define	ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
#define	ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
#define	ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
#define	ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK \| ADC_CHANNEL_ID_BITFIELD_MASK \| ADC_CHANNEL_ID_INTERNAL_CH_MASK)
#define	ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
#define	ADC_CHANNEL_ID_INTERNAL_CH (0x80000000U) /* Marker of internal channel */
#define	ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define	ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_ID_INTERNAL_CH_2)
#define	ADC_SMPR1_REGOFFSET (0x00000000U)
#define	ADC_SMPR2_REGOFFSET (0x02000000U)
#define	ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET \| ADC_SMPR2_REGOFFSET)
#define	ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000U)
#define	ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
#define	ADC_CHANNEL_0_NUMBER (0x00000000U)
#define	ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
#define	ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
#define	ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_1 )
#define	ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_1 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
#define	ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_1 )
#define	ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_1 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_2 )
#define	ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_1 )
#define	ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_1 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
#define	ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 \| ADC_CFGR_AWD1CH_1 )
#define	ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
#define	ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
#define	ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
#define	ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
#define	ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
#define	ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
#define	ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
#define	ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
#define	ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
#define	ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
#define	ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
#define	ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
#define	ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
#define	ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
#define	ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
#define	ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
#define	ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
#define	ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
#define	ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
#define	ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET \| (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */
#define	ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET \| (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */
#define	ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET \| (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */
#define	ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET \| (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */
#define	ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET \| ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */
#define	ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET \| ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */
#define	ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET \| ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */
#define	ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET \| ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */
#define	ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET \| ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */
#define	ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET \| ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */
#define	ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET \| (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
#define	ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET \| (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
#define	ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET \| (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
#define	ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET \| (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
#define	ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET \| ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
#define	ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET \| ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
#define	ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET \| ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
#define	ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET \| ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
#define	ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET \| ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
#define	ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
#define	ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D \| ADC_CALFACT_CALFACT_S)
#define	ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
#define	ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
#define	ADC_AWD_CR1_REGOFFSET (0x00000000U)
#define	ADC_AWD_CR2_REGOFFSET (0x00100000U)
#define	ADC_AWD_CR3_REGOFFSET (0x00200000U)
#define	ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define	ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024U)
#define	ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET \| ADC_AWD_CR2_REGOFFSET \| ADC_AWD_CR3_REGOFFSET)
#define	ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define	ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR23_CHANNEL_MASK)
#define	ADC_AWD_CRX_REGOFFSET_POS (20U) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
#define	ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define	ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define	ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
#define	ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET \| ADC_AWD_TR2_REGOFFSET \| ADC_AWD_TR3_REGOFFSET)
#define	ADC_OFR1_REGOFFSET (0x00000000U)
#define	ADC_OFR2_REGOFFSET (0x00000001U)
#define	ADC_OFR3_REGOFFSET (0x00000002U)
#define	ADC_OFR4_REGOFFSET (0x00000003U)
#define	ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET \| ADC_OFR2_REGOFFSET \| ADC_OFR3_REGOFFSET \| ADC_OFR4_REGOFFSET)
#define	ADC_CFGR_RES_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */
#define	ADC_CFGR_AWD1SGL_BITOFFSET_POS (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */
#define	ADC_CFGR_AWD1EN_BITOFFSET_POS (23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */
#define	ADC_CFGR_JAWD1EN_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */
#define	ADC_TR1_HT1_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */
#define	ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL \| ADC_CR_JADSTP \| ADC_CR_ADSTP \| ADC_CR_JADSTART \| ADC_CR_ADSTART \| ADC_CR_ADDIS \| ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
#define	VREFINT_CAL_ADDR ((uint16_t) (0x1FFF75AAU)) / Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define	VREFINT_CAL_VREF ( 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
#define	TEMPSENSOR_CAL1_ADDR ((uint16_t) (0x1FFF75A8U)) / Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define	TEMPSENSOR_CAL2_ADDR ((uint16_t) (0x1FFF75CAU)) / Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature defined by TEMPSENSOR_CAL2_TEMP (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define	TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define	TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define	TEMPSENSOR_CAL_VREFANALOG ( 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */

Define Documentation

#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)

Definition at line 321 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024U)

Definition at line 322 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

Definition at line 326 of file stm32l4xx_ll_adc.h.

#define ADC_AWD_CR1_REGOFFSET (0x00000000U)

Definition at line 315 of file stm32l4xx_ll_adc.h.

#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)

Definition at line 327 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels().

#define ADC_AWD_CR2_REGOFFSET (0x00100000U)

Definition at line 316 of file stm32l4xx_ll_adc.h.

#define ADC_AWD_CR3_REGOFFSET (0x00200000U)

Definition at line 317 of file stm32l4xx_ll_adc.h.

#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)

Definition at line 328 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)

Definition at line 324 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_CRX_REGOFFSET_POS (20U) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */

Definition at line 330 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDMonitChannels(), and LL_ADC_SetAnalogWDMonitChannels().

#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)

Definition at line 333 of file stm32l4xx_ll_adc.h.

#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)

Definition at line 334 of file stm32l4xx_ll_adc.h.

#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)

Definition at line 335 of file stm32l4xx_ll_adc.h.

#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)

Definition at line 336 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds(), LL_ADC_GetAnalogWDThresholds(), and LL_ADC_SetAnalogWDThresholds().

#define ADC_CFGR_AWD1EN_BITOFFSET_POS (23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */

Definition at line 356 of file stm32l4xx_ll_adc.h.

#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */

Definition at line 355 of file stm32l4xx_ll_adc.h.

#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */

Definition at line 357 of file stm32l4xx_ll_adc.h.

#define ADC_CFGR_RES_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */

Definition at line 354 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)

Definition at line 246 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_0_NUMBER (0x00000000U)

Definition at line 224 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */

Definition at line 268 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)

Definition at line 256 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )

Definition at line 234 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */

Definition at line 278 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)

Definition at line 257 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 235 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */

Definition at line 279 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)

Definition at line 258 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )

Definition at line 236 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */

Definition at line 280 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)

Definition at line 259 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)

Definition at line 237 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */

Definition at line 281 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)

Definition at line 260 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )

Definition at line 238 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */

Definition at line 282 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)

Definition at line 261 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 239 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */

Definition at line 283 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)

Definition at line 262 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )

Definition at line 240 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */

Definition at line 284 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)

Definition at line 263 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)

Definition at line 241 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */

Definition at line 285 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)

Definition at line 264 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )

Definition at line 242 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */

Definition at line 286 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)

Definition at line 247 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)

Definition at line 225 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */

Definition at line 269 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)

Definition at line 248 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )

Definition at line 226 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */

Definition at line 270 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)

Definition at line 249 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 227 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */

Definition at line 271 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)

Definition at line 250 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )

Definition at line 228 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */

Definition at line 272 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)

Definition at line 251 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)

Definition at line 229 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */

Definition at line 273 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)

Definition at line 252 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )

Definition at line 230 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */

Definition at line 274 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)

Definition at line 253 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

Definition at line 231 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */

Definition at line 275 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)

Definition at line 254 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )

Definition at line 232 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */

Definition at line 276 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)

Definition at line 255 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)

Definition at line 233 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */

Definition at line 277 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)

Definition at line 199 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000U) /* Marker of internal channel */

Definition at line 206 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */

Definition at line 207 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)

Definition at line 208 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)

Definition at line 201 of file stm32l4xx_ll_adc.h.

#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */

Definition at line 200 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_GetSequencerRanks(), LL_ADC_INJ_SetSequencerRanks(), LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)

Definition at line 198 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_GetSequencerRanks(), LL_ADC_INJ_SetSequencerRanks(), LL_ADC_REG_SetSequencerRanks(), and LL_ADC_SetOffset().

#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */

Definition at line 203 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)

Definition at line 214 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000U)

Definition at line 219 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */

Definition at line 220 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)

Definition at line 83 of file stm32l4xx_ll_adc.c.

#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */

Definition at line 362 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_Disable(), LL_ADC_DisableDeepPowerDown(), LL_ADC_DisableInternalRegulator(), LL_ADC_Enable(), LL_ADC_EnableDeepPowerDown(), LL_ADC_EnableInternalRegulator(), LL_ADC_INJ_StartConversion(), LL_ADC_INJ_StopConversion(), LL_ADC_REG_StartConversion(), LL_ADC_REG_StopConversion(), and LL_ADC_StartCalibration().

#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)

Definition at line 116 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ReadConversionData10(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData32(), LL_ADC_INJ_ReadConversionData6(), and LL_ADC_INJ_ReadConversionData8().

#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */

Definition at line 124 of file stm32l4xx_ll_adc.h.

#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */

Definition at line 125 of file stm32l4xx_ll_adc.h.

#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */

Definition at line 126 of file stm32l4xx_ll_adc.h.

#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */

Definition at line 127 of file stm32l4xx_ll_adc.h.

#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

Definition at line 117 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_ConfigQueueContext(), LL_ADC_INJ_GetSequencerRanks(), and LL_ADC_INJ_SetSequencerRanks().

#define ADC_INJ_TRIG_EDGE_MASK

Value:

(((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0U)) | \
                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1U)) | \
                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2U)) | \
                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3U))  )

Definition at line 176 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_GetTriggerSource().

#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

Definition at line 163 of file stm32l4xx_ll_adc.h.

#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */

Definition at line 183 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_GetTriggerSource().

#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */

Definition at line 182 of file stm32l4xx_ll_adc.h.

#define ADC_INJ_TRIG_SOURCE_MASK

Value:

(((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0U)) | \
                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 1U)) | \
                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 2U)) | \
                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 3U))  )

Definition at line 168 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_INJ_GetTriggerSource().

#define ADC_JDR1_REGOFFSET (0x00000000U)

Definition at line 111 of file stm32l4xx_ll_adc.h.

#define ADC_JDR2_REGOFFSET (0x00000100U)

Definition at line 112 of file stm32l4xx_ll_adc.h.

#define ADC_JDR3_REGOFFSET (0x00000200U)

Definition at line 113 of file stm32l4xx_ll_adc.h.

#define ADC_JDR4_REGOFFSET (0x00000300U)

Definition at line 114 of file stm32l4xx_ll_adc.h.

#define ADC_OFR1_REGOFFSET (0x00000000U)

Definition at line 346 of file stm32l4xx_ll_adc.h.

#define ADC_OFR2_REGOFFSET (0x00000001U)

Definition at line 347 of file stm32l4xx_ll_adc.h.

#define ADC_OFR3_REGOFFSET (0x00000002U)

Definition at line 348 of file stm32l4xx_ll_adc.h.

#define ADC_OFR4_REGOFFSET (0x00000003U)

Definition at line 349 of file stm32l4xx_ll_adc.h.

#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)

Definition at line 350 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */

Definition at line 94 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */

Definition at line 95 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */

Definition at line 96 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */

Definition at line 97 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */

Definition at line 98 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */

Definition at line 99 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */

Definition at line 100 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */

Definition at line 85 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */

Definition at line 86 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */

Definition at line 87 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */

Definition at line 88 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */

Definition at line 89 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */

Definition at line 90 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */

Definition at line 91 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */

Definition at line 92 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */

Definition at line 93 of file stm32l4xx_ll_adc.h.

#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

Definition at line 81 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)

Definition at line 77 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_REG_TRIG_EDGE_MASK

Value:

(((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0U)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1U)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2U)) | \
                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3U))  )

Definition at line 148 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_GetTriggerSource().

#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

Definition at line 135 of file stm32l4xx_ll_adc.h.

#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */

Definition at line 155 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_GetTriggerSource().

#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */

Definition at line 154 of file stm32l4xx_ll_adc.h.

#define ADC_REG_TRIG_SOURCE_MASK

Value:

(((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0U)) | \
                                             ((ADC_CFGR_EXTSEL)                            << (4U * 1U)) | \
                                             ((ADC_CFGR_EXTSEL)                            << (4U * 2U)) | \
                                             ((ADC_CFGR_EXTSEL)                            << (4U * 3U))  )

Definition at line 140 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_REG_GetTriggerSource().

#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)

Definition at line 296 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetCalibrationFactor(), and LL_ADC_SetCalibrationFactor().

#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)

Definition at line 295 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_StartCalibration().

#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */

Definition at line 297 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSingleDiff(), and LL_ADC_SetChannelSingleDiff().

#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */

Definition at line 298 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_SetChannelSingleDiff().

#define ADC_SMPR1_REGOFFSET (0x00000000U)

Definition at line 212 of file stm32l4xx_ll_adc.h.

#define ADC_SMPR2_REGOFFSET (0x02000000U)

Definition at line 213 of file stm32l4xx_ll_adc.h.

#define ADC_SQR1_REGOFFSET (0x00000000U)

Definition at line 72 of file stm32l4xx_ll_adc.h.

#define ADC_SQR2_REGOFFSET (0x00000100U)

Definition at line 73 of file stm32l4xx_ll_adc.h.

#define ADC_SQR3_REGOFFSET (0x00000200U)

Definition at line 74 of file stm32l4xx_ll_adc.h.

#define ADC_SQR4_REGOFFSET (0x00000300U)

Definition at line 75 of file stm32l4xx_ll_adc.h.

#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)

Definition at line 84 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_DeInit().

#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)

Definition at line 85 of file stm32l4xx_ll_adc.c.

Referenced by LL_ADC_DeInit().

#define ADC_TR1_HT1_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */

Definition at line 358 of file stm32l4xx_ll_adc.h.

Referenced by LL_ADC_ConfigAnalogWDThresholds().

#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

Definition at line 370 of file stm32l4xx_ll_adc.h.

#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */

Definition at line 372 of file stm32l4xx_ll_adc.h.

#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature defined by TEMPSENSOR_CAL2_TEMP (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

Definition at line 371 of file stm32l4xx_ll_adc.h.

#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */

Definition at line 374 of file stm32l4xx_ll_adc.h.

#define TEMPSENSOR_CAL_VREFANALOG ( 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */

Definition at line 378 of file stm32l4xx_ll_adc.h.

#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */

Definition at line 367 of file stm32l4xx_ll_adc.h.

#define VREFINT_CAL_VREF ( 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */

Definition at line 368 of file stm32l4xx_ll_adc.h.

Defines

Define Documentation