STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_adc.h 00004 * @author MCD Application Team 00005 * @brief Header file of ADC LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_LL_ADC_H 00038 #define __STM32L4xx_LL_ADC_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx.h" 00046 00047 /** @addtogroup STM32L4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined (ADC1) || defined (ADC2) || defined (ADC3) 00052 00053 /** @defgroup ADC_LL ADC 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 00060 /* Private constants ---------------------------------------------------------*/ 00061 /** @defgroup ADC_LL_Private_Constants ADC Private Constants 00062 * @{ 00063 */ 00064 00065 /* Internal mask for ADC group regular sequencer: */ 00066 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ 00067 /* - sequencer register offset */ 00068 /* - sequencer rank bits position into the selected register */ 00069 00070 /* Internal register offset for ADC group regular sequencer configuration */ 00071 /* (offset placed into a spare area of literal definition) */ 00072 #define ADC_SQR1_REGOFFSET (0x00000000U) 00073 #define ADC_SQR2_REGOFFSET (0x00000100U) 00074 #define ADC_SQR3_REGOFFSET (0x00000200U) 00075 #define ADC_SQR4_REGOFFSET (0x00000300U) 00076 00077 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) 00078 #if defined(CORE_CM0PLUS) 00079 #define ADC_SQRX_REGOFFSET_POS (8U) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */ 00080 #endif 00081 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) 00082 00083 /* Definition of ADC group regular sequencer bits information to be inserted */ 00084 /* into ADC group regular sequencer ranks literals definition. */ 00085 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */ 00086 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */ 00087 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */ 00088 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */ 00089 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */ 00090 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */ 00091 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ 00092 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ 00093 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ 00094 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */ 00095 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */ 00096 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */ 00097 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */ 00098 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */ 00099 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */ 00100 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */ 00101 00102 00103 00104 /* Internal mask for ADC group injected sequencer: */ 00105 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ 00106 /* - data register offset */ 00107 /* - sequencer rank bits position into the selected register */ 00108 00109 /* Internal register offset for ADC group injected data register */ 00110 /* (offset placed into a spare area of literal definition) */ 00111 #define ADC_JDR1_REGOFFSET (0x00000000U) 00112 #define ADC_JDR2_REGOFFSET (0x00000100U) 00113 #define ADC_JDR3_REGOFFSET (0x00000200U) 00114 #define ADC_JDR4_REGOFFSET (0x00000300U) 00115 00116 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) 00117 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) 00118 #if defined(CORE_CM0PLUS) 00119 #define ADC_JDRX_REGOFFSET_POS (8U) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */ 00120 #endif 00121 00122 /* Definition of ADC group injected sequencer bits information to be inserted */ 00123 /* into ADC group injected sequencer ranks literals definition. */ 00124 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */ 00125 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */ 00126 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */ 00127 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */ 00128 00129 00130 00131 /* Internal mask for ADC group regular trigger: */ 00132 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ 00133 /* - regular trigger source */ 00134 /* - regular trigger edge */ 00135 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ 00136 00137 /* Mask containing trigger source masks for each of possible */ 00138 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00139 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00140 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0U)) | \ 00141 ((ADC_CFGR_EXTSEL) << (4U * 1U)) | \ 00142 ((ADC_CFGR_EXTSEL) << (4U * 2U)) | \ 00143 ((ADC_CFGR_EXTSEL) << (4U * 3U)) ) 00144 00145 /* Mask containing trigger edge masks for each of possible */ 00146 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00147 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00148 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0U)) | \ 00149 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \ 00150 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \ 00151 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) ) 00152 00153 /* Definition of ADC group regular trigger bits information. */ 00154 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */ 00155 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */ 00156 00157 00158 00159 /* Internal mask for ADC group injected trigger: */ 00160 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ 00161 /* - injected trigger source */ 00162 /* - injected trigger edge */ 00163 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ 00164 00165 /* Mask containing trigger source masks for each of possible */ 00166 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00167 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00168 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0U)) | \ 00169 ((ADC_JSQR_JEXTSEL) << (4U * 1U)) | \ 00170 ((ADC_JSQR_JEXTSEL) << (4U * 2U)) | \ 00171 ((ADC_JSQR_JEXTSEL) << (4U * 3U)) ) 00172 00173 /* Mask containing trigger edge masks for each of possible */ 00174 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00175 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00176 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0U)) | \ 00177 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \ 00178 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \ 00179 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) ) 00180 00181 /* Definition of ADC group injected trigger bits information. */ 00182 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */ 00183 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */ 00184 00185 00186 00187 00188 00189 00190 /* Internal mask for ADC channel: */ 00191 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ 00192 /* - channel identifier defined by number */ 00193 /* - channel identifier defined by bitfield */ 00194 /* - channel differentiation between external channels (connected to */ 00195 /* GPIO pins) and internal channels (connected to internal paths) */ 00196 /* - channel sampling time defined by SMPRx register offset */ 00197 /* and SMPx bits positions into SMPRx register */ 00198 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH) 00199 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH) 00200 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ 00201 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) 00202 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ 00203 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ 00204 00205 /* Channel differentiation between external and internal channels */ 00206 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000U) /* Marker of internal channel */ 00207 #define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ 00208 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) 00209 00210 /* Internal register offset for ADC channel sampling time configuration */ 00211 /* (offset placed into a spare area of literal definition) */ 00212 #define ADC_SMPR1_REGOFFSET (0x00000000U) 00213 #define ADC_SMPR2_REGOFFSET (0x02000000U) 00214 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) 00215 #if defined(CORE_CM0PLUS) 00216 #define ADC_SMPRX_REGOFFSET_POS (25U) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */ 00217 #endif 00218 00219 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000U) 00220 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ 00221 00222 /* Definition of channels ID number information to be inserted into */ 00223 /* channels literals definition. */ 00224 #define ADC_CHANNEL_0_NUMBER (0x00000000U) 00225 #define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0) 00226 #define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 ) 00227 #define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) 00228 #define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 ) 00229 #define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) 00230 #define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 ) 00231 #define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) 00232 #define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 ) 00233 #define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0) 00234 #define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 ) 00235 #define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) 00236 #define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 ) 00237 #define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) 00238 #define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 ) 00239 #define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) 00240 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 ) 00241 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0) 00242 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 ) 00243 00244 /* Definition of channels ID bitfield information to be inserted into */ 00245 /* channels literals definition. */ 00246 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0) 00247 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1) 00248 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2) 00249 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3) 00250 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4) 00251 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5) 00252 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6) 00253 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7) 00254 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8) 00255 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9) 00256 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10) 00257 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11) 00258 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12) 00259 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13) 00260 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14) 00261 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15) 00262 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16) 00263 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17) 00264 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18) 00265 00266 /* Definition of channels sampling time information to be inserted into */ 00267 /* channels literals definition. */ 00268 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */ 00269 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */ 00270 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */ 00271 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */ 00272 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */ 00273 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */ 00274 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */ 00275 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */ 00276 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */ 00277 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */ 00278 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */ 00279 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */ 00280 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */ 00281 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */ 00282 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */ 00283 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */ 00284 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */ 00285 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */ 00286 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */ 00287 00288 00289 /* Internal mask for ADC mode single or differential ended: */ 00290 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */ 00291 /* the relevant bits for: */ 00292 /* (concatenation of multiple bits used in different registers) */ 00293 /* - ADC calibration: calibration start, calibration factor get or set */ 00294 /* - ADC channels: set each ADC channel ending mode */ 00295 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF) 00296 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S) 00297 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */ 00298 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */ 00299 #if defined(CORE_CM0PLUS) 00300 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000U) /* Selection of 1 bit to discriminate differential mode: mask of bit */ 00301 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16U) /* Selection of 1 bit to discriminate differential mode: position of bit */ 00302 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4U) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */ 00303 #endif 00304 00305 /* Internal mask for ADC analog watchdog: */ 00306 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ 00307 /* (concatenation of multiple bits used in different analog watchdogs, */ 00308 /* (feature of several watchdogs not available on all STM32 families)). */ 00309 /* - analog watchdog 1: monitored channel defined by number, */ 00310 /* selection of ADC group (ADC groups regular and-or injected). */ 00311 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */ 00312 /* selection on groups. */ 00313 00314 /* Internal register offset for ADC analog watchdog channel configuration */ 00315 #define ADC_AWD_CR1_REGOFFSET (0x00000000U) 00316 #define ADC_AWD_CR2_REGOFFSET (0x00100000U) 00317 #define ADC_AWD_CR3_REGOFFSET (0x00200000U) 00318 00319 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */ 00320 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */ 00321 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0) 00322 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024U) 00323 00324 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET) 00325 00326 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) 00327 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH) 00328 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK) 00329 00330 #define ADC_AWD_CRX_REGOFFSET_POS (20U) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */ 00331 00332 /* Internal register offset for ADC analog watchdog threshold configuration */ 00333 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) 00334 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET) 00335 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET) 00336 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET) 00337 #if defined(CORE_CM0PLUS) 00338 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */ 00339 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000U) /* Selection of 1 bit to discriminate threshold high: mask of bit */ 00340 #define ADC_AWD_TRX_BIT_HIGH_POS (16U) /* Selection of 1 bit to discriminate threshold high: position of bit */ 00341 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4U) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */ 00342 #endif 00343 00344 /* Internal mask for ADC offset: */ 00345 /* Internal register offset for ADC offset number configuration */ 00346 #define ADC_OFR1_REGOFFSET (0x00000000U) 00347 #define ADC_OFR2_REGOFFSET (0x00000001U) 00348 #define ADC_OFR3_REGOFFSET (0x00000002U) 00349 #define ADC_OFR4_REGOFFSET (0x00000003U) 00350 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET) 00351 00352 00353 /* ADC registers bits positions */ 00354 #define ADC_CFGR_RES_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */ 00355 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */ 00356 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */ 00357 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */ 00358 #define ADC_TR1_HT1_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */ 00359 00360 00361 /* ADC registers bits groups */ 00362 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */ 00363 00364 00365 /* ADC internal channels related definitions */ 00366 /* Internal voltage reference VrefInt */ 00367 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ 00368 #define VREFINT_CAL_VREF ( 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ 00369 /* Temperature sensor */ 00370 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ 00371 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature defined by TEMPSENSOR_CAL2_TEMP (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ 00372 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ 00373 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00374 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ 00375 #else 00376 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ 00377 #endif 00378 #define TEMPSENSOR_CAL_VREFANALOG ( 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ 00379 00380 00381 /** 00382 * @} 00383 */ 00384 00385 00386 /* Private macros ------------------------------------------------------------*/ 00387 /** @defgroup ADC_LL_Private_Macros ADC Private Macros 00388 * @{ 00389 */ 00390 00391 /** 00392 * @brief Driver macro reserved for internal use: isolate bits with the 00393 * selected mask and shift them to the register LSB 00394 * (shift mask on register position bit 0). 00395 * @param __BITS__ Bits in register 32 bits 00396 * @param __MASK__ Mask in register 32 bits 00397 * @retval Bits in register 32 bits 00398 */ 00399 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ 00400 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) 00401 00402 /** 00403 * @brief Driver macro reserved for internal use: set a pointer to 00404 * a register from a register basis from which an offset 00405 * is applied. 00406 * @param __REG__ Register basis from which the offset is applied. 00407 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). 00408 * @retval Pointer to register address 00409 */ 00410 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ 00411 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) 00412 00413 /** 00414 * @} 00415 */ 00416 00417 00418 /* Exported types ------------------------------------------------------------*/ 00419 #if defined(USE_FULL_LL_DRIVER) 00420 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure 00421 * @{ 00422 */ 00423 00424 /** 00425 * @brief Structure definition of some features of ADC common parameters 00426 * and multimode 00427 * (all ADC instances belonging to the same ADC common instance). 00428 * @note The setting of these parameters by function @ref LL_ADC_CommonInit() 00429 * is conditioned to ADC instances state (all ADC instances 00430 * sharing the same ADC common instance): 00431 * All ADC instances sharing the same ADC common instance must be 00432 * disabled. 00433 */ 00434 typedef struct 00435 { 00436 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. 00437 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE 00438 @note On this STM32 serie, if ADC group injected is used, some 00439 clock ratio constraints between ADC clock and AHB clock 00440 must be respected. Refer to reference manual. 00441 00442 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ 00443 00444 #if defined(ADC_MULTIMODE_SUPPORT) 00445 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). 00446 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE 00447 00448 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ 00449 00450 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA. 00451 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER 00452 00453 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */ 00454 00455 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases. 00456 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY 00457 00458 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */ 00459 #endif /* ADC_MULTIMODE_SUPPORT */ 00460 00461 } LL_ADC_CommonInitTypeDef; 00462 00463 /** 00464 * @brief Structure definition of some features of ADC instance. 00465 * @note These parameters have an impact on ADC scope: ADC instance. 00466 * Affects both group regular and group injected (availability 00467 * of ADC group injected depends on STM32 families). 00468 * Refer to corresponding unitary functions into 00469 * @ref ADC_LL_EF_Configuration_ADC_Instance . 00470 * @note The setting of these parameters by function @ref LL_ADC_Init() 00471 * is conditioned to ADC state: 00472 * ADC instance must be disabled. 00473 * This condition is applied to all ADC features, for efficiency 00474 * and compatibility over all STM32 families. However, the different 00475 * features can be set under different ADC state conditions 00476 * (setting possible with ADC enabled without conversion on going, 00477 * ADC enabled with conversion on going, ...) 00478 * Each feature can be updated afterwards with a unitary function 00479 * and potentially with ADC in a different state than disabled, 00480 * refer to description of each function for setting 00481 * conditioned to ADC state. 00482 */ 00483 typedef struct 00484 { 00485 uint32_t Resolution; /*!< Set ADC resolution. 00486 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION 00487 00488 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ 00489 00490 uint32_t DataAlignment; /*!< Set ADC conversion data alignment. 00491 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN 00492 00493 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ 00494 00495 uint32_t LowPowerMode; /*!< Set ADC low power mode. 00496 This parameter can be a value of @ref ADC_LL_EC_LP_MODE 00497 00498 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */ 00499 00500 } LL_ADC_InitTypeDef; 00501 00502 /** 00503 * @brief Structure definition of some features of ADC group regular. 00504 * @note These parameters have an impact on ADC scope: ADC group regular. 00505 * Refer to corresponding unitary functions into 00506 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 00507 * (functions with prefix "REG"). 00508 * @note The setting of these parameters by function @ref LL_ADC_REG_Init() 00509 * is conditioned to ADC state: 00510 * ADC instance must be disabled. 00511 * This condition is applied to all ADC features, for efficiency 00512 * and compatibility over all STM32 families. However, the different 00513 * features can be set under different ADC state conditions 00514 * (setting possible with ADC enabled without conversion on going, 00515 * ADC enabled with conversion on going, ...) 00516 * Each feature can be updated afterwards with a unitary function 00517 * and potentially with ADC in a different state than disabled, 00518 * refer to description of each function for setting 00519 * conditioned to ADC state. 00520 */ 00521 typedef struct 00522 { 00523 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). 00524 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE 00525 @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge 00526 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). 00527 In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). 00528 00529 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ 00530 00531 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. 00532 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH 00533 00534 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ 00535 00536 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. 00537 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE 00538 @note This parameter has an effect only if group regular sequencer is enabled 00539 (scan length of 2 ranks or more). 00540 00541 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ 00542 00543 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). 00544 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE 00545 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. 00546 00547 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ 00548 00549 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. 00550 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER 00551 00552 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ 00553 00554 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun: 00555 data preserved or overwritten. 00556 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR 00557 00558 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */ 00559 00560 } LL_ADC_REG_InitTypeDef; 00561 00562 /** 00563 * @brief Structure definition of some features of ADC group injected. 00564 * @note These parameters have an impact on ADC scope: ADC group injected. 00565 * Refer to corresponding unitary functions into 00566 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 00567 * (functions with prefix "INJ"). 00568 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() 00569 * is conditioned to ADC state: 00570 * ADC instance must be disabled. 00571 * This condition is applied to all ADC features, for efficiency 00572 * and compatibility over all STM32 families. However, the different 00573 * features can be set under different ADC state conditions 00574 * (setting possible with ADC enabled without conversion on going, 00575 * ADC enabled with conversion on going, ...) 00576 * Each feature can be updated afterwards with a unitary function 00577 * and potentially with ADC in a different state than disabled, 00578 * refer to description of each function for setting 00579 * conditioned to ADC state. 00580 */ 00581 typedef struct 00582 { 00583 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). 00584 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE 00585 @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge 00586 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). 00587 In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge(). 00588 00589 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ 00590 00591 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. 00592 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH 00593 00594 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ 00595 00596 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. 00597 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE 00598 @note This parameter has an effect only if group injected sequencer is enabled 00599 (scan length of 2 ranks or more). 00600 00601 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ 00602 00603 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. 00604 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO 00605 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. 00606 00607 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ 00608 00609 } LL_ADC_INJ_InitTypeDef; 00610 00611 /** 00612 * @} 00613 */ 00614 #endif /* USE_FULL_LL_DRIVER */ 00615 00616 /* Exported constants --------------------------------------------------------*/ 00617 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants 00618 * @{ 00619 */ 00620 00621 /** @defgroup ADC_LL_EC_FLAG ADC flags 00622 * @brief Flags defines which can be used with LL_ADC_ReadReg function 00623 * @{ 00624 */ 00625 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */ 00626 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */ 00627 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */ 00628 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */ 00629 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */ 00630 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */ 00631 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */ 00632 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */ 00633 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */ 00634 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */ 00635 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */ 00636 #if defined(ADC_MULTIMODE_SUPPORT) 00637 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */ 00638 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */ 00639 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */ 00640 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */ 00641 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */ 00642 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */ 00643 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */ 00644 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */ 00645 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */ 00646 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */ 00647 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */ 00648 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */ 00649 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */ 00650 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */ 00651 #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */ 00652 #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */ 00653 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ 00654 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */ 00655 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */ 00656 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */ 00657 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */ 00658 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */ 00659 #endif 00660 /** 00661 * @} 00662 */ 00663 00664 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) 00665 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions 00666 * @{ 00667 */ 00668 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */ 00669 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */ 00670 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */ 00671 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */ 00672 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */ 00673 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */ 00674 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */ 00675 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */ 00676 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */ 00677 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */ 00678 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */ 00679 /** 00680 * @} 00681 */ 00682 00683 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose 00684 * @{ 00685 */ 00686 /* List of ADC registers intended to be used (most commonly) with */ 00687 /* DMA transfer. */ 00688 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ 00689 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ 00690 #if defined(ADC_MULTIMODE_SUPPORT) 00691 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ 00692 #endif 00693 /** 00694 * @} 00695 */ 00696 00697 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 00698 * @{ 00699 */ 00700 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */ 00701 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ 00702 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ 00703 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock without prescaler */ 00704 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */ 00705 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */ 00706 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */ 00707 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8 */ 00708 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */ 00709 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12 */ 00710 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */ 00711 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */ 00712 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */ 00713 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */ 00714 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */ 00715 /** 00716 * @} 00717 */ 00718 00719 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels 00720 * @{ 00721 */ 00722 /* Note: Other measurement paths to internal channels may be available */ 00723 /* (connections to other peripherals). */ 00724 /* If they are not listed below, they do not require any specific */ 00725 /* path enable. In this case, Access to measurement path is done */ 00726 /* only by selecting the corresponding ADC internal channel. */ 00727 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000U)/*!< ADC measurement pathes all disabled */ 00728 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ 00729 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */ 00730 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */ 00731 /** 00732 * @} 00733 */ 00734 00735 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution 00736 * @{ 00737 */ 00738 #define LL_ADC_RESOLUTION_12B (0x00000000U) /*!< ADC resolution 12 bits */ 00739 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */ 00740 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */ 00741 #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */ 00742 /** 00743 * @} 00744 */ 00745 00746 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment 00747 * @{ 00748 */ 00749 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ 00750 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ 00751 /** 00752 * @} 00753 */ 00754 00755 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode 00756 * @{ 00757 */ 00758 #define LL_ADC_LP_MODE_NONE (0x00000000U) /*!< No ADC low power mode activated */ 00759 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */ 00760 /** 00761 * @} 00762 */ 00763 00764 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number 00765 * @{ 00766 */ 00767 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00768 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00769 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00770 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00771 /** 00772 * @} 00773 */ 00774 00775 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state 00776 * @{ 00777 */ 00778 #define LL_ADC_OFFSET_DISABLE (0x00000000U)/*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */ 00779 #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */ 00780 /** 00781 * @} 00782 */ 00783 00784 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups 00785 * @{ 00786 */ 00787 #define LL_ADC_GROUP_REGULAR (0x00000001U) /*!< ADC group regular (available on all STM32 devices) */ 00788 #define LL_ADC_GROUP_INJECTED (0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/ 00789 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003U) /*!< ADC both groups regular and injected */ 00790 /** 00791 * @} 00792 */ 00793 00794 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number 00795 * @{ 00796 */ 00797 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 00798 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 00799 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 00800 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 00801 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 00802 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 00803 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 00804 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 00805 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 00806 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 00807 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 00808 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 00809 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 00810 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 00811 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 00812 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 00813 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 00814 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 00815 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ 00816 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32L4, ADC channel available only on ADC instance: ADC1. */ 00817 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */ 00818 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */ 00819 #if defined(ADC1) && !defined(ADC2) 00820 #define LL_ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */ 00821 #define LL_ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */ 00822 #elif defined(ADC2) 00823 #define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */ 00824 #define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */ 00825 #if defined(ADC3) 00826 #define LL_ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */ 00827 #define LL_ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */ 00828 #endif 00829 #endif 00830 /** 00831 * @} 00832 */ 00833 00834 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source 00835 * @{ 00836 */ 00837 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */ 00838 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 00839 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ 00840 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00841 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00842 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00843 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 00844 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00845 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 00846 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00847 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 00848 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00849 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ 00850 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 00851 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ 00852 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ 00853 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ 00854 /** 00855 * @} 00856 */ 00857 00858 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge 00859 * @{ 00860 */ 00861 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ 00862 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */ 00863 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ 00864 /** 00865 * @} 00866 */ 00867 00868 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode 00869 * @{ 00870 */ 00871 #define LL_ADC_REG_CONV_SINGLE (0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */ 00872 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ 00873 /** 00874 * @} 00875 */ 00876 00877 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data 00878 * @{ 00879 */ 00880 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DMA */ 00881 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ 00882 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ 00883 /** 00884 * @} 00885 */ 00886 00887 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 00888 /** @defgroup ADC_LL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data 00889 * @{ 00890 */ 00891 #define LL_ADC_REG_DFSDM_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DFSDM. */ 00892 #define LL_ADC_REG_DFSDM_TRANSFER_ENABLE (ADC_CFGR_DFSDMCFG) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ 00893 /** 00894 * @} 00895 */ 00896 #endif 00897 00898 #if defined(ADC_SMPR1_SMPPLUS) 00899 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration 00900 * @{ 00901 */ 00902 #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000U) /*!< ADC sampling time let to default settings. */ 00903 #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling time 2.5 ADC clock cycles, whatever channels mapped on ADC groups regular or injected). */ 00904 /** 00905 * @} 00906 */ 00907 #endif 00908 00909 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 00910 * @{ 00911 */ 00912 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000U) /*!< ADC group regular behavior in case of overrun: data preserved */ 00913 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ 00914 /** 00915 * @} 00916 */ 00917 00918 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length 00919 * @{ 00920 */ 00921 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ 00922 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ 00923 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ 00924 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ 00925 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ 00926 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ 00927 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ 00928 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ 00929 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ 00930 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ 00931 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ 00932 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ 00933 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ 00934 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ 00935 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ 00936 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ 00937 /** 00938 * @} 00939 */ 00940 00941 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode 00942 * @{ 00943 */ 00944 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */ 00945 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ 00946 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ 00947 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ 00948 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ 00949 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ 00950 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ 00951 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ 00952 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ 00953 /** 00954 * @} 00955 */ 00956 00957 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 00958 * @{ 00959 */ 00960 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ 00961 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ 00962 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ 00963 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ 00964 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ 00965 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ 00966 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ 00967 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ 00968 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ 00969 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ 00970 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ 00971 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ 00972 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ 00973 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ 00974 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ 00975 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ 00976 /** 00977 * @} 00978 */ 00979 00980 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source 00981 * @{ 00982 */ 00983 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000U) /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */ 00984 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 00985 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ 00986 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00987 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 00988 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00989 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 00990 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00991 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00992 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00993 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 00994 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ 00995 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00996 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 00997 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ 00998 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ 00999 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 01000 /** 01001 * @} 01002 */ 01003 01004 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge 01005 * @{ 01006 */ 01007 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */ 01008 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */ 01009 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */ 01010 /** 01011 * @} 01012 */ 01013 01014 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode 01015 * @{ 01016 */ 01017 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000U) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ 01018 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ 01019 /** 01020 * @} 01021 */ 01022 01023 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode 01024 * @{ 01025 */ 01026 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000U) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */ 01027 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */ 01028 #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */ 01029 /** 01030 * @} 01031 */ 01032 01033 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length 01034 * @{ 01035 */ 01036 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ 01037 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ 01038 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ 01039 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ 01040 /** 01041 * @} 01042 */ 01043 01044 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode 01045 * @{ 01046 */ 01047 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group injected sequencer discontinuous mode disable */ 01048 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ 01049 /** 01050 * @} 01051 */ 01052 01053 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 01054 * @{ 01055 */ 01056 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */ 01057 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */ 01058 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */ 01059 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */ 01060 /** 01061 * @} 01062 */ 01063 01064 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 01065 * @{ 01066 */ 01067 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000U) /*!< Sampling time 2.5 ADC clock cycles */ 01068 #define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */ 01069 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles */ 01070 #define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */ 01071 #define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 47.5 ADC clock cycles */ 01072 #define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */ 01073 #define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 247.5 ADC clock cycles */ 01074 #define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */ 01075 /** 01076 * @} 01077 */ 01078 01079 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 01080 * @{ 01081 */ 01082 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ 01083 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ 01084 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */ 01085 /** 01086 * @} 01087 */ 01088 01089 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 01090 * @{ 01091 */ 01092 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ 01093 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */ 01094 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */ 01095 /** 01096 * @} 01097 */ 01098 01099 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels 01100 * @{ 01101 */ 01102 #define LL_ADC_AWD_DISABLE (0x00000000U) /*!< ADC analog watchdog monitoring disabled */ 01103 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ 01104 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ 01105 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ 01106 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ 01107 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ 01108 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ 01109 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ 01110 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ 01111 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ 01112 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ 01113 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ 01114 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ 01115 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ 01116 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ 01117 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ 01118 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ 01119 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ 01120 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ 01121 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ 01122 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ 01123 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ 01124 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ 01125 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ 01126 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ 01127 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ 01128 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ 01129 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ 01130 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ 01131 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ 01132 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ 01133 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ 01134 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ 01135 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ 01136 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ 01137 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ 01138 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ 01139 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ 01140 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ 01141 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ 01142 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ 01143 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ 01144 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ 01145 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ 01146 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ 01147 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ 01148 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ 01149 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ 01150 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ 01151 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ 01152 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ 01153 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ 01154 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ 01155 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ 01156 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ 01157 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ 01158 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ 01159 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ 01160 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */ 01161 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */ 01162 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */ 01163 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ 01164 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ 01165 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ 01166 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ 01167 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */ 01168 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */ 01169 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ 01170 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */ 01171 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */ 01172 #if defined(ADC1) && !defined(ADC2) 01173 #define LL_ADC_AWD_CH_DAC1CH1_REG ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only */ 01174 #define LL_ADC_AWD_CH_DAC1CH1_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only */ 01175 #define LL_ADC_AWD_CH_DAC1CH1_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected */ 01176 #define LL_ADC_AWD_CH_DAC1CH2_REG ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only */ 01177 #define LL_ADC_AWD_CH_DAC1CH2_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only */ 01178 #define LL_ADC_AWD_CH_DAC1CH2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected */ 01179 #elif defined(ADC2) 01180 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */ 01181 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */ 01182 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */ 01183 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */ 01184 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */ 01185 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */ 01186 #if defined(ADC3) 01187 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */ 01188 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */ 01189 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */ 01190 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */ 01191 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */ 01192 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */ 01193 #endif 01194 #endif 01195 /** 01196 * @} 01197 */ 01198 01199 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds 01200 * @{ 01201 */ 01202 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */ 01203 #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */ 01204 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */ 01205 /** 01206 * @} 01207 */ 01208 01209 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope 01210 * @{ 01211 */ 01212 #define LL_ADC_OVS_DISABLE (0x00000000U) /*!< ADC oversampling disabled. */ 01213 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */ 01214 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ 01215 #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */ 01216 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ 01217 /** 01218 * @} 01219 */ 01220 01221 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 01222 * @{ 01223 */ 01224 #define LL_ADC_OVS_REG_CONT (0x00000000U) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ 01225 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ 01226 /** 01227 * @} 01228 */ 01229 01230 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio 01231 * @{ 01232 */ 01233 #define LL_ADC_OVS_RATIO_2 (0x00000000U) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 01234 #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 01235 #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 01236 #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 01237 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 01238 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 01239 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 01240 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 01241 /** 01242 * @} 01243 */ 01244 01245 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift 01246 * @{ 01247 */ 01248 #define LL_ADC_OVS_SHIFT_NONE (0x00000000U) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ 01249 #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ 01250 #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ 01251 #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ 01252 #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ 01253 #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ 01254 #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ 01255 #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ 01256 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ 01257 /** 01258 * @} 01259 */ 01260 01261 #if defined(ADC_MULTIMODE_SUPPORT) 01262 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode 01263 * @{ 01264 */ 01265 #define LL_ADC_MULTI_INDEPENDENT (0x00000000U) /*!< ADC dual mode disabled (ADC independent mode) */ 01266 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ 01267 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */ 01268 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */ 01269 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 01270 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 01271 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 01272 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ 01273 /** 01274 * @} 01275 */ 01276 01277 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer 01278 * @{ 01279 */ 01280 #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000U) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ 01281 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */ 01282 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */ 01283 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */ 01284 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */ 01285 /** 01286 * @} 01287 */ 01288 01289 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 01290 * @{ 01291 */ 01292 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000U) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ 01293 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ 01294 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ 01295 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ 01296 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ 01297 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ 01298 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ 01299 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ 01300 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ 01301 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ 01302 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ 01303 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ 01304 /** 01305 * @} 01306 */ 01307 01308 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave 01309 * @{ 01310 */ 01311 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */ 01312 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */ 01313 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ 01314 /** 01315 * @} 01316 */ 01317 01318 #endif /* ADC_MULTIMODE_SUPPORT */ 01319 01320 /** @defgroup ADC_LL_EC_LEGACY ADC literals legacy naming 01321 * @{ 01322 */ 01323 #define LL_ADC_REG_TRIG_SW_START (LL_ADC_REG_TRIG_SOFTWARE) 01324 #define LL_ADC_REG_TRIG_EXT_TIM1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) 01325 #define LL_ADC_REG_TRIG_EXT_TIM1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) 01326 #define LL_ADC_REG_TRIG_EXT_TIM1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) 01327 #define LL_ADC_REG_TRIG_EXT_TIM2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) 01328 #define LL_ADC_REG_TRIG_EXT_TIM3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) 01329 #define LL_ADC_REG_TRIG_EXT_TIM4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) 01330 01331 #define LL_ADC_INJ_TRIG_SW_START (LL_ADC_INJ_TRIG_SOFTWARE) 01332 #define LL_ADC_INJ_TRIG_EXT_TIM1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) 01333 #define LL_ADC_INJ_TRIG_EXT_TIM2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) 01334 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) 01335 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) 01336 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) 01337 #define LL_ADC_INJ_TRIG_EXT_TIM8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) 01338 01339 #define LL_ADC_OVS_DATA_SHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) 01340 #define LL_ADC_OVS_DATA_SHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) 01341 #define LL_ADC_OVS_DATA_SHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) 01342 #define LL_ADC_OVS_DATA_SHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) 01343 #define LL_ADC_OVS_DATA_SHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) 01344 #define LL_ADC_OVS_DATA_SHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) 01345 #define LL_ADC_OVS_DATA_SHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) 01346 #define LL_ADC_OVS_DATA_SHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) 01347 #define LL_ADC_OVS_DATA_SHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) 01348 01349 /** 01350 * @} 01351 */ 01352 01353 01354 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays 01355 * @note Only ADC IP HW delays are defined in ADC LL driver driver, 01356 * not timeout values. 01357 * For details on delays values, refer to descriptions in source code 01358 * above each literal definition. 01359 * @{ 01360 */ 01361 01362 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ 01363 /* not timeout values. */ 01364 /* Timeout values for ADC operations are dependent to device clock */ 01365 /* configuration (system clock versus ADC clock), */ 01366 /* and therefore must be defined in user application. */ 01367 /* Indications for estimation of ADC timeout delays, for this */ 01368 /* STM32 serie: */ 01369 /* - ADC calibration time: maximum delay is 112/fADC. */ 01370 /* (refer to device datasheet, parameter "tCAL") */ 01371 /* - ADC enable time: maximum delay is 1 conversion cycle. */ 01372 /* (refer to device datasheet, parameter "tSTAB") */ 01373 /* - ADC disable time: maximum delay should be a few ADC clock cycles */ 01374 /* - ADC stop conversion time: maximum delay should be a few ADC clock */ 01375 /* cycles */ 01376 /* - ADC conversion time: duration depending on ADC clock and ADC */ 01377 /* configuration. */ 01378 /* (refer to device reference manual, section "Timing") */ 01379 01380 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */ 01381 /* Delay set to maximum value (refer to device datasheet, */ 01382 /* parameter "tADCVREG_STUP"). */ 01383 /* Unit: us */ 01384 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10U) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ 01385 01386 /* Delay for internal voltage reference stabilization time. */ 01387 /* Delay set to maximum value (refer to device datasheet, */ 01388 /* parameter "tstart_vrefint"). */ 01389 /* Unit: us */ 01390 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12U) /*!< Delay for internal voltage reference stabilization time */ 01391 01392 /* Delay for temperature sensor stabilization time. */ 01393 /* Literal set to maximum value (refer to device datasheet, */ 01394 /* parameter "tSTART"). */ 01395 /* Unit: us */ 01396 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 120U) /*!< Delay for temperature sensor stabilization time */ 01397 01398 /* Delay required between ADC end of calibration and ADC enable. */ 01399 /* Note: On this STM32 serie, a minimum number of ADC clock cycles */ 01400 /* are required between ADC end of calibration and ADC enable. */ 01401 /* Wait time can be computed in user application by waiting for the */ 01402 /* equivalent number of CPU cycles, by taking into account */ 01403 /* ratio of CPU clock versus ADC clock prescalers. */ 01404 /* Unit: ADC clock cycles. */ 01405 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4U) /*!< Delay required between ADC end of calibration and ADC enable */ 01406 01407 /** 01408 * @} 01409 */ 01410 01411 /** 01412 * @} 01413 */ 01414 01415 01416 /* Exported macro ------------------------------------------------------------*/ 01417 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros 01418 * @{ 01419 */ 01420 01421 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros 01422 * @{ 01423 */ 01424 01425 /** 01426 * @brief Write a value in ADC register 01427 * @param __INSTANCE__ ADC Instance 01428 * @param __REG__ Register to be written 01429 * @param __VALUE__ Value to be written in the register 01430 * @retval None 01431 */ 01432 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 01433 01434 /** 01435 * @brief Read a value in ADC register 01436 * @param __INSTANCE__ ADC Instance 01437 * @param __REG__ Register to be read 01438 * @retval Register value 01439 */ 01440 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 01441 /** 01442 * @} 01443 */ 01444 01445 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro 01446 * @{ 01447 */ 01448 01449 /** 01450 * @brief Helper macro to get ADC channel number in decimal format 01451 * from literals LL_ADC_CHANNEL_x. 01452 * @note Example: 01453 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) 01454 * will return decimal number "4". 01455 * @note The input can be a value from functions where a channel 01456 * number is returned, either defined with number 01457 * or with bitfield (only one bit must be set). 01458 * @param __CHANNEL__ This parameter can be one of the following values: 01459 * @arg @ref LL_ADC_CHANNEL_0 01460 * @arg @ref LL_ADC_CHANNEL_1 (7) 01461 * @arg @ref LL_ADC_CHANNEL_2 (7) 01462 * @arg @ref LL_ADC_CHANNEL_3 (7) 01463 * @arg @ref LL_ADC_CHANNEL_4 (7) 01464 * @arg @ref LL_ADC_CHANNEL_5 (7) 01465 * @arg @ref LL_ADC_CHANNEL_6 01466 * @arg @ref LL_ADC_CHANNEL_7 01467 * @arg @ref LL_ADC_CHANNEL_8 01468 * @arg @ref LL_ADC_CHANNEL_9 01469 * @arg @ref LL_ADC_CHANNEL_10 01470 * @arg @ref LL_ADC_CHANNEL_11 01471 * @arg @ref LL_ADC_CHANNEL_12 01472 * @arg @ref LL_ADC_CHANNEL_13 01473 * @arg @ref LL_ADC_CHANNEL_14 01474 * @arg @ref LL_ADC_CHANNEL_15 01475 * @arg @ref LL_ADC_CHANNEL_16 01476 * @arg @ref LL_ADC_CHANNEL_17 01477 * @arg @ref LL_ADC_CHANNEL_18 01478 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01479 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 01480 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 01481 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 01482 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 01483 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01484 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01485 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01486 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01487 * 01488 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01489 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01490 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01491 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01492 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01493 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01494 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01495 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 01496 * @retval Value between Min_Data=0 and Max_Data=18 01497 */ 01498 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 01499 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \ 01500 ? ( \ 01501 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ 01502 ) \ 01503 : \ 01504 ( \ 01505 POSITION_VAL((__CHANNEL__)) \ 01506 ) \ 01507 ) 01508 01509 /** 01510 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x 01511 * from number in decimal format. 01512 * @note Example: 01513 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) 01514 * will return a data equivalent to "LL_ADC_CHANNEL_4". 01515 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 01516 * @retval Returned value can be one of the following values: 01517 * @arg @ref LL_ADC_CHANNEL_0 01518 * @arg @ref LL_ADC_CHANNEL_1 (7) 01519 * @arg @ref LL_ADC_CHANNEL_2 (7) 01520 * @arg @ref LL_ADC_CHANNEL_3 (7) 01521 * @arg @ref LL_ADC_CHANNEL_4 (7) 01522 * @arg @ref LL_ADC_CHANNEL_5 (7) 01523 * @arg @ref LL_ADC_CHANNEL_6 01524 * @arg @ref LL_ADC_CHANNEL_7 01525 * @arg @ref LL_ADC_CHANNEL_8 01526 * @arg @ref LL_ADC_CHANNEL_9 01527 * @arg @ref LL_ADC_CHANNEL_10 01528 * @arg @ref LL_ADC_CHANNEL_11 01529 * @arg @ref LL_ADC_CHANNEL_12 01530 * @arg @ref LL_ADC_CHANNEL_13 01531 * @arg @ref LL_ADC_CHANNEL_14 01532 * @arg @ref LL_ADC_CHANNEL_15 01533 * @arg @ref LL_ADC_CHANNEL_16 01534 * @arg @ref LL_ADC_CHANNEL_17 01535 * @arg @ref LL_ADC_CHANNEL_18 01536 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01537 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 01538 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 01539 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 01540 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 01541 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01542 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01543 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01544 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01545 * 01546 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01547 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01548 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01549 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01550 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01551 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01552 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01553 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n 01554 * (1, 2, 3, 4) For ADC channel read back from ADC register, 01555 * comparison with internal channel parameter to be done 01556 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 01557 */ 01558 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 01559 (((__DECIMAL_NB__) <= 9U) \ 01560 ? ( \ 01561 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ 01562 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ 01563 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ 01564 ) \ 01565 : \ 01566 ( \ 01567 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ 01568 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ 01569 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ 01570 ) \ 01571 ) 01572 01573 /** 01574 * @brief Helper macro to determine whether the selected channel 01575 * corresponds to literal definitions of driver. 01576 * @note The different literal definitions of ADC channels are: 01577 * - ADC internal channel: 01578 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... 01579 * - ADC external channel (channel connected to a GPIO pin): 01580 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... 01581 * @note The channel parameter must be a value defined from literal 01582 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 01583 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 01584 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), 01585 * must not be a value from functions where a channel number is 01586 * returned from ADC registers, 01587 * because internal and external channels share the same channel 01588 * number in ADC registers. The differentiation is made only with 01589 * parameters definitions of driver. 01590 * @param __CHANNEL__ This parameter can be one of the following values: 01591 * @arg @ref LL_ADC_CHANNEL_0 01592 * @arg @ref LL_ADC_CHANNEL_1 (7) 01593 * @arg @ref LL_ADC_CHANNEL_2 (7) 01594 * @arg @ref LL_ADC_CHANNEL_3 (7) 01595 * @arg @ref LL_ADC_CHANNEL_4 (7) 01596 * @arg @ref LL_ADC_CHANNEL_5 (7) 01597 * @arg @ref LL_ADC_CHANNEL_6 01598 * @arg @ref LL_ADC_CHANNEL_7 01599 * @arg @ref LL_ADC_CHANNEL_8 01600 * @arg @ref LL_ADC_CHANNEL_9 01601 * @arg @ref LL_ADC_CHANNEL_10 01602 * @arg @ref LL_ADC_CHANNEL_11 01603 * @arg @ref LL_ADC_CHANNEL_12 01604 * @arg @ref LL_ADC_CHANNEL_13 01605 * @arg @ref LL_ADC_CHANNEL_14 01606 * @arg @ref LL_ADC_CHANNEL_15 01607 * @arg @ref LL_ADC_CHANNEL_16 01608 * @arg @ref LL_ADC_CHANNEL_17 01609 * @arg @ref LL_ADC_CHANNEL_18 01610 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01611 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 01612 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 01613 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 01614 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 01615 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01616 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01617 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01618 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01619 * 01620 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01621 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01622 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01623 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01624 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01625 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01626 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01627 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 01628 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 01629 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 01630 */ 01631 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 01632 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) 01633 01634 /** 01635 * @brief Helper macro to convert a channel defined from parameter 01636 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 01637 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 01638 * to its equivalent parameter definition of a ADC external channel 01639 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). 01640 * @note The channel parameter can be, additionally to a value 01641 * defined from parameter definition of a ADC internal channel 01642 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), 01643 * a value defined from parameter definition of 01644 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) 01645 * or a value from functions where a channel number is returned 01646 * from ADC registers. 01647 * @param __CHANNEL__ This parameter can be one of the following values: 01648 * @arg @ref LL_ADC_CHANNEL_0 01649 * @arg @ref LL_ADC_CHANNEL_1 (7) 01650 * @arg @ref LL_ADC_CHANNEL_2 (7) 01651 * @arg @ref LL_ADC_CHANNEL_3 (7) 01652 * @arg @ref LL_ADC_CHANNEL_4 (7) 01653 * @arg @ref LL_ADC_CHANNEL_5 (7) 01654 * @arg @ref LL_ADC_CHANNEL_6 01655 * @arg @ref LL_ADC_CHANNEL_7 01656 * @arg @ref LL_ADC_CHANNEL_8 01657 * @arg @ref LL_ADC_CHANNEL_9 01658 * @arg @ref LL_ADC_CHANNEL_10 01659 * @arg @ref LL_ADC_CHANNEL_11 01660 * @arg @ref LL_ADC_CHANNEL_12 01661 * @arg @ref LL_ADC_CHANNEL_13 01662 * @arg @ref LL_ADC_CHANNEL_14 01663 * @arg @ref LL_ADC_CHANNEL_15 01664 * @arg @ref LL_ADC_CHANNEL_16 01665 * @arg @ref LL_ADC_CHANNEL_17 01666 * @arg @ref LL_ADC_CHANNEL_18 01667 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01668 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 01669 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 01670 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 01671 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 01672 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01673 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01674 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01675 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01676 * 01677 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01678 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01679 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01680 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01681 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01682 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01683 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01684 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 01685 * @retval Returned value can be one of the following values: 01686 * @arg @ref LL_ADC_CHANNEL_0 01687 * @arg @ref LL_ADC_CHANNEL_1 01688 * @arg @ref LL_ADC_CHANNEL_2 01689 * @arg @ref LL_ADC_CHANNEL_3 01690 * @arg @ref LL_ADC_CHANNEL_4 01691 * @arg @ref LL_ADC_CHANNEL_5 01692 * @arg @ref LL_ADC_CHANNEL_6 01693 * @arg @ref LL_ADC_CHANNEL_7 01694 * @arg @ref LL_ADC_CHANNEL_8 01695 * @arg @ref LL_ADC_CHANNEL_9 01696 * @arg @ref LL_ADC_CHANNEL_10 01697 * @arg @ref LL_ADC_CHANNEL_11 01698 * @arg @ref LL_ADC_CHANNEL_12 01699 * @arg @ref LL_ADC_CHANNEL_13 01700 * @arg @ref LL_ADC_CHANNEL_14 01701 * @arg @ref LL_ADC_CHANNEL_15 01702 * @arg @ref LL_ADC_CHANNEL_16 01703 * @arg @ref LL_ADC_CHANNEL_17 01704 * @arg @ref LL_ADC_CHANNEL_18 01705 */ 01706 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 01707 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) 01708 01709 /** 01710 * @brief Helper macro to determine whether the internal channel 01711 * selected is available on the ADC instance selected. 01712 * @note The channel parameter must be a value defined from parameter 01713 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 01714 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 01715 * must not be a value defined from parameter definition of 01716 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) 01717 * or a value from functions where a channel number is 01718 * returned from ADC registers, 01719 * because internal and external channels share the same channel 01720 * number in ADC registers. The differentiation is made only with 01721 * parameters definitions of driver. 01722 * @param __ADC_INSTANCE__ ADC instance 01723 * @param __CHANNEL__ This parameter can be one of the following values: 01724 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01725 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 01726 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 01727 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 01728 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 01729 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01730 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01731 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01732 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01733 * 01734 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01735 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01736 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01737 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01738 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01739 * (6) On STM32L4, parameter available on devices with several ADC instances. 01740 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 01741 * Value "1" if the internal channel selected is available on the ADC instance selected. 01742 */ 01743 #if defined (ADC1) && defined (ADC2) && defined (ADC3) 01744 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 01745 (((__ADC_INSTANCE__) == ADC1) \ 01746 ? ( \ 01747 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ 01748 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ 01749 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \ 01750 ) \ 01751 : \ 01752 ((__ADC_INSTANCE__) == ADC2) \ 01753 ? ( \ 01754 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ 01755 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \ 01756 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \ 01757 ) \ 01758 : \ 01759 ((__ADC_INSTANCE__) == ADC3) \ 01760 ? ( \ 01761 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ 01762 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ 01763 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ 01764 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC3) || \ 01765 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC3) \ 01766 ) \ 01767 : \ 01768 (0U) \ 01769 ) 01770 #elif defined (ADC1) && defined (ADC2) 01771 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 01772 (((__ADC_INSTANCE__) == ADC1) \ 01773 ? ( \ 01774 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ 01775 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ 01776 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \ 01777 ) \ 01778 : \ 01779 ((__ADC_INSTANCE__) == ADC2) \ 01780 ? ( \ 01781 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ 01782 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \ 01783 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \ 01784 ) \ 01785 : \ 01786 (0U) \ 01787 ) 01788 #elif defined (ADC1) 01789 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 01790 ( \ 01791 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ 01792 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ 01793 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ 01794 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1) || \ 01795 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2) \ 01796 ) 01797 #endif 01798 01799 /** 01800 * @brief Helper macro to define ADC analog watchdog parameter: 01801 * define a single channel to monitor with analog watchdog 01802 * from sequencer channel and groups definition. 01803 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). 01804 * Example: 01805 * LL_ADC_SetAnalogWDMonitChannels( 01806 * ADC1, LL_ADC_AWD1, 01807 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) 01808 * @param __CHANNEL__ This parameter can be one of the following values: 01809 * @arg @ref LL_ADC_CHANNEL_0 01810 * @arg @ref LL_ADC_CHANNEL_1 (7) 01811 * @arg @ref LL_ADC_CHANNEL_2 (7) 01812 * @arg @ref LL_ADC_CHANNEL_3 (7) 01813 * @arg @ref LL_ADC_CHANNEL_4 (7) 01814 * @arg @ref LL_ADC_CHANNEL_5 (7) 01815 * @arg @ref LL_ADC_CHANNEL_6 01816 * @arg @ref LL_ADC_CHANNEL_7 01817 * @arg @ref LL_ADC_CHANNEL_8 01818 * @arg @ref LL_ADC_CHANNEL_9 01819 * @arg @ref LL_ADC_CHANNEL_10 01820 * @arg @ref LL_ADC_CHANNEL_11 01821 * @arg @ref LL_ADC_CHANNEL_12 01822 * @arg @ref LL_ADC_CHANNEL_13 01823 * @arg @ref LL_ADC_CHANNEL_14 01824 * @arg @ref LL_ADC_CHANNEL_15 01825 * @arg @ref LL_ADC_CHANNEL_16 01826 * @arg @ref LL_ADC_CHANNEL_17 01827 * @arg @ref LL_ADC_CHANNEL_18 01828 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01829 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 01830 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 01831 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 01832 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 01833 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01834 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01835 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01836 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01837 * 01838 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01839 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01840 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01841 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01842 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01843 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01844 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01845 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n 01846 * (1, 2, 3, 4) For ADC channel read back from ADC register, 01847 * comparison with internal channel parameter to be done 01848 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 01849 * @param __GROUP__ This parameter can be one of the following values: 01850 * @arg @ref LL_ADC_GROUP_REGULAR 01851 * @arg @ref LL_ADC_GROUP_INJECTED 01852 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED 01853 * @retval Returned value can be one of the following values: 01854 * @arg @ref LL_ADC_AWD_DISABLE 01855 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) 01856 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) 01857 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 01858 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) 01859 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) 01860 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 01861 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) 01862 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) 01863 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 01864 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) 01865 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) 01866 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 01867 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) 01868 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) 01869 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 01870 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) 01871 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) 01872 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 01873 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) 01874 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) 01875 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 01876 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) 01877 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) 01878 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 01879 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) 01880 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) 01881 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 01882 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) 01883 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) 01884 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 01885 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) 01886 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) 01887 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 01888 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) 01889 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) 01890 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 01891 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) 01892 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) 01893 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 01894 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) 01895 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) 01896 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 01897 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) 01898 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) 01899 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 01900 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) 01901 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) 01902 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 01903 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) 01904 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) 01905 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 01906 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) 01907 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) 01908 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 01909 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) 01910 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) 01911 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 01912 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) 01913 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) 01914 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ 01915 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1) 01916 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1) 01917 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) 01918 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4) 01919 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(4) 01920 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4) 01921 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(4) 01922 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(4) 01923 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (4) 01924 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG (0)(2)(5) 01925 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ (0)(2)(5) 01926 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ (2)(5) 01927 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG (0)(2)(5) 01928 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ (0)(2)(5) 01929 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ (2)(5) 01930 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)(6) 01931 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)(6) 01932 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)(6) 01933 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)(6) 01934 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)(6) 01935 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)(6) 01936 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)(6) 01937 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)(6) 01938 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)(6) 01939 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6) 01940 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6) 01941 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6) 01942 * 01943 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n 01944 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01945 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01946 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01947 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3. 01948 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01949 * (6) On STM32L4, parameter available on devices with several ADC instances. 01950 */ 01951 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ 01952 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ 01953 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ 01954 : \ 01955 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ 01956 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \ 01957 : \ 01958 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ 01959 ) 01960 01961 /** 01962 * @brief Helper macro to set the value of ADC analog watchdog threshold high 01963 * or low in function of ADC resolution, when ADC resolution is 01964 * different of 12 bits. 01965 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds() 01966 * or @ref LL_ADC_SetAnalogWDThresholds(). 01967 * Example, with a ADC resolution of 8 bits, to set the value of 01968 * analog watchdog threshold high (on 8 bits): 01969 * LL_ADC_SetAnalogWDThresholds 01970 * (< ADCx param >, 01971 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>) 01972 * ); 01973 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01974 * @arg @ref LL_ADC_RESOLUTION_12B 01975 * @arg @ref LL_ADC_RESOLUTION_10B 01976 * @arg @ref LL_ADC_RESOLUTION_8B 01977 * @arg @ref LL_ADC_RESOLUTION_6B 01978 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF 01979 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01980 */ 01981 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ 01982 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) 01983 01984 /** 01985 * @brief Helper macro to get the value of ADC analog watchdog threshold high 01986 * or low in function of ADC resolution, when ADC resolution is 01987 * different of 12 bits. 01988 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). 01989 * Example, with a ADC resolution of 8 bits, to get the value of 01990 * analog watchdog threshold high (on 8 bits): 01991 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION 01992 * (LL_ADC_RESOLUTION_8B, 01993 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH) 01994 * ); 01995 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01996 * @arg @ref LL_ADC_RESOLUTION_12B 01997 * @arg @ref LL_ADC_RESOLUTION_10B 01998 * @arg @ref LL_ADC_RESOLUTION_8B 01999 * @arg @ref LL_ADC_RESOLUTION_6B 02000 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF 02001 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 02002 */ 02003 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ 02004 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) 02005 02006 /** 02007 * @brief Helper macro to get the ADC analog watchdog threshold high 02008 * or low from raw value containing both thresholds concatenated. 02009 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). 02010 * Example, to get analog watchdog threshold high from the register raw value: 02011 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>); 02012 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values: 02013 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH 02014 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW 02015 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 02016 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 02017 */ 02018 #if defined(CORE_CM0PLUS) 02019 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ 02020 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW) 02021 #else 02022 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ 02023 (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW) 02024 #endif 02025 02026 /** 02027 * @brief Helper macro to set the ADC calibration value with both single ended 02028 * and differential modes calibration factors concatenated. 02029 * @note To be used with function @ref LL_ADC_SetCalibrationFactor(). 02030 * Example, to set calibration factors single ended to 0x55 02031 * and differential ended to 0x2A: 02032 * LL_ADC_SetCalibrationFactor( 02033 * ADC1, 02034 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A)) 02035 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F 02036 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F 02037 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 02038 */ 02039 #if defined(CORE_CM0PLUS) 02040 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \ 02041 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__)) 02042 #else 02043 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \ 02044 (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__)) 02045 #endif 02046 02047 #if defined(ADC_MULTIMODE_SUPPORT) 02048 /** 02049 * @brief Helper macro to get the ADC multimode conversion data of ADC master 02050 * or ADC slave from raw value with both ADC conversion data concatenated. 02051 * @note This macro is intended to be used when multimode transfer by DMA 02052 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 02053 * In this case the transferred data need to processed with this macro 02054 * to separate the conversion data of ADC master and ADC slave. 02055 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 02056 * @arg @ref LL_ADC_MULTI_MASTER 02057 * @arg @ref LL_ADC_MULTI_SLAVE 02058 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 02059 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 02060 */ 02061 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 02062 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) 02063 #endif 02064 02065 /** 02066 * @brief Helper macro to select the ADC common instance 02067 * to which is belonging the selected ADC instance. 02068 * @note ADC common register instance can be used for: 02069 * - Set parameters common to several ADC instances 02070 * - Multimode (for devices with several ADC instances) 02071 * Refer to functions having argument "ADCxy_COMMON" as parameter. 02072 * @param __ADCx__ ADC instance 02073 * @retval ADC common register instance 02074 */ 02075 #if defined(ADC1) && defined(ADC2) && defined(ADC3) 02076 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 02077 (ADC123_COMMON) 02078 #elif defined(ADC1) && defined(ADC2) 02079 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 02080 (ADC12_COMMON) 02081 #else 02082 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 02083 (ADC1_COMMON) 02084 #endif 02085 02086 /** 02087 * @brief Helper macro to check if all ADC instances sharing the same 02088 * ADC common instance are disabled. 02089 * @note This check is required by functions with setting conditioned to 02090 * ADC state: 02091 * All ADC instances of the ADC common group must be disabled. 02092 * Refer to functions having argument "ADCxy_COMMON" as parameter. 02093 * @note On devices with only 1 ADC common instance, parameter of this macro 02094 * is useless and can be ignored (parameter kept for compatibility 02095 * with devices featuring several ADC common instances). 02096 * @param __ADCXY_COMMON__ ADC common instance 02097 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 02098 * @retval Value "0" if all ADC instances sharing the same ADC common instance 02099 * are disabled. 02100 * Value "1" if at least one ADC instance sharing the same ADC common instance 02101 * is enabled. 02102 */ 02103 #if defined(ADC1) && defined(ADC2) && defined(ADC3) 02104 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 02105 (LL_ADC_IsEnabled(ADC1) | \ 02106 LL_ADC_IsEnabled(ADC2) | \ 02107 LL_ADC_IsEnabled(ADC3) ) 02108 #elif defined(ADC1) && defined(ADC2) 02109 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 02110 (LL_ADC_IsEnabled(ADC1) | \ 02111 LL_ADC_IsEnabled(ADC2) ) 02112 #else 02113 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 02114 (LL_ADC_IsEnabled(ADC1)) 02115 #endif 02116 02117 /** 02118 * @brief Helper macro to define the ADC conversion data full-scale digital 02119 * value corresponding to the selected ADC resolution. 02120 * @note ADC conversion data full-scale corresponds to voltage range 02121 * determined by analog voltage references Vref+ and Vref- 02122 * (refer to reference manual). 02123 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 02124 * @arg @ref LL_ADC_RESOLUTION_12B 02125 * @arg @ref LL_ADC_RESOLUTION_10B 02126 * @arg @ref LL_ADC_RESOLUTION_8B 02127 * @arg @ref LL_ADC_RESOLUTION_6B 02128 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 02129 */ 02130 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 02131 (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))) 02132 02133 /** 02134 * @brief Helper macro to convert the ADC conversion data from 02135 * a resolution to another resolution. 02136 * @param __DATA__ ADC conversion data to be converted 02137 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted 02138 * This parameter can be one of the following values: 02139 * @arg @ref LL_ADC_RESOLUTION_12B 02140 * @arg @ref LL_ADC_RESOLUTION_10B 02141 * @arg @ref LL_ADC_RESOLUTION_8B 02142 * @arg @ref LL_ADC_RESOLUTION_6B 02143 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 02144 * This parameter can be one of the following values: 02145 * @arg @ref LL_ADC_RESOLUTION_12B 02146 * @arg @ref LL_ADC_RESOLUTION_10B 02147 * @arg @ref LL_ADC_RESOLUTION_8B 02148 * @arg @ref LL_ADC_RESOLUTION_6B 02149 * @retval ADC conversion data to the requested resolution 02150 */ 02151 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 02152 __ADC_RESOLUTION_CURRENT__,\ 02153 __ADC_RESOLUTION_TARGET__) \ 02154 (((__DATA__) \ 02155 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))) \ 02156 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)) \ 02157 ) 02158 02159 /** 02160 * @brief Helper macro to calculate the voltage (unit: mVolt) 02161 * corresponding to a ADC conversion data (unit: digital value). 02162 * @note Analog reference voltage (Vref+) must be either known from 02163 * user board environment or can be calculated using ADC measurement 02164 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 02165 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 02166 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 02167 * (unit: digital value). 02168 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 02169 * @arg @ref LL_ADC_RESOLUTION_12B 02170 * @arg @ref LL_ADC_RESOLUTION_10B 02171 * @arg @ref LL_ADC_RESOLUTION_8B 02172 * @arg @ref LL_ADC_RESOLUTION_6B 02173 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 02174 */ 02175 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 02176 __ADC_DATA__,\ 02177 __ADC_RESOLUTION__) \ 02178 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ 02179 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 02180 ) 02181 02182 /* Legacy define */ 02183 #define __LL_ADC_CALC_DATA_VOLTAGE() __LL_ADC_CALC_DATA_TO_VOLTAGE() 02184 02185 /** 02186 * @brief Helper macro to calculate analog reference voltage (Vref+) 02187 * (unit: mVolt) from ADC conversion data of internal voltage 02188 * reference VrefInt. 02189 * @note Computation is using VrefInt calibration value 02190 * stored in system memory for each device during production. 02191 * @note This voltage depends on user board environment: voltage level 02192 * connected to pin Vref+. 02193 * On devices with small package, the pin Vref+ is not present 02194 * and internally bonded to pin Vdda. 02195 * @note On this STM32 serie, calibration data of internal voltage reference 02196 * VrefInt corresponds to a resolution of 12 bits, 02197 * this is the recommended ADC resolution to convert voltage of 02198 * internal voltage reference VrefInt. 02199 * Otherwise, this macro performs the processing to scale 02200 * ADC conversion data to 12 bits. 02201 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 02202 * of internal voltage reference VrefInt (unit: digital value). 02203 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 02204 * @arg @ref LL_ADC_RESOLUTION_12B 02205 * @arg @ref LL_ADC_RESOLUTION_10B 02206 * @arg @ref LL_ADC_RESOLUTION_8B 02207 * @arg @ref LL_ADC_RESOLUTION_6B 02208 * @retval Analog reference voltage (unit: mV) 02209 */ 02210 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 02211 __ADC_RESOLUTION__) \ 02212 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ 02213 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ 02214 (__ADC_RESOLUTION__), \ 02215 LL_ADC_RESOLUTION_12B) \ 02216 ) 02217 02218 /** 02219 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 02220 * from ADC conversion data of internal temperature sensor. 02221 * @note Computation is using temperature sensor calibration values 02222 * stored in system memory for each device during production. 02223 * @note Calculation formula: 02224 * Temperature = ((TS_ADC_DATA - TS_CAL1) 02225 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 02226 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 02227 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 02228 * Avg_Slope = (TS_CAL2 - TS_CAL1) 02229 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 02230 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 02231 * TEMP_DEGC_CAL1 (calibrated in factory) 02232 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 02233 * TEMP_DEGC_CAL2 (calibrated in factory) 02234 * Caution: Calculation relevancy under reserve that calibration 02235 * parameters are correct (address and data). 02236 * To calculate temperature using temperature sensor 02237 * datasheet typical values (generic values less, therefore 02238 * less accurate than calibrated values), 02239 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 02240 * @note As calculation input, the analog reference voltage (Vref+) must be 02241 * defined as it impacts the ADC LSB equivalent voltage. 02242 * @note Analog reference voltage (Vref+) must be either known from 02243 * user board environment or can be calculated using ADC measurement 02244 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 02245 * @note On this STM32 serie, calibration data of temperature sensor 02246 * corresponds to a resolution of 12 bits, 02247 * this is the recommended ADC resolution to convert voltage of 02248 * temperature sensor. 02249 * Otherwise, this macro performs the processing to scale 02250 * ADC conversion data to 12 bits. 02251 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 02252 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 02253 * temperature sensor (unit: digital value). 02254 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 02255 * sensor voltage has been measured. 02256 * This parameter can be one of the following values: 02257 * @arg @ref LL_ADC_RESOLUTION_12B 02258 * @arg @ref LL_ADC_RESOLUTION_10B 02259 * @arg @ref LL_ADC_RESOLUTION_8B 02260 * @arg @ref LL_ADC_RESOLUTION_6B 02261 * @retval Temperature (unit: degree Celsius) 02262 */ 02263 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 02264 __TEMPSENSOR_ADC_DATA__,\ 02265 __ADC_RESOLUTION__) \ 02266 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ 02267 (__ADC_RESOLUTION__), \ 02268 LL_ADC_RESOLUTION_12B) \ 02269 * (__VREFANALOG_VOLTAGE__)) \ 02270 / TEMPSENSOR_CAL_VREFANALOG) \ 02271 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ 02272 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ 02273 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ 02274 ) + TEMPSENSOR_CAL1_TEMP \ 02275 ) 02276 02277 /** 02278 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 02279 * from ADC conversion data of internal temperature sensor. 02280 * @note Computation is using temperature sensor typical values 02281 * (refer to device datasheet). 02282 * @note Calculation formula: 02283 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 02284 * / Avg_Slope + CALx_TEMP 02285 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 02286 * (unit: digital value) 02287 * Avg_Slope = temperature sensor slope 02288 * (unit: uV/Degree Celsius) 02289 * TS_TYP_CALx_VOLT = temperature sensor digital value at 02290 * temperature CALx_TEMP (unit: mV) 02291 * Caution: Calculation relevancy under reserve the temperature sensor 02292 * of the current device has characteristics in line with 02293 * datasheet typical values. 02294 * If temperature sensor calibration values are available on 02295 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 02296 * temperature calculation will be more accurate using 02297 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 02298 * @note As calculation input, the analog reference voltage (Vref+) must be 02299 * defined as it impacts the ADC LSB equivalent voltage. 02300 * @note Analog reference voltage (Vref+) must be either known from 02301 * user board environment or can be calculated using ADC measurement 02302 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 02303 * @note ADC measurement data must correspond to a resolution of 12 bits 02304 * (full scale digital value 4095). If not the case, the data must be 02305 * preliminarily rescaled to an equivalent resolution of 12 bits. 02306 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). 02307 * On STM32L4, refer to device datasheet parameter "Avg_Slope". 02308 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). 02309 * On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). 02310 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) 02311 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 02312 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 02313 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 02314 * This parameter can be one of the following values: 02315 * @arg @ref LL_ADC_RESOLUTION_12B 02316 * @arg @ref LL_ADC_RESOLUTION_10B 02317 * @arg @ref LL_ADC_RESOLUTION_8B 02318 * @arg @ref LL_ADC_RESOLUTION_6B 02319 * @retval Temperature (unit: degree Celsius) 02320 */ 02321 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 02322 __TEMPSENSOR_TYP_CALX_V__,\ 02323 __TEMPSENSOR_CALX_TEMP__,\ 02324 __VREFANALOG_VOLTAGE__,\ 02325 __TEMPSENSOR_ADC_DATA__,\ 02326 __ADC_RESOLUTION__) \ 02327 ((( ( \ 02328 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ 02329 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ 02330 * 1000) \ 02331 - \ 02332 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ 02333 * 1000) \ 02334 ) \ 02335 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ 02336 ) + (__TEMPSENSOR_CALX_TEMP__) \ 02337 ) 02338 02339 /** 02340 * @} 02341 */ 02342 02343 /** 02344 * @} 02345 */ 02346 02347 02348 /* Exported functions --------------------------------------------------------*/ 02349 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions 02350 * @{ 02351 */ 02352 02353 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management 02354 * @{ 02355 */ 02356 /* Note: LL ADC functions to set DMA transfer are located into sections of */ 02357 /* configuration of ADC instance, groups and multimode (if available): */ 02358 /* @ref LL_ADC_REG_SetDMATransfer(), ... */ 02359 02360 /** 02361 * @brief Function to help to configure DMA transfer from ADC: retrieve the 02362 * ADC register address from ADC instance and a list of ADC registers 02363 * intended to be used (most commonly) with DMA transfer. 02364 * @note These ADC registers are data registers: 02365 * when ADC conversion data is available in ADC data registers, 02366 * ADC generates a DMA transfer request. 02367 * @note This macro is intended to be used with LL DMA driver, refer to 02368 * function "LL_DMA_ConfigAddresses()". 02369 * Example: 02370 * LL_DMA_ConfigAddresses(DMA1, 02371 * LL_DMA_CHANNEL_1, 02372 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), 02373 * (uint32_t)&< array or variable >, 02374 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); 02375 * @note For devices with several ADC: in multimode, some devices 02376 * use a different data register outside of ADC instance scope 02377 * (common data register). This macro manages this register difference, 02378 * only ADC instance has to be set as parameter. 02379 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n 02380 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n 02381 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr 02382 * @param ADCx ADC instance 02383 * @param Register This parameter can be one of the following values: 02384 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA 02385 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) 02386 * 02387 * (1) Available on devices with several ADC instances. 02388 * @retval ADC register address 02389 */ 02390 #if defined(ADC_MULTIMODE_SUPPORT) 02391 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) 02392 { 02393 register uint32_t data_reg_addr = 0U; 02394 02395 if (Register == LL_ADC_DMA_REG_REGULAR_DATA) 02396 { 02397 /* Retrieve address of register DR */ 02398 data_reg_addr = (uint32_t)&(ADCx->DR); 02399 } 02400 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ 02401 { 02402 /* Retrieve address of register CDR */ 02403 data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); 02404 } 02405 02406 return data_reg_addr; 02407 } 02408 #else 02409 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) 02410 { 02411 /* Prevent unused argument(s) compilation warning */ 02412 (void)(Register); 02413 02414 /* Retrieve address of register DR */ 02415 return (uint32_t)&(ADCx->DR); 02416 } 02417 #endif 02418 02419 /** 02420 * @} 02421 */ 02422 02423 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances 02424 * @{ 02425 */ 02426 02427 /** 02428 * @brief Set parameter common to several ADC: Clock source and prescaler. 02429 * @note On this STM32 serie, if ADC group injected is used, some 02430 * clock ratio constraints between ADC clock and AHB clock 02431 * must be respected. 02432 * Refer to reference manual. 02433 * @note On this STM32 serie, setting of this feature is conditioned to 02434 * ADC state: 02435 * All ADC instances of the ADC common group must be disabled. 02436 * This check can be done with function @ref LL_ADC_IsEnabled() for each 02437 * ADC instance or by using helper macro helper macro 02438 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). 02439 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n 02440 * CCR PRESC LL_ADC_SetCommonClock 02441 * @param ADCxy_COMMON ADC common instance 02442 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 02443 * @param CommonClock This parameter can be one of the following values: 02444 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 02445 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 02446 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 02447 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 02448 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 02449 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 02450 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 02451 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 02452 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 02453 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 02454 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 02455 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 02456 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 02457 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 02458 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 02459 * @retval None 02460 */ 02461 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) 02462 { 02463 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); 02464 } 02465 02466 /** 02467 * @brief Get parameter common to several ADC: Clock source and prescaler. 02468 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n 02469 * CCR PRESC LL_ADC_GetCommonClock 02470 * @param ADCxy_COMMON ADC common instance 02471 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 02472 * @retval Returned value can be one of the following values: 02473 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 02474 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 02475 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 02476 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 02477 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 02478 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 02479 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 02480 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 02481 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 02482 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 02483 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 02484 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 02485 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 02486 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 02487 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 02488 */ 02489 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) 02490 { 02491 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC)); 02492 } 02493 02494 /** 02495 * @brief Set parameter common to several ADC: measurement path to internal 02496 * channels (VrefInt, temperature sensor, ...). 02497 * @note One or several values can be selected. 02498 * Example: (LL_ADC_PATH_INTERNAL_VREFINT | 02499 * LL_ADC_PATH_INTERNAL_TEMPSENSOR) 02500 * @note Stabilization time of measurement path to internal channel: 02501 * After enabling internal paths, before starting ADC conversion, 02502 * a delay is required for internal voltage reference and 02503 * temperature sensor stabilization time. 02504 * Refer to device datasheet. 02505 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. 02506 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. 02507 * @note ADC internal channel sampling time constraint: 02508 * For ADC conversion of internal channels, 02509 * a sampling time minimum value is required. 02510 * Refer to device datasheet. 02511 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n 02512 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n 02513 * CCR VBATEN LL_ADC_SetCommonPathInternalCh 02514 * @param ADCxy_COMMON ADC common instance 02515 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 02516 * @param PathInternal This parameter can be a combination of the following values: 02517 * @arg @ref LL_ADC_PATH_INTERNAL_NONE 02518 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT 02519 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR 02520 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT 02521 * @retval None 02522 */ 02523 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) 02524 { 02525 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); 02526 } 02527 02528 /** 02529 * @brief Get parameter common to several ADC: measurement path to internal 02530 * channels (VrefInt, temperature sensor, ...). 02531 * @note One or several values can be selected. 02532 * Example: (LL_ADC_PATH_INTERNAL_VREFINT | 02533 * LL_ADC_PATH_INTERNAL_TEMPSENSOR) 02534 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n 02535 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n 02536 * CCR VBATEN LL_ADC_GetCommonPathInternalCh 02537 * @param ADCxy_COMMON ADC common instance 02538 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 02539 * @retval Returned value can be a combination of the following values: 02540 * @arg @ref LL_ADC_PATH_INTERNAL_NONE 02541 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT 02542 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR 02543 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT 02544 */ 02545 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) 02546 { 02547 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 02548 } 02549 02550 /** 02551 * @} 02552 */ 02553 02554 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance 02555 * @{ 02556 */ 02557 02558 /** 02559 * @brief Set ADC calibration factor in the mode single-ended 02560 * or differential (for devices with differential mode available). 02561 * @note This function is intended to set calibration parameters 02562 * without having to perform a new calibration using 02563 * @ref LL_ADC_StartCalibration(). 02564 * @note For devices with differential mode available: 02565 * Calibration of offset is specific to each of 02566 * single-ended and differential modes 02567 * (calibration factor must be specified for each of these 02568 * differential modes, if used afterwards and if the application 02569 * requires their calibration). 02570 * @note In case of setting calibration factors of both modes single ended 02571 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED): 02572 * both calibration factors must be concatenated. 02573 * To perform this processing, use helper macro 02574 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(). 02575 * @note On this STM32 serie, setting of this feature is conditioned to 02576 * ADC state: 02577 * ADC must be enabled, without calibration on going, without conversion 02578 * on going on group regular. 02579 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n 02580 * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor 02581 * @param ADCx ADC instance 02582 * @param SingleDiff This parameter can be one of the following values: 02583 * @arg @ref LL_ADC_SINGLE_ENDED 02584 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED 02585 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED 02586 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F 02587 * @retval None 02588 */ 02589 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor) 02590 { 02591 #if defined(CORE_CM0PLUS) 02592 MODIFY_REG(ADCx->CALFACT, 02593 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, 02594 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S))); 02595 #else 02596 MODIFY_REG(ADCx->CALFACT, 02597 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, 02598 CalibrationFactor << POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)); 02599 #endif 02600 } 02601 02602 /** 02603 * @brief Get ADC calibration factor in the mode single-ended 02604 * or differential (for devices with differential mode available). 02605 * @note Calibration factors are set by hardware after performing 02606 * a calibration run using function @ref LL_ADC_StartCalibration(). 02607 * @note For devices with differential mode available: 02608 * Calibration of offset is specific to each of 02609 * single-ended and differential modes 02610 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n 02611 * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor 02612 * @param ADCx ADC instance 02613 * @param SingleDiff This parameter can be one of the following values: 02614 * @arg @ref LL_ADC_SINGLE_ENDED 02615 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED 02616 * @retval Value between Min_Data=0x00 and Max_Data=0x7F 02617 */ 02618 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff) 02619 { 02620 /* Retrieve bits with position in register depending on parameter */ 02621 /* "SingleDiff". */ 02622 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ 02623 /* containing other bits reserved for other purpose. */ 02624 #if defined(CORE_CM0PLUS) 02625 return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); 02626 #else 02627 return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)); 02628 #endif 02629 } 02630 02631 /** 02632 * @brief Set ADC resolution. 02633 * Refer to reference manual for alignments formats 02634 * dependencies to ADC resolutions. 02635 * @note On this STM32 serie, setting of this feature is conditioned to 02636 * ADC state: 02637 * ADC must be disabled or enabled without conversion on going 02638 * on either groups regular or injected. 02639 * @rmtoll CFGR RES LL_ADC_SetResolution 02640 * @param ADCx ADC instance 02641 * @param Resolution This parameter can be one of the following values: 02642 * @arg @ref LL_ADC_RESOLUTION_12B 02643 * @arg @ref LL_ADC_RESOLUTION_10B 02644 * @arg @ref LL_ADC_RESOLUTION_8B 02645 * @arg @ref LL_ADC_RESOLUTION_6B 02646 * @retval None 02647 */ 02648 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) 02649 { 02650 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution); 02651 } 02652 02653 /** 02654 * @brief Get ADC resolution. 02655 * Refer to reference manual for alignments formats 02656 * dependencies to ADC resolutions. 02657 * @rmtoll CFGR RES LL_ADC_GetResolution 02658 * @param ADCx ADC instance 02659 * @retval Returned value can be one of the following values: 02660 * @arg @ref LL_ADC_RESOLUTION_12B 02661 * @arg @ref LL_ADC_RESOLUTION_10B 02662 * @arg @ref LL_ADC_RESOLUTION_8B 02663 * @arg @ref LL_ADC_RESOLUTION_6B 02664 */ 02665 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) 02666 { 02667 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)); 02668 } 02669 02670 /** 02671 * @brief Set ADC conversion data alignment. 02672 * @note Refer to reference manual for alignments formats 02673 * dependencies to ADC resolutions. 02674 * @note On this STM32 serie, setting of this feature is conditioned to 02675 * ADC state: 02676 * ADC must be disabled or enabled without conversion on going 02677 * on either groups regular or injected. 02678 * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment 02679 * @param ADCx ADC instance 02680 * @param DataAlignment This parameter can be one of the following values: 02681 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT 02682 * @arg @ref LL_ADC_DATA_ALIGN_LEFT 02683 * @retval None 02684 */ 02685 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) 02686 { 02687 MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment); 02688 } 02689 02690 /** 02691 * @brief Get ADC conversion data alignment. 02692 * @note Refer to reference manual for alignments formats 02693 * dependencies to ADC resolutions. 02694 * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment 02695 * @param ADCx ADC instance 02696 * @retval Returned value can be one of the following values: 02697 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT 02698 * @arg @ref LL_ADC_DATA_ALIGN_LEFT 02699 */ 02700 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) 02701 { 02702 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN)); 02703 } 02704 02705 /** 02706 * @brief Set ADC low power mode. 02707 * @note Description of ADC low power modes: 02708 * - ADC low power mode "auto wait": Dynamic low power mode, 02709 * ADC conversions occurrences are limited to the minimum necessary 02710 * in order to reduce power consumption. 02711 * New ADC conversion starts only when the previous 02712 * unitary conversion data (for ADC group regular) 02713 * or previous sequence conversions data (for ADC group injected) 02714 * has been retrieved by user software. 02715 * In the meantime, ADC remains idle: does not performs any 02716 * other conversion. 02717 * This mode allows to automatically adapt the ADC conversions 02718 * triggers to the speed of the software that reads the data. 02719 * Moreover, this avoids risk of overrun for low frequency 02720 * applications. 02721 * How to use this low power mode: 02722 * - Do not use with interruption or DMA since these modes 02723 * have to clear immediately the EOC flag to free the 02724 * IRQ vector sequencer. 02725 * - Do use with polling: 1. Start conversion, 02726 * 2. Later on, when conversion data is needed: poll for end of 02727 * conversion to ensure that conversion is completed and 02728 * retrieve ADC conversion data. This will trig another 02729 * ADC conversion start. 02730 * - ADC low power mode "auto power-off" (feature available on 02731 * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available): 02732 * the ADC automatically powers-off after a conversion and 02733 * automatically wakes up when a new conversion is triggered 02734 * (with startup time between trigger and start of sampling). 02735 * This feature can be combined with low power mode "auto wait". 02736 * @note With ADC low power mode "auto wait", the ADC conversion data read 02737 * is corresponding to previous ADC conversion start, independently 02738 * of delay during which ADC was idle. 02739 * Therefore, the ADC conversion data may be outdated: does not 02740 * correspond to the current voltage level on the selected 02741 * ADC channel. 02742 * @note On this STM32 serie, setting of this feature is conditioned to 02743 * ADC state: 02744 * ADC must be disabled or enabled without conversion on going 02745 * on either groups regular or injected. 02746 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode 02747 * @param ADCx ADC instance 02748 * @param LowPowerMode This parameter can be one of the following values: 02749 * @arg @ref LL_ADC_LP_MODE_NONE 02750 * @arg @ref LL_ADC_LP_AUTOWAIT 02751 * @retval None 02752 */ 02753 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode) 02754 { 02755 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode); 02756 } 02757 02758 /** 02759 * @brief Get ADC low power mode: 02760 * @note Description of ADC low power modes: 02761 * - ADC low power mode "auto wait": Dynamic low power mode, 02762 * ADC conversions occurrences are limited to the minimum necessary 02763 * in order to reduce power consumption. 02764 * New ADC conversion starts only when the previous 02765 * unitary conversion data (for ADC group regular) 02766 * or previous sequence conversions data (for ADC group injected) 02767 * has been retrieved by user software. 02768 * In the meantime, ADC remains idle: does not performs any 02769 * other conversion. 02770 * This mode allows to automatically adapt the ADC conversions 02771 * triggers to the speed of the software that reads the data. 02772 * Moreover, this avoids risk of overrun for low frequency 02773 * applications. 02774 * How to use this low power mode: 02775 * - Do not use with interruption or DMA since these modes 02776 * have to clear immediately the EOC flag to free the 02777 * IRQ vector sequencer. 02778 * - Do use with polling: 1. Start conversion, 02779 * 2. Later on, when conversion data is needed: poll for end of 02780 * conversion to ensure that conversion is completed and 02781 * retrieve ADC conversion data. This will trig another 02782 * ADC conversion start. 02783 * - ADC low power mode "auto power-off" (feature available on 02784 * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available): 02785 * the ADC automatically powers-off after a conversion and 02786 * automatically wakes up when a new conversion is triggered 02787 * (with startup time between trigger and start of sampling). 02788 * This feature can be combined with low power mode "auto wait". 02789 * @note With ADC low power mode "auto wait", the ADC conversion data read 02790 * is corresponding to previous ADC conversion start, independently 02791 * of delay during which ADC was idle. 02792 * Therefore, the ADC conversion data may be outdated: does not 02793 * correspond to the current voltage level on the selected 02794 * ADC channel. 02795 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode 02796 * @param ADCx ADC instance 02797 * @retval Returned value can be one of the following values: 02798 * @arg @ref LL_ADC_LP_MODE_NONE 02799 * @arg @ref LL_ADC_LP_AUTOWAIT 02800 */ 02801 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) 02802 { 02803 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY)); 02804 } 02805 02806 /** 02807 * @brief Set ADC selected offset number 1, 2, 3 or 4. 02808 * @note This function set the 2 items of offset configuration: 02809 * - ADC channel to which the offset programmed will be applied 02810 * (independently of channel mapped on ADC group regular 02811 * or group injected) 02812 * - Offset level (offset to be subtracted from the raw 02813 * converted data). 02814 * @note Caution: Offset format is dependent to ADC resolution: 02815 * offset has to be left-aligned on bit 11, the LSB (right bits) 02816 * are set to 0. 02817 * @note This function enables the offset, by default. It can be forced 02818 * to disable state using function LL_ADC_SetOffsetState(). 02819 * @note If a channel is mapped on several offsets numbers, only the offset 02820 * with the lowest value is considered for the subtraction. 02821 * @note On this STM32 serie, setting of this feature is conditioned to 02822 * ADC state: 02823 * ADC must be disabled or enabled without conversion on going 02824 * on either groups regular or injected. 02825 * @note On STM32L4, some fast channels are available: fast analog inputs 02826 * coming from GPIO pads (ADC_IN1..5). 02827 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n 02828 * OFR1 OFFSET1 LL_ADC_SetOffset\n 02829 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n 02830 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n 02831 * OFR2 OFFSET2 LL_ADC_SetOffset\n 02832 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n 02833 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n 02834 * OFR3 OFFSET3 LL_ADC_SetOffset\n 02835 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n 02836 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n 02837 * OFR4 OFFSET4 LL_ADC_SetOffset\n 02838 * OFR4 OFFSET4_EN LL_ADC_SetOffset 02839 * @param ADCx ADC instance 02840 * @param Offsety This parameter can be one of the following values: 02841 * @arg @ref LL_ADC_OFFSET_1 02842 * @arg @ref LL_ADC_OFFSET_2 02843 * @arg @ref LL_ADC_OFFSET_3 02844 * @arg @ref LL_ADC_OFFSET_4 02845 * @param Channel This parameter can be one of the following values: 02846 * @arg @ref LL_ADC_CHANNEL_0 02847 * @arg @ref LL_ADC_CHANNEL_1 (7) 02848 * @arg @ref LL_ADC_CHANNEL_2 (7) 02849 * @arg @ref LL_ADC_CHANNEL_3 (7) 02850 * @arg @ref LL_ADC_CHANNEL_4 (7) 02851 * @arg @ref LL_ADC_CHANNEL_5 (7) 02852 * @arg @ref LL_ADC_CHANNEL_6 02853 * @arg @ref LL_ADC_CHANNEL_7 02854 * @arg @ref LL_ADC_CHANNEL_8 02855 * @arg @ref LL_ADC_CHANNEL_9 02856 * @arg @ref LL_ADC_CHANNEL_10 02857 * @arg @ref LL_ADC_CHANNEL_11 02858 * @arg @ref LL_ADC_CHANNEL_12 02859 * @arg @ref LL_ADC_CHANNEL_13 02860 * @arg @ref LL_ADC_CHANNEL_14 02861 * @arg @ref LL_ADC_CHANNEL_15 02862 * @arg @ref LL_ADC_CHANNEL_16 02863 * @arg @ref LL_ADC_CHANNEL_17 02864 * @arg @ref LL_ADC_CHANNEL_18 02865 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 02866 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 02867 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 02868 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 02869 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 02870 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 02871 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 02872 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 02873 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 02874 * 02875 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 02876 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 02877 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 02878 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 02879 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 02880 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 02881 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 02882 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 02883 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF 02884 * @retval None 02885 */ 02886 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) 02887 { 02888 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 02889 02890 MODIFY_REG(*preg, 02891 ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, 02892 ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); 02893 } 02894 02895 /** 02896 * @brief Get for the ADC selected offset number 1, 2, 3 or 4: 02897 * Channel to which the offset programmed will be applied 02898 * (independently of channel mapped on ADC group regular 02899 * or group injected) 02900 * @note Usage of the returned channel number: 02901 * - To reinject this channel into another function LL_ADC_xxx: 02902 * the returned channel number is only partly formatted on definition 02903 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 02904 * with parts of literals LL_ADC_CHANNEL_x or using 02905 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 02906 * Then the selected literal LL_ADC_CHANNEL_x can be used 02907 * as parameter for another function. 02908 * - To get the channel number in decimal format: 02909 * process the returned value with the helper macro 02910 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 02911 * @note On STM32L4, some fast channels are available: fast analog inputs 02912 * coming from GPIO pads (ADC_IN1..5). 02913 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n 02914 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n 02915 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n 02916 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel 02917 * @param ADCx ADC instance 02918 * @param Offsety This parameter can be one of the following values: 02919 * @arg @ref LL_ADC_OFFSET_1 02920 * @arg @ref LL_ADC_OFFSET_2 02921 * @arg @ref LL_ADC_OFFSET_3 02922 * @arg @ref LL_ADC_OFFSET_4 02923 * @retval Returned value can be one of the following values: 02924 * @arg @ref LL_ADC_CHANNEL_0 02925 * @arg @ref LL_ADC_CHANNEL_1 (7) 02926 * @arg @ref LL_ADC_CHANNEL_2 (7) 02927 * @arg @ref LL_ADC_CHANNEL_3 (7) 02928 * @arg @ref LL_ADC_CHANNEL_4 (7) 02929 * @arg @ref LL_ADC_CHANNEL_5 (7) 02930 * @arg @ref LL_ADC_CHANNEL_6 02931 * @arg @ref LL_ADC_CHANNEL_7 02932 * @arg @ref LL_ADC_CHANNEL_8 02933 * @arg @ref LL_ADC_CHANNEL_9 02934 * @arg @ref LL_ADC_CHANNEL_10 02935 * @arg @ref LL_ADC_CHANNEL_11 02936 * @arg @ref LL_ADC_CHANNEL_12 02937 * @arg @ref LL_ADC_CHANNEL_13 02938 * @arg @ref LL_ADC_CHANNEL_14 02939 * @arg @ref LL_ADC_CHANNEL_15 02940 * @arg @ref LL_ADC_CHANNEL_16 02941 * @arg @ref LL_ADC_CHANNEL_17 02942 * @arg @ref LL_ADC_CHANNEL_18 02943 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 02944 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 02945 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 02946 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 02947 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 02948 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 02949 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 02950 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 02951 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 02952 * 02953 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 02954 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 02955 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 02956 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 02957 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 02958 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 02959 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 02960 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n 02961 * (1, 2, 3, 4) For ADC channel read back from ADC register, 02962 * comparison with internal channel parameter to be done 02963 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 02964 */ 02965 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) 02966 { 02967 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 02968 02969 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 02970 } 02971 02972 /** 02973 * @brief Get for the ADC selected offset number 1, 2, 3 or 4: 02974 * Offset level (offset to be subtracted from the raw 02975 * converted data). 02976 * @note Caution: Offset format is dependent to ADC resolution: 02977 * offset has to be left-aligned on bit 11, the LSB (right bits) 02978 * are set to 0. 02979 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n 02980 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n 02981 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n 02982 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel 02983 * @param ADCx ADC instance 02984 * @param Offsety This parameter can be one of the following values: 02985 * @arg @ref LL_ADC_OFFSET_1 02986 * @arg @ref LL_ADC_OFFSET_2 02987 * @arg @ref LL_ADC_OFFSET_3 02988 * @arg @ref LL_ADC_OFFSET_4 02989 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 02990 */ 02991 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) 02992 { 02993 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 02994 02995 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1); 02996 } 02997 02998 /** 02999 * @brief Set for the ADC selected offset number 1, 2, 3 or 4: 03000 * force offset state disable or enable 03001 * without modifying offset channel or offset value. 03002 * @note This function should be needed only in case of offset to be 03003 * enabled-disabled dynamically, and should not be needed in other cases: 03004 * function LL_ADC_SetOffset() automatically enables the offset. 03005 * @note On this STM32 serie, setting of this feature is conditioned to 03006 * ADC state: 03007 * ADC must be disabled or enabled without conversion on going 03008 * on either groups regular or injected. 03009 * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n 03010 * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n 03011 * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n 03012 * OFR4 OFFSET4_EN LL_ADC_SetOffsetState 03013 * @param ADCx ADC instance 03014 * @param Offsety This parameter can be one of the following values: 03015 * @arg @ref LL_ADC_OFFSET_1 03016 * @arg @ref LL_ADC_OFFSET_2 03017 * @arg @ref LL_ADC_OFFSET_3 03018 * @arg @ref LL_ADC_OFFSET_4 03019 * @param OffsetState This parameter can be one of the following values: 03020 * @arg @ref LL_ADC_OFFSET_DISABLE 03021 * @arg @ref LL_ADC_OFFSET_ENABLE 03022 * @retval None 03023 */ 03024 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) 03025 { 03026 register uint32_t *preg = (uint32_t *)((uint32_t) 03027 ((uint32_t)(&ADCx->OFR1) + (Offsety*4U))); 03028 03029 MODIFY_REG(*preg, 03030 ADC_OFR1_OFFSET1_EN, 03031 OffsetState); 03032 } 03033 03034 /** 03035 * @brief Get for the ADC selected offset number 1, 2, 3 or 4: 03036 * offset state disabled or enabled. 03037 * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n 03038 * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n 03039 * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n 03040 * OFR4 OFFSET4_EN LL_ADC_GetOffsetState 03041 * @param ADCx ADC instance 03042 * @param Offsety This parameter can be one of the following values: 03043 * @arg @ref LL_ADC_OFFSET_1 03044 * @arg @ref LL_ADC_OFFSET_2 03045 * @arg @ref LL_ADC_OFFSET_3 03046 * @arg @ref LL_ADC_OFFSET_4 03047 * @retval Returned value can be one of the following values: 03048 * @arg @ref LL_ADC_OFFSET_DISABLE 03049 * @arg @ref LL_ADC_OFFSET_ENABLE 03050 */ 03051 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety) 03052 { 03053 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 03054 03055 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN); 03056 } 03057 03058 #if defined(ADC_SMPR1_SMPPLUS) 03059 /** 03060 * @brief Set ADC sampling time common configuration impacting 03061 * settings of sampling time channel wise. 03062 * @note On this STM32 serie, setting of this feature is conditioned to 03063 * ADC state: 03064 * ADC must be disabled or enabled without conversion on going 03065 * on either groups regular or injected. 03066 * @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig 03067 * @param ADCx ADC instance 03068 * @param SamplingTimeCommonConfig This parameter can be one of the following values: 03069 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT 03070 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 03071 * @retval None 03072 */ 03073 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig) 03074 { 03075 MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig); 03076 } 03077 03078 /** 03079 * @brief Get ADC sampling time common configuration impacting 03080 * settings of sampling time channel wise. 03081 * @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig 03082 * @param ADCx ADC instance 03083 * @retval Returned value can be one of the following values: 03084 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT 03085 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 03086 */ 03087 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx) 03088 { 03089 return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS)); 03090 } 03091 #endif /* ADC_SMPR1_SMPPLUS */ 03092 03093 /** 03094 * @} 03095 */ 03096 03097 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular 03098 * @{ 03099 */ 03100 03101 /** 03102 * @brief Set ADC group regular conversion trigger source: 03103 * internal (SW start) or from external IP (timer event, 03104 * external interrupt line). 03105 * @note On this STM32 serie, setting trigger source to external trigger 03106 * also set trigger polarity to rising edge 03107 * (default setting for compatibility with some ADC on other 03108 * STM32 families having this setting set by HW default value). 03109 * In case of need to modify trigger edge, use 03110 * function @ref LL_ADC_REG_SetTriggerEdge(). 03111 * @note Availability of parameters of trigger sources from timer 03112 * depends on timers availability on the selected device. 03113 * @note On this STM32 serie, setting of this feature is conditioned to 03114 * ADC state: 03115 * ADC must be disabled or enabled without conversion on going 03116 * on group regular. 03117 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n 03118 * CFGR EXTEN LL_ADC_REG_SetTriggerSource 03119 * @param ADCx ADC instance 03120 * @param TriggerSource This parameter can be one of the following values: 03121 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE 03122 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO 03123 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 03124 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 03125 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 03126 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 03127 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO 03128 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 03129 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO 03130 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 03131 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO 03132 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 03133 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO 03134 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO 03135 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 03136 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO 03137 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 03138 * @retval None 03139 */ 03140 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 03141 { 03142 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource); 03143 } 03144 03145 /** 03146 * @brief Get ADC group regular conversion trigger source: 03147 * internal (SW start) or from external IP (timer event, 03148 * external interrupt line). 03149 * @note To determine whether group regular trigger source is 03150 * internal (SW start) or external, without detail 03151 * of which peripheral is selected as external trigger, 03152 * (equivalent to 03153 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") 03154 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. 03155 * @note Availability of parameters of trigger sources from timer 03156 * depends on timers availability on the selected device. 03157 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n 03158 * CFGR EXTEN LL_ADC_REG_GetTriggerSource 03159 * @param ADCx ADC instance 03160 * @retval Returned value can be one of the following values: 03161 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE 03162 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO 03163 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 03164 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 03165 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 03166 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 03167 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO 03168 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 03169 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO 03170 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 03171 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO 03172 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 03173 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO 03174 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO 03175 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 03176 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO 03177 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 03178 */ 03179 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) 03180 { 03181 register uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); 03182 03183 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ 03184 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */ 03185 register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); 03186 03187 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */ 03188 /* to match with triggers literals definition. */ 03189 return ((TriggerSource 03190 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL) 03191 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN) 03192 ); 03193 } 03194 03195 /** 03196 * @brief Get ADC group regular conversion trigger source internal (SW start) 03197 * or external. 03198 * @note In case of group regular trigger source set to external trigger, 03199 * to determine which peripheral is selected as external trigger, 03200 * use function @ref LL_ADC_REG_GetTriggerSource(). 03201 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart 03202 * @param ADCx ADC instance 03203 * @retval Value "0" if trigger source external trigger 03204 * Value "1" if trigger source SW start. 03205 */ 03206 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) 03207 { 03208 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)); 03209 } 03210 03211 /** 03212 * @brief Set ADC group regular conversion trigger polarity. 03213 * @note Applicable only for trigger source set to external trigger. 03214 * @note On this STM32 serie, setting of this feature is conditioned to 03215 * ADC state: 03216 * ADC must be disabled or enabled without conversion on going 03217 * on group regular. 03218 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge 03219 * @param ADCx ADC instance 03220 * @param ExternalTriggerEdge This parameter can be one of the following values: 03221 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING 03222 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING 03223 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING 03224 * @retval None 03225 */ 03226 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) 03227 { 03228 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge); 03229 } 03230 03231 /** 03232 * @brief Get ADC group regular conversion trigger polarity. 03233 * @note Applicable only for trigger source set to external trigger. 03234 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge 03235 * @param ADCx ADC instance 03236 * @retval Returned value can be one of the following values: 03237 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING 03238 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING 03239 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING 03240 */ 03241 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) 03242 { 03243 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN)); 03244 } 03245 03246 /** 03247 * @brief Set ADC group regular sequencer length and scan direction. 03248 * @note Description of ADC group regular sequencer features: 03249 * - For devices with sequencer fully configurable 03250 * (function "LL_ADC_REG_SetSequencerRanks()" available): 03251 * sequencer length and each rank affectation to a channel 03252 * are configurable. 03253 * This function performs configuration of: 03254 * - Sequence length: Number of ranks in the scan sequence. 03255 * - Sequence direction: Unless specified in parameters, sequencer 03256 * scan direction is forward (from rank 1 to rank n). 03257 * Sequencer ranks are selected using 03258 * function "LL_ADC_REG_SetSequencerRanks()". 03259 * - For devices with sequencer not fully configurable 03260 * (function "LL_ADC_REG_SetSequencerChannels()" available): 03261 * sequencer length and each rank affectation to a channel 03262 * are defined by channel number. 03263 * This function performs configuration of: 03264 * - Sequence length: Number of ranks in the scan sequence is 03265 * defined by number of channels set in the sequence, 03266 * rank of each channel is fixed by channel HW number. 03267 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 03268 * - Sequence direction: Unless specified in parameters, sequencer 03269 * scan direction is forward (from lowest channel number to 03270 * highest channel number). 03271 * Sequencer ranks are selected using 03272 * function "LL_ADC_REG_SetSequencerChannels()". 03273 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 03274 * ADC conversion on only 1 channel. 03275 * @note On this STM32 serie, setting of this feature is conditioned to 03276 * ADC state: 03277 * ADC must be disabled or enabled without conversion on going 03278 * on group regular. 03279 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength 03280 * @param ADCx ADC instance 03281 * @param SequencerNbRanks This parameter can be one of the following values: 03282 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE 03283 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS 03284 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS 03285 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS 03286 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS 03287 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS 03288 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS 03289 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS 03290 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS 03291 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS 03292 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS 03293 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS 03294 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS 03295 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS 03296 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS 03297 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS 03298 * @retval None 03299 */ 03300 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) 03301 { 03302 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); 03303 } 03304 03305 /** 03306 * @brief Get ADC group regular sequencer length and scan direction. 03307 * @note Description of ADC group regular sequencer features: 03308 * - For devices with sequencer fully configurable 03309 * (function "LL_ADC_REG_SetSequencerRanks()" available): 03310 * sequencer length and each rank affectation to a channel 03311 * are configurable. 03312 * This function retrieves: 03313 * - Sequence length: Number of ranks in the scan sequence. 03314 * - Sequence direction: Unless specified in parameters, sequencer 03315 * scan direction is forward (from rank 1 to rank n). 03316 * Sequencer ranks are selected using 03317 * function "LL_ADC_REG_SetSequencerRanks()". 03318 * - For devices with sequencer not fully configurable 03319 * (function "LL_ADC_REG_SetSequencerChannels()" available): 03320 * sequencer length and each rank affectation to a channel 03321 * are defined by channel number. 03322 * This function retrieves: 03323 * - Sequence length: Number of ranks in the scan sequence is 03324 * defined by number of channels set in the sequence, 03325 * rank of each channel is fixed by channel HW number. 03326 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 03327 * - Sequence direction: Unless specified in parameters, sequencer 03328 * scan direction is forward (from lowest channel number to 03329 * highest channel number). 03330 * Sequencer ranks are selected using 03331 * function "LL_ADC_REG_SetSequencerChannels()". 03332 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 03333 * ADC conversion on only 1 channel. 03334 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength 03335 * @param ADCx ADC instance 03336 * @retval Returned value can be one of the following values: 03337 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE 03338 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS 03339 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS 03340 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS 03341 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS 03342 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS 03343 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS 03344 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS 03345 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS 03346 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS 03347 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS 03348 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS 03349 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS 03350 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS 03351 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS 03352 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS 03353 */ 03354 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) 03355 { 03356 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); 03357 } 03358 03359 /** 03360 * @brief Set ADC group regular sequencer discontinuous mode: 03361 * sequence subdivided and scan conversions interrupted every selected 03362 * number of ranks. 03363 * @note It is not possible to enable both ADC group regular 03364 * continuous mode and sequencer discontinuous mode. 03365 * @note It is not possible to enable both ADC auto-injected mode 03366 * and ADC group regular sequencer discontinuous mode. 03367 * @note On this STM32 serie, setting of this feature is conditioned to 03368 * ADC state: 03369 * ADC must be disabled or enabled without conversion on going 03370 * on group regular. 03371 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n 03372 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont 03373 * @param ADCx ADC instance 03374 * @param SeqDiscont This parameter can be one of the following values: 03375 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE 03376 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK 03377 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS 03378 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS 03379 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS 03380 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS 03381 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS 03382 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS 03383 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS 03384 * @retval None 03385 */ 03386 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) 03387 { 03388 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont); 03389 } 03390 03391 /** 03392 * @brief Get ADC group regular sequencer discontinuous mode: 03393 * sequence subdivided and scan conversions interrupted every selected 03394 * number of ranks. 03395 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n 03396 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont 03397 * @param ADCx ADC instance 03398 * @retval Returned value can be one of the following values: 03399 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE 03400 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK 03401 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS 03402 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS 03403 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS 03404 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS 03405 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS 03406 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS 03407 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS 03408 */ 03409 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) 03410 { 03411 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM)); 03412 } 03413 03414 /** 03415 * @brief Set ADC group regular sequence: channel on the selected 03416 * scan sequence rank. 03417 * @note This function performs configuration of: 03418 * - Channels ordering into each rank of scan sequence: 03419 * whatever channel can be placed into whatever rank. 03420 * @note On this STM32 serie, ADC group regular sequencer is 03421 * fully configurable: sequencer length and each rank 03422 * affectation to a channel are configurable. 03423 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). 03424 * @note Depending on devices and packages, some channels may not be available. 03425 * Refer to device datasheet for channels availability. 03426 * @note On this STM32 serie, to measure internal channels (VrefInt, 03427 * TempSensor, ...), measurement paths to internal channels must be 03428 * enabled separately. 03429 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). 03430 * @note On this STM32 serie, setting of this feature is conditioned to 03431 * ADC state: 03432 * ADC must be disabled or enabled without conversion on going 03433 * on group regular. 03434 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n 03435 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n 03436 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n 03437 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n 03438 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n 03439 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n 03440 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n 03441 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n 03442 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n 03443 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n 03444 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n 03445 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n 03446 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n 03447 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n 03448 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n 03449 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks 03450 * @param ADCx ADC instance 03451 * @param Rank This parameter can be one of the following values: 03452 * @arg @ref LL_ADC_REG_RANK_1 03453 * @arg @ref LL_ADC_REG_RANK_2 03454 * @arg @ref LL_ADC_REG_RANK_3 03455 * @arg @ref LL_ADC_REG_RANK_4 03456 * @arg @ref LL_ADC_REG_RANK_5 03457 * @arg @ref LL_ADC_REG_RANK_6 03458 * @arg @ref LL_ADC_REG_RANK_7 03459 * @arg @ref LL_ADC_REG_RANK_8 03460 * @arg @ref LL_ADC_REG_RANK_9 03461 * @arg @ref LL_ADC_REG_RANK_10 03462 * @arg @ref LL_ADC_REG_RANK_11 03463 * @arg @ref LL_ADC_REG_RANK_12 03464 * @arg @ref LL_ADC_REG_RANK_13 03465 * @arg @ref LL_ADC_REG_RANK_14 03466 * @arg @ref LL_ADC_REG_RANK_15 03467 * @arg @ref LL_ADC_REG_RANK_16 03468 * @param Channel This parameter can be one of the following values: 03469 * @arg @ref LL_ADC_CHANNEL_0 03470 * @arg @ref LL_ADC_CHANNEL_1 (7) 03471 * @arg @ref LL_ADC_CHANNEL_2 (7) 03472 * @arg @ref LL_ADC_CHANNEL_3 (7) 03473 * @arg @ref LL_ADC_CHANNEL_4 (7) 03474 * @arg @ref LL_ADC_CHANNEL_5 (7) 03475 * @arg @ref LL_ADC_CHANNEL_6 03476 * @arg @ref LL_ADC_CHANNEL_7 03477 * @arg @ref LL_ADC_CHANNEL_8 03478 * @arg @ref LL_ADC_CHANNEL_9 03479 * @arg @ref LL_ADC_CHANNEL_10 03480 * @arg @ref LL_ADC_CHANNEL_11 03481 * @arg @ref LL_ADC_CHANNEL_12 03482 * @arg @ref LL_ADC_CHANNEL_13 03483 * @arg @ref LL_ADC_CHANNEL_14 03484 * @arg @ref LL_ADC_CHANNEL_15 03485 * @arg @ref LL_ADC_CHANNEL_16 03486 * @arg @ref LL_ADC_CHANNEL_17 03487 * @arg @ref LL_ADC_CHANNEL_18 03488 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 03489 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 03490 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 03491 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 03492 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 03493 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 03494 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 03495 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 03496 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 03497 * 03498 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 03499 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 03500 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 03501 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 03502 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 03503 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 03504 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 03505 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 03506 * @retval None 03507 */ 03508 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) 03509 { 03510 /* Set bits with content of parameter "Channel" with bits position */ 03511 /* in register and register position depending on parameter "Rank". */ 03512 /* Parameters "Rank" and "Channel" are used with masks because containing */ 03513 /* other bits reserved for other purpose. */ 03514 #if defined(CORE_CM0PLUS) 03515 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); 03516 #else 03517 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); 03518 #endif 03519 03520 MODIFY_REG(*preg, 03521 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), 03522 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); 03523 } 03524 03525 /** 03526 * @brief Get ADC group regular sequence: channel on the selected 03527 * scan sequence rank. 03528 * @note On this STM32 serie, ADC group regular sequencer is 03529 * fully configurable: sequencer length and each rank 03530 * affectation to a channel are configurable. 03531 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). 03532 * @note Depending on devices and packages, some channels may not be available. 03533 * Refer to device datasheet for channels availability. 03534 * @note Usage of the returned channel number: 03535 * - To reinject this channel into another function LL_ADC_xxx: 03536 * the returned channel number is only partly formatted on definition 03537 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 03538 * with parts of literals LL_ADC_CHANNEL_x or using 03539 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 03540 * Then the selected literal LL_ADC_CHANNEL_x can be used 03541 * as parameter for another function. 03542 * - To get the channel number in decimal format: 03543 * process the returned value with the helper macro 03544 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 03545 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n 03546 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n 03547 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n 03548 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n 03549 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n 03550 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n 03551 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n 03552 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n 03553 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n 03554 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n 03555 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n 03556 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n 03557 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n 03558 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n 03559 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n 03560 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks 03561 * @param ADCx ADC instance 03562 * @param Rank This parameter can be one of the following values: 03563 * @arg @ref LL_ADC_REG_RANK_1 03564 * @arg @ref LL_ADC_REG_RANK_2 03565 * @arg @ref LL_ADC_REG_RANK_3 03566 * @arg @ref LL_ADC_REG_RANK_4 03567 * @arg @ref LL_ADC_REG_RANK_5 03568 * @arg @ref LL_ADC_REG_RANK_6 03569 * @arg @ref LL_ADC_REG_RANK_7 03570 * @arg @ref LL_ADC_REG_RANK_8 03571 * @arg @ref LL_ADC_REG_RANK_9 03572 * @arg @ref LL_ADC_REG_RANK_10 03573 * @arg @ref LL_ADC_REG_RANK_11 03574 * @arg @ref LL_ADC_REG_RANK_12 03575 * @arg @ref LL_ADC_REG_RANK_13 03576 * @arg @ref LL_ADC_REG_RANK_14 03577 * @arg @ref LL_ADC_REG_RANK_15 03578 * @arg @ref LL_ADC_REG_RANK_16 03579 * @retval Returned value can be one of the following values: 03580 * @arg @ref LL_ADC_CHANNEL_0 03581 * @arg @ref LL_ADC_CHANNEL_1 (7) 03582 * @arg @ref LL_ADC_CHANNEL_2 (7) 03583 * @arg @ref LL_ADC_CHANNEL_3 (7) 03584 * @arg @ref LL_ADC_CHANNEL_4 (7) 03585 * @arg @ref LL_ADC_CHANNEL_5 (7) 03586 * @arg @ref LL_ADC_CHANNEL_6 03587 * @arg @ref LL_ADC_CHANNEL_7 03588 * @arg @ref LL_ADC_CHANNEL_8 03589 * @arg @ref LL_ADC_CHANNEL_9 03590 * @arg @ref LL_ADC_CHANNEL_10 03591 * @arg @ref LL_ADC_CHANNEL_11 03592 * @arg @ref LL_ADC_CHANNEL_12 03593 * @arg @ref LL_ADC_CHANNEL_13 03594 * @arg @ref LL_ADC_CHANNEL_14 03595 * @arg @ref LL_ADC_CHANNEL_15 03596 * @arg @ref LL_ADC_CHANNEL_16 03597 * @arg @ref LL_ADC_CHANNEL_17 03598 * @arg @ref LL_ADC_CHANNEL_18 03599 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 03600 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 03601 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 03602 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 03603 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 03604 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 03605 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 03606 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 03607 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 03608 * 03609 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 03610 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 03611 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 03612 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 03613 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 03614 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 03615 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 03616 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n 03617 * (1, 2, 3, 4) For ADC channel read back from ADC register, 03618 * comparison with internal channel parameter to be done 03619 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 03620 */ 03621 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) 03622 { 03623 #if defined(CORE_CM0PLUS) 03624 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); 03625 #else 03626 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); 03627 #endif 03628 03629 return (uint32_t) ((READ_BIT(*preg, 03630 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) 03631 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS 03632 ); 03633 } 03634 03635 /** 03636 * @brief Set ADC continuous conversion mode on ADC group regular. 03637 * @note Description of ADC continuous conversion mode: 03638 * - single mode: one conversion per trigger 03639 * - continuous mode: after the first trigger, following 03640 * conversions launched successively automatically. 03641 * @note It is not possible to enable both ADC group regular 03642 * continuous mode and sequencer discontinuous mode. 03643 * @note On this STM32 serie, setting of this feature is conditioned to 03644 * ADC state: 03645 * ADC must be disabled or enabled without conversion on going 03646 * on group regular. 03647 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode 03648 * @param ADCx ADC instance 03649 * @param Continuous This parameter can be one of the following values: 03650 * @arg @ref LL_ADC_REG_CONV_SINGLE 03651 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS 03652 * @retval None 03653 */ 03654 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) 03655 { 03656 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous); 03657 } 03658 03659 /** 03660 * @brief Get ADC continuous conversion mode on ADC group regular. 03661 * @note Description of ADC continuous conversion mode: 03662 * - single mode: one conversion per trigger 03663 * - continuous mode: after the first trigger, following 03664 * conversions launched successively automatically. 03665 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode 03666 * @param ADCx ADC instance 03667 * @retval Returned value can be one of the following values: 03668 * @arg @ref LL_ADC_REG_CONV_SINGLE 03669 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS 03670 */ 03671 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) 03672 { 03673 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT)); 03674 } 03675 03676 /** 03677 * @brief Set ADC group regular conversion data transfer: no transfer or 03678 * transfer by DMA, and DMA requests mode. 03679 * @note If transfer by DMA selected, specifies the DMA requests 03680 * mode: 03681 * - Limited mode (One shot mode): DMA transfer requests are stopped 03682 * when number of DMA data transfers (number of 03683 * ADC conversions) is reached. 03684 * This ADC mode is intended to be used with DMA mode non-circular. 03685 * - Unlimited mode: DMA transfer requests are unlimited, 03686 * whatever number of DMA data transfers (number of 03687 * ADC conversions). 03688 * This ADC mode is intended to be used with DMA mode circular. 03689 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 03690 * mode non-circular: 03691 * when DMA transfers size will be reached, DMA will stop transfers of 03692 * ADC conversions data ADC will raise an overrun error 03693 * (overrun flag and interruption if enabled). 03694 * @note For devices with several ADC instances: ADC multimode DMA 03695 * settings are available using function @ref LL_ADC_SetMultiDMATransfer(). 03696 * @note To configure DMA source address (peripheral address), 03697 * use function @ref LL_ADC_DMA_GetRegAddr(). 03698 * @note On this STM32 serie, setting of this feature is conditioned to 03699 * ADC state: 03700 * ADC must be disabled or enabled without conversion on going 03701 * on either groups regular or injected. 03702 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n 03703 * CFGR DMACFG LL_ADC_REG_SetDMATransfer 03704 * @param ADCx ADC instance 03705 * @param DMATransfer This parameter can be one of the following values: 03706 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE 03707 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED 03708 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED 03709 * @retval None 03710 */ 03711 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) 03712 { 03713 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer); 03714 } 03715 03716 /** 03717 * @brief Get ADC group regular conversion data transfer: no transfer or 03718 * transfer by DMA, and DMA requests mode. 03719 * @note If transfer by DMA selected, specifies the DMA requests 03720 * mode: 03721 * - Limited mode (One shot mode): DMA transfer requests are stopped 03722 * when number of DMA data transfers (number of 03723 * ADC conversions) is reached. 03724 * This ADC mode is intended to be used with DMA mode non-circular. 03725 * - Unlimited mode: DMA transfer requests are unlimited, 03726 * whatever number of DMA data transfers (number of 03727 * ADC conversions). 03728 * This ADC mode is intended to be used with DMA mode circular. 03729 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 03730 * mode non-circular: 03731 * when DMA transfers size will be reached, DMA will stop transfers of 03732 * ADC conversions data ADC will raise an overrun error 03733 * (overrun flag and interruption if enabled). 03734 * @note For devices with several ADC instances: ADC multimode DMA 03735 * settings are available using function @ref LL_ADC_GetMultiDMATransfer(). 03736 * @note To configure DMA source address (peripheral address), 03737 * use function @ref LL_ADC_DMA_GetRegAddr(). 03738 * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n 03739 * CFGR DMACFG LL_ADC_REG_GetDMATransfer 03740 * @param ADCx ADC instance 03741 * @retval Returned value can be one of the following values: 03742 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE 03743 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED 03744 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED 03745 */ 03746 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) 03747 { 03748 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG)); 03749 } 03750 03751 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 03752 /** 03753 * @brief Set ADC group regular conversion data transfer to DFSDM. 03754 * @note DFSDM transfer cannot be used if DMA transfer is enabled. 03755 * @note To configure DFSDM source address (peripheral address), 03756 * use the same function as for DMA transfer: 03757 * function @ref LL_ADC_DMA_GetRegAddr(). 03758 * @note On this STM32 serie, setting of this feature is conditioned to 03759 * ADC state: 03760 * ADC must be disabled or enabled without conversion on going 03761 * on either groups regular or injected. 03762 * @rmtoll CFGR DFSDMCFG LL_ADC_REG_GetDFSDMTransfer 03763 * @param ADCx ADC instance 03764 * @param DFSDMTransfer This parameter can be one of the following values: 03765 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_NONE 03766 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_ENABLE 03767 * @retval None 03768 */ 03769 __STATIC_INLINE void LL_ADC_REG_SetDFSDMTransfer(ADC_TypeDef *ADCx, uint32_t DFSDMTransfer) 03770 { 03771 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DFSDMCFG, DFSDMTransfer); 03772 } 03773 03774 /** 03775 * @brief Get ADC group regular conversion data transfer to DFSDM. 03776 * @rmtoll CFGR DFSDMCFG LL_ADC_REG_GetDFSDMTransfer 03777 * @param ADCx ADC instance 03778 * @retval Returned value can be one of the following values: 03779 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_NONE 03780 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_ENABLE 03781 */ 03782 __STATIC_INLINE uint32_t LL_ADC_REG_GetDFSDMTransfer(ADC_TypeDef *ADCx) 03783 { 03784 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DFSDMCFG)); 03785 } 03786 #endif 03787 03788 /** 03789 * @brief Set ADC group regular behavior in case of overrun: 03790 * data preserved or overwritten. 03791 * @note Compatibility with devices without feature overrun: 03792 * other devices without this feature have a behavior 03793 * equivalent to data overwritten. 03794 * The default setting of overrun is data preserved. 03795 * Therefore, for compatibility with all devices, parameter 03796 * overrun should be set to data overwritten. 03797 * @note On this STM32 serie, setting of this feature is conditioned to 03798 * ADC state: 03799 * ADC must be disabled or enabled without conversion on going 03800 * on group regular. 03801 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun 03802 * @param ADCx ADC instance 03803 * @param Overrun This parameter can be one of the following values: 03804 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED 03805 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN 03806 * @retval None 03807 */ 03808 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) 03809 { 03810 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun); 03811 } 03812 03813 /** 03814 * @brief Get ADC group regular behavior in case of overrun: 03815 * data preserved or overwritten. 03816 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun 03817 * @param ADCx ADC instance 03818 * @retval Returned value can be one of the following values: 03819 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED 03820 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN 03821 */ 03822 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) 03823 { 03824 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD)); 03825 } 03826 03827 /** 03828 * @} 03829 */ 03830 03831 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected 03832 * @{ 03833 */ 03834 03835 /** 03836 * @brief Set ADC group injected conversion trigger source: 03837 * internal (SW start) or from external IP (timer event, 03838 * external interrupt line). 03839 * @note On this STM32 serie, setting trigger source to external trigger 03840 * also set trigger polarity to rising edge 03841 * (default setting for compatibility with some ADC on other 03842 * STM32 families having this setting set by HW default value). 03843 * In case of need to modify trigger edge, use 03844 * function @ref LL_ADC_INJ_SetTriggerEdge(). 03845 * @note Availability of parameters of trigger sources from timer 03846 * depends on timers availability on the selected device. 03847 * @note On this STM32 serie, setting of this feature is conditioned to 03848 * ADC state: 03849 * ADC must not be disabled. Can be enabled with or without conversion 03850 * on going on either groups regular or injected. 03851 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n 03852 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource 03853 * @param ADCx ADC instance 03854 * @param TriggerSource This parameter can be one of the following values: 03855 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE 03856 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 03857 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 03858 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 03859 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO 03860 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 03861 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO 03862 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 03863 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 03864 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 03865 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO 03866 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO 03867 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 03868 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO 03869 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 03870 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO 03871 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 03872 * @retval None 03873 */ 03874 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 03875 { 03876 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource); 03877 } 03878 03879 /** 03880 * @brief Get ADC group injected conversion trigger source: 03881 * internal (SW start) or from external IP (timer event, 03882 * external interrupt line). 03883 * @note To determine whether group injected trigger source is 03884 * internal (SW start) or external, without detail 03885 * of which peripheral is selected as external trigger, 03886 * (equivalent to 03887 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") 03888 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. 03889 * @note Availability of parameters of trigger sources from timer 03890 * depends on timers availability on the selected device. 03891 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n 03892 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource 03893 * @param ADCx ADC instance 03894 * @retval Returned value can be one of the following values: 03895 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE 03896 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 03897 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 03898 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 03899 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO 03900 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 03901 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO 03902 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 03903 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 03904 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 03905 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO 03906 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO 03907 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 03908 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO 03909 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 03910 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO 03911 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 03912 */ 03913 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) 03914 { 03915 register uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); 03916 03917 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ 03918 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */ 03919 register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U)); 03920 03921 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */ 03922 /* to match with triggers literals definition. */ 03923 return ((TriggerSource 03924 & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL) 03925 | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN) 03926 ); 03927 } 03928 03929 /** 03930 * @brief Get ADC group injected conversion trigger source internal (SW start) 03931 or external 03932 * @note In case of group injected trigger source set to external trigger, 03933 * to determine which peripheral is selected as external trigger, 03934 * use function @ref LL_ADC_INJ_GetTriggerSource. 03935 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart 03936 * @param ADCx ADC instance 03937 * @retval Value "0" if trigger source external trigger 03938 * Value "1" if trigger source SW start. 03939 */ 03940 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) 03941 { 03942 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)); 03943 } 03944 03945 /** 03946 * @brief Set ADC group injected conversion trigger polarity. 03947 * Applicable only for trigger source set to external trigger. 03948 * @note On this STM32 serie, setting of this feature is conditioned to 03949 * ADC state: 03950 * ADC must not be disabled. Can be enabled with or without conversion 03951 * on going on either groups regular or injected. 03952 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge 03953 * @param ADCx ADC instance 03954 * @param ExternalTriggerEdge This parameter can be one of the following values: 03955 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING 03956 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING 03957 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING 03958 * @retval None 03959 */ 03960 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) 03961 { 03962 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge); 03963 } 03964 03965 /** 03966 * @brief Get ADC group injected conversion trigger polarity. 03967 * Applicable only for trigger source set to external trigger. 03968 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge 03969 * @param ADCx ADC instance 03970 * @retval Returned value can be one of the following values: 03971 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING 03972 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING 03973 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING 03974 */ 03975 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) 03976 { 03977 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN)); 03978 } 03979 03980 /** 03981 * @brief Set ADC group injected sequencer length and scan direction. 03982 * @note This function performs configuration of: 03983 * - Sequence length: Number of ranks in the scan sequence. 03984 * - Sequence direction: Unless specified in parameters, sequencer 03985 * scan direction is forward (from rank 1 to rank n). 03986 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 03987 * ADC conversion on only 1 channel. 03988 * @note On this STM32 serie, setting of this feature is conditioned to 03989 * ADC state: 03990 * ADC must not be disabled. Can be enabled with or without conversion 03991 * on going on either groups regular or injected. 03992 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength 03993 * @param ADCx ADC instance 03994 * @param SequencerNbRanks This parameter can be one of the following values: 03995 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE 03996 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS 03997 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS 03998 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS 03999 * @retval None 04000 */ 04001 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) 04002 { 04003 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); 04004 } 04005 04006 /** 04007 * @brief Get ADC group injected sequencer length and scan direction. 04008 * @note This function retrieves: 04009 * - Sequence length: Number of ranks in the scan sequence. 04010 * - Sequence direction: Unless specified in parameters, sequencer 04011 * scan direction is forward (from rank 1 to rank n). 04012 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 04013 * ADC conversion on only 1 channel. 04014 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength 04015 * @param ADCx ADC instance 04016 * @retval Returned value can be one of the following values: 04017 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE 04018 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS 04019 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS 04020 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS 04021 */ 04022 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) 04023 { 04024 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); 04025 } 04026 04027 /** 04028 * @brief Set ADC group injected sequencer discontinuous mode: 04029 * sequence subdivided and scan conversions interrupted every selected 04030 * number of ranks. 04031 * @note It is not possible to enable both ADC group injected 04032 * auto-injected mode and sequencer discontinuous mode. 04033 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont 04034 * @param ADCx ADC instance 04035 * @param SeqDiscont This parameter can be one of the following values: 04036 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE 04037 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK 04038 * @retval None 04039 */ 04040 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) 04041 { 04042 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont); 04043 } 04044 04045 /** 04046 * @brief Get ADC group injected sequencer discontinuous mode: 04047 * sequence subdivided and scan conversions interrupted every selected 04048 * number of ranks. 04049 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont 04050 * @param ADCx ADC instance 04051 * @retval Returned value can be one of the following values: 04052 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE 04053 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK 04054 */ 04055 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) 04056 { 04057 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN)); 04058 } 04059 04060 /** 04061 * @brief Set ADC group injected sequence: channel on the selected 04062 * sequence rank. 04063 * @note Depending on devices and packages, some channels may not be available. 04064 * Refer to device datasheet for channels availability. 04065 * @note On this STM32 serie, to measure internal channels (VrefInt, 04066 * TempSensor, ...), measurement paths to internal channels must be 04067 * enabled separately. 04068 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). 04069 * @note On STM32L4, some fast channels are available: fast analog inputs 04070 * coming from GPIO pads (ADC_IN1..5). 04071 * @note On this STM32 serie, setting of this feature is conditioned to 04072 * ADC state: 04073 * ADC must not be disabled. Can be enabled with or without conversion 04074 * on going on either groups regular or injected. 04075 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n 04076 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n 04077 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n 04078 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks 04079 * @param ADCx ADC instance 04080 * @param Rank This parameter can be one of the following values: 04081 * @arg @ref LL_ADC_INJ_RANK_1 04082 * @arg @ref LL_ADC_INJ_RANK_2 04083 * @arg @ref LL_ADC_INJ_RANK_3 04084 * @arg @ref LL_ADC_INJ_RANK_4 04085 * @param Channel This parameter can be one of the following values: 04086 * @arg @ref LL_ADC_CHANNEL_0 04087 * @arg @ref LL_ADC_CHANNEL_1 (7) 04088 * @arg @ref LL_ADC_CHANNEL_2 (7) 04089 * @arg @ref LL_ADC_CHANNEL_3 (7) 04090 * @arg @ref LL_ADC_CHANNEL_4 (7) 04091 * @arg @ref LL_ADC_CHANNEL_5 (7) 04092 * @arg @ref LL_ADC_CHANNEL_6 04093 * @arg @ref LL_ADC_CHANNEL_7 04094 * @arg @ref LL_ADC_CHANNEL_8 04095 * @arg @ref LL_ADC_CHANNEL_9 04096 * @arg @ref LL_ADC_CHANNEL_10 04097 * @arg @ref LL_ADC_CHANNEL_11 04098 * @arg @ref LL_ADC_CHANNEL_12 04099 * @arg @ref LL_ADC_CHANNEL_13 04100 * @arg @ref LL_ADC_CHANNEL_14 04101 * @arg @ref LL_ADC_CHANNEL_15 04102 * @arg @ref LL_ADC_CHANNEL_16 04103 * @arg @ref LL_ADC_CHANNEL_17 04104 * @arg @ref LL_ADC_CHANNEL_18 04105 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 04106 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 04107 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 04108 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 04109 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 04110 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 04111 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 04112 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 04113 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 04114 * 04115 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 04116 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 04117 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 04118 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 04119 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 04120 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 04121 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 04122 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 04123 * @retval None 04124 */ 04125 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) 04126 { 04127 /* Set bits with content of parameter "Channel" with bits position */ 04128 /* in register depending on parameter "Rank". */ 04129 /* Parameters "Rank" and "Channel" are used with masks because containing */ 04130 /* other bits reserved for other purpose. */ 04131 MODIFY_REG(ADCx->JSQR, 04132 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK), 04133 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)); 04134 } 04135 04136 /** 04137 * @brief Get ADC group injected sequence: channel on the selected 04138 * sequence rank. 04139 * @note Depending on devices and packages, some channels may not be available. 04140 * Refer to device datasheet for channels availability. 04141 * @note Usage of the returned channel number: 04142 * - To reinject this channel into another function LL_ADC_xxx: 04143 * the returned channel number is only partly formatted on definition 04144 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 04145 * with parts of literals LL_ADC_CHANNEL_x or using 04146 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 04147 * Then the selected literal LL_ADC_CHANNEL_x can be used 04148 * as parameter for another function. 04149 * - To get the channel number in decimal format: 04150 * process the returned value with the helper macro 04151 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 04152 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n 04153 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n 04154 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n 04155 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks 04156 * @param ADCx ADC instance 04157 * @param Rank This parameter can be one of the following values: 04158 * @arg @ref LL_ADC_INJ_RANK_1 04159 * @arg @ref LL_ADC_INJ_RANK_2 04160 * @arg @ref LL_ADC_INJ_RANK_3 04161 * @arg @ref LL_ADC_INJ_RANK_4 04162 * @retval Returned value can be one of the following values: 04163 * @arg @ref LL_ADC_CHANNEL_0 04164 * @arg @ref LL_ADC_CHANNEL_1 (7) 04165 * @arg @ref LL_ADC_CHANNEL_2 (7) 04166 * @arg @ref LL_ADC_CHANNEL_3 (7) 04167 * @arg @ref LL_ADC_CHANNEL_4 (7) 04168 * @arg @ref LL_ADC_CHANNEL_5 (7) 04169 * @arg @ref LL_ADC_CHANNEL_6 04170 * @arg @ref LL_ADC_CHANNEL_7 04171 * @arg @ref LL_ADC_CHANNEL_8 04172 * @arg @ref LL_ADC_CHANNEL_9 04173 * @arg @ref LL_ADC_CHANNEL_10 04174 * @arg @ref LL_ADC_CHANNEL_11 04175 * @arg @ref LL_ADC_CHANNEL_12 04176 * @arg @ref LL_ADC_CHANNEL_13 04177 * @arg @ref LL_ADC_CHANNEL_14 04178 * @arg @ref LL_ADC_CHANNEL_15 04179 * @arg @ref LL_ADC_CHANNEL_16 04180 * @arg @ref LL_ADC_CHANNEL_17 04181 * @arg @ref LL_ADC_CHANNEL_18 04182 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 04183 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 04184 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 04185 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 04186 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 04187 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 04188 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 04189 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 04190 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 04191 * 04192 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 04193 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 04194 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 04195 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 04196 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 04197 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 04198 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 04199 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n 04200 * (1, 2, 3, 4) For ADC channel read back from ADC register, 04201 * comparison with internal channel parameter to be done 04202 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 04203 */ 04204 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) 04205 { 04206 return (uint32_t)((READ_BIT(ADCx->JSQR, 04207 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) 04208 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS 04209 ); 04210 } 04211 04212 /** 04213 * @brief Set ADC group injected conversion trigger: 04214 * independent or from ADC group regular. 04215 * @note This mode can be used to extend number of data registers 04216 * updated after one ADC conversion trigger and with data 04217 * permanently kept (not erased by successive conversions of scan of 04218 * ADC sequencer ranks), up to 5 data registers: 04219 * 1 data register on ADC group regular, 4 data registers 04220 * on ADC group injected. 04221 * @note If ADC group injected injected trigger source is set to an 04222 * external trigger, this feature must be must be set to 04223 * independent trigger. 04224 * ADC group injected automatic trigger is compliant only with 04225 * group injected trigger source set to SW start, without any 04226 * further action on ADC group injected conversion start or stop: 04227 * in this case, ADC group injected is controlled only 04228 * from ADC group regular. 04229 * @note It is not possible to enable both ADC group injected 04230 * auto-injected mode and sequencer discontinuous mode. 04231 * @note On this STM32 serie, setting of this feature is conditioned to 04232 * ADC state: 04233 * ADC must be disabled or enabled without conversion on going 04234 * on either groups regular or injected. 04235 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto 04236 * @param ADCx ADC instance 04237 * @param TrigAuto This parameter can be one of the following values: 04238 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT 04239 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR 04240 * @retval None 04241 */ 04242 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) 04243 { 04244 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto); 04245 } 04246 04247 /** 04248 * @brief Get ADC group injected conversion trigger: 04249 * independent or from ADC group regular. 04250 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto 04251 * @param ADCx ADC instance 04252 * @retval Returned value can be one of the following values: 04253 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT 04254 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR 04255 */ 04256 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) 04257 { 04258 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO)); 04259 } 04260 04261 /** 04262 * @brief Set ADC group injected contexts queue mode. 04263 * @note A context is a setting of group injected sequencer: 04264 * - group injected trigger 04265 * - sequencer length 04266 * - sequencer ranks 04267 * If contexts queue is disabled: 04268 * - only 1 sequence can be configured 04269 * and is active perpetually. 04270 * If contexts queue is enabled: 04271 * - up to 2 contexts can be queued 04272 * and are checked in and out as a FIFO stack (first-in, first-out). 04273 * - If a new context is set when queues is full, error is triggered 04274 * by interruption "Injected Queue Overflow". 04275 * - Two behaviors are possible when all contexts have been processed: 04276 * the contexts queue can maintain the last context active perpetually 04277 * or can be empty and injected group triggers are disabled. 04278 * - Triggers can be only external (not internal SW start) 04279 * - Caution: The sequence must be fully configured in one time 04280 * (one write of register JSQR makes a check-in of a new context 04281 * into the queue). 04282 * Therefore functions to set separately injected trigger and 04283 * sequencer channels cannot be used, register JSQR must be set 04284 * using function @ref LL_ADC_INJ_ConfigQueueContext(). 04285 * @note This parameter can be modified only when no conversion is on going 04286 * on either groups regular or injected. 04287 * @note A modification of the context mode (bit JQDIS) causes the contexts 04288 * queue to be flushed and the register JSQR is cleared. 04289 * @note On this STM32 serie, setting of this feature is conditioned to 04290 * ADC state: 04291 * ADC must be disabled or enabled without conversion on going 04292 * on either groups regular or injected. 04293 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n 04294 * CFGR JQDIS LL_ADC_INJ_SetQueueMode 04295 * @param ADCx ADC instance 04296 * @param QueueMode This parameter can be one of the following values: 04297 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE 04298 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE 04299 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY 04300 * @retval None 04301 */ 04302 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode) 04303 { 04304 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode); 04305 } 04306 04307 /** 04308 * @brief Get ADC group injected context queue mode. 04309 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n 04310 * CFGR JQDIS LL_ADC_INJ_GetQueueMode 04311 * @param ADCx ADC instance 04312 * @retval Returned value can be one of the following values: 04313 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE 04314 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE 04315 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY 04316 */ 04317 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) 04318 { 04319 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS)); 04320 } 04321 04322 /** 04323 * @brief Set one context on ADC group injected that will be checked in 04324 * contexts queue. 04325 * @note A context is a setting of group injected sequencer: 04326 * - group injected trigger 04327 * - sequencer length 04328 * - sequencer ranks 04329 * This function is intended to be used when contexts queue is enabled, 04330 * because the sequence must be fully configured in one time 04331 * (functions to set separately injected trigger and sequencer channels 04332 * cannot be used): 04333 * Refer to function @ref LL_ADC_INJ_SetQueueMode(). 04334 * @note In the contexts queue, only the active context can be read. 04335 * The parameters of this function can be read using functions: 04336 * @arg @ref LL_ADC_INJ_GetTriggerSource() 04337 * @arg @ref LL_ADC_INJ_GetTriggerEdge() 04338 * @arg @ref LL_ADC_INJ_GetSequencerRanks() 04339 * @note On this STM32 serie, to measure internal channels (VrefInt, 04340 * TempSensor, ...), measurement paths to internal channels must be 04341 * enabled separately. 04342 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). 04343 * @note On STM32L4, some fast channels are available: fast analog inputs 04344 * coming from GPIO pads (ADC_IN1..5). 04345 * @note On this STM32 serie, setting of this feature is conditioned to 04346 * ADC state: 04347 * ADC must not be disabled. Can be enabled with or without conversion 04348 * on going on either groups regular or injected. 04349 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n 04350 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n 04351 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n 04352 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n 04353 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n 04354 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n 04355 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext 04356 * @param ADCx ADC instance 04357 * @param TriggerSource This parameter can be one of the following values: 04358 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE 04359 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 04360 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 04361 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 04362 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO 04363 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 04364 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO 04365 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 04366 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 04367 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 04368 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO 04369 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO 04370 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 04371 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO 04372 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 04373 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO 04374 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 04375 * @param ExternalTriggerEdge This parameter can be one of the following values: 04376 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING 04377 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING 04378 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING 04379 * 04380 * Note: This parameter is discarded in case of SW start: 04381 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE". 04382 * @param SequencerNbRanks This parameter can be one of the following values: 04383 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE 04384 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS 04385 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS 04386 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS 04387 * @param Rank1_Channel This parameter can be one of the following values: 04388 * @arg @ref LL_ADC_CHANNEL_0 04389 * @arg @ref LL_ADC_CHANNEL_1 (7) 04390 * @arg @ref LL_ADC_CHANNEL_2 (7) 04391 * @arg @ref LL_ADC_CHANNEL_3 (7) 04392 * @arg @ref LL_ADC_CHANNEL_4 (7) 04393 * @arg @ref LL_ADC_CHANNEL_5 (7) 04394 * @arg @ref LL_ADC_CHANNEL_6 04395 * @arg @ref LL_ADC_CHANNEL_7 04396 * @arg @ref LL_ADC_CHANNEL_8 04397 * @arg @ref LL_ADC_CHANNEL_9 04398 * @arg @ref LL_ADC_CHANNEL_10 04399 * @arg @ref LL_ADC_CHANNEL_11 04400 * @arg @ref LL_ADC_CHANNEL_12 04401 * @arg @ref LL_ADC_CHANNEL_13 04402 * @arg @ref LL_ADC_CHANNEL_14 04403 * @arg @ref LL_ADC_CHANNEL_15 04404 * @arg @ref LL_ADC_CHANNEL_16 04405 * @arg @ref LL_ADC_CHANNEL_17 04406 * @arg @ref LL_ADC_CHANNEL_18 04407 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 04408 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 04409 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 04410 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 04411 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 04412 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 04413 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 04414 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 04415 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 04416 * 04417 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 04418 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 04419 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 04420 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 04421 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 04422 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 04423 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 04424 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 04425 * @param Rank2_Channel This parameter can be one of the following values: 04426 * @arg @ref LL_ADC_CHANNEL_0 04427 * @arg @ref LL_ADC_CHANNEL_1 (7) 04428 * @arg @ref LL_ADC_CHANNEL_2 (7) 04429 * @arg @ref LL_ADC_CHANNEL_3 (7) 04430 * @arg @ref LL_ADC_CHANNEL_4 (7) 04431 * @arg @ref LL_ADC_CHANNEL_5 (7) 04432 * @arg @ref LL_ADC_CHANNEL_6 04433 * @arg @ref LL_ADC_CHANNEL_7 04434 * @arg @ref LL_ADC_CHANNEL_8 04435 * @arg @ref LL_ADC_CHANNEL_9 04436 * @arg @ref LL_ADC_CHANNEL_10 04437 * @arg @ref LL_ADC_CHANNEL_11 04438 * @arg @ref LL_ADC_CHANNEL_12 04439 * @arg @ref LL_ADC_CHANNEL_13 04440 * @arg @ref LL_ADC_CHANNEL_14 04441 * @arg @ref LL_ADC_CHANNEL_15 04442 * @arg @ref LL_ADC_CHANNEL_16 04443 * @arg @ref LL_ADC_CHANNEL_17 04444 * @arg @ref LL_ADC_CHANNEL_18 04445 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 04446 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 04447 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 04448 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 04449 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 04450 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 04451 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 04452 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 04453 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 04454 * 04455 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 04456 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 04457 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 04458 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 04459 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 04460 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 04461 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 04462 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 04463 * @param Rank3_Channel This parameter can be one of the following values: 04464 * @arg @ref LL_ADC_CHANNEL_0 04465 * @arg @ref LL_ADC_CHANNEL_1 (7) 04466 * @arg @ref LL_ADC_CHANNEL_2 (7) 04467 * @arg @ref LL_ADC_CHANNEL_3 (7) 04468 * @arg @ref LL_ADC_CHANNEL_4 (7) 04469 * @arg @ref LL_ADC_CHANNEL_5 (7) 04470 * @arg @ref LL_ADC_CHANNEL_6 04471 * @arg @ref LL_ADC_CHANNEL_7 04472 * @arg @ref LL_ADC_CHANNEL_8 04473 * @arg @ref LL_ADC_CHANNEL_9 04474 * @arg @ref LL_ADC_CHANNEL_10 04475 * @arg @ref LL_ADC_CHANNEL_11 04476 * @arg @ref LL_ADC_CHANNEL_12 04477 * @arg @ref LL_ADC_CHANNEL_13 04478 * @arg @ref LL_ADC_CHANNEL_14 04479 * @arg @ref LL_ADC_CHANNEL_15 04480 * @arg @ref LL_ADC_CHANNEL_16 04481 * @arg @ref LL_ADC_CHANNEL_17 04482 * @arg @ref LL_ADC_CHANNEL_18 04483 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 04484 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 04485 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 04486 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 04487 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 04488 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 04489 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 04490 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 04491 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 04492 * 04493 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 04494 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 04495 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 04496 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 04497 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 04498 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 04499 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 04500 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 04501 * @param Rank4_Channel This parameter can be one of the following values: 04502 * @arg @ref LL_ADC_CHANNEL_0 04503 * @arg @ref LL_ADC_CHANNEL_1 (7) 04504 * @arg @ref LL_ADC_CHANNEL_2 (7) 04505 * @arg @ref LL_ADC_CHANNEL_3 (7) 04506 * @arg @ref LL_ADC_CHANNEL_4 (7) 04507 * @arg @ref LL_ADC_CHANNEL_5 (7) 04508 * @arg @ref LL_ADC_CHANNEL_6 04509 * @arg @ref LL_ADC_CHANNEL_7 04510 * @arg @ref LL_ADC_CHANNEL_8 04511 * @arg @ref LL_ADC_CHANNEL_9 04512 * @arg @ref LL_ADC_CHANNEL_10 04513 * @arg @ref LL_ADC_CHANNEL_11 04514 * @arg @ref LL_ADC_CHANNEL_12 04515 * @arg @ref LL_ADC_CHANNEL_13 04516 * @arg @ref LL_ADC_CHANNEL_14 04517 * @arg @ref LL_ADC_CHANNEL_15 04518 * @arg @ref LL_ADC_CHANNEL_16 04519 * @arg @ref LL_ADC_CHANNEL_17 04520 * @arg @ref LL_ADC_CHANNEL_18 04521 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 04522 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 04523 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 04524 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 04525 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 04526 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 04527 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 04528 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 04529 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 04530 * 04531 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 04532 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 04533 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 04534 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 04535 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 04536 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 04537 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 04538 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 04539 * @retval None 04540 */ 04541 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, 04542 uint32_t TriggerSource, 04543 uint32_t ExternalTriggerEdge, 04544 uint32_t SequencerNbRanks, 04545 uint32_t Rank1_Channel, 04546 uint32_t Rank2_Channel, 04547 uint32_t Rank3_Channel, 04548 uint32_t Rank4_Channel) 04549 { 04550 /* Set bits with content of parameter "Rankx_Channel" with bits position */ 04551 /* in register depending on literal "LL_ADC_INJ_RANK_x". */ 04552 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */ 04553 /* because containing other bits reserved for other purpose. */ 04554 /* If parameter "TriggerSource" is set to SW start, then parameter */ 04555 /* "ExternalTriggerEdge" is discarded. */ 04556 register uint32_t is_trigger_not_sw = (uint32_t)(TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE); 04557 MODIFY_REG(ADCx->JSQR , 04558 ADC_JSQR_JEXTSEL | 04559 ADC_JSQR_JEXTEN | 04560 ADC_JSQR_JSQ4 | 04561 ADC_JSQR_JSQ3 | 04562 ADC_JSQR_JSQ2 | 04563 ADC_JSQR_JSQ1 | 04564 ADC_JSQR_JL , 04565 TriggerSource | 04566 (ExternalTriggerEdge * (is_trigger_not_sw)) | 04567 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) | 04568 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) | 04569 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) | 04570 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) | 04571 SequencerNbRanks 04572 ); 04573 } 04574 04575 /** 04576 * @} 04577 */ 04578 04579 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels 04580 * @{ 04581 */ 04582 04583 /** 04584 * @brief Set sampling time of the selected ADC channel 04585 * Unit: ADC clock cycles. 04586 * @note On this device, sampling time is on channel scope: independently 04587 * of channel mapped on ADC group regular or injected. 04588 * @note In case of internal channel (VrefInt, TempSensor, ...) to be 04589 * converted: 04590 * sampling time constraints must be respected (sampling time can be 04591 * adjusted in function of ADC clock frequency and sampling time 04592 * setting). 04593 * Refer to device datasheet for timings values (parameters TS_vrefint, 04594 * TS_temp, ...). 04595 * @note Conversion time is the addition of sampling time and processing time. 04596 * On this STM32 serie, ADC processing time is: 04597 * - 12.5 ADC clock cycles at ADC resolution 12 bits 04598 * - 10.5 ADC clock cycles at ADC resolution 10 bits 04599 * - 8.5 ADC clock cycles at ADC resolution 8 bits 04600 * - 6.5 ADC clock cycles at ADC resolution 6 bits 04601 * @note In case of ADC conversion of internal channel (VrefInt, 04602 * temperature sensor, ...), a sampling time minimum value 04603 * is required. 04604 * Refer to device datasheet. 04605 * @note On this STM32 serie, setting of this feature is conditioned to 04606 * ADC state: 04607 * ADC must be disabled or enabled without conversion on going 04608 * on either groups regular or injected. 04609 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n 04610 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n 04611 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n 04612 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n 04613 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n 04614 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n 04615 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n 04616 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n 04617 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n 04618 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n 04619 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n 04620 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n 04621 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n 04622 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n 04623 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n 04624 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n 04625 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n 04626 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n 04627 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime 04628 * @param ADCx ADC instance 04629 * @param Channel This parameter can be one of the following values: 04630 * @arg @ref LL_ADC_CHANNEL_0 04631 * @arg @ref LL_ADC_CHANNEL_1 (7) 04632 * @arg @ref LL_ADC_CHANNEL_2 (7) 04633 * @arg @ref LL_ADC_CHANNEL_3 (7) 04634 * @arg @ref LL_ADC_CHANNEL_4 (7) 04635 * @arg @ref LL_ADC_CHANNEL_5 (7) 04636 * @arg @ref LL_ADC_CHANNEL_6 04637 * @arg @ref LL_ADC_CHANNEL_7 04638 * @arg @ref LL_ADC_CHANNEL_8 04639 * @arg @ref LL_ADC_CHANNEL_9 04640 * @arg @ref LL_ADC_CHANNEL_10 04641 * @arg @ref LL_ADC_CHANNEL_11 04642 * @arg @ref LL_ADC_CHANNEL_12 04643 * @arg @ref LL_ADC_CHANNEL_13 04644 * @arg @ref LL_ADC_CHANNEL_14 04645 * @arg @ref LL_ADC_CHANNEL_15 04646 * @arg @ref LL_ADC_CHANNEL_16 04647 * @arg @ref LL_ADC_CHANNEL_17 04648 * @arg @ref LL_ADC_CHANNEL_18 04649 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 04650 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 04651 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 04652 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 04653 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 04654 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 04655 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 04656 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 04657 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 04658 * 04659 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 04660 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 04661 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 04662 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 04663 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 04664 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 04665 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 04666 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 04667 * @param SamplingTime This parameter can be one of the following values: 04668 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1) 04669 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5 04670 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 04671 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5 04672 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5 04673 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5 04674 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5 04675 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5 04676 * 04677 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles 04678 * can be replaced by 3.5 ADC clock cycles. 04679 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig(). 04680 * @retval None 04681 */ 04682 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) 04683 { 04684 /* Set bits with content of parameter "SamplingTime" with bits position */ 04685 /* in register and register position depending on parameter "Channel". */ 04686 /* Parameter "Channel" is used with masks because containing */ 04687 /* other bits reserved for other purpose. */ 04688 #if defined(CORE_CM0PLUS) 04689 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 04690 04691 MODIFY_REG(*preg, 04692 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), 04693 SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); 04694 #else 04695 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); 04696 04697 MODIFY_REG(*preg, 04698 ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), 04699 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); 04700 #endif 04701 } 04702 04703 /** 04704 * @brief Get sampling time of the selected ADC channel 04705 * Unit: ADC clock cycles. 04706 * @note On this device, sampling time is on channel scope: independently 04707 * of channel mapped on ADC group regular or injected. 04708 * @note Conversion time is the addition of sampling time and processing time. 04709 * On this STM32 serie, ADC processing time is: 04710 * - 12.5 ADC clock cycles at ADC resolution 12 bits 04711 * - 10.5 ADC clock cycles at ADC resolution 10 bits 04712 * - 8.5 ADC clock cycles at ADC resolution 8 bits 04713 * - 6.5 ADC clock cycles at ADC resolution 6 bits 04714 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n 04715 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n 04716 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n 04717 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n 04718 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n 04719 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n 04720 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n 04721 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n 04722 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n 04723 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n 04724 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n 04725 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n 04726 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n 04727 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n 04728 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n 04729 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n 04730 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n 04731 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n 04732 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime 04733 * @param ADCx ADC instance 04734 * @param Channel This parameter can be one of the following values: 04735 * @arg @ref LL_ADC_CHANNEL_0 04736 * @arg @ref LL_ADC_CHANNEL_1 (7) 04737 * @arg @ref LL_ADC_CHANNEL_2 (7) 04738 * @arg @ref LL_ADC_CHANNEL_3 (7) 04739 * @arg @ref LL_ADC_CHANNEL_4 (7) 04740 * @arg @ref LL_ADC_CHANNEL_5 (7) 04741 * @arg @ref LL_ADC_CHANNEL_6 04742 * @arg @ref LL_ADC_CHANNEL_7 04743 * @arg @ref LL_ADC_CHANNEL_8 04744 * @arg @ref LL_ADC_CHANNEL_9 04745 * @arg @ref LL_ADC_CHANNEL_10 04746 * @arg @ref LL_ADC_CHANNEL_11 04747 * @arg @ref LL_ADC_CHANNEL_12 04748 * @arg @ref LL_ADC_CHANNEL_13 04749 * @arg @ref LL_ADC_CHANNEL_14 04750 * @arg @ref LL_ADC_CHANNEL_15 04751 * @arg @ref LL_ADC_CHANNEL_16 04752 * @arg @ref LL_ADC_CHANNEL_17 04753 * @arg @ref LL_ADC_CHANNEL_18 04754 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 04755 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4) 04756 * @arg @ref LL_ADC_CHANNEL_VBAT (4) 04757 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5) 04758 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5) 04759 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 04760 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 04761 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 04762 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 04763 * 04764 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 04765 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 04766 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 04767 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 04768 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 04769 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 04770 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 04771 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 04772 * @retval Returned value can be one of the following values: 04773 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1) 04774 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5 04775 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 04776 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5 04777 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5 04778 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5 04779 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5 04780 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5 04781 * 04782 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles 04783 * can be replaced by 3.5 ADC clock cycles. 04784 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig(). 04785 */ 04786 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) 04787 { 04788 #if defined(CORE_CM0PLUS) 04789 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 04790 04791 return (uint32_t)(READ_BIT(*preg, 04792 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)) 04793 >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS) 04794 ); 04795 #else 04796 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); 04797 04798 return (uint32_t)(READ_BIT(*preg, 04799 ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) 04800 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) 04801 ); 04802 #endif 04803 } 04804 04805 /** 04806 * @brief Set mode single-ended or differential input of the selected 04807 * ADC channel. 04808 * @note Channel ending is on channel scope: independently of channel mapped 04809 * on ADC group regular or injected. 04810 * In differential mode: Differential measurement is carried out 04811 * between the selected channel 'i' (positive input) and 04812 * channel 'i+1' (negative input). Only channel 'i' has to be 04813 * configured, channel 'i+1' is configured automatically. 04814 * @note Refer to Reference Manual to ensure the selected channel is 04815 * available in differential mode. 04816 * For example, internal channels (VrefInt, TempSensor, ...) are 04817 * not available in differential mode. 04818 * @note When configuring a channel 'i' in differential mode, 04819 * the channel 'i+1' is not usable separately. 04820 * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available) 04821 * are internally fixed to single-ended inputs configuration. 04822 * @note For ADC channels configured in differential mode, both inputs 04823 * should be biased at (Vref+)/2 +/-200mV. 04824 * (Vref+ is the analog voltage reference) 04825 * @note On this STM32 serie, setting of this feature is conditioned to 04826 * ADC state: 04827 * ADC must be ADC disabled. 04828 * @note One or several values can be selected. 04829 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) 04830 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff 04831 * @param ADCx ADC instance 04832 * @param Channel This parameter can be one of the following values: 04833 * @arg @ref LL_ADC_CHANNEL_1 04834 * @arg @ref LL_ADC_CHANNEL_2 04835 * @arg @ref LL_ADC_CHANNEL_3 04836 * @arg @ref LL_ADC_CHANNEL_4 04837 * @arg @ref LL_ADC_CHANNEL_5 04838 * @arg @ref LL_ADC_CHANNEL_6 04839 * @arg @ref LL_ADC_CHANNEL_7 04840 * @arg @ref LL_ADC_CHANNEL_8 04841 * @arg @ref LL_ADC_CHANNEL_9 04842 * @arg @ref LL_ADC_CHANNEL_10 04843 * @arg @ref LL_ADC_CHANNEL_11 04844 * @arg @ref LL_ADC_CHANNEL_12 04845 * @arg @ref LL_ADC_CHANNEL_13 04846 * @arg @ref LL_ADC_CHANNEL_14 04847 * @arg @ref LL_ADC_CHANNEL_15 04848 * @param SingleDiff This parameter can be a combination of the following values: 04849 * @arg @ref LL_ADC_SINGLE_ENDED 04850 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED 04851 * @retval None 04852 */ 04853 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) 04854 { 04855 /* Bits of channels in single or differential mode are set only for */ 04856 /* differential mode (for single mode, mask of bits allowed to be set is */ 04857 /* shifted out of range of bits of channels in single or differential mode. */ 04858 MODIFY_REG(ADCx->DIFSEL, 04859 Channel & ADC_SINGLEDIFF_CHANNEL_MASK, 04860 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL << (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); 04861 } 04862 04863 /** 04864 * @brief Get mode single-ended or differential input of the selected 04865 * ADC channel. 04866 * @note When configuring a channel 'i' in differential mode, 04867 * the channel 'i+1' is not usable separately. 04868 * Therefore, to ensure a channel is configured in single-ended mode, 04869 * the configuration of channel itself and the channel 'i-1' must be 04870 * read back (to ensure that the selected channel channel has not been 04871 * configured in differential mode by the previous channel). 04872 * @note Refer to Reference Manual to ensure the selected channel is 04873 * available in differential mode. 04874 * For example, internal channels (VrefInt, TempSensor, ...) are 04875 * not available in differential mode. 04876 * @note When configuring a channel 'i' in differential mode, 04877 * the channel 'i+1' is not usable separately. 04878 * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available) 04879 * are internally fixed to single-ended inputs configuration. 04880 * @note One or several values can be selected. In this case, the value 04881 * returned is null if all channels are in single ended-mode. 04882 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) 04883 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff 04884 * @param ADCx ADC instance 04885 * @param Channel This parameter can be a combination of the following values: 04886 * @arg @ref LL_ADC_CHANNEL_1 04887 * @arg @ref LL_ADC_CHANNEL_2 04888 * @arg @ref LL_ADC_CHANNEL_3 04889 * @arg @ref LL_ADC_CHANNEL_4 04890 * @arg @ref LL_ADC_CHANNEL_5 04891 * @arg @ref LL_ADC_CHANNEL_6 04892 * @arg @ref LL_ADC_CHANNEL_7 04893 * @arg @ref LL_ADC_CHANNEL_8 04894 * @arg @ref LL_ADC_CHANNEL_9 04895 * @arg @ref LL_ADC_CHANNEL_10 04896 * @arg @ref LL_ADC_CHANNEL_11 04897 * @arg @ref LL_ADC_CHANNEL_12 04898 * @arg @ref LL_ADC_CHANNEL_13 04899 * @arg @ref LL_ADC_CHANNEL_14 04900 * @arg @ref LL_ADC_CHANNEL_15 04901 * @retval 0: channel in single-ended mode, else: channel in differential mode 04902 */ 04903 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel) 04904 { 04905 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK))); 04906 } 04907 04908 /** 04909 * @} 04910 */ 04911 04912 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog 04913 * @{ 04914 */ 04915 04916 /** 04917 * @brief Set ADC analog watchdog monitored channels: 04918 * a single channel, multiple channels or all channels, 04919 * on ADC groups regular and-or injected. 04920 * @note Once monitored channels are selected, analog watchdog 04921 * is enabled. 04922 * @note In case of need to define a single channel to monitor 04923 * with analog watchdog from sequencer channel definition, 04924 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). 04925 * @note On this STM32 serie, there are 2 kinds of analog watchdog 04926 * instance: 04927 * - AWD standard (instance AWD1): 04928 * - channels monitored: can monitor 1 channel or all channels. 04929 * - groups monitored: ADC groups regular and-or injected. 04930 * - resolution: resolution is not limited (corresponds to 04931 * ADC resolution configured). 04932 * - AWD flexible (instances AWD2, AWD3): 04933 * - channels monitored: flexible on channels monitored, selection is 04934 * channel wise, from from 1 to all channels. 04935 * Specificity of this analog watchdog: Multiple channels can 04936 * be selected. For example: 04937 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) 04938 * - groups monitored: not selection possible (monitoring on both 04939 * groups regular and injected). 04940 * Channels selected are monitored on groups regular and injected: 04941 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters 04942 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) 04943 * - resolution: resolution is limited to 8 bits: if ADC resolution is 04944 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits 04945 * the 2 LSB are ignored. 04946 * @note On this STM32 serie, setting of this feature is conditioned to 04947 * ADC state: 04948 * ADC must be disabled or enabled without conversion on going 04949 * on either groups regular or injected. 04950 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n 04951 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n 04952 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n 04953 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n 04954 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n 04955 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels 04956 * @param ADCx ADC instance 04957 * @param AWDy This parameter can be one of the following values: 04958 * @arg @ref LL_ADC_AWD1 04959 * @arg @ref LL_ADC_AWD2 04960 * @arg @ref LL_ADC_AWD3 04961 * @param AWDChannelGroup This parameter can be one of the following values: 04962 * @arg @ref LL_ADC_AWD_DISABLE 04963 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) 04964 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) 04965 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 04966 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) 04967 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) 04968 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 04969 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) 04970 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) 04971 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 04972 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) 04973 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) 04974 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 04975 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) 04976 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) 04977 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 04978 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) 04979 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) 04980 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 04981 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) 04982 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) 04983 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 04984 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) 04985 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) 04986 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 04987 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) 04988 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) 04989 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 04990 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) 04991 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) 04992 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 04993 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) 04994 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) 04995 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 04996 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) 04997 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) 04998 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 04999 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) 05000 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) 05001 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 05002 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) 05003 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) 05004 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 05005 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) 05006 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) 05007 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 05008 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) 05009 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) 05010 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 05011 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) 05012 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) 05013 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 05014 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) 05015 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) 05016 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 05017 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) 05018 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) 05019 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 05020 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) 05021 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) 05022 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ 05023 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1) 05024 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1) 05025 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) 05026 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4) 05027 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(4) 05028 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4) 05029 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(4) 05030 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(4) 05031 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (4) 05032 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG (0)(2)(5) 05033 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ (0)(2)(5) 05034 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ (2)(5) 05035 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG (0)(2)(5) 05036 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ (0)(2)(5) 05037 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ (2)(5) 05038 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)(6) 05039 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)(6) 05040 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)(6) 05041 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)(6) 05042 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)(6) 05043 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)(6) 05044 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)(6) 05045 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)(6) 05046 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)(6) 05047 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6) 05048 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6) 05049 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6) 05050 * 05051 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n 05052 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 05053 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 05054 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 05055 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3. 05056 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 05057 * (6) On STM32L4, parameter available on devices with several ADC instances. 05058 * @retval None 05059 */ 05060 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup) 05061 { 05062 /* Set bits with content of parameter "AWDChannelGroup" with bits position */ 05063 /* in register and register position depending on parameter "AWDy". */ 05064 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ 05065 /* containing other bits reserved for other purpose. */ 05066 #if defined(CORE_CM0PLUS) 05067 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) 05068 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); 05069 05070 MODIFY_REG(*preg, 05071 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), 05072 AWDChannelGroup & AWDy); 05073 #else 05074 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK) 05075 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); 05076 05077 MODIFY_REG(*preg, 05078 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), 05079 AWDChannelGroup & AWDy); 05080 #endif 05081 } 05082 05083 /** 05084 * @brief Get ADC analog watchdog monitored channel. 05085 * @note Usage of the returned channel number: 05086 * - To reinject this channel into another function LL_ADC_xxx: 05087 * the returned channel number is only partly formatted on definition 05088 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 05089 * with parts of literals LL_ADC_CHANNEL_x or using 05090 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 05091 * Then the selected literal LL_ADC_CHANNEL_x can be used 05092 * as parameter for another function. 05093 * - To get the channel number in decimal format: 05094 * process the returned value with the helper macro 05095 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 05096 * Applicable only when the analog watchdog is set to monitor 05097 * one channel. 05098 * @note On this STM32 serie, there are 2 kinds of analog watchdog 05099 * instance: 05100 * - AWD standard (instance AWD1): 05101 * - channels monitored: can monitor 1 channel or all channels. 05102 * - groups monitored: ADC groups regular and-or injected. 05103 * - resolution: resolution is not limited (corresponds to 05104 * ADC resolution configured). 05105 * - AWD flexible (instances AWD2, AWD3): 05106 * - channels monitored: flexible on channels monitored, selection is 05107 * channel wise, from from 1 to all channels. 05108 * Specificity of this analog watchdog: Multiple channels can 05109 * be selected. For example: 05110 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) 05111 * - groups monitored: not selection possible (monitoring on both 05112 * groups regular and injected). 05113 * Channels selected are monitored on groups regular and injected: 05114 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters 05115 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) 05116 * - resolution: resolution is limited to 8 bits: if ADC resolution is 05117 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits 05118 * the 2 LSB are ignored. 05119 * @note On this STM32 serie, setting of this feature is conditioned to 05120 * ADC state: 05121 * ADC must be disabled or enabled without conversion on going 05122 * on either groups regular or injected. 05123 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n 05124 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n 05125 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n 05126 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n 05127 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n 05128 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels 05129 * @param ADCx ADC instance 05130 * @param AWDy This parameter can be one of the following values: 05131 * @arg @ref LL_ADC_AWD1 05132 * @arg @ref LL_ADC_AWD2 (1) 05133 * @arg @ref LL_ADC_AWD3 (1) 05134 * 05135 * (1) On this AWD number, monitored channel can be retrieved 05136 * if only 1 channel is programmed (or none or all channels). 05137 * This function cannot retrieve monitored channel if 05138 * multiple channels are programmed simultaneously 05139 * by bitfield. 05140 * @retval Returned value can be one of the following values: 05141 * @arg @ref LL_ADC_AWD_DISABLE 05142 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) 05143 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) 05144 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 05145 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) 05146 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) 05147 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 05148 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) 05149 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) 05150 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 05151 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) 05152 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) 05153 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 05154 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) 05155 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) 05156 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 05157 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) 05158 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) 05159 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 05160 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) 05161 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) 05162 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 05163 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) 05164 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) 05165 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 05166 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) 05167 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) 05168 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 05169 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) 05170 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) 05171 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 05172 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) 05173 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) 05174 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 05175 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) 05176 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) 05177 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 05178 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) 05179 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) 05180 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 05181 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) 05182 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) 05183 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 05184 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) 05185 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) 05186 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 05187 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) 05188 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) 05189 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 05190 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) 05191 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) 05192 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 05193 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) 05194 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) 05195 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 05196 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) 05197 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) 05198 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 05199 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) 05200 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) 05201 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ 05202 * 05203 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1. 05204 */ 05205 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) 05206 { 05207 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) 05208 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); 05209 05210 register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); 05211 05212 /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ 05213 /* (parameter value LL_ADC_AWD_DISABLE). */ 05214 /* Else, the selected AWD is enabled and is monitoring a group of channels */ 05215 /* or a single channel. */ 05216 if(AnalogWDMonitChannels != 0) 05217 { 05218 if(AWDy == LL_ADC_AWD1) 05219 { 05220 if((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0) 05221 { 05222 /* AWD monitoring a group of channels */ 05223 AnalogWDMonitChannels = (( AnalogWDMonitChannels 05224 | (ADC_AWD_CR23_CHANNEL_MASK) 05225 ) 05226 & (~(ADC_CFGR_AWD1CH)) 05227 ); 05228 } 05229 else 05230 { 05231 /* AWD monitoring a single channel */ 05232 AnalogWDMonitChannels = (AnalogWDMonitChannels 05233 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos)) 05234 ); 05235 } 05236 } 05237 else 05238 { 05239 if((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) 05240 { 05241 /* AWD monitoring a group of channels */ 05242 AnalogWDMonitChannels = ( ADC_AWD_CR23_CHANNEL_MASK 05243 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)) 05244 ); 05245 } 05246 else 05247 { 05248 /* AWD monitoring a single channel */ 05249 /* AWD monitoring a group of channels */ 05250 AnalogWDMonitChannels = ( AnalogWDMonitChannels 05251 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) 05252 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos) 05253 ); 05254 } 05255 } 05256 } 05257 05258 return AnalogWDMonitChannels; 05259 05260 } 05261 05262 /** 05263 * @brief Set ADC analog watchdog thresholds value of both thresholds 05264 * high and low. 05265 * @note If value of only one threshold high or low must be set, 05266 * use function @ref LL_ADC_SetAnalogWDThresholds(). 05267 * @note In case of ADC resolution different of 12 bits, 05268 * analog watchdog thresholds data require a specific shift. 05269 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). 05270 * @note On this STM32 serie, there are 2 kinds of analog watchdog 05271 * instance: 05272 * - AWD standard (instance AWD1): 05273 * - channels monitored: can monitor 1 channel or all channels. 05274 * - groups monitored: ADC groups regular and-or injected. 05275 * - resolution: resolution is not limited (corresponds to 05276 * ADC resolution configured). 05277 * - AWD flexible (instances AWD2, AWD3): 05278 * - channels monitored: flexible on channels monitored, selection is 05279 * channel wise, from from 1 to all channels. 05280 * Specificity of this analog watchdog: Multiple channels can 05281 * be selected. For example: 05282 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) 05283 * - groups monitored: not selection possible (monitoring on both 05284 * groups regular and injected). 05285 * Channels selected are monitored on groups regular and injected: 05286 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters 05287 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) 05288 * - resolution: resolution is limited to 8 bits: if ADC resolution is 05289 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits 05290 * the 2 LSB are ignored. 05291 * @note On this STM32 serie, setting of this feature is conditioned to 05292 * ADC state: 05293 * ADC must be disabled or enabled without conversion on going 05294 * on either groups regular or injected. 05295 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n 05296 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n 05297 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n 05298 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n 05299 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n 05300 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds 05301 * @param ADCx ADC instance 05302 * @param AWDy This parameter can be one of the following values: 05303 * @arg @ref LL_ADC_AWD1 05304 * @arg @ref LL_ADC_AWD2 05305 * @arg @ref LL_ADC_AWD3 05306 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF 05307 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF 05308 * @retval None 05309 */ 05310 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue) 05311 { 05312 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ 05313 /* position in register and register position depending on parameter */ 05314 /* "AWDy". */ 05315 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ 05316 /* containing other bits reserved for other purpose. */ 05317 #if defined(CORE_CM0PLUS) 05318 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); 05319 #else 05320 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); 05321 #endif 05322 05323 MODIFY_REG(*preg, 05324 ADC_TR1_HT1 | ADC_TR1_LT1, 05325 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue); 05326 } 05327 05328 /** 05329 * @brief Set ADC analog watchdog threshold value of threshold 05330 * high or low. 05331 * @note If values of both thresholds high or low must be set, 05332 * use function @ref LL_ADC_ConfigAnalogWDThresholds(). 05333 * @note In case of ADC resolution different of 12 bits, 05334 * analog watchdog thresholds data require a specific shift. 05335 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). 05336 * @note On this STM32 serie, there are 2 kinds of analog watchdog 05337 * instance: 05338 * - AWD standard (instance AWD1): 05339 * - channels monitored: can monitor 1 channel or all channels. 05340 * - groups monitored: ADC groups regular and-or injected. 05341 * - resolution: resolution is not limited (corresponds to 05342 * ADC resolution configured). 05343 * - AWD flexible (instances AWD2, AWD3): 05344 * - channels monitored: flexible on channels monitored, selection is 05345 * channel wise, from from 1 to all channels. 05346 * Specificity of this analog watchdog: Multiple channels can 05347 * be selected. For example: 05348 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) 05349 * - groups monitored: not selection possible (monitoring on both 05350 * groups regular and injected). 05351 * Channels selected are monitored on groups regular and injected: 05352 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters 05353 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) 05354 * - resolution: resolution is limited to 8 bits: if ADC resolution is 05355 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits 05356 * the 2 LSB are ignored. 05357 * @note On this STM32 serie, setting of this feature is conditioned to 05358 * ADC state: 05359 * ADC must be disabled or enabled without conversion on going 05360 * on either ADC groups regular or injected. 05361 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n 05362 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n 05363 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n 05364 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n 05365 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n 05366 * TR3 LT3 LL_ADC_SetAnalogWDThresholds 05367 * @param ADCx ADC instance 05368 * @param AWDy This parameter can be one of the following values: 05369 * @arg @ref LL_ADC_AWD1 05370 * @arg @ref LL_ADC_AWD2 05371 * @arg @ref LL_ADC_AWD3 05372 * @param AWDThresholdsHighLow This parameter can be one of the following values: 05373 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH 05374 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW 05375 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF 05376 * @retval None 05377 */ 05378 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) 05379 { 05380 /* Set bits with content of parameter "AWDThresholdValue" with bits */ 05381 /* position in register and register position depending on parameters */ 05382 /* "AWDThresholdsHighLow" and "AWDy". */ 05383 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ 05384 /* containing other bits reserved for other purpose. */ 05385 #if defined(CORE_CM0PLUS) 05386 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); 05387 05388 MODIFY_REG(*preg, 05389 AWDThresholdsHighLow, 05390 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)); 05391 #else 05392 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); 05393 05394 MODIFY_REG(*preg, 05395 AWDThresholdsHighLow, 05396 AWDThresholdValue << POSITION_VAL(AWDThresholdsHighLow)); 05397 #endif 05398 } 05399 05400 /** 05401 * @brief Get ADC analog watchdog threshold value of threshold high, 05402 * threshold low or raw data with ADC thresholds high and low 05403 * concatenated. 05404 * @note If raw data with ADC thresholds high and low is retrieved, 05405 * the data of each threshold high or low can be isolated 05406 * using helper macro: 05407 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(). 05408 * @note In case of ADC resolution different of 12 bits, 05409 * analog watchdog thresholds data require a specific shift. 05410 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). 05411 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n 05412 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n 05413 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n 05414 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n 05415 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n 05416 * TR3 LT3 LL_ADC_GetAnalogWDThresholds 05417 * @param ADCx ADC instance 05418 * @param AWDy This parameter can be one of the following values: 05419 * @arg @ref LL_ADC_AWD1 05420 * @arg @ref LL_ADC_AWD2 05421 * @arg @ref LL_ADC_AWD3 05422 * @param AWDThresholdsHighLow This parameter can be one of the following values: 05423 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH 05424 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW 05425 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW 05426 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 05427 */ 05428 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) 05429 { 05430 #if defined(CORE_CM0PLUS) 05431 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); 05432 05433 return (uint32_t)(READ_BIT(*preg, 05434 (AWDThresholdsHighLow | ADC_TR1_LT1)) 05435 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1)) 05436 ); 05437 #else 05438 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK)); 05439 05440 return (uint32_t)(READ_BIT(*preg, 05441 (AWDThresholdsHighLow | ADC_TR1_LT1)) 05442 >> POSITION_VAL(AWDThresholdsHighLow) 05443 ); 05444 #endif 05445 } 05446 05447 /** 05448 * @} 05449 */ 05450 05451 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling 05452 * @{ 05453 */ 05454 05455 /** 05456 * @brief Set ADC oversampling scope: ADC groups regular and-or injected 05457 * (availability of ADC group injected depends on STM32 families). 05458 * @note If both groups regular and injected are selected, 05459 * specify behavior of ADC group injected interrupting 05460 * group regular: when ADC group injected is triggered, 05461 * the oversampling on ADC group regular is either 05462 * temporary stopped and continued, or resumed from start 05463 * (oversampler buffer reset). 05464 * @note On this STM32 serie, setting of this feature is conditioned to 05465 * ADC state: 05466 * ADC must be disabled or enabled without conversion on going 05467 * on either groups regular or injected. 05468 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n 05469 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n 05470 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope 05471 * @param ADCx ADC instance 05472 * @param OvsScope This parameter can be one of the following values: 05473 * @arg @ref LL_ADC_OVS_DISABLE 05474 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED 05475 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED 05476 * @arg @ref LL_ADC_OVS_GRP_INJECTED 05477 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED 05478 * @retval None 05479 */ 05480 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope) 05481 { 05482 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope); 05483 } 05484 05485 /** 05486 * @brief Get ADC oversampling scope: ADC groups regular and-or injected 05487 * (availability of ADC group injected depends on STM32 families). 05488 * @note If both groups regular and injected are selected, 05489 * specify behavior of ADC group injected interrupting 05490 * group regular: when ADC group injected is triggered, 05491 * the oversampling on ADC group regular is either 05492 * temporary stopped and continued, or resumed from start 05493 * (oversampler buffer reset). 05494 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n 05495 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n 05496 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope 05497 * @param ADCx ADC instance 05498 * @retval Returned value can be one of the following values: 05499 * @arg @ref LL_ADC_OVS_DISABLE 05500 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED 05501 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED 05502 * @arg @ref LL_ADC_OVS_GRP_INJECTED 05503 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED 05504 */ 05505 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) 05506 { 05507 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM)); 05508 } 05509 05510 /** 05511 * @brief Set ADC oversampling discontinuous mode (triggered mode) 05512 * on the selected ADC group. 05513 * @note Number of oversampled conversions are done either in: 05514 * - continuous mode (all conversions of oversampling ratio 05515 * are done from 1 trigger) 05516 * - discontinuous mode (each conversion of oversampling ratio 05517 * needs a trigger) 05518 * @note On this STM32 serie, setting of this feature is conditioned to 05519 * ADC state: 05520 * ADC must be disabled or enabled without conversion on going 05521 * on group regular. 05522 * @note On this STM32 serie, oversampling discontinuous mode 05523 * (triggered mode) can be used only when oversampling is 05524 * set on group regular only and in resumed mode. 05525 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont 05526 * @param ADCx ADC instance 05527 * @param OverSamplingDiscont This parameter can be one of the following values: 05528 * @arg @ref LL_ADC_OVS_REG_CONT 05529 * @arg @ref LL_ADC_OVS_REG_DISCONT 05530 * @retval None 05531 */ 05532 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont) 05533 { 05534 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont); 05535 } 05536 05537 /** 05538 * @brief Get ADC oversampling discontinuous mode (triggered mode) 05539 * on the selected ADC group. 05540 * @note Number of oversampled conversions are done either in: 05541 * - continuous mode (all conversions of oversampling ratio 05542 * are done from 1 trigger) 05543 * - discontinuous mode (each conversion of oversampling ratio 05544 * needs a trigger) 05545 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont 05546 * @param ADCx ADC instance 05547 * @retval Returned value can be one of the following values: 05548 * @arg @ref LL_ADC_OVS_REG_CONT 05549 * @arg @ref LL_ADC_OVS_REG_DISCONT 05550 */ 05551 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) 05552 { 05553 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS)); 05554 } 05555 05556 /** 05557 * @brief Set ADC oversampling 05558 * (impacting both ADC groups regular and injected) 05559 * @note This function set the 2 items of oversampling configuration: 05560 * - ratio 05561 * - shift 05562 * @note On this STM32 serie, setting of this feature is conditioned to 05563 * ADC state: 05564 * ADC must be disabled or enabled without conversion on going 05565 * on either groups regular or injected. 05566 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n 05567 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift 05568 * @param ADCx ADC instance 05569 * @param Ratio This parameter can be one of the following values: 05570 * @arg @ref LL_ADC_OVS_RATIO_2 05571 * @arg @ref LL_ADC_OVS_RATIO_4 05572 * @arg @ref LL_ADC_OVS_RATIO_8 05573 * @arg @ref LL_ADC_OVS_RATIO_16 05574 * @arg @ref LL_ADC_OVS_RATIO_32 05575 * @arg @ref LL_ADC_OVS_RATIO_64 05576 * @arg @ref LL_ADC_OVS_RATIO_128 05577 * @arg @ref LL_ADC_OVS_RATIO_256 05578 * @param Shift This parameter can be one of the following values: 05579 * @arg @ref LL_ADC_OVS_SHIFT_NONE 05580 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 05581 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 05582 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 05583 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 05584 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 05585 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 05586 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 05587 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 05588 * @retval None 05589 */ 05590 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift) 05591 { 05592 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); 05593 } 05594 05595 /** 05596 * @brief Get ADC oversampling ratio 05597 * (impacting both ADC groups regular and injected) 05598 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio 05599 * @param ADCx ADC instance 05600 * @retval Ratio This parameter can be one of the following values: 05601 * @arg @ref LL_ADC_OVS_RATIO_2 05602 * @arg @ref LL_ADC_OVS_RATIO_4 05603 * @arg @ref LL_ADC_OVS_RATIO_8 05604 * @arg @ref LL_ADC_OVS_RATIO_16 05605 * @arg @ref LL_ADC_OVS_RATIO_32 05606 * @arg @ref LL_ADC_OVS_RATIO_64 05607 * @arg @ref LL_ADC_OVS_RATIO_128 05608 * @arg @ref LL_ADC_OVS_RATIO_256 05609 */ 05610 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) 05611 { 05612 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); 05613 } 05614 05615 /** 05616 * @brief Get ADC oversampling shift 05617 * (impacting both ADC groups regular and injected) 05618 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift 05619 * @param ADCx ADC instance 05620 * @retval Shift This parameter can be one of the following values: 05621 * @arg @ref LL_ADC_OVS_SHIFT_NONE 05622 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 05623 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 05624 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 05625 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 05626 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 05627 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 05628 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 05629 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 05630 */ 05631 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) 05632 { 05633 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); 05634 } 05635 05636 /** 05637 * @} 05638 */ 05639 05640 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode 05641 * @{ 05642 */ 05643 05644 #if defined(ADC_MULTIMODE_SUPPORT) 05645 /** 05646 * @brief Set ADC multimode configuration to operate in independent mode 05647 * or multimode (for devices with several ADC instances). 05648 * @note If multimode configuration: the selected ADC instance is 05649 * either master or slave depending on hardware. 05650 * Refer to reference manual. 05651 * @note On this STM32 serie, setting of this feature is conditioned to 05652 * ADC state: 05653 * All ADC instances of the ADC common group must be disabled. 05654 * This check can be done with function @ref LL_ADC_IsEnabled() for each 05655 * ADC instance or by using helper macro 05656 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). 05657 * @rmtoll CCR DUAL LL_ADC_SetMultimode 05658 * @param ADCxy_COMMON ADC common instance 05659 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 05660 * @param Multimode This parameter can be one of the following values: 05661 * @arg @ref LL_ADC_MULTI_INDEPENDENT 05662 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT 05663 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL 05664 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT 05665 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN 05666 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM 05667 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT 05668 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM 05669 * @retval None 05670 */ 05671 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) 05672 { 05673 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode); 05674 } 05675 05676 /** 05677 * @brief Get ADC multimode configuration to operate in independent mode 05678 * or multimode (for devices with several ADC instances). 05679 * @note If multimode configuration: the selected ADC instance is 05680 * either master or slave depending on hardware. 05681 * Refer to reference manual. 05682 * @rmtoll CCR DUAL LL_ADC_GetMultimode 05683 * @param ADCxy_COMMON ADC common instance 05684 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 05685 * @retval Returned value can be one of the following values: 05686 * @arg @ref LL_ADC_MULTI_INDEPENDENT 05687 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT 05688 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL 05689 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT 05690 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN 05691 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM 05692 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT 05693 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM 05694 */ 05695 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) 05696 { 05697 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 05698 } 05699 05700 /** 05701 * @brief Set ADC multimode conversion data transfer: no transfer 05702 * or transfer by DMA. 05703 * @note If ADC multimode transfer by DMA is not selected: 05704 * each ADC uses its own DMA channel, with its individual 05705 * DMA transfer settings. 05706 * If ADC multimode transfer by DMA is selected: 05707 * One DMA channel is used for both ADC (DMA of ADC master) 05708 * Specifies the DMA requests mode: 05709 * - Limited mode (One shot mode): DMA transfer requests are stopped 05710 * when number of DMA data transfers (number of 05711 * ADC conversions) is reached. 05712 * This ADC mode is intended to be used with DMA mode non-circular. 05713 * - Unlimited mode: DMA transfer requests are unlimited, 05714 * whatever number of DMA data transfers (number of 05715 * ADC conversions). 05716 * This ADC mode is intended to be used with DMA mode circular. 05717 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 05718 * mode non-circular: 05719 * when DMA transfers size will be reached, DMA will stop transfers of 05720 * ADC conversions data ADC will raise an overrun error 05721 * (overrun flag and interruption if enabled). 05722 * @note How to retrieve multimode conversion data: 05723 * Whatever multimode transfer by DMA setting: using function 05724 * @ref LL_ADC_REG_ReadMultiConversionData32(). 05725 * If ADC multimode transfer by DMA is selected: conversion data 05726 * is a raw data with ADC master and slave concatenated. 05727 * A macro is available to get the conversion data of 05728 * ADC master or ADC slave: see helper macro 05729 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 05730 * @note On this STM32 serie, setting of this feature is conditioned to 05731 * ADC state: 05732 * All ADC instances of the ADC common group must be disabled 05733 * or enabled without conversion on going on group regular. 05734 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n 05735 * CCR DMACFG LL_ADC_SetMultiDMATransfer 05736 * @param ADCxy_COMMON ADC common instance 05737 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 05738 * @param MultiDMATransfer This parameter can be one of the following values: 05739 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC 05740 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B 05741 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B 05742 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B 05743 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B 05744 * @retval None 05745 */ 05746 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer) 05747 { 05748 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer); 05749 } 05750 05751 /** 05752 * @brief Get ADC multimode conversion data transfer: no transfer 05753 * or transfer by DMA. 05754 * @note If ADC multimode transfer by DMA is not selected: 05755 * each ADC uses its own DMA channel, with its individual 05756 * DMA transfer settings. 05757 * If ADC multimode transfer by DMA is selected: 05758 * One DMA channel is used for both ADC (DMA of ADC master) 05759 * Specifies the DMA requests mode: 05760 * - Limited mode (One shot mode): DMA transfer requests are stopped 05761 * when number of DMA data transfers (number of 05762 * ADC conversions) is reached. 05763 * This ADC mode is intended to be used with DMA mode non-circular. 05764 * - Unlimited mode: DMA transfer requests are unlimited, 05765 * whatever number of DMA data transfers (number of 05766 * ADC conversions). 05767 * This ADC mode is intended to be used with DMA mode circular. 05768 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 05769 * mode non-circular: 05770 * when DMA transfers size will be reached, DMA will stop transfers of 05771 * ADC conversions data ADC will raise an overrun error 05772 * (overrun flag and interruption if enabled). 05773 * @note How to retrieve multimode conversion data: 05774 * Whatever multimode transfer by DMA setting: using function 05775 * @ref LL_ADC_REG_ReadMultiConversionData32(). 05776 * If ADC multimode transfer by DMA is selected: conversion data 05777 * is a raw data with ADC master and slave concatenated. 05778 * A macro is available to get the conversion data of 05779 * ADC master or ADC slave: see helper macro 05780 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 05781 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n 05782 * CCR DMACFG LL_ADC_GetMultiDMATransfer 05783 * @param ADCxy_COMMON ADC common instance 05784 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 05785 * @retval Returned value can be one of the following values: 05786 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC 05787 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B 05788 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B 05789 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B 05790 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B 05791 */ 05792 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON) 05793 { 05794 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG)); 05795 } 05796 05797 /** 05798 * @brief Set ADC multimode delay between 2 sampling phases. 05799 * @note The sampling delay range depends on ADC resolution: 05800 * - ADC resolution 12 bits can have maximum delay of 12 cycles. 05801 * - ADC resolution 10 bits can have maximum delay of 10 cycles. 05802 * - ADC resolution 8 bits can have maximum delay of 8 cycles. 05803 * - ADC resolution 6 bits can have maximum delay of 6 cycles. 05804 * @note On this STM32 serie, setting of this feature is conditioned to 05805 * ADC state: 05806 * All ADC instances of the ADC common group must be disabled. 05807 * This check can be done with function @ref LL_ADC_IsEnabled() for each 05808 * ADC instance or by using helper macro helper macro 05809 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). 05810 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay 05811 * @param ADCxy_COMMON ADC common instance 05812 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 05813 * @param MultiTwoSamplingDelay This parameter can be one of the following values: 05814 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE 05815 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES 05816 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES 05817 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES 05818 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 05819 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1) 05820 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1) 05821 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2) 05822 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2) 05823 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2) 05824 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3) 05825 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3) 05826 * 05827 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n 05828 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n 05829 * (3) Parameter available only if ADC resolution is 12 bits. 05830 * @retval None 05831 */ 05832 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay) 05833 { 05834 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay); 05835 } 05836 05837 /** 05838 * @brief Get ADC multimode delay between 2 sampling phases. 05839 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay 05840 * @param ADCxy_COMMON ADC common instance 05841 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 05842 * @retval Returned value can be one of the following values: 05843 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE 05844 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES 05845 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES 05846 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES 05847 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 05848 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1) 05849 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1) 05850 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2) 05851 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2) 05852 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2) 05853 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3) 05854 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3) 05855 * 05856 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n 05857 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n 05858 * (3) Parameter available only if ADC resolution is 12 bits. 05859 */ 05860 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON) 05861 { 05862 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); 05863 } 05864 #endif /* ADC_MULTIMODE_SUPPORT */ 05865 05866 /** 05867 * @} 05868 */ 05869 /** @defgroup ADC_LL_EF_Configuration_Leg_Functions Configuration of ADC alternate functions name 05870 * @{ 05871 */ 05872 /* Old functions name kept for legacy purpose, to be replaced by the */ 05873 /* current functions name. */ 05874 __STATIC_INLINE void LL_ADC_REG_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 05875 { 05876 LL_ADC_REG_SetTriggerSource(ADCx, TriggerSource); 05877 } 05878 __STATIC_INLINE void LL_ADC_INJ_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 05879 { 05880 LL_ADC_INJ_SetTriggerSource(ADCx, TriggerSource); 05881 } 05882 05883 /** 05884 * @} 05885 */ 05886 05887 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance 05888 * @{ 05889 */ 05890 05891 /** 05892 * @brief Put ADC instance in deep power down state. 05893 * @note In case of ADC calibration necessary: When ADC is in deep-power-down 05894 * state, the internal analog calibration is lost. After exiting from 05895 * deep power down, calibration must be relaunched or calibration factor 05896 * (preliminarily saved) must be set back into calibration register. 05897 * @note On this STM32 serie, setting of this feature is conditioned to 05898 * ADC state: 05899 * ADC must be ADC disabled. 05900 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown 05901 * @param ADCx ADC instance 05902 * @retval None 05903 */ 05904 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx) 05905 { 05906 /* Note: Write register with some additional bits forced to state reset */ 05907 /* instead of modifying only the selected bit for this function, */ 05908 /* to not interfere with bits with HW property "rs". */ 05909 MODIFY_REG(ADCx->CR, 05910 ADC_CR_BITS_PROPERTY_RS, 05911 ADC_CR_DEEPPWD); 05912 } 05913 05914 /** 05915 * @brief Disable ADC deep power down mode. 05916 * @note In case of ADC calibration necessary: When ADC is in deep-power-down 05917 * state, the internal analog calibration is lost. After exiting from 05918 * deep power down, calibration must be relaunched or calibration factor 05919 * (preliminarily saved) must be set back into calibration register. 05920 * @note On this STM32 serie, setting of this feature is conditioned to 05921 * ADC state: 05922 * ADC must be ADC disabled. 05923 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown 05924 * @param ADCx ADC instance 05925 * @retval None 05926 */ 05927 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) 05928 { 05929 /* Note: Write register with some additional bits forced to state reset */ 05930 /* instead of modifying only the selected bit for this function, */ 05931 /* to not interfere with bits with HW property "rs". */ 05932 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); 05933 } 05934 05935 /** 05936 * @brief Get the selected ADC instance deep power down state. 05937 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled 05938 * @param ADCx ADC instance 05939 * @retval 0: deep power down is disabled, 1: deep power down is enabled. 05940 */ 05941 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) 05942 { 05943 return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)); 05944 } 05945 05946 /** 05947 * @brief Enable ADC instance internal voltage regulator. 05948 * @note On this STM32 serie, after ADC internal voltage regulator enable, 05949 * a delay for ADC internal voltage regulator stabilization 05950 * is required before performing a ADC calibration or ADC enable. 05951 * Refer to device datasheet, parameter tADCVREG_STUP. 05952 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US. 05953 * @note On this STM32 serie, setting of this feature is conditioned to 05954 * ADC state: 05955 * ADC must be ADC disabled. 05956 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator 05957 * @param ADCx ADC instance 05958 * @retval None 05959 */ 05960 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) 05961 { 05962 /* Note: Write register with some additional bits forced to state reset */ 05963 /* instead of modifying only the selected bit for this function, */ 05964 /* to not interfere with bits with HW property "rs". */ 05965 MODIFY_REG(ADCx->CR, 05966 ADC_CR_BITS_PROPERTY_RS, 05967 ADC_CR_ADVREGEN); 05968 } 05969 05970 /** 05971 * @brief Disable ADC internal voltage regulator. 05972 * @note On this STM32 serie, setting of this feature is conditioned to 05973 * ADC state: 05974 * ADC must be ADC disabled. 05975 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator 05976 * @param ADCx ADC instance 05977 * @retval None 05978 */ 05979 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) 05980 { 05981 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS)); 05982 } 05983 05984 /** 05985 * @brief Get the selected ADC instance internal voltage regulator state. 05986 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled 05987 * @param ADCx ADC instance 05988 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. 05989 */ 05990 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) 05991 { 05992 return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)); 05993 } 05994 05995 /** 05996 * @brief Enable the selected ADC instance. 05997 * @note On this STM32 serie, after ADC enable, a delay for 05998 * ADC internal analog stabilization is required before performing a 05999 * ADC conversion start. 06000 * Refer to device datasheet, parameter tSTAB. 06001 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC 06002 * is enabled and when conversion clock is active. 06003 * (not only core clock: this ADC has a dual clock domain) 06004 * @note On this STM32 serie, setting of this feature is conditioned to 06005 * ADC state: 06006 * ADC must be ADC disabled and ADC internal voltage regulator enabled. 06007 * @rmtoll CR ADEN LL_ADC_Enable 06008 * @param ADCx ADC instance 06009 * @retval None 06010 */ 06011 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) 06012 { 06013 /* Note: Write register with some additional bits forced to state reset */ 06014 /* instead of modifying only the selected bit for this function, */ 06015 /* to not interfere with bits with HW property "rs". */ 06016 MODIFY_REG(ADCx->CR, 06017 ADC_CR_BITS_PROPERTY_RS, 06018 ADC_CR_ADEN); 06019 } 06020 06021 /** 06022 * @brief Disable the selected ADC instance. 06023 * @note On this STM32 serie, setting of this feature is conditioned to 06024 * ADC state: 06025 * ADC must be not disabled. Must be enabled without conversion on going 06026 * on either groups regular or injected. 06027 * @rmtoll CR ADDIS LL_ADC_Disable 06028 * @param ADCx ADC instance 06029 * @retval None 06030 */ 06031 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) 06032 { 06033 /* Note: Write register with some additional bits forced to state reset */ 06034 /* instead of modifying only the selected bit for this function, */ 06035 /* to not interfere with bits with HW property "rs". */ 06036 MODIFY_REG(ADCx->CR, 06037 ADC_CR_BITS_PROPERTY_RS, 06038 ADC_CR_ADDIS); 06039 } 06040 06041 /** 06042 * @brief Get the selected ADC instance enable state. 06043 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC 06044 * is enabled and when conversion clock is active. 06045 * (not only core clock: this ADC has a dual clock domain) 06046 * @rmtoll CR ADEN LL_ADC_IsEnabled 06047 * @param ADCx ADC instance 06048 * @retval 0: ADC is disabled, 1: ADC is enabled. 06049 */ 06050 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) 06051 { 06052 return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)); 06053 } 06054 06055 /** 06056 * @brief Get the selected ADC instance disable state. 06057 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing 06058 * @param ADCx ADC instance 06059 * @retval 0: no ADC disable command on going. 06060 */ 06061 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) 06062 { 06063 return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)); 06064 } 06065 06066 /** 06067 * @brief Start ADC calibration in the mode single-ended 06068 * or differential (for devices with differential mode available). 06069 * @note On this STM32 serie, a minimum number of ADC clock cycles 06070 * are required between ADC end of calibration and ADC enable. 06071 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. 06072 * @note For devices with differential mode available: 06073 * Calibration of offset is specific to each of 06074 * single-ended and differential modes 06075 * (calibration run must be performed for each of these 06076 * differential modes, if used afterwards and if the application 06077 * requires their calibration). 06078 * @note On this STM32 serie, setting of this feature is conditioned to 06079 * ADC state: 06080 * ADC must be ADC disabled. 06081 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n 06082 * CR ADCALDIF LL_ADC_StartCalibration 06083 * @param ADCx ADC instance 06084 * @param SingleDiff This parameter can be one of the following values: 06085 * @arg @ref LL_ADC_SINGLE_ENDED 06086 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED 06087 * @retval None 06088 */ 06089 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff) 06090 { 06091 /* Note: Write register with some additional bits forced to state reset */ 06092 /* instead of modifying only the selected bit for this function, */ 06093 /* to not interfere with bits with HW property "rs". */ 06094 MODIFY_REG(ADCx->CR, 06095 ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS, 06096 ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK)); 06097 } 06098 06099 /** 06100 * @brief Get ADC calibration state. 06101 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing 06102 * @param ADCx ADC instance 06103 * @retval 0: calibration complete, 1: calibration in progress. 06104 */ 06105 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) 06106 { 06107 return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)); 06108 } 06109 06110 /** 06111 * @} 06112 */ 06113 06114 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular 06115 * @{ 06116 */ 06117 06118 /** 06119 * @brief Start ADC group regular conversion. 06120 * @note On this STM32 serie, this function is relevant for both 06121 * internal trigger (SW start) and external trigger: 06122 * - If ADC trigger has been set to software start, ADC conversion 06123 * starts immediately. 06124 * - If ADC trigger has been set to external trigger, ADC conversion 06125 * will start at next trigger event (on the selected trigger edge) 06126 * following the ADC start conversion command. 06127 * @note On this STM32 serie, setting of this feature is conditioned to 06128 * ADC state: 06129 * ADC must be enabled without conversion on going on group regular, 06130 * without conversion stop command on going on group regular, 06131 * without ADC disable command on going. 06132 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion 06133 * @param ADCx ADC instance 06134 * @retval None 06135 */ 06136 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) 06137 { 06138 /* Note: Write register with some additional bits forced to state reset */ 06139 /* instead of modifying only the selected bit for this function, */ 06140 /* to not interfere with bits with HW property "rs". */ 06141 MODIFY_REG(ADCx->CR, 06142 ADC_CR_BITS_PROPERTY_RS, 06143 ADC_CR_ADSTART); 06144 } 06145 06146 /** 06147 * @brief Stop ADC group regular conversion. 06148 * @note On this STM32 serie, setting of this feature is conditioned to 06149 * ADC state: 06150 * ADC must be enabled with conversion on going on group regular, 06151 * without ADC disable command on going. 06152 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion 06153 * @param ADCx ADC instance 06154 * @retval None 06155 */ 06156 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) 06157 { 06158 /* Note: Write register with some additional bits forced to state reset */ 06159 /* instead of modifying only the selected bit for this function, */ 06160 /* to not interfere with bits with HW property "rs". */ 06161 MODIFY_REG(ADCx->CR, 06162 ADC_CR_BITS_PROPERTY_RS, 06163 ADC_CR_ADSTP); 06164 } 06165 06166 /** 06167 * @brief Get ADC group regular conversion state. 06168 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing 06169 * @param ADCx ADC instance 06170 * @retval 0: no conversion is on going on ADC group regular. 06171 */ 06172 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) 06173 { 06174 return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)); 06175 } 06176 06177 /** 06178 * @brief Get ADC group regular command of conversion stop state 06179 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing 06180 * @param ADCx ADC instance 06181 * @retval 0: no command of conversion stop is on going on ADC group regular. 06182 */ 06183 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) 06184 { 06185 return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)); 06186 } 06187 06188 /** 06189 * @brief Get ADC group regular conversion data, range fit for 06190 * all ADC configurations: all ADC resolutions and 06191 * all oversampling increased data width (for devices 06192 * with feature oversampling). 06193 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 06194 * @param ADCx ADC instance 06195 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 06196 */ 06197 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) 06198 { 06199 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); 06200 } 06201 06202 /** 06203 * @brief Get ADC group regular conversion data, range fit for 06204 * ADC resolution 12 bits. 06205 * @note For devices with feature oversampling: Oversampling 06206 * can increase data width, function for extended range 06207 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 06208 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 06209 * @param ADCx ADC instance 06210 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 06211 */ 06212 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) 06213 { 06214 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); 06215 } 06216 06217 /** 06218 * @brief Get ADC group regular conversion data, range fit for 06219 * ADC resolution 10 bits. 06220 * @note For devices with feature oversampling: Oversampling 06221 * can increase data width, function for extended range 06222 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 06223 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10 06224 * @param ADCx ADC instance 06225 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 06226 */ 06227 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) 06228 { 06229 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); 06230 } 06231 06232 /** 06233 * @brief Get ADC group regular conversion data, range fit for 06234 * ADC resolution 8 bits. 06235 * @note For devices with feature oversampling: Oversampling 06236 * can increase data width, function for extended range 06237 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 06238 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8 06239 * @param ADCx ADC instance 06240 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 06241 */ 06242 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) 06243 { 06244 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); 06245 } 06246 06247 /** 06248 * @brief Get ADC group regular conversion data, range fit for 06249 * ADC resolution 6 bits. 06250 * @note For devices with feature oversampling: Oversampling 06251 * can increase data width, function for extended range 06252 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 06253 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6 06254 * @param ADCx ADC instance 06255 * @retval Value between Min_Data=0x00 and Max_Data=0x3F 06256 */ 06257 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) 06258 { 06259 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); 06260 } 06261 06262 #if defined(ADC_MULTIMODE_SUPPORT) 06263 /** 06264 * @brief Get ADC multimode conversion data of ADC master, ADC slave 06265 * or raw data with ADC master and slave concatenated. 06266 * @note If raw data with ADC master and slave concatenated is retrieved, 06267 * a macro is available to get the conversion data of 06268 * ADC master or ADC slave: see helper macro 06269 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 06270 * (however this macro is mainly intended for multimode 06271 * transfer by DMA, because this function can do the same 06272 * by getting multimode conversion data of ADC master or ADC slave 06273 * separately). 06274 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n 06275 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32 06276 * @param ADCxy_COMMON ADC common instance 06277 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06278 * @param ConversionData This parameter can be one of the following values: 06279 * @arg @ref LL_ADC_MULTI_MASTER 06280 * @arg @ref LL_ADC_MULTI_SLAVE 06281 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE 06282 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 06283 */ 06284 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) 06285 { 06286 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, 06287 ConversionData) 06288 >> POSITION_VAL(ConversionData) 06289 ); 06290 } 06291 #endif /* ADC_MULTIMODE_SUPPORT */ 06292 06293 /** 06294 * @} 06295 */ 06296 06297 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected 06298 * @{ 06299 */ 06300 06301 /** 06302 * @brief Start ADC group injected conversion. 06303 * @note On this STM32 serie, this function is relevant for both 06304 * internal trigger (SW start) and external trigger: 06305 * - If ADC trigger has been set to software start, ADC conversion 06306 * starts immediately. 06307 * - If ADC trigger has been set to external trigger, ADC conversion 06308 * will start at next trigger event (on the selected trigger edge) 06309 * following the ADC start conversion command. 06310 * @note On this STM32 serie, setting of this feature is conditioned to 06311 * ADC state: 06312 * ADC must be enabled without conversion on going on group injected, 06313 * without conversion stop command on going on group injected, 06314 * without ADC disable command on going. 06315 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion 06316 * @param ADCx ADC instance 06317 * @retval None 06318 */ 06319 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx) 06320 { 06321 /* Note: Write register with some additional bits forced to state reset */ 06322 /* instead of modifying only the selected bit for this function, */ 06323 /* to not interfere with bits with HW property "rs". */ 06324 MODIFY_REG(ADCx->CR, 06325 ADC_CR_BITS_PROPERTY_RS, 06326 ADC_CR_JADSTART); 06327 } 06328 06329 /** 06330 * @brief Stop ADC group injected conversion. 06331 * @note On this STM32 serie, setting of this feature is conditioned to 06332 * ADC state: 06333 * ADC must be enabled with conversion on going on group injected, 06334 * without ADC disable command on going. 06335 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion 06336 * @param ADCx ADC instance 06337 * @retval None 06338 */ 06339 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) 06340 { 06341 /* Note: Write register with some additional bits forced to state reset */ 06342 /* instead of modifying only the selected bit for this function, */ 06343 /* to not interfere with bits with HW property "rs". */ 06344 MODIFY_REG(ADCx->CR, 06345 ADC_CR_BITS_PROPERTY_RS, 06346 ADC_CR_JADSTP); 06347 } 06348 06349 /** 06350 * @brief Get ADC group injected conversion state. 06351 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing 06352 * @param ADCx ADC instance 06353 * @retval 0: no conversion is on going on ADC group injected. 06354 */ 06355 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) 06356 { 06357 return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)); 06358 } 06359 06360 /** 06361 * @brief Get ADC group injected command of conversion stop state 06362 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing 06363 * @param ADCx ADC instance 06364 * @retval 0: no command of conversion stop is on going on ADC group injected. 06365 */ 06366 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) 06367 { 06368 return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)); 06369 } 06370 06371 /** 06372 * @brief Get ADC group regular conversion data, range fit for 06373 * all ADC configurations: all ADC resolutions and 06374 * all oversampling increased data width (for devices 06375 * with feature oversampling). 06376 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n 06377 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n 06378 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n 06379 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 06380 * @param ADCx ADC instance 06381 * @param Rank This parameter can be one of the following values: 06382 * @arg @ref LL_ADC_INJ_RANK_1 06383 * @arg @ref LL_ADC_INJ_RANK_2 06384 * @arg @ref LL_ADC_INJ_RANK_3 06385 * @arg @ref LL_ADC_INJ_RANK_4 06386 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 06387 */ 06388 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) 06389 { 06390 #if defined(CORE_CM0PLUS) 06391 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); 06392 #else 06393 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 06394 #endif 06395 06396 return (uint32_t)(READ_BIT(*preg, 06397 ADC_JDR1_JDATA) 06398 ); 06399 } 06400 06401 /** 06402 * @brief Get ADC group injected conversion data, range fit for 06403 * ADC resolution 12 bits. 06404 * @note For devices with feature oversampling: Oversampling 06405 * can increase data width, function for extended range 06406 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 06407 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n 06408 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n 06409 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n 06410 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 06411 * @param ADCx ADC instance 06412 * @param Rank This parameter can be one of the following values: 06413 * @arg @ref LL_ADC_INJ_RANK_1 06414 * @arg @ref LL_ADC_INJ_RANK_2 06415 * @arg @ref LL_ADC_INJ_RANK_3 06416 * @arg @ref LL_ADC_INJ_RANK_4 06417 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 06418 */ 06419 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) 06420 { 06421 #if defined(CORE_CM0PLUS) 06422 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); 06423 #else 06424 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 06425 #endif 06426 06427 return (uint16_t)(READ_BIT(*preg, 06428 ADC_JDR1_JDATA) 06429 ); 06430 } 06431 06432 /** 06433 * @brief Get ADC group injected conversion data, range fit for 06434 * ADC resolution 10 bits. 06435 * @note For devices with feature oversampling: Oversampling 06436 * can increase data width, function for extended range 06437 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 06438 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n 06439 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n 06440 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n 06441 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10 06442 * @param ADCx ADC instance 06443 * @param Rank This parameter can be one of the following values: 06444 * @arg @ref LL_ADC_INJ_RANK_1 06445 * @arg @ref LL_ADC_INJ_RANK_2 06446 * @arg @ref LL_ADC_INJ_RANK_3 06447 * @arg @ref LL_ADC_INJ_RANK_4 06448 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 06449 */ 06450 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) 06451 { 06452 #if defined(CORE_CM0PLUS) 06453 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); 06454 #else 06455 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 06456 #endif 06457 06458 return (uint16_t)(READ_BIT(*preg, 06459 ADC_JDR1_JDATA) 06460 ); 06461 } 06462 06463 /** 06464 * @brief Get ADC group injected conversion data, range fit for 06465 * ADC resolution 8 bits. 06466 * @note For devices with feature oversampling: Oversampling 06467 * can increase data width, function for extended range 06468 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 06469 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n 06470 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n 06471 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n 06472 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8 06473 * @param ADCx ADC instance 06474 * @param Rank This parameter can be one of the following values: 06475 * @arg @ref LL_ADC_INJ_RANK_1 06476 * @arg @ref LL_ADC_INJ_RANK_2 06477 * @arg @ref LL_ADC_INJ_RANK_3 06478 * @arg @ref LL_ADC_INJ_RANK_4 06479 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 06480 */ 06481 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) 06482 { 06483 #if defined(CORE_CM0PLUS) 06484 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); 06485 #else 06486 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 06487 #endif 06488 06489 return (uint8_t)(READ_BIT(*preg, 06490 ADC_JDR1_JDATA) 06491 ); 06492 } 06493 06494 /** 06495 * @brief Get ADC group injected conversion data, range fit for 06496 * ADC resolution 6 bits. 06497 * @note For devices with feature oversampling: Oversampling 06498 * can increase data width, function for extended range 06499 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 06500 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n 06501 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n 06502 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n 06503 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6 06504 * @param ADCx ADC instance 06505 * @param Rank This parameter can be one of the following values: 06506 * @arg @ref LL_ADC_INJ_RANK_1 06507 * @arg @ref LL_ADC_INJ_RANK_2 06508 * @arg @ref LL_ADC_INJ_RANK_3 06509 * @arg @ref LL_ADC_INJ_RANK_4 06510 * @retval Value between Min_Data=0x00 and Max_Data=0x3F 06511 */ 06512 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) 06513 { 06514 #if defined(CORE_CM0PLUS) 06515 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); 06516 #else 06517 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 06518 #endif 06519 06520 return (uint8_t)(READ_BIT(*preg, 06521 ADC_JDR1_JDATA) 06522 ); 06523 } 06524 06525 /** 06526 * @} 06527 */ 06528 06529 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management 06530 * @{ 06531 */ 06532 06533 /** 06534 * @brief Get flag ADC ready. 06535 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC 06536 * is enabled and when conversion clock is active. 06537 * (not only core clock: this ADC has a dual clock domain) 06538 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY 06539 * @param ADCx ADC instance 06540 * @retval State of bit (1 or 0). 06541 */ 06542 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) 06543 { 06544 return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)); 06545 } 06546 06547 /** 06548 * @brief Get flag ADC group regular end of unitary conversion. 06549 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC 06550 * @param ADCx ADC instance 06551 * @retval State of bit (1 or 0). 06552 */ 06553 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) 06554 { 06555 return (uint32_t)(READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)); 06556 } 06557 06558 /** 06559 * @brief Get flag ADC group regular end of sequence conversions. 06560 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS 06561 * @param ADCx ADC instance 06562 * @retval State of bit (1 or 0). 06563 */ 06564 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) 06565 { 06566 return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)); 06567 } 06568 06569 /** 06570 * @brief Get flag ADC group regular overrun. 06571 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR 06572 * @param ADCx ADC instance 06573 * @retval State of bit (1 or 0). 06574 */ 06575 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) 06576 { 06577 return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)); 06578 } 06579 06580 /** 06581 * @brief Get flag ADC group regular end of sampling phase. 06582 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP 06583 * @param ADCx ADC instance 06584 * @retval State of bit (1 or 0). 06585 */ 06586 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) 06587 { 06588 return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)); 06589 } 06590 06591 /** 06592 * @brief Get flag ADC group injected end of unitary conversion. 06593 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC 06594 * @param ADCx ADC instance 06595 * @retval State of bit (1 or 0). 06596 */ 06597 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) 06598 { 06599 return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)); 06600 } 06601 06602 /** 06603 * @brief Get flag ADC group injected end of sequence conversions. 06604 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS 06605 * @param ADCx ADC instance 06606 * @retval State of bit (1 or 0). 06607 */ 06608 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) 06609 { 06610 return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); 06611 } 06612 06613 /** 06614 * @brief Get flag ADC group injected contexts queue overflow. 06615 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF 06616 * @param ADCx ADC instance 06617 * @retval State of bit (1 or 0). 06618 */ 06619 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) 06620 { 06621 return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)); 06622 } 06623 06624 /** 06625 * @brief Get flag ADC analog watchdog 1 flag 06626 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1 06627 * @param ADCx ADC instance 06628 * @retval State of bit (1 or 0). 06629 */ 06630 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) 06631 { 06632 return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); 06633 } 06634 06635 /** 06636 * @brief Get flag ADC analog watchdog 2. 06637 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2 06638 * @param ADCx ADC instance 06639 * @retval State of bit (1 or 0). 06640 */ 06641 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) 06642 { 06643 return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)); 06644 } 06645 06646 /** 06647 * @brief Get flag ADC analog watchdog 3. 06648 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3 06649 * @param ADCx ADC instance 06650 * @retval State of bit (1 or 0). 06651 */ 06652 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) 06653 { 06654 return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)); 06655 } 06656 06657 /** 06658 * @brief Clear flag ADC ready. 06659 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC 06660 * is enabled and when conversion clock is active. 06661 * (not only core clock: this ADC has a dual clock domain) 06662 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY 06663 * @param ADCx ADC instance 06664 * @retval None 06665 */ 06666 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx) 06667 { 06668 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY); 06669 } 06670 06671 /** 06672 * @brief Clear flag ADC group regular end of unitary conversion. 06673 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC 06674 * @param ADCx ADC instance 06675 * @retval None 06676 */ 06677 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx) 06678 { 06679 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC); 06680 } 06681 06682 /** 06683 * @brief Clear flag ADC group regular end of sequence conversions. 06684 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS 06685 * @param ADCx ADC instance 06686 * @retval None 06687 */ 06688 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) 06689 { 06690 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS); 06691 } 06692 06693 /** 06694 * @brief Clear flag ADC group regular overrun. 06695 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR 06696 * @param ADCx ADC instance 06697 * @retval None 06698 */ 06699 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) 06700 { 06701 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR); 06702 } 06703 06704 /** 06705 * @brief Clear flag ADC group regular end of sampling phase. 06706 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP 06707 * @param ADCx ADC instance 06708 * @retval None 06709 */ 06710 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx) 06711 { 06712 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP); 06713 } 06714 06715 /** 06716 * @brief Clear flag ADC group injected end of unitary conversion. 06717 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC 06718 * @param ADCx ADC instance 06719 * @retval None 06720 */ 06721 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx) 06722 { 06723 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC); 06724 } 06725 06726 /** 06727 * @brief Clear flag ADC group injected end of sequence conversions. 06728 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS 06729 * @param ADCx ADC instance 06730 * @retval None 06731 */ 06732 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) 06733 { 06734 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS); 06735 } 06736 06737 /** 06738 * @brief Clear flag ADC group injected contexts queue overflow. 06739 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF 06740 * @param ADCx ADC instance 06741 * @retval None 06742 */ 06743 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx) 06744 { 06745 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF); 06746 } 06747 06748 /** 06749 * @brief Clear flag ADC analog watchdog 1. 06750 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1 06751 * @param ADCx ADC instance 06752 * @retval None 06753 */ 06754 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) 06755 { 06756 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1); 06757 } 06758 06759 /** 06760 * @brief Clear flag ADC analog watchdog 2. 06761 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2 06762 * @param ADCx ADC instance 06763 * @retval None 06764 */ 06765 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx) 06766 { 06767 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2); 06768 } 06769 06770 /** 06771 * @brief Clear flag ADC analog watchdog 3. 06772 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3 06773 * @param ADCx ADC instance 06774 * @retval None 06775 */ 06776 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) 06777 { 06778 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3); 06779 } 06780 06781 #if defined(ADC_MULTIMODE_SUPPORT) 06782 /** 06783 * @brief Get flag multimode ADC ready of the ADC master. 06784 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY 06785 * @param ADCxy_COMMON ADC common instance 06786 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06787 * @retval State of bit (1 or 0). 06788 */ 06789 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) 06790 { 06791 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)); 06792 } 06793 06794 /** 06795 * @brief Get flag multimode ADC ready of the ADC slave. 06796 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY 06797 * @param ADCxy_COMMON ADC common instance 06798 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06799 * @retval State of bit (1 or 0). 06800 */ 06801 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) 06802 { 06803 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)); 06804 } 06805 06806 /** 06807 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master. 06808 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC 06809 * @param ADCxy_COMMON ADC common instance 06810 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06811 * @retval State of bit (1 or 0). 06812 */ 06813 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON) 06814 { 06815 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)); 06816 } 06817 06818 /** 06819 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave. 06820 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC 06821 * @param ADCxy_COMMON ADC common instance 06822 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06823 * @retval State of bit (1 or 0). 06824 */ 06825 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON) 06826 { 06827 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)); 06828 } 06829 06830 /** 06831 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master. 06832 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS 06833 * @param ADCxy_COMMON ADC common instance 06834 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06835 * @retval State of bit (1 or 0). 06836 */ 06837 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) 06838 { 06839 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)); 06840 } 06841 06842 /** 06843 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave. 06844 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS 06845 * @param ADCxy_COMMON ADC common instance 06846 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06847 * @retval State of bit (1 or 0). 06848 */ 06849 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) 06850 { 06851 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)); 06852 } 06853 06854 /** 06855 * @brief Get flag multimode ADC group regular overrun of the ADC master. 06856 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR 06857 * @param ADCxy_COMMON ADC common instance 06858 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06859 * @retval State of bit (1 or 0). 06860 */ 06861 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) 06862 { 06863 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)); 06864 } 06865 06866 /** 06867 * @brief Get flag multimode ADC group regular overrun of the ADC slave. 06868 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR 06869 * @param ADCxy_COMMON ADC common instance 06870 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06871 * @retval State of bit (1 or 0). 06872 */ 06873 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON) 06874 { 06875 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)); 06876 } 06877 06878 /** 06879 * @brief Get flag multimode ADC group regular end of sampling of the ADC master. 06880 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP 06881 * @param ADCxy_COMMON ADC common instance 06882 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06883 * @retval State of bit (1 or 0). 06884 */ 06885 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) 06886 { 06887 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)); 06888 } 06889 06890 /** 06891 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave. 06892 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP 06893 * @param ADCxy_COMMON ADC common instance 06894 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06895 * @retval State of bit (1 or 0). 06896 */ 06897 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) 06898 { 06899 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)); 06900 } 06901 06902 /** 06903 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master. 06904 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC 06905 * @param ADCxy_COMMON ADC common instance 06906 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06907 * @retval State of bit (1 or 0). 06908 */ 06909 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) 06910 { 06911 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)); 06912 } 06913 06914 /** 06915 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave. 06916 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC 06917 * @param ADCxy_COMMON ADC common instance 06918 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06919 * @retval State of bit (1 or 0). 06920 */ 06921 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) 06922 { 06923 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)); 06924 } 06925 06926 /** 06927 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. 06928 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS 06929 * @param ADCxy_COMMON ADC common instance 06930 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06931 * @retval State of bit (1 or 0). 06932 */ 06933 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) 06934 { 06935 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)); 06936 } 06937 06938 /** 06939 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave. 06940 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS 06941 * @param ADCxy_COMMON ADC common instance 06942 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06943 * @retval State of bit (1 or 0). 06944 */ 06945 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) 06946 { 06947 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)); 06948 } 06949 06950 /** 06951 * @brief Get flag multimode ADC group injected context queue overflow of the ADC master. 06952 * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF 06953 * @param ADCxy_COMMON ADC common instance 06954 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06955 * @retval State of bit (1 or 0). 06956 */ 06957 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) 06958 { 06959 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)); 06960 } 06961 06962 /** 06963 * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave. 06964 * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF 06965 * @param ADCxy_COMMON ADC common instance 06966 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06967 * @retval State of bit (1 or 0). 06968 */ 06969 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) 06970 { 06971 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)); 06972 } 06973 06974 /** 06975 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. 06976 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1 06977 * @param ADCxy_COMMON ADC common instance 06978 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06979 * @retval State of bit (1 or 0). 06980 */ 06981 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) 06982 { 06983 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)); 06984 } 06985 06986 /** 06987 * @brief Get flag multimode analog watchdog 1 of the ADC slave. 06988 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1 06989 * @param ADCxy_COMMON ADC common instance 06990 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 06991 * @retval State of bit (1 or 0). 06992 */ 06993 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) 06994 { 06995 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)); 06996 } 06997 06998 /** 06999 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master. 07000 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2 07001 * @param ADCxy_COMMON ADC common instance 07002 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 07003 * @retval State of bit (1 or 0). 07004 */ 07005 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) 07006 { 07007 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)); 07008 } 07009 07010 /** 07011 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave. 07012 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2 07013 * @param ADCxy_COMMON ADC common instance 07014 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 07015 * @retval State of bit (1 or 0). 07016 */ 07017 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) 07018 { 07019 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)); 07020 } 07021 07022 /** 07023 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master. 07024 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3 07025 * @param ADCxy_COMMON ADC common instance 07026 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 07027 * @retval State of bit (1 or 0). 07028 */ 07029 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) 07030 { 07031 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)); 07032 } 07033 07034 /** 07035 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave. 07036 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3 07037 * @param ADCxy_COMMON ADC common instance 07038 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 07039 * @retval State of bit (1 or 0). 07040 */ 07041 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) 07042 { 07043 return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)); 07044 } 07045 #endif /* ADC_MULTIMODE_SUPPORT */ 07046 07047 /** 07048 * @} 07049 */ 07050 07051 /** @defgroup ADC_LL_EF_IT_Management ADC IT management 07052 * @{ 07053 */ 07054 07055 /** 07056 * @brief Enable ADC ready. 07057 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY 07058 * @param ADCx ADC instance 07059 * @retval None 07060 */ 07061 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx) 07062 { 07063 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY); 07064 } 07065 07066 /** 07067 * @brief Enable interruption ADC group regular end of unitary conversion. 07068 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC 07069 * @param ADCx ADC instance 07070 * @retval None 07071 */ 07072 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx) 07073 { 07074 SET_BIT(ADCx->IER, LL_ADC_IT_EOC); 07075 } 07076 07077 /** 07078 * @brief Enable interruption ADC group regular end of sequence conversions. 07079 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS 07080 * @param ADCx ADC instance 07081 * @retval None 07082 */ 07083 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) 07084 { 07085 SET_BIT(ADCx->IER, LL_ADC_IT_EOS); 07086 } 07087 07088 /** 07089 * @brief Enable ADC group regular interruption overrun. 07090 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR 07091 * @param ADCx ADC instance 07092 * @retval None 07093 */ 07094 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) 07095 { 07096 SET_BIT(ADCx->IER, LL_ADC_IT_OVR); 07097 } 07098 07099 /** 07100 * @brief Enable interruption ADC group regular end of sampling. 07101 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP 07102 * @param ADCx ADC instance 07103 * @retval None 07104 */ 07105 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx) 07106 { 07107 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP); 07108 } 07109 07110 /** 07111 * @brief Enable interruption ADC group injected end of unitary conversion. 07112 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC 07113 * @param ADCx ADC instance 07114 * @retval None 07115 */ 07116 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx) 07117 { 07118 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC); 07119 } 07120 07121 /** 07122 * @brief Enable interruption ADC group injected end of sequence conversions. 07123 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS 07124 * @param ADCx ADC instance 07125 * @retval None 07126 */ 07127 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) 07128 { 07129 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS); 07130 } 07131 07132 /** 07133 * @brief Enable interruption ADC group injected context queue overflow. 07134 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF 07135 * @param ADCx ADC instance 07136 * @retval None 07137 */ 07138 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx) 07139 { 07140 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF); 07141 } 07142 07143 /** 07144 * @brief Enable interruption ADC analog watchdog 1. 07145 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1 07146 * @param ADCx ADC instance 07147 * @retval None 07148 */ 07149 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) 07150 { 07151 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1); 07152 } 07153 07154 /** 07155 * @brief Enable interruption ADC analog watchdog 2. 07156 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2 07157 * @param ADCx ADC instance 07158 * @retval None 07159 */ 07160 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx) 07161 { 07162 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2); 07163 } 07164 07165 /** 07166 * @brief Enable interruption ADC analog watchdog 3. 07167 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3 07168 * @param ADCx ADC instance 07169 * @retval None 07170 */ 07171 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx) 07172 { 07173 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3); 07174 } 07175 07176 /** 07177 * @brief Disable interruption ADC ready. 07178 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY 07179 * @param ADCx ADC instance 07180 * @retval None 07181 */ 07182 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx) 07183 { 07184 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY); 07185 } 07186 07187 /** 07188 * @brief Disable interruption ADC group regular end of unitary conversion. 07189 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC 07190 * @param ADCx ADC instance 07191 * @retval None 07192 */ 07193 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx) 07194 { 07195 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC); 07196 } 07197 07198 /** 07199 * @brief Disable interruption ADC group regular end of sequence conversions. 07200 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS 07201 * @param ADCx ADC instance 07202 * @retval None 07203 */ 07204 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) 07205 { 07206 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS); 07207 } 07208 07209 /** 07210 * @brief Disable interruption ADC group regular overrun. 07211 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR 07212 * @param ADCx ADC instance 07213 * @retval None 07214 */ 07215 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) 07216 { 07217 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR); 07218 } 07219 07220 /** 07221 * @brief Disable interruption ADC group regular end of sampling. 07222 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP 07223 * @param ADCx ADC instance 07224 * @retval None 07225 */ 07226 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx) 07227 { 07228 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP); 07229 } 07230 07231 /** 07232 * @brief Disable interruption ADC group regular end of unitary conversion. 07233 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC 07234 * @param ADCx ADC instance 07235 * @retval None 07236 */ 07237 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx) 07238 { 07239 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC); 07240 } 07241 07242 /** 07243 * @brief Disable interruption ADC group injected end of sequence conversions. 07244 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS 07245 * @param ADCx ADC instance 07246 * @retval None 07247 */ 07248 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) 07249 { 07250 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS); 07251 } 07252 07253 /** 07254 * @brief Disable interruption ADC group injected context queue overflow. 07255 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF 07256 * @param ADCx ADC instance 07257 * @retval None 07258 */ 07259 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx) 07260 { 07261 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF); 07262 } 07263 07264 /** 07265 * @brief Disable interruption ADC analog watchdog 1. 07266 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1 07267 * @param ADCx ADC instance 07268 * @retval None 07269 */ 07270 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) 07271 { 07272 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1); 07273 } 07274 07275 /** 07276 * @brief Disable interruption ADC analog watchdog 2. 07277 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2 07278 * @param ADCx ADC instance 07279 * @retval None 07280 */ 07281 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx) 07282 { 07283 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2); 07284 } 07285 07286 /** 07287 * @brief Disable interruption ADC analog watchdog 3. 07288 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3 07289 * @param ADCx ADC instance 07290 * @retval None 07291 */ 07292 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) 07293 { 07294 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3); 07295 } 07296 07297 /** 07298 * @brief Get state of interruption ADC ready 07299 * (0: interrupt disabled, 1: interrupt enabled). 07300 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY 07301 * @param ADCx ADC instance 07302 * @retval State of bit (1 or 0). 07303 */ 07304 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) 07305 { 07306 return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)); 07307 } 07308 07309 /** 07310 * @brief Get state of interruption ADC group regular end of unitary conversion 07311 * (0: interrupt disabled, 1: interrupt enabled). 07312 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC 07313 * @param ADCx ADC instance 07314 * @retval State of bit (1 or 0). 07315 */ 07316 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) 07317 { 07318 return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)); 07319 } 07320 07321 /** 07322 * @brief Get state of interruption ADC group regular end of sequence conversions 07323 * (0: interrupt disabled, 1: interrupt enabled). 07324 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS 07325 * @param ADCx ADC instance 07326 * @retval State of bit (1 or 0). 07327 */ 07328 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) 07329 { 07330 return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)); 07331 } 07332 07333 /** 07334 * @brief Get state of interruption ADC group regular overrun 07335 * (0: interrupt disabled, 1: interrupt enabled). 07336 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR 07337 * @param ADCx ADC instance 07338 * @retval State of bit (1 or 0). 07339 */ 07340 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) 07341 { 07342 return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)); 07343 } 07344 07345 /** 07346 * @brief Get state of interruption ADC group regular end of sampling 07347 * (0: interrupt disabled, 1: interrupt enabled). 07348 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP 07349 * @param ADCx ADC instance 07350 * @retval State of bit (1 or 0). 07351 */ 07352 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) 07353 { 07354 return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)); 07355 } 07356 07357 /** 07358 * @brief Get state of interruption ADC group injected end of unitary conversion 07359 * (0: interrupt disabled, 1: interrupt enabled). 07360 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC 07361 * @param ADCx ADC instance 07362 * @retval State of bit (1 or 0). 07363 */ 07364 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) 07365 { 07366 return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)); 07367 } 07368 07369 /** 07370 * @brief Get state of interruption ADC group injected end of sequence conversions 07371 * (0: interrupt disabled, 1: interrupt enabled). 07372 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS 07373 * @param ADCx ADC instance 07374 * @retval State of bit (1 or 0). 07375 */ 07376 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) 07377 { 07378 return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); 07379 } 07380 07381 /** 07382 * @brief Get state of interruption ADC group injected context queue overflow interrupt state 07383 * (0: interrupt disabled, 1: interrupt enabled). 07384 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF 07385 * @param ADCx ADC instance 07386 * @retval State of bit (1 or 0). 07387 */ 07388 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) 07389 { 07390 return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)); 07391 } 07392 07393 /** 07394 * @brief Get state of interruption ADC analog watchdog 1 07395 * (0: interrupt disabled, 1: interrupt enabled). 07396 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1 07397 * @param ADCx ADC instance 07398 * @retval State of bit (1 or 0). 07399 */ 07400 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) 07401 { 07402 return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); 07403 } 07404 07405 /** 07406 * @brief Get state of interruption Get ADC analog watchdog 2 07407 * (0: interrupt disabled, 1: interrupt enabled). 07408 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2 07409 * @param ADCx ADC instance 07410 * @retval State of bit (1 or 0). 07411 */ 07412 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) 07413 { 07414 return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)); 07415 } 07416 07417 /** 07418 * @brief Get state of interruption Get ADC analog watchdog 3 07419 * (0: interrupt disabled, 1: interrupt enabled). 07420 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3 07421 * @param ADCx ADC instance 07422 * @retval State of bit (1 or 0). 07423 */ 07424 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) 07425 { 07426 return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)); 07427 } 07428 07429 /** 07430 * @} 07431 */ 07432 07433 #if defined(USE_FULL_LL_DRIVER) 07434 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions 07435 * @{ 07436 */ 07437 07438 /* Initialization of some features of ADC common parameters and multimode */ 07439 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); 07440 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); 07441 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); 07442 07443 /* De-initialization of ADC instance, ADC group regular and ADC group injected */ 07444 /* (availability of ADC group injected depends on STM32 families) */ 07445 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); 07446 07447 /* Initialization of some features of ADC instance */ 07448 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); 07449 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); 07450 07451 /* Initialization of some features of ADC instance and ADC group regular */ 07452 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); 07453 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); 07454 07455 /* Initialization of some features of ADC instance and ADC group injected */ 07456 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); 07457 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); 07458 07459 /** 07460 * @} 07461 */ 07462 #endif /* USE_FULL_LL_DRIVER */ 07463 07464 /** 07465 * @} 07466 */ 07467 07468 /** 07469 * @} 07470 */ 07471 07472 #endif /* ADC1 || ADC2 || ADC3 */ 07473 07474 /** 07475 * @} 07476 */ 07477 07478 #ifdef __cplusplus 07479 } 07480 #endif 07481 07482 #endif /* __STM32L4xx_LL_ADC_H */ 07483 07484 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/