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STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_adc.h 00004 * @author MCD Application Team 00005 * @brief Header file of ADC LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32F4xx_LL_ADC_H 00038 #define __STM32F4xx_LL_ADC_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32f4xx.h" 00046 00047 /** @addtogroup STM32F4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined (ADC1) || defined (ADC2) || defined (ADC3) 00052 00053 /** @defgroup ADC_LL ADC 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 00060 /* Private constants ---------------------------------------------------------*/ 00061 /** @defgroup ADC_LL_Private_Constants ADC Private Constants 00062 * @{ 00063 */ 00064 00065 /* Internal mask for ADC group regular sequencer: */ 00066 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ 00067 /* - sequencer register offset */ 00068 /* - sequencer rank bits position into the selected register */ 00069 00070 /* Internal register offset for ADC group regular sequencer configuration */ 00071 /* (offset placed into a spare area of literal definition) */ 00072 #define ADC_SQR1_REGOFFSET 0x00000000U 00073 #define ADC_SQR2_REGOFFSET 0x00000100U 00074 #define ADC_SQR3_REGOFFSET 0x00000200U 00075 #define ADC_SQR4_REGOFFSET 0x00000300U 00076 00077 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) 00078 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) 00079 00080 /* Definition of ADC group regular sequencer bits information to be inserted */ 00081 /* into ADC group regular sequencer ranks literals definition. */ 00082 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */ 00083 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */ 00084 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */ 00085 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */ 00086 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */ 00087 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */ 00088 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ 00089 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ 00090 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ 00091 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */ 00092 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */ 00093 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */ 00094 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */ 00095 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */ 00096 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */ 00097 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */ 00098 00099 /* Internal mask for ADC group injected sequencer: */ 00100 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ 00101 /* - data register offset */ 00102 /* - offset register offset */ 00103 /* - sequencer rank bits position into the selected register */ 00104 00105 /* Internal register offset for ADC group injected data register */ 00106 /* (offset placed into a spare area of literal definition) */ 00107 #define ADC_JDR1_REGOFFSET 0x00000000U 00108 #define ADC_JDR2_REGOFFSET 0x00000100U 00109 #define ADC_JDR3_REGOFFSET 0x00000200U 00110 #define ADC_JDR4_REGOFFSET 0x00000300U 00111 00112 /* Internal register offset for ADC group injected offset configuration */ 00113 /* (offset placed into a spare area of literal definition) */ 00114 #define ADC_JOFR1_REGOFFSET 0x00000000U 00115 #define ADC_JOFR2_REGOFFSET 0x00001000U 00116 #define ADC_JOFR3_REGOFFSET 0x00002000U 00117 #define ADC_JOFR4_REGOFFSET 0x00003000U 00118 00119 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) 00120 #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET) 00121 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) 00122 00123 /* Internal mask for ADC group regular trigger: */ 00124 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ 00125 /* - regular trigger source */ 00126 /* - regular trigger edge */ 00127 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ 00128 00129 /* Mask containing trigger source masks for each of possible */ 00130 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00131 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00132 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \ 00133 ((ADC_CR2_EXTSEL) >> (4U * 1U)) | \ 00134 ((ADC_CR2_EXTSEL) >> (4U * 2U)) | \ 00135 ((ADC_CR2_EXTSEL) >> (4U * 3U))) 00136 00137 /* Mask containing trigger edge masks for each of possible */ 00138 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00139 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00140 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \ 00141 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \ 00142 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \ 00143 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U))) 00144 00145 /* Definition of ADC group regular trigger bits information. */ 00146 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */ 00147 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */ 00148 00149 00150 00151 /* Internal mask for ADC group injected trigger: */ 00152 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ 00153 /* - injected trigger source */ 00154 /* - injected trigger edge */ 00155 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ 00156 00157 /* Mask containing trigger source masks for each of possible */ 00158 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00159 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00160 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \ 00161 ((ADC_CR2_JEXTSEL) >> (4U * 1U)) | \ 00162 ((ADC_CR2_JEXTSEL) >> (4U * 2U)) | \ 00163 ((ADC_CR2_JEXTSEL) >> (4U * 3U))) 00164 00165 /* Mask containing trigger edge masks for each of possible */ 00166 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ 00167 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ 00168 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \ 00169 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \ 00170 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \ 00171 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U))) 00172 00173 /* Definition of ADC group injected trigger bits information. */ 00174 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */ 00175 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */ 00176 00177 /* Internal mask for ADC channel: */ 00178 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ 00179 /* - channel identifier defined by number */ 00180 /* - channel differentiation between external channels (connected to */ 00181 /* GPIO pins) and internal channels (connected to internal paths) */ 00182 /* - channel sampling time defined by SMPRx register offset */ 00183 /* and SMPx bits positions into SMPRx register */ 00184 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH) 00185 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ 00186 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) 00187 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ 00188 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ 00189 00190 /* Channel differentiation between external and internal channels */ 00191 #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */ 00192 #define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ 00193 #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */ 00194 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) 00195 00196 /* Internal register offset for ADC channel sampling time configuration */ 00197 /* (offset placed into a spare area of literal definition) */ 00198 #define ADC_SMPR1_REGOFFSET 0x00000000U 00199 #define ADC_SMPR2_REGOFFSET 0x02000000U 00200 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) 00201 00202 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U 00203 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ 00204 00205 /* Definition of channels ID number information to be inserted into */ 00206 /* channels literals definition. */ 00207 #define ADC_CHANNEL_0_NUMBER 0x00000000U 00208 #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0) 00209 #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 ) 00210 #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 00211 #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 ) 00212 #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) 00213 #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) 00214 #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 00215 #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 ) 00216 #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0) 00217 #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 ) 00218 #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 00219 #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 ) 00220 #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) 00221 #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) 00222 #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 00223 #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 ) 00224 #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0) 00225 #define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 ) 00226 00227 /* Definition of channels sampling time information to be inserted into */ 00228 /* channels literals definition. */ 00229 #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */ 00230 #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */ 00231 #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */ 00232 #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */ 00233 #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */ 00234 #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */ 00235 #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */ 00236 #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */ 00237 #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */ 00238 #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */ 00239 #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */ 00240 #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */ 00241 #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */ 00242 #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */ 00243 #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */ 00244 #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */ 00245 #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */ 00246 #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */ 00247 #define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */ 00248 00249 /* Internal mask for ADC analog watchdog: */ 00250 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ 00251 /* (concatenation of multiple bits used in different analog watchdogs, */ 00252 /* (feature of several watchdogs not available on all STM32 families)). */ 00253 /* - analog watchdog 1: monitored channel defined by number, */ 00254 /* selection of ADC group (ADC groups regular and-or injected). */ 00255 00256 /* Internal register offset for ADC analog watchdog channel configuration */ 00257 #define ADC_AWD_CR1_REGOFFSET 0x00000000U 00258 00259 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) 00260 00261 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) 00262 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) 00263 00264 /* Internal register offset for ADC analog watchdog threshold configuration */ 00265 #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U 00266 #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U 00267 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET) 00268 00269 /* ADC registers bits positions */ 00270 #define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */ 00271 #define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */ 00272 /** 00273 * @} 00274 */ 00275 00276 00277 /* Private macros ------------------------------------------------------------*/ 00278 /** @defgroup ADC_LL_Private_Macros ADC Private Macros 00279 * @{ 00280 */ 00281 00282 /** 00283 * @brief Driver macro reserved for internal use: isolate bits with the 00284 * selected mask and shift them to the register LSB 00285 * (shift mask on register position bit 0). 00286 * @param __BITS__ Bits in register 32 bits 00287 * @param __MASK__ Mask in register 32 bits 00288 * @retval Bits in register 32 bits 00289 */ 00290 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ 00291 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) 00292 00293 /** 00294 * @brief Driver macro reserved for internal use: set a pointer to 00295 * a register from a register basis from which an offset 00296 * is applied. 00297 * @param __REG__ Register basis from which the offset is applied. 00298 * @param __REG_OFFFSET__ Offset to be applied (unit number of registers). 00299 * @retval Pointer to register address 00300 */ 00301 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ 00302 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) 00303 00304 /** 00305 * @} 00306 */ 00307 00308 00309 /* Exported types ------------------------------------------------------------*/ 00310 #if defined(USE_FULL_LL_DRIVER) 00311 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure 00312 * @{ 00313 */ 00314 00315 /** 00316 * @brief Structure definition of some features of ADC common parameters 00317 * and multimode 00318 * (all ADC instances belonging to the same ADC common instance). 00319 * @note The setting of these parameters by function @ref LL_ADC_CommonInit() 00320 * is conditioned to ADC instances state (all ADC instances 00321 * sharing the same ADC common instance): 00322 * All ADC instances sharing the same ADC common instance must be 00323 * disabled. 00324 */ 00325 typedef struct 00326 { 00327 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. 00328 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE 00329 00330 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ 00331 00332 #if defined(ADC_MULTIMODE_SUPPORT) 00333 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). 00334 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE 00335 00336 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ 00337 00338 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA. 00339 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER 00340 00341 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */ 00342 00343 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases. 00344 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY 00345 00346 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */ 00347 #endif /* ADC_MULTIMODE_SUPPORT */ 00348 00349 } LL_ADC_CommonInitTypeDef; 00350 00351 /** 00352 * @brief Structure definition of some features of ADC instance. 00353 * @note These parameters have an impact on ADC scope: ADC instance. 00354 * Affects both group regular and group injected (availability 00355 * of ADC group injected depends on STM32 families). 00356 * Refer to corresponding unitary functions into 00357 * @ref ADC_LL_EF_Configuration_ADC_Instance . 00358 * @note The setting of these parameters by function @ref LL_ADC_Init() 00359 * is conditioned to ADC state: 00360 * ADC instance must be disabled. 00361 * This condition is applied to all ADC features, for efficiency 00362 * and compatibility over all STM32 families. However, the different 00363 * features can be set under different ADC state conditions 00364 * (setting possible with ADC enabled without conversion on going, 00365 * ADC enabled with conversion on going, ...) 00366 * Each feature can be updated afterwards with a unitary function 00367 * and potentially with ADC in a different state than disabled, 00368 * refer to description of each function for setting 00369 * conditioned to ADC state. 00370 */ 00371 typedef struct 00372 { 00373 uint32_t Resolution; /*!< Set ADC resolution. 00374 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION 00375 00376 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ 00377 00378 uint32_t DataAlignment; /*!< Set ADC conversion data alignment. 00379 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN 00380 00381 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ 00382 00383 uint32_t SequencersScanMode; /*!< Set ADC scan selection. 00384 This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION 00385 00386 This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */ 00387 00388 } LL_ADC_InitTypeDef; 00389 00390 /** 00391 * @brief Structure definition of some features of ADC group regular. 00392 * @note These parameters have an impact on ADC scope: ADC group regular. 00393 * Refer to corresponding unitary functions into 00394 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 00395 * (functions with prefix "REG"). 00396 * @note The setting of these parameters by function @ref LL_ADC_REG_Init() 00397 * is conditioned to ADC state: 00398 * ADC instance must be disabled. 00399 * This condition is applied to all ADC features, for efficiency 00400 * and compatibility over all STM32 families. However, the different 00401 * features can be set under different ADC state conditions 00402 * (setting possible with ADC enabled without conversion on going, 00403 * ADC enabled with conversion on going, ...) 00404 * Each feature can be updated afterwards with a unitary function 00405 * and potentially with ADC in a different state than disabled, 00406 * refer to description of each function for setting 00407 * conditioned to ADC state. 00408 */ 00409 typedef struct 00410 { 00411 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). 00412 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE 00413 @note On this STM32 serie, setting of external trigger edge is performed 00414 using function @ref LL_ADC_REG_StartConversionExtTrig(). 00415 00416 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ 00417 00418 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. 00419 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH 00420 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). 00421 00422 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ 00423 00424 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. 00425 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE 00426 @note This parameter has an effect only if group regular sequencer is enabled 00427 (scan length of 2 ranks or more). 00428 00429 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ 00430 00431 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). 00432 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE 00433 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. 00434 00435 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ 00436 00437 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. 00438 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER 00439 00440 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ 00441 00442 } LL_ADC_REG_InitTypeDef; 00443 00444 /** 00445 * @brief Structure definition of some features of ADC group injected. 00446 * @note These parameters have an impact on ADC scope: ADC group injected. 00447 * Refer to corresponding unitary functions into 00448 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 00449 * (functions with prefix "INJ"). 00450 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() 00451 * is conditioned to ADC state: 00452 * ADC instance must be disabled. 00453 * This condition is applied to all ADC features, for efficiency 00454 * and compatibility over all STM32 families. However, the different 00455 * features can be set under different ADC state conditions 00456 * (setting possible with ADC enabled without conversion on going, 00457 * ADC enabled with conversion on going, ...) 00458 * Each feature can be updated afterwards with a unitary function 00459 * and potentially with ADC in a different state than disabled, 00460 * refer to description of each function for setting 00461 * conditioned to ADC state. 00462 */ 00463 typedef struct 00464 { 00465 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). 00466 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE 00467 @note On this STM32 serie, setting of external trigger edge is performed 00468 using function @ref LL_ADC_INJ_StartConversionExtTrig(). 00469 00470 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ 00471 00472 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. 00473 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH 00474 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). 00475 00476 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ 00477 00478 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. 00479 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE 00480 @note This parameter has an effect only if group injected sequencer is enabled 00481 (scan length of 2 ranks or more). 00482 00483 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ 00484 00485 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. 00486 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO 00487 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. 00488 00489 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ 00490 00491 } LL_ADC_INJ_InitTypeDef; 00492 00493 /** 00494 * @} 00495 */ 00496 #endif /* USE_FULL_LL_DRIVER */ 00497 00498 /* Exported constants --------------------------------------------------------*/ 00499 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants 00500 * @{ 00501 */ 00502 00503 /** @defgroup ADC_LL_EC_FLAG ADC flags 00504 * @brief Flags defines which can be used with LL_ADC_ReadReg function 00505 * @{ 00506 */ 00507 #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */ 00508 #define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ 00509 #define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */ 00510 #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */ 00511 #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 00512 #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */ 00513 #if defined(ADC_MULTIMODE_SUPPORT) 00514 #define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ 00515 #define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ 00516 #define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ 00517 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */ 00518 #define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */ 00519 #define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */ 00520 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 00521 #define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 00522 #define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 00523 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ 00524 #define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */ 00525 #define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */ 00526 #endif 00527 /** 00528 * @} 00529 */ 00530 00531 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) 00532 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions 00533 * @{ 00534 */ 00535 #define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ 00536 #define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */ 00537 #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 00538 #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */ 00539 /** 00540 * @} 00541 */ 00542 00543 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose 00544 * @{ 00545 */ 00546 /* List of ADC registers intended to be used (most commonly) with */ 00547 /* DMA transfer. */ 00548 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ 00549 #define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ 00550 #if defined(ADC_MULTIMODE_SUPPORT) 00551 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ 00552 #endif 00553 /** 00554 * @} 00555 */ 00556 00557 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 00558 * @{ 00559 */ 00560 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ 00561 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ 00562 #define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */ 00563 #define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */ 00564 /** 00565 * @} 00566 */ 00567 00568 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels 00569 * @{ 00570 */ 00571 /* Note: Other measurement paths to internal channels may be available */ 00572 /* (connections to other peripherals). */ 00573 /* If they are not listed below, they do not require any specific */ 00574 /* path enable. In this case, Access to measurement path is done */ 00575 /* only by selecting the corresponding ADC internal channel. */ 00576 #define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement pathes all disabled */ 00577 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */ 00578 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */ 00579 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */ 00580 /** 00581 * @} 00582 */ 00583 00584 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution 00585 * @{ 00586 */ 00587 #define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */ 00588 #define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */ 00589 #define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */ 00590 #define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */ 00591 /** 00592 * @} 00593 */ 00594 00595 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment 00596 * @{ 00597 */ 00598 #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ 00599 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ 00600 /** 00601 * @} 00602 */ 00603 00604 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection 00605 * @{ 00606 */ 00607 #define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/ 00608 #define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */ 00609 /** 00610 * @} 00611 */ 00612 00613 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups 00614 * @{ 00615 */ 00616 #define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */ 00617 #define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/ 00618 #define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */ 00619 /** 00620 * @} 00621 */ 00622 00623 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number 00624 * @{ 00625 */ 00626 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 00627 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 00628 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 00629 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 00630 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 00631 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 00632 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 00633 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 00634 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 00635 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 00636 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 00637 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 00638 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 00639 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 00640 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 00641 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 00642 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 00643 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 00644 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ 00645 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F4, ADC channel available only on ADC instance: ADC1. */ 00646 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F4, ADC channel available only on ADC instance: ADC1. */ 00647 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx) 00648 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. */ 00649 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */ 00650 #if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 00651 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ 00652 #endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 00653 /** 00654 * @} 00655 */ 00656 00657 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source 00658 * @{ 00659 */ 00660 #define LL_ADC_REG_TRIG_SOFTWARE 0x00000000U /*!< ADC group regular conversion trigger internal: SW start. */ 00661 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00662 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00663 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00664 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00665 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00666 #define LL_ADC_REG_TRIG_EXT_TIM2_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00667 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 00668 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00669 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 00670 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00671 #define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00672 #define LL_ADC_REG_TRIG_EXT_TIM5_CH2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00673 #define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00674 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00675 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 00676 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ 00677 /** 00678 * @} 00679 */ 00680 00681 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge 00682 * @{ 00683 */ 00684 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ 00685 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */ 00686 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ 00687 /** 00688 * @} 00689 */ 00690 00691 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode 00692 * @{ 00693 */ 00694 #define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */ 00695 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ 00696 /** 00697 * @} 00698 */ 00699 00700 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data 00701 * @{ 00702 */ 00703 #define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */ 00704 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ 00705 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ 00706 /** 00707 * @} 00708 */ 00709 00710 /** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions) 00711 * @{ 00712 */ 00713 #define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000U /*!< ADC flag EOC (end of unitary conversion) selected */ 00714 #define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */ 00715 /** 00716 * @} 00717 */ 00718 00719 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length 00720 * @{ 00721 */ 00722 #define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ 00723 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ 00724 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ 00725 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ 00726 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ 00727 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ 00728 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ 00729 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ 00730 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ 00731 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ 00732 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ 00733 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ 00734 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ 00735 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ 00736 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ 00737 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ 00738 /** 00739 * @} 00740 */ 00741 00742 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode 00743 * @{ 00744 */ 00745 #define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */ 00746 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ 00747 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ 00748 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ 00749 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ 00750 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ 00751 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ 00752 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ 00753 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ 00754 /** 00755 * @} 00756 */ 00757 00758 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 00759 * @{ 00760 */ 00761 #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ 00762 #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ 00763 #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ 00764 #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ 00765 #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ 00766 #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ 00767 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ 00768 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ 00769 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ 00770 #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ 00771 #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ 00772 #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ 00773 #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ 00774 #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ 00775 #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ 00776 #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ 00777 /** 00778 * @} 00779 */ 00780 00781 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source 00782 * @{ 00783 */ 00784 #define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000U /*!< ADC group injected conversion trigger internal: SW start. */ 00785 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00786 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 00787 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00788 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 00789 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH2 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00790 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00791 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH1 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00792 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH2 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00793 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00794 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 00795 #define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00796 #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */ 00797 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00798 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00799 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00800 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 00801 /** 00802 * @} 00803 */ 00804 00805 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge 00806 * @{ 00807 */ 00808 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */ 00809 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */ 00810 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */ 00811 /** 00812 * @} 00813 */ 00814 00815 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode 00816 * @{ 00817 */ 00818 #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ 00819 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ 00820 /** 00821 * @} 00822 */ 00823 00824 00825 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length 00826 * @{ 00827 */ 00828 #define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ 00829 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ 00830 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ 00831 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ 00832 /** 00833 * @} 00834 */ 00835 00836 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode 00837 * @{ 00838 */ 00839 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */ 00840 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ 00841 /** 00842 * @} 00843 */ 00844 00845 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 00846 * @{ 00847 */ 00848 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */ 00849 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */ 00850 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */ 00851 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */ 00852 /** 00853 * @} 00854 */ 00855 00856 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 00857 * @{ 00858 */ 00859 #define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000U /*!< Sampling time 3 ADC clock cycles */ 00860 #define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */ 00861 #define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */ 00862 #define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */ 00863 #define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /*!< Sampling time 84 ADC clock cycles */ 00864 #define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0) /*!< Sampling time 112 ADC clock cycles */ 00865 #define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1) /*!< Sampling time 144 ADC clock cycles */ 00866 #define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /*!< Sampling time 480 ADC clock cycles */ 00867 /** 00868 * @} 00869 */ 00870 00871 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 00872 * @{ 00873 */ 00874 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ 00875 /** 00876 * @} 00877 */ 00878 00879 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels 00880 * @{ 00881 */ 00882 #define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */ 00883 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ 00884 #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ 00885 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ 00886 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ 00887 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ 00888 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ 00889 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ 00890 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ 00891 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ 00892 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ 00893 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ 00894 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ 00895 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ 00896 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ 00897 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ 00898 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ 00899 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ 00900 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ 00901 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ 00902 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ 00903 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ 00904 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ 00905 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ 00906 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ 00907 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ 00908 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ 00909 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ 00910 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ 00911 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ 00912 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ 00913 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ 00914 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ 00915 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ 00916 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ 00917 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ 00918 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ 00919 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ 00920 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ 00921 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ 00922 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ 00923 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ 00924 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ 00925 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ 00926 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ 00927 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ 00928 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ 00929 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ 00930 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ 00931 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ 00932 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ 00933 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ 00934 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ 00935 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ 00936 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ 00937 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ 00938 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ 00939 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ 00940 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */ 00941 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */ 00942 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */ 00943 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ 00944 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ 00945 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ 00946 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ 00947 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */ 00948 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */ 00949 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx) 00950 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ 00951 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */ 00952 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */ 00953 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */ 00954 #if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 00955 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ 00956 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ 00957 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ 00958 #endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 00959 /** 00960 * @} 00961 */ 00962 00963 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds 00964 * @{ 00965 */ 00966 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */ 00967 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */ 00968 /** 00969 * @} 00970 */ 00971 00972 #if defined(ADC_MULTIMODE_SUPPORT) 00973 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode 00974 * @{ 00975 */ 00976 #define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ 00977 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ 00978 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */ 00979 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */ 00980 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 00981 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 00982 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 00983 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ 00984 #if defined(ADC3) 00985 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */ 00986 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 00987 #define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */ 00988 #define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: group regular simultaneous */ 00989 #define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */ 00990 #define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 00991 #endif 00992 /** 00993 * @} 00994 */ 00995 00996 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer 00997 * @{ 00998 */ 00999 #define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000U /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ 01000 #define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */ 01001 #define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */ 01002 #define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */ 01003 #define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */ 01004 #define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */ 01005 #define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */ 01006 /** 01007 * @} 01008 */ 01009 01010 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 01011 * @{ 01012 */ 01013 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000U /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/ 01014 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ 01015 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ 01016 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ 01017 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ 01018 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ 01019 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ 01020 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ 01021 #define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */ 01022 #define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */ 01023 #define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */ 01024 #define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */ 01025 #define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */ 01026 #define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */ 01027 #define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */ 01028 #define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */ 01029 /** 01030 * @} 01031 */ 01032 01033 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave 01034 * @{ 01035 */ 01036 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */ 01037 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */ 01038 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ 01039 /** 01040 * @} 01041 */ 01042 01043 #endif /* ADC_MULTIMODE_SUPPORT */ 01044 01045 01046 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays 01047 * @note Only ADC IP HW delays are defined in ADC LL driver driver, 01048 * not timeout values. 01049 * For details on delays values, refer to descriptions in source code 01050 * above each literal definition. 01051 * @{ 01052 */ 01053 01054 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ 01055 /* not timeout values. */ 01056 /* Timeout values for ADC operations are dependent to device clock */ 01057 /* configuration (system clock versus ADC clock), */ 01058 /* and therefore must be defined in user application. */ 01059 /* Indications for estimation of ADC timeout delays, for this */ 01060 /* STM32 serie: */ 01061 /* - ADC enable time: maximum delay is 2us */ 01062 /* (refer to device datasheet, parameter "tSTAB") */ 01063 /* - ADC conversion time: duration depending on ADC clock and ADC */ 01064 /* configuration. */ 01065 /* (refer to device reference manual, section "Timing") */ 01066 01067 /* Delay for internal voltage reference stabilization time. */ 01068 /* Delay set to maximum value (refer to device datasheet, */ 01069 /* parameter "tSTART"). */ 01070 /* Unit: us */ 01071 #define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */ 01072 01073 /* Delay for temperature sensor stabilization time. */ 01074 /* Literal set to maximum value (refer to device datasheet, */ 01075 /* parameter "tSTART"). */ 01076 /* Unit: us */ 01077 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */ 01078 01079 /** 01080 * @} 01081 */ 01082 01083 /** 01084 * @} 01085 */ 01086 01087 01088 /* Exported macro ------------------------------------------------------------*/ 01089 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros 01090 * @{ 01091 */ 01092 01093 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros 01094 * @{ 01095 */ 01096 01097 /** 01098 * @brief Write a value in ADC register 01099 * @param __INSTANCE__ ADC Instance 01100 * @param __REG__ Register to be written 01101 * @param __VALUE__ Value to be written in the register 01102 * @retval None 01103 */ 01104 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 01105 01106 /** 01107 * @brief Read a value in ADC register 01108 * @param __INSTANCE__ ADC Instance 01109 * @param __REG__ Register to be read 01110 * @retval Register value 01111 */ 01112 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 01113 /** 01114 * @} 01115 */ 01116 01117 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro 01118 * @{ 01119 */ 01120 01121 /** 01122 * @brief Helper macro to get ADC channel number in decimal format 01123 * from literals LL_ADC_CHANNEL_x. 01124 * @note Example: 01125 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) 01126 * will return decimal number "4". 01127 * @note The input can be a value from functions where a channel 01128 * number is returned, either defined with number 01129 * or with bitfield (only one bit must be set). 01130 * @param __CHANNEL__ This parameter can be one of the following values: 01131 * @arg @ref LL_ADC_CHANNEL_0 01132 * @arg @ref LL_ADC_CHANNEL_1 01133 * @arg @ref LL_ADC_CHANNEL_2 01134 * @arg @ref LL_ADC_CHANNEL_3 01135 * @arg @ref LL_ADC_CHANNEL_4 01136 * @arg @ref LL_ADC_CHANNEL_5 01137 * @arg @ref LL_ADC_CHANNEL_6 01138 * @arg @ref LL_ADC_CHANNEL_7 01139 * @arg @ref LL_ADC_CHANNEL_8 01140 * @arg @ref LL_ADC_CHANNEL_9 01141 * @arg @ref LL_ADC_CHANNEL_10 01142 * @arg @ref LL_ADC_CHANNEL_11 01143 * @arg @ref LL_ADC_CHANNEL_12 01144 * @arg @ref LL_ADC_CHANNEL_13 01145 * @arg @ref LL_ADC_CHANNEL_14 01146 * @arg @ref LL_ADC_CHANNEL_15 01147 * @arg @ref LL_ADC_CHANNEL_16 01148 * @arg @ref LL_ADC_CHANNEL_17 01149 * @arg @ref LL_ADC_CHANNEL_18 01150 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01151 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 01152 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 01153 * 01154 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 01155 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 01156 * @retval Value between Min_Data=0 and Max_Data=18 01157 */ 01158 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 01159 (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) 01160 01161 /** 01162 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x 01163 * from number in decimal format. 01164 * @note Example: 01165 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) 01166 * will return a data equivalent to "LL_ADC_CHANNEL_4". 01167 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 01168 * @retval Returned value can be one of the following values: 01169 * @arg @ref LL_ADC_CHANNEL_0 01170 * @arg @ref LL_ADC_CHANNEL_1 01171 * @arg @ref LL_ADC_CHANNEL_2 01172 * @arg @ref LL_ADC_CHANNEL_3 01173 * @arg @ref LL_ADC_CHANNEL_4 01174 * @arg @ref LL_ADC_CHANNEL_5 01175 * @arg @ref LL_ADC_CHANNEL_6 01176 * @arg @ref LL_ADC_CHANNEL_7 01177 * @arg @ref LL_ADC_CHANNEL_8 01178 * @arg @ref LL_ADC_CHANNEL_9 01179 * @arg @ref LL_ADC_CHANNEL_10 01180 * @arg @ref LL_ADC_CHANNEL_11 01181 * @arg @ref LL_ADC_CHANNEL_12 01182 * @arg @ref LL_ADC_CHANNEL_13 01183 * @arg @ref LL_ADC_CHANNEL_14 01184 * @arg @ref LL_ADC_CHANNEL_15 01185 * @arg @ref LL_ADC_CHANNEL_16 01186 * @arg @ref LL_ADC_CHANNEL_17 01187 * @arg @ref LL_ADC_CHANNEL_18 01188 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01189 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 01190 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 01191 * 01192 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 01193 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n 01194 * (1) For ADC channel read back from ADC register, 01195 * comparison with internal channel parameter to be done 01196 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 01197 */ 01198 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 01199 (((__DECIMAL_NB__) <= 9U) \ 01200 ? ( \ 01201 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ 01202 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ 01203 ) \ 01204 : \ 01205 ( \ 01206 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ 01207 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ 01208 ) \ 01209 ) 01210 01211 /** 01212 * @brief Helper macro to determine whether the selected channel 01213 * corresponds to literal definitions of driver. 01214 * @note The different literal definitions of ADC channels are: 01215 * - ADC internal channel: 01216 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... 01217 * - ADC external channel (channel connected to a GPIO pin): 01218 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... 01219 * @note The channel parameter must be a value defined from literal 01220 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 01221 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 01222 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), 01223 * must not be a value from functions where a channel number is 01224 * returned from ADC registers, 01225 * because internal and external channels share the same channel 01226 * number in ADC registers. The differentiation is made only with 01227 * parameters definitions of driver. 01228 * @param __CHANNEL__ This parameter can be one of the following values: 01229 * @arg @ref LL_ADC_CHANNEL_0 01230 * @arg @ref LL_ADC_CHANNEL_1 01231 * @arg @ref LL_ADC_CHANNEL_2 01232 * @arg @ref LL_ADC_CHANNEL_3 01233 * @arg @ref LL_ADC_CHANNEL_4 01234 * @arg @ref LL_ADC_CHANNEL_5 01235 * @arg @ref LL_ADC_CHANNEL_6 01236 * @arg @ref LL_ADC_CHANNEL_7 01237 * @arg @ref LL_ADC_CHANNEL_8 01238 * @arg @ref LL_ADC_CHANNEL_9 01239 * @arg @ref LL_ADC_CHANNEL_10 01240 * @arg @ref LL_ADC_CHANNEL_11 01241 * @arg @ref LL_ADC_CHANNEL_12 01242 * @arg @ref LL_ADC_CHANNEL_13 01243 * @arg @ref LL_ADC_CHANNEL_14 01244 * @arg @ref LL_ADC_CHANNEL_15 01245 * @arg @ref LL_ADC_CHANNEL_16 01246 * @arg @ref LL_ADC_CHANNEL_17 01247 * @arg @ref LL_ADC_CHANNEL_18 01248 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01249 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 01250 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 01251 * 01252 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 01253 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 01254 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 01255 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 01256 */ 01257 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 01258 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) 01259 01260 /** 01261 * @brief Helper macro to convert a channel defined from parameter 01262 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 01263 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 01264 * to its equivalent parameter definition of a ADC external channel 01265 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). 01266 * @note The channel parameter can be, additionally to a value 01267 * defined from parameter definition of a ADC internal channel 01268 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), 01269 * a value defined from parameter definition of 01270 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) 01271 * or a value from functions where a channel number is returned 01272 * from ADC registers. 01273 * @param __CHANNEL__ This parameter can be one of the following values: 01274 * @arg @ref LL_ADC_CHANNEL_0 01275 * @arg @ref LL_ADC_CHANNEL_1 01276 * @arg @ref LL_ADC_CHANNEL_2 01277 * @arg @ref LL_ADC_CHANNEL_3 01278 * @arg @ref LL_ADC_CHANNEL_4 01279 * @arg @ref LL_ADC_CHANNEL_5 01280 * @arg @ref LL_ADC_CHANNEL_6 01281 * @arg @ref LL_ADC_CHANNEL_7 01282 * @arg @ref LL_ADC_CHANNEL_8 01283 * @arg @ref LL_ADC_CHANNEL_9 01284 * @arg @ref LL_ADC_CHANNEL_10 01285 * @arg @ref LL_ADC_CHANNEL_11 01286 * @arg @ref LL_ADC_CHANNEL_12 01287 * @arg @ref LL_ADC_CHANNEL_13 01288 * @arg @ref LL_ADC_CHANNEL_14 01289 * @arg @ref LL_ADC_CHANNEL_15 01290 * @arg @ref LL_ADC_CHANNEL_16 01291 * @arg @ref LL_ADC_CHANNEL_17 01292 * @arg @ref LL_ADC_CHANNEL_18 01293 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01294 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 01295 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 01296 * 01297 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 01298 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 01299 * @retval Returned value can be one of the following values: 01300 * @arg @ref LL_ADC_CHANNEL_0 01301 * @arg @ref LL_ADC_CHANNEL_1 01302 * @arg @ref LL_ADC_CHANNEL_2 01303 * @arg @ref LL_ADC_CHANNEL_3 01304 * @arg @ref LL_ADC_CHANNEL_4 01305 * @arg @ref LL_ADC_CHANNEL_5 01306 * @arg @ref LL_ADC_CHANNEL_6 01307 * @arg @ref LL_ADC_CHANNEL_7 01308 * @arg @ref LL_ADC_CHANNEL_8 01309 * @arg @ref LL_ADC_CHANNEL_9 01310 * @arg @ref LL_ADC_CHANNEL_10 01311 * @arg @ref LL_ADC_CHANNEL_11 01312 * @arg @ref LL_ADC_CHANNEL_12 01313 * @arg @ref LL_ADC_CHANNEL_13 01314 * @arg @ref LL_ADC_CHANNEL_14 01315 * @arg @ref LL_ADC_CHANNEL_15 01316 * @arg @ref LL_ADC_CHANNEL_16 01317 * @arg @ref LL_ADC_CHANNEL_17 01318 * @arg @ref LL_ADC_CHANNEL_18 01319 */ 01320 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 01321 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) 01322 01323 /** 01324 * @brief Helper macro to determine whether the internal channel 01325 * selected is available on the ADC instance selected. 01326 * @note The channel parameter must be a value defined from parameter 01327 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 01328 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 01329 * must not be a value defined from parameter definition of 01330 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) 01331 * or a value from functions where a channel number is 01332 * returned from ADC registers, 01333 * because internal and external channels share the same channel 01334 * number in ADC registers. The differentiation is made only with 01335 * parameters definitions of driver. 01336 * @param __ADC_INSTANCE__ ADC instance 01337 * @param __CHANNEL__ This parameter can be one of the following values: 01338 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01339 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 01340 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 01341 * 01342 * (1) On STM32F4, parameter available only on ADC instance: ADC1. 01343 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 01344 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 01345 * Value "1" if the internal channel selected is available on the ADC instance selected. 01346 */ 01347 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 01348 ( \ 01349 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ 01350 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ 01351 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \ 01352 ) 01353 /** 01354 * @brief Helper macro to define ADC analog watchdog parameter: 01355 * define a single channel to monitor with analog watchdog 01356 * from sequencer channel and groups definition. 01357 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). 01358 * Example: 01359 * LL_ADC_SetAnalogWDMonitChannels( 01360 * ADC1, LL_ADC_AWD1, 01361 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) 01362 * @param __CHANNEL__ This parameter can be one of the following values: 01363 * @arg @ref LL_ADC_CHANNEL_0 01364 * @arg @ref LL_ADC_CHANNEL_1 01365 * @arg @ref LL_ADC_CHANNEL_2 01366 * @arg @ref LL_ADC_CHANNEL_3 01367 * @arg @ref LL_ADC_CHANNEL_4 01368 * @arg @ref LL_ADC_CHANNEL_5 01369 * @arg @ref LL_ADC_CHANNEL_6 01370 * @arg @ref LL_ADC_CHANNEL_7 01371 * @arg @ref LL_ADC_CHANNEL_8 01372 * @arg @ref LL_ADC_CHANNEL_9 01373 * @arg @ref LL_ADC_CHANNEL_10 01374 * @arg @ref LL_ADC_CHANNEL_11 01375 * @arg @ref LL_ADC_CHANNEL_12 01376 * @arg @ref LL_ADC_CHANNEL_13 01377 * @arg @ref LL_ADC_CHANNEL_14 01378 * @arg @ref LL_ADC_CHANNEL_15 01379 * @arg @ref LL_ADC_CHANNEL_16 01380 * @arg @ref LL_ADC_CHANNEL_17 01381 * @arg @ref LL_ADC_CHANNEL_18 01382 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 01383 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 01384 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 01385 * 01386 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 01387 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n 01388 * (1) For ADC channel read back from ADC register, 01389 * comparison with internal channel parameter to be done 01390 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 01391 * @param __GROUP__ This parameter can be one of the following values: 01392 * @arg @ref LL_ADC_GROUP_REGULAR 01393 * @arg @ref LL_ADC_GROUP_INJECTED 01394 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED 01395 * @retval Returned value can be one of the following values: 01396 * @arg @ref LL_ADC_AWD_DISABLE 01397 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG 01398 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ 01399 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 01400 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG 01401 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 01402 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 01403 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG 01404 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 01405 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 01406 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG 01407 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 01408 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 01409 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG 01410 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 01411 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 01412 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG 01413 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 01414 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 01415 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG 01416 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 01417 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 01418 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG 01419 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 01420 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 01421 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG 01422 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 01423 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 01424 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG 01425 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 01426 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 01427 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG 01428 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 01429 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 01430 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG 01431 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ 01432 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 01433 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG 01434 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ 01435 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 01436 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG 01437 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ 01438 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 01439 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG 01440 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ 01441 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 01442 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG 01443 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ 01444 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 01445 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG 01446 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ 01447 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 01448 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG 01449 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ 01450 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 01451 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG 01452 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ 01453 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 01454 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG 01455 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ 01456 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ 01457 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) 01458 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) 01459 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) 01460 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2) 01461 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2) 01462 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2) 01463 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1) 01464 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1) 01465 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) 01466 * 01467 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 01468 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 01469 */ 01470 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ 01471 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ 01472 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ 01473 : \ 01474 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ 01475 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \ 01476 : \ 01477 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ 01478 ) 01479 01480 /** 01481 * @brief Helper macro to set the value of ADC analog watchdog threshold high 01482 * or low in function of ADC resolution, when ADC resolution is 01483 * different of 12 bits. 01484 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds(). 01485 * Example, with a ADC resolution of 8 bits, to set the value of 01486 * analog watchdog threshold high (on 8 bits): 01487 * LL_ADC_SetAnalogWDThresholds 01488 * (< ADCx param >, 01489 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>) 01490 * ); 01491 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01492 * @arg @ref LL_ADC_RESOLUTION_12B 01493 * @arg @ref LL_ADC_RESOLUTION_10B 01494 * @arg @ref LL_ADC_RESOLUTION_8B 01495 * @arg @ref LL_ADC_RESOLUTION_6B 01496 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF 01497 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01498 */ 01499 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ 01500 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U ))) 01501 01502 /** 01503 * @brief Helper macro to get the value of ADC analog watchdog threshold high 01504 * or low in function of ADC resolution, when ADC resolution is 01505 * different of 12 bits. 01506 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). 01507 * Example, with a ADC resolution of 8 bits, to get the value of 01508 * analog watchdog threshold high (on 8 bits): 01509 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION 01510 * (LL_ADC_RESOLUTION_8B, 01511 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH) 01512 * ); 01513 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01514 * @arg @ref LL_ADC_RESOLUTION_12B 01515 * @arg @ref LL_ADC_RESOLUTION_10B 01516 * @arg @ref LL_ADC_RESOLUTION_8B 01517 * @arg @ref LL_ADC_RESOLUTION_6B 01518 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF 01519 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01520 */ 01521 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ 01522 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U ))) 01523 01524 #if defined(ADC_MULTIMODE_SUPPORT) 01525 /** 01526 * @brief Helper macro to get the ADC multimode conversion data of ADC master 01527 * or ADC slave from raw value with both ADC conversion data concatenated. 01528 * @note This macro is intended to be used when multimode transfer by DMA 01529 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 01530 * In this case the transferred data need to processed with this macro 01531 * to separate the conversion data of ADC master and ADC slave. 01532 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 01533 * @arg @ref LL_ADC_MULTI_MASTER 01534 * @arg @ref LL_ADC_MULTI_SLAVE 01535 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 01536 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01537 */ 01538 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 01539 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) 01540 #endif 01541 01542 /** 01543 * @brief Helper macro to select the ADC common instance 01544 * to which is belonging the selected ADC instance. 01545 * @note ADC common register instance can be used for: 01546 * - Set parameters common to several ADC instances 01547 * - Multimode (for devices with several ADC instances) 01548 * Refer to functions having argument "ADCxy_COMMON" as parameter. 01549 * @param __ADCx__ ADC instance 01550 * @retval ADC common register instance 01551 */ 01552 #if defined(ADC1) && defined(ADC2) && defined(ADC3) 01553 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 01554 (ADC123_COMMON) 01555 #elif defined(ADC1) && defined(ADC2) 01556 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 01557 (ADC12_COMMON) 01558 #else 01559 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 01560 (ADC1_COMMON) 01561 #endif 01562 01563 /** 01564 * @brief Helper macro to check if all ADC instances sharing the same 01565 * ADC common instance are disabled. 01566 * @note This check is required by functions with setting conditioned to 01567 * ADC state: 01568 * All ADC instances of the ADC common group must be disabled. 01569 * Refer to functions having argument "ADCxy_COMMON" as parameter. 01570 * @note On devices with only 1 ADC common instance, parameter of this macro 01571 * is useless and can be ignored (parameter kept for compatibility 01572 * with devices featuring several ADC common instances). 01573 * @param __ADCXY_COMMON__ ADC common instance 01574 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 01575 * @retval Value "0" if all ADC instances sharing the same ADC common instance 01576 * are disabled. 01577 * Value "1" if at least one ADC instance sharing the same ADC common instance 01578 * is enabled. 01579 */ 01580 #if defined(ADC1) && defined(ADC2) && defined(ADC3) 01581 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 01582 (LL_ADC_IsEnabled(ADC1) | \ 01583 LL_ADC_IsEnabled(ADC2) | \ 01584 LL_ADC_IsEnabled(ADC3) ) 01585 #elif defined(ADC1) && defined(ADC2) 01586 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 01587 (LL_ADC_IsEnabled(ADC1) | \ 01588 LL_ADC_IsEnabled(ADC2) ) 01589 #else 01590 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 01591 (LL_ADC_IsEnabled(ADC1)) 01592 #endif 01593 01594 /** 01595 * @brief Helper macro to define the ADC conversion data full-scale digital 01596 * value corresponding to the selected ADC resolution. 01597 * @note ADC conversion data full-scale corresponds to voltage range 01598 * determined by analog voltage references Vref+ and Vref- 01599 * (refer to reference manual). 01600 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01601 * @arg @ref LL_ADC_RESOLUTION_12B 01602 * @arg @ref LL_ADC_RESOLUTION_10B 01603 * @arg @ref LL_ADC_RESOLUTION_8B 01604 * @arg @ref LL_ADC_RESOLUTION_6B 01605 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 01606 */ 01607 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 01608 (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) 01609 01610 /** 01611 * @brief Helper macro to convert the ADC conversion data from 01612 * a resolution to another resolution. 01613 * @param __DATA__ ADC conversion data to be converted 01614 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 01615 * This parameter can be one of the following values: 01616 * @arg @ref LL_ADC_RESOLUTION_12B 01617 * @arg @ref LL_ADC_RESOLUTION_10B 01618 * @arg @ref LL_ADC_RESOLUTION_8B 01619 * @arg @ref LL_ADC_RESOLUTION_6B 01620 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 01621 * This parameter can be one of the following values: 01622 * @arg @ref LL_ADC_RESOLUTION_12B 01623 * @arg @ref LL_ADC_RESOLUTION_10B 01624 * @arg @ref LL_ADC_RESOLUTION_8B 01625 * @arg @ref LL_ADC_RESOLUTION_6B 01626 * @retval ADC conversion data to the requested resolution 01627 */ 01628 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \ 01629 (((__DATA__) \ 01630 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) \ 01631 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)) \ 01632 ) 01633 01634 /** 01635 * @brief Helper macro to calculate the voltage (unit: mVolt) 01636 * corresponding to a ADC conversion data (unit: digital value). 01637 * @note Analog reference voltage (Vref+) must be either known from 01638 * user board environment or can be calculated using ADC measurement 01639 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 01640 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) 01641 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 01642 * (unit: digital value). 01643 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01644 * @arg @ref LL_ADC_RESOLUTION_12B 01645 * @arg @ref LL_ADC_RESOLUTION_10B 01646 * @arg @ref LL_ADC_RESOLUTION_8B 01647 * @arg @ref LL_ADC_RESOLUTION_6B 01648 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 01649 */ 01650 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 01651 __ADC_DATA__,\ 01652 __ADC_RESOLUTION__) \ 01653 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ 01654 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 01655 ) 01656 01657 01658 /** 01659 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 01660 * from ADC conversion data of internal temperature sensor. 01661 * @note Computation is using temperature sensor typical values 01662 * (refer to device datasheet). 01663 * @note Calculation formula: 01664 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 01665 * / Avg_Slope + CALx_TEMP 01666 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 01667 * (unit: digital value) 01668 * Avg_Slope = temperature sensor slope 01669 * (unit: uV/Degree Celsius) 01670 * TS_TYP_CALx_VOLT = temperature sensor digital value at 01671 * temperature CALx_TEMP (unit: mV) 01672 * Caution: Calculation relevancy under reserve the temperature sensor 01673 * of the current device has characteristics in line with 01674 * datasheet typical values. 01675 * If temperature sensor calibration values are available on 01676 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 01677 * temperature calculation will be more accurate using 01678 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 01679 * @note As calculation input, the analog reference voltage (Vref+) must be 01680 * defined as it impacts the ADC LSB equivalent voltage. 01681 * @note Analog reference voltage (Vref+) must be either known from 01682 * user board environment or can be calculated using ADC measurement 01683 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 01684 * @note ADC measurement data must correspond to a resolution of 12bits 01685 * (full scale digital value 4095). If not the case, the data must be 01686 * preliminarily rescaled to an equivalent resolution of 12 bits. 01687 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius). 01688 * On STM32F4, refer to device datasheet parameter "Avg_Slope". 01689 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV). 01690 * On STM32F4, refer to device datasheet parameter "V25". 01691 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV) 01692 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV) 01693 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value). 01694 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 01695 * This parameter can be one of the following values: 01696 * @arg @ref LL_ADC_RESOLUTION_12B 01697 * @arg @ref LL_ADC_RESOLUTION_10B 01698 * @arg @ref LL_ADC_RESOLUTION_8B 01699 * @arg @ref LL_ADC_RESOLUTION_6B 01700 * @retval Temperature (unit: degree Celsius) 01701 */ 01702 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 01703 __TEMPSENSOR_TYP_CALX_V__,\ 01704 __TEMPSENSOR_CALX_TEMP__,\ 01705 __VREFANALOG_VOLTAGE__,\ 01706 __TEMPSENSOR_ADC_DATA__,\ 01707 __ADC_RESOLUTION__) \ 01708 ((( ( \ 01709 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ 01710 * 1000) \ 01711 - \ 01712 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ 01713 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ 01714 * 1000) \ 01715 ) \ 01716 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ 01717 ) + (__TEMPSENSOR_CALX_TEMP__) \ 01718 ) 01719 01720 /** 01721 * @} 01722 */ 01723 01724 /** 01725 * @} 01726 */ 01727 01728 01729 /* Exported functions --------------------------------------------------------*/ 01730 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions 01731 * @{ 01732 */ 01733 01734 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management 01735 * @{ 01736 */ 01737 /* Note: LL ADC functions to set DMA transfer are located into sections of */ 01738 /* configuration of ADC instance, groups and multimode (if available): */ 01739 /* @ref LL_ADC_REG_SetDMATransfer(), ... */ 01740 01741 /** 01742 * @brief Function to help to configure DMA transfer from ADC: retrieve the 01743 * ADC register address from ADC instance and a list of ADC registers 01744 * intended to be used (most commonly) with DMA transfer. 01745 * @note These ADC registers are data registers: 01746 * when ADC conversion data is available in ADC data registers, 01747 * ADC generates a DMA transfer request. 01748 * @note This macro is intended to be used with LL DMA driver, refer to 01749 * function "LL_DMA_ConfigAddresses()". 01750 * Example: 01751 * LL_DMA_ConfigAddresses(DMA1, 01752 * LL_DMA_CHANNEL_1, 01753 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), 01754 * (uint32_t)&< array or variable >, 01755 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); 01756 * @note For devices with several ADC: in multimode, some devices 01757 * use a different data register outside of ADC instance scope 01758 * (common data register). This macro manages this register difference, 01759 * only ADC instance has to be set as parameter. 01760 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n 01761 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n 01762 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr 01763 * @param ADCx ADC instance 01764 * @param Register This parameter can be one of the following values: 01765 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA 01766 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) 01767 * 01768 * (1) Available on devices with several ADC instances. 01769 * @retval ADC register address 01770 */ 01771 #if defined(ADC_MULTIMODE_SUPPORT) 01772 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) 01773 { 01774 register uint32_t data_reg_addr = 0U; 01775 01776 if (Register == LL_ADC_DMA_REG_REGULAR_DATA) 01777 { 01778 /* Retrieve address of register DR */ 01779 data_reg_addr = (uint32_t)&(ADCx->DR); 01780 } 01781 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ 01782 { 01783 /* Retrieve address of register CDR */ 01784 data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); 01785 } 01786 01787 return data_reg_addr; 01788 } 01789 #else 01790 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) 01791 { 01792 /* Retrieve address of register DR */ 01793 return (uint32_t)&(ADCx->DR); 01794 } 01795 #endif 01796 01797 /** 01798 * @} 01799 */ 01800 01801 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances 01802 * @{ 01803 */ 01804 01805 /** 01806 * @brief Set parameter common to several ADC: Clock source and prescaler. 01807 * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock 01808 * @param ADCxy_COMMON ADC common instance 01809 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 01810 * @param CommonClock This parameter can be one of the following values: 01811 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 01812 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 01813 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6 01814 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 01815 * @retval None 01816 */ 01817 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) 01818 { 01819 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock); 01820 } 01821 01822 /** 01823 * @brief Get parameter common to several ADC: Clock source and prescaler. 01824 * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock 01825 * @param ADCxy_COMMON ADC common instance 01826 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 01827 * @retval Returned value can be one of the following values: 01828 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 01829 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 01830 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6 01831 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 01832 */ 01833 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) 01834 { 01835 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE)); 01836 } 01837 01838 /** 01839 * @brief Set parameter common to several ADC: measurement path to internal 01840 * channels (VrefInt, temperature sensor, ...). 01841 * @note One or several values can be selected. 01842 * Example: (LL_ADC_PATH_INTERNAL_VREFINT | 01843 * LL_ADC_PATH_INTERNAL_TEMPSENSOR) 01844 * @note Stabilization time of measurement path to internal channel: 01845 * After enabling internal paths, before starting ADC conversion, 01846 * a delay is required for internal voltage reference and 01847 * temperature sensor stabilization time. 01848 * Refer to device datasheet. 01849 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. 01850 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. 01851 * @note ADC internal channel sampling time constraint: 01852 * For ADC conversion of internal channels, 01853 * a sampling time minimum value is required. 01854 * Refer to device datasheet. 01855 * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n 01856 * CCR VBATE LL_ADC_SetCommonPathInternalCh 01857 * @param ADCxy_COMMON ADC common instance 01858 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 01859 * @param PathInternal This parameter can be a combination of the following values: 01860 * @arg @ref LL_ADC_PATH_INTERNAL_NONE 01861 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT 01862 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR 01863 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT 01864 * @retval None 01865 */ 01866 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) 01867 { 01868 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal); 01869 } 01870 01871 /** 01872 * @brief Get parameter common to several ADC: measurement path to internal 01873 * channels (VrefInt, temperature sensor, ...). 01874 * @note One or several values can be selected. 01875 * Example: (LL_ADC_PATH_INTERNAL_VREFINT | 01876 * LL_ADC_PATH_INTERNAL_TEMPSENSOR) 01877 * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n 01878 * CCR VBATE LL_ADC_GetCommonPathInternalCh 01879 * @param ADCxy_COMMON ADC common instance 01880 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 01881 * @retval Returned value can be a combination of the following values: 01882 * @arg @ref LL_ADC_PATH_INTERNAL_NONE 01883 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT 01884 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR 01885 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT 01886 */ 01887 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) 01888 { 01889 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE)); 01890 } 01891 01892 /** 01893 * @} 01894 */ 01895 01896 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance 01897 * @{ 01898 */ 01899 01900 /** 01901 * @brief Set ADC resolution. 01902 * Refer to reference manual for alignments formats 01903 * dependencies to ADC resolutions. 01904 * @rmtoll CR1 RES LL_ADC_SetResolution 01905 * @param ADCx ADC instance 01906 * @param Resolution This parameter can be one of the following values: 01907 * @arg @ref LL_ADC_RESOLUTION_12B 01908 * @arg @ref LL_ADC_RESOLUTION_10B 01909 * @arg @ref LL_ADC_RESOLUTION_8B 01910 * @arg @ref LL_ADC_RESOLUTION_6B 01911 * @retval None 01912 */ 01913 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) 01914 { 01915 MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution); 01916 } 01917 01918 /** 01919 * @brief Get ADC resolution. 01920 * Refer to reference manual for alignments formats 01921 * dependencies to ADC resolutions. 01922 * @rmtoll CR1 RES LL_ADC_GetResolution 01923 * @param ADCx ADC instance 01924 * @retval Returned value can be one of the following values: 01925 * @arg @ref LL_ADC_RESOLUTION_12B 01926 * @arg @ref LL_ADC_RESOLUTION_10B 01927 * @arg @ref LL_ADC_RESOLUTION_8B 01928 * @arg @ref LL_ADC_RESOLUTION_6B 01929 */ 01930 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) 01931 { 01932 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES)); 01933 } 01934 01935 /** 01936 * @brief Set ADC conversion data alignment. 01937 * @note Refer to reference manual for alignments formats 01938 * dependencies to ADC resolutions. 01939 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment 01940 * @param ADCx ADC instance 01941 * @param DataAlignment This parameter can be one of the following values: 01942 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT 01943 * @arg @ref LL_ADC_DATA_ALIGN_LEFT 01944 * @retval None 01945 */ 01946 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) 01947 { 01948 MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment); 01949 } 01950 01951 /** 01952 * @brief Get ADC conversion data alignment. 01953 * @note Refer to reference manual for alignments formats 01954 * dependencies to ADC resolutions. 01955 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment 01956 * @param ADCx ADC instance 01957 * @retval Returned value can be one of the following values: 01958 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT 01959 * @arg @ref LL_ADC_DATA_ALIGN_LEFT 01960 */ 01961 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) 01962 { 01963 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN)); 01964 } 01965 01966 /** 01967 * @brief Set ADC sequencers scan mode, for all ADC groups 01968 * (group regular, group injected). 01969 * @note According to sequencers scan mode : 01970 * - If disabled: ADC conversion is performed in unitary conversion 01971 * mode (one channel converted, that defined in rank 1). 01972 * Configuration of sequencers of all ADC groups 01973 * (sequencer scan length, ...) is discarded: equivalent to 01974 * scan length of 1 rank. 01975 * - If enabled: ADC conversions are performed in sequence conversions 01976 * mode, according to configuration of sequencers of 01977 * each ADC group (sequencer scan length, ...). 01978 * Refer to function @ref LL_ADC_REG_SetSequencerLength() 01979 * and to function @ref LL_ADC_INJ_SetSequencerLength(). 01980 * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode 01981 * @param ADCx ADC instance 01982 * @param ScanMode This parameter can be one of the following values: 01983 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE 01984 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE 01985 * @retval None 01986 */ 01987 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode) 01988 { 01989 MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode); 01990 } 01991 01992 /** 01993 * @brief Get ADC sequencers scan mode, for all ADC groups 01994 * (group regular, group injected). 01995 * @note According to sequencers scan mode : 01996 * - If disabled: ADC conversion is performed in unitary conversion 01997 * mode (one channel converted, that defined in rank 1). 01998 * Configuration of sequencers of all ADC groups 01999 * (sequencer scan length, ...) is discarded: equivalent to 02000 * scan length of 1 rank. 02001 * - If enabled: ADC conversions are performed in sequence conversions 02002 * mode, according to configuration of sequencers of 02003 * each ADC group (sequencer scan length, ...). 02004 * Refer to function @ref LL_ADC_REG_SetSequencerLength() 02005 * and to function @ref LL_ADC_INJ_SetSequencerLength(). 02006 * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode 02007 * @param ADCx ADC instance 02008 * @retval Returned value can be one of the following values: 02009 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE 02010 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE 02011 */ 02012 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) 02013 { 02014 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN)); 02015 } 02016 02017 /** 02018 * @} 02019 */ 02020 02021 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular 02022 * @{ 02023 */ 02024 02025 /** 02026 * @brief Set ADC group regular conversion trigger source: 02027 * internal (SW start) or from external IP (timer event, 02028 * external interrupt line). 02029 * @note On this STM32 serie, setting of external trigger edge is performed 02030 * using function @ref LL_ADC_REG_StartConversionExtTrig(). 02031 * @note Availability of parameters of trigger sources from timer 02032 * depends on timers availability on the selected device. 02033 * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n 02034 * CR2 EXTEN LL_ADC_REG_SetTriggerSource 02035 * @param ADCx ADC instance 02036 * @param TriggerSource This parameter can be one of the following values: 02037 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE 02038 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 02039 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 02040 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 02041 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 02042 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 02043 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4 02044 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO 02045 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 02046 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO 02047 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 02048 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 02049 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2 02050 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 02051 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 02052 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO 02053 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 02054 * @retval None 02055 */ 02056 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 02057 { 02058 /* Note: On this STM32 serie, ADC group regular external trigger edge */ 02059 /* is used to perform a ADC conversion start. */ 02060 /* This function does not set external trigger edge. */ 02061 /* This feature is set using function */ 02062 /* @ref LL_ADC_REG_StartConversionExtTrig(). */ 02063 MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL)); 02064 } 02065 02066 /** 02067 * @brief Get ADC group regular conversion trigger source: 02068 * internal (SW start) or from external IP (timer event, 02069 * external interrupt line). 02070 * @note To determine whether group regular trigger source is 02071 * internal (SW start) or external, without detail 02072 * of which peripheral is selected as external trigger, 02073 * (equivalent to 02074 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") 02075 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. 02076 * @note Availability of parameters of trigger sources from timer 02077 * depends on timers availability on the selected device. 02078 * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n 02079 * CR2 EXTEN LL_ADC_REG_GetTriggerSource 02080 * @param ADCx ADC instance 02081 * @retval Returned value can be one of the following values: 02082 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE 02083 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 02084 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 02085 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 02086 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 02087 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 02088 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4 02089 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO 02090 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 02091 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO 02092 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 02093 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 02094 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2 02095 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 02096 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 02097 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO 02098 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 02099 */ 02100 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) 02101 { 02102 register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN); 02103 02104 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ 02105 /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */ 02106 register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); 02107 02108 /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */ 02109 /* to match with triggers literals definition. */ 02110 return ((TriggerSource 02111 & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL) 02112 | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN) 02113 ); 02114 } 02115 02116 /** 02117 * @brief Get ADC group regular conversion trigger source internal (SW start) 02118 or external. 02119 * @note In case of group regular trigger source set to external trigger, 02120 * to determine which peripheral is selected as external trigger, 02121 * use function @ref LL_ADC_REG_GetTriggerSource(). 02122 * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart 02123 * @param ADCx ADC instance 02124 * @retval Value "0" if trigger source external trigger 02125 * Value "1" if trigger source SW start. 02126 */ 02127 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) 02128 { 02129 return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN)); 02130 } 02131 02132 /** 02133 * @brief Get ADC group regular conversion trigger polarity. 02134 * @note Applicable only for trigger source set to external trigger. 02135 * @note On this STM32 serie, setting of external trigger edge is performed 02136 * using function @ref LL_ADC_REG_StartConversionExtTrig(). 02137 * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge 02138 * @param ADCx ADC instance 02139 * @retval Returned value can be one of the following values: 02140 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING 02141 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING 02142 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING 02143 */ 02144 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) 02145 { 02146 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN)); 02147 } 02148 02149 02150 /** 02151 * @brief Set ADC group regular sequencer length and scan direction. 02152 * @note Description of ADC group regular sequencer features: 02153 * - For devices with sequencer fully configurable 02154 * (function "LL_ADC_REG_SetSequencerRanks()" available): 02155 * sequencer length and each rank affectation to a channel 02156 * are configurable. 02157 * This function performs configuration of: 02158 * - Sequence length: Number of ranks in the scan sequence. 02159 * - Sequence direction: Unless specified in parameters, sequencer 02160 * scan direction is forward (from rank 1 to rank n). 02161 * Sequencer ranks are selected using 02162 * function "LL_ADC_REG_SetSequencerRanks()". 02163 * - For devices with sequencer not fully configurable 02164 * (function "LL_ADC_REG_SetSequencerChannels()" available): 02165 * sequencer length and each rank affectation to a channel 02166 * are defined by channel number. 02167 * This function performs configuration of: 02168 * - Sequence length: Number of ranks in the scan sequence is 02169 * defined by number of channels set in the sequence, 02170 * rank of each channel is fixed by channel HW number. 02171 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 02172 * - Sequence direction: Unless specified in parameters, sequencer 02173 * scan direction is forward (from lowest channel number to 02174 * highest channel number). 02175 * Sequencer ranks are selected using 02176 * function "LL_ADC_REG_SetSequencerChannels()". 02177 * @note On this STM32 serie, group regular sequencer configuration 02178 * is conditioned to ADC instance sequencer mode. 02179 * If ADC instance sequencer mode is disabled, sequencers of 02180 * all groups (group regular, group injected) can be configured 02181 * but their execution is disabled (limited to rank 1). 02182 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 02183 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 02184 * ADC conversion on only 1 channel. 02185 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength 02186 * @param ADCx ADC instance 02187 * @param SequencerNbRanks This parameter can be one of the following values: 02188 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE 02189 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS 02190 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS 02191 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS 02192 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS 02193 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS 02194 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS 02195 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS 02196 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS 02197 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS 02198 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS 02199 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS 02200 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS 02201 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS 02202 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS 02203 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS 02204 * @retval None 02205 */ 02206 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) 02207 { 02208 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); 02209 } 02210 02211 /** 02212 * @brief Get ADC group regular sequencer length and scan direction. 02213 * @note Description of ADC group regular sequencer features: 02214 * - For devices with sequencer fully configurable 02215 * (function "LL_ADC_REG_SetSequencerRanks()" available): 02216 * sequencer length and each rank affectation to a channel 02217 * are configurable. 02218 * This function retrieves: 02219 * - Sequence length: Number of ranks in the scan sequence. 02220 * - Sequence direction: Unless specified in parameters, sequencer 02221 * scan direction is forward (from rank 1 to rank n). 02222 * Sequencer ranks are selected using 02223 * function "LL_ADC_REG_SetSequencerRanks()". 02224 * - For devices with sequencer not fully configurable 02225 * (function "LL_ADC_REG_SetSequencerChannels()" available): 02226 * sequencer length and each rank affectation to a channel 02227 * are defined by channel number. 02228 * This function retrieves: 02229 * - Sequence length: Number of ranks in the scan sequence is 02230 * defined by number of channels set in the sequence, 02231 * rank of each channel is fixed by channel HW number. 02232 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 02233 * - Sequence direction: Unless specified in parameters, sequencer 02234 * scan direction is forward (from lowest channel number to 02235 * highest channel number). 02236 * Sequencer ranks are selected using 02237 * function "LL_ADC_REG_SetSequencerChannels()". 02238 * @note On this STM32 serie, group regular sequencer configuration 02239 * is conditioned to ADC instance sequencer mode. 02240 * If ADC instance sequencer mode is disabled, sequencers of 02241 * all groups (group regular, group injected) can be configured 02242 * but their execution is disabled (limited to rank 1). 02243 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 02244 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 02245 * ADC conversion on only 1 channel. 02246 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength 02247 * @param ADCx ADC instance 02248 * @retval Returned value can be one of the following values: 02249 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE 02250 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS 02251 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS 02252 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS 02253 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS 02254 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS 02255 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS 02256 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS 02257 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS 02258 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS 02259 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS 02260 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS 02261 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS 02262 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS 02263 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS 02264 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS 02265 */ 02266 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) 02267 { 02268 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); 02269 } 02270 02271 /** 02272 * @brief Set ADC group regular sequencer discontinuous mode: 02273 * sequence subdivided and scan conversions interrupted every selected 02274 * number of ranks. 02275 * @note It is not possible to enable both ADC group regular 02276 * continuous mode and sequencer discontinuous mode. 02277 * @note It is not possible to enable both ADC auto-injected mode 02278 * and ADC group regular sequencer discontinuous mode. 02279 * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n 02280 * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont 02281 * @param ADCx ADC instance 02282 * @param SeqDiscont This parameter can be one of the following values: 02283 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE 02284 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK 02285 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS 02286 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS 02287 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS 02288 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS 02289 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS 02290 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS 02291 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS 02292 * @retval None 02293 */ 02294 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) 02295 { 02296 MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont); 02297 } 02298 02299 /** 02300 * @brief Get ADC group regular sequencer discontinuous mode: 02301 * sequence subdivided and scan conversions interrupted every selected 02302 * number of ranks. 02303 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n 02304 * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont 02305 * @param ADCx ADC instance 02306 * @retval Returned value can be one of the following values: 02307 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE 02308 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK 02309 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS 02310 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS 02311 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS 02312 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS 02313 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS 02314 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS 02315 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS 02316 */ 02317 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) 02318 { 02319 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM)); 02320 } 02321 02322 /** 02323 * @brief Set ADC group regular sequence: channel on the selected 02324 * scan sequence rank. 02325 * @note This function performs configuration of: 02326 * - Channels ordering into each rank of scan sequence: 02327 * whatever channel can be placed into whatever rank. 02328 * @note On this STM32 serie, ADC group regular sequencer is 02329 * fully configurable: sequencer length and each rank 02330 * affectation to a channel are configurable. 02331 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). 02332 * @note Depending on devices and packages, some channels may not be available. 02333 * Refer to device datasheet for channels availability. 02334 * @note On this STM32 serie, to measure internal channels (VrefInt, 02335 * TempSensor, ...), measurement paths to internal channels must be 02336 * enabled separately. 02337 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). 02338 * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n 02339 * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n 02340 * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n 02341 * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n 02342 * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n 02343 * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n 02344 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n 02345 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n 02346 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n 02347 * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n 02348 * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n 02349 * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n 02350 * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n 02351 * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n 02352 * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n 02353 * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks 02354 * @param ADCx ADC instance 02355 * @param Rank This parameter can be one of the following values: 02356 * @arg @ref LL_ADC_REG_RANK_1 02357 * @arg @ref LL_ADC_REG_RANK_2 02358 * @arg @ref LL_ADC_REG_RANK_3 02359 * @arg @ref LL_ADC_REG_RANK_4 02360 * @arg @ref LL_ADC_REG_RANK_5 02361 * @arg @ref LL_ADC_REG_RANK_6 02362 * @arg @ref LL_ADC_REG_RANK_7 02363 * @arg @ref LL_ADC_REG_RANK_8 02364 * @arg @ref LL_ADC_REG_RANK_9 02365 * @arg @ref LL_ADC_REG_RANK_10 02366 * @arg @ref LL_ADC_REG_RANK_11 02367 * @arg @ref LL_ADC_REG_RANK_12 02368 * @arg @ref LL_ADC_REG_RANK_13 02369 * @arg @ref LL_ADC_REG_RANK_14 02370 * @arg @ref LL_ADC_REG_RANK_15 02371 * @arg @ref LL_ADC_REG_RANK_16 02372 * @param Channel This parameter can be one of the following values: 02373 * @arg @ref LL_ADC_CHANNEL_0 02374 * @arg @ref LL_ADC_CHANNEL_1 02375 * @arg @ref LL_ADC_CHANNEL_2 02376 * @arg @ref LL_ADC_CHANNEL_3 02377 * @arg @ref LL_ADC_CHANNEL_4 02378 * @arg @ref LL_ADC_CHANNEL_5 02379 * @arg @ref LL_ADC_CHANNEL_6 02380 * @arg @ref LL_ADC_CHANNEL_7 02381 * @arg @ref LL_ADC_CHANNEL_8 02382 * @arg @ref LL_ADC_CHANNEL_9 02383 * @arg @ref LL_ADC_CHANNEL_10 02384 * @arg @ref LL_ADC_CHANNEL_11 02385 * @arg @ref LL_ADC_CHANNEL_12 02386 * @arg @ref LL_ADC_CHANNEL_13 02387 * @arg @ref LL_ADC_CHANNEL_14 02388 * @arg @ref LL_ADC_CHANNEL_15 02389 * @arg @ref LL_ADC_CHANNEL_16 02390 * @arg @ref LL_ADC_CHANNEL_17 02391 * @arg @ref LL_ADC_CHANNEL_18 02392 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 02393 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 02394 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 02395 * 02396 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 02397 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 02398 * @retval None 02399 */ 02400 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) 02401 { 02402 /* Set bits with content of parameter "Channel" with bits position */ 02403 /* in register and register position depending on parameter "Rank". */ 02404 /* Parameters "Rank" and "Channel" are used with masks because containing */ 02405 /* other bits reserved for other purpose. */ 02406 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); 02407 02408 MODIFY_REG(*preg, 02409 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK), 02410 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); 02411 } 02412 02413 /** 02414 * @brief Get ADC group regular sequence: channel on the selected 02415 * scan sequence rank. 02416 * @note On this STM32 serie, ADC group regular sequencer is 02417 * fully configurable: sequencer length and each rank 02418 * affectation to a channel are configurable. 02419 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). 02420 * @note Depending on devices and packages, some channels may not be available. 02421 * Refer to device datasheet for channels availability. 02422 * @note Usage of the returned channel number: 02423 * - To reinject this channel into another function LL_ADC_xxx: 02424 * the returned channel number is only partly formatted on definition 02425 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 02426 * with parts of literals LL_ADC_CHANNEL_x or using 02427 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 02428 * Then the selected literal LL_ADC_CHANNEL_x can be used 02429 * as parameter for another function. 02430 * - To get the channel number in decimal format: 02431 * process the returned value with the helper macro 02432 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 02433 * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n 02434 * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n 02435 * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n 02436 * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n 02437 * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n 02438 * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n 02439 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n 02440 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n 02441 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n 02442 * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n 02443 * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n 02444 * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n 02445 * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n 02446 * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n 02447 * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n 02448 * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks 02449 * @param ADCx ADC instance 02450 * @param Rank This parameter can be one of the following values: 02451 * @arg @ref LL_ADC_REG_RANK_1 02452 * @arg @ref LL_ADC_REG_RANK_2 02453 * @arg @ref LL_ADC_REG_RANK_3 02454 * @arg @ref LL_ADC_REG_RANK_4 02455 * @arg @ref LL_ADC_REG_RANK_5 02456 * @arg @ref LL_ADC_REG_RANK_6 02457 * @arg @ref LL_ADC_REG_RANK_7 02458 * @arg @ref LL_ADC_REG_RANK_8 02459 * @arg @ref LL_ADC_REG_RANK_9 02460 * @arg @ref LL_ADC_REG_RANK_10 02461 * @arg @ref LL_ADC_REG_RANK_11 02462 * @arg @ref LL_ADC_REG_RANK_12 02463 * @arg @ref LL_ADC_REG_RANK_13 02464 * @arg @ref LL_ADC_REG_RANK_14 02465 * @arg @ref LL_ADC_REG_RANK_15 02466 * @arg @ref LL_ADC_REG_RANK_16 02467 * @retval Returned value can be one of the following values: 02468 * @arg @ref LL_ADC_CHANNEL_0 02469 * @arg @ref LL_ADC_CHANNEL_1 02470 * @arg @ref LL_ADC_CHANNEL_2 02471 * @arg @ref LL_ADC_CHANNEL_3 02472 * @arg @ref LL_ADC_CHANNEL_4 02473 * @arg @ref LL_ADC_CHANNEL_5 02474 * @arg @ref LL_ADC_CHANNEL_6 02475 * @arg @ref LL_ADC_CHANNEL_7 02476 * @arg @ref LL_ADC_CHANNEL_8 02477 * @arg @ref LL_ADC_CHANNEL_9 02478 * @arg @ref LL_ADC_CHANNEL_10 02479 * @arg @ref LL_ADC_CHANNEL_11 02480 * @arg @ref LL_ADC_CHANNEL_12 02481 * @arg @ref LL_ADC_CHANNEL_13 02482 * @arg @ref LL_ADC_CHANNEL_14 02483 * @arg @ref LL_ADC_CHANNEL_15 02484 * @arg @ref LL_ADC_CHANNEL_16 02485 * @arg @ref LL_ADC_CHANNEL_17 02486 * @arg @ref LL_ADC_CHANNEL_18 02487 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 02488 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 02489 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 02490 * 02491 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 02492 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n 02493 * (1) For ADC channel read back from ADC register, 02494 * comparison with internal channel parameter to be done 02495 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 02496 */ 02497 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) 02498 { 02499 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); 02500 02501 return (uint32_t) (READ_BIT(*preg, 02502 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) 02503 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) 02504 ); 02505 } 02506 02507 /** 02508 * @brief Set ADC continuous conversion mode on ADC group regular. 02509 * @note Description of ADC continuous conversion mode: 02510 * - single mode: one conversion per trigger 02511 * - continuous mode: after the first trigger, following 02512 * conversions launched successively automatically. 02513 * @note It is not possible to enable both ADC group regular 02514 * continuous mode and sequencer discontinuous mode. 02515 * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode 02516 * @param ADCx ADC instance 02517 * @param Continuous This parameter can be one of the following values: 02518 * @arg @ref LL_ADC_REG_CONV_SINGLE 02519 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS 02520 * @retval None 02521 */ 02522 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) 02523 { 02524 MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous); 02525 } 02526 02527 /** 02528 * @brief Get ADC continuous conversion mode on ADC group regular. 02529 * @note Description of ADC continuous conversion mode: 02530 * - single mode: one conversion per trigger 02531 * - continuous mode: after the first trigger, following 02532 * conversions launched successively automatically. 02533 * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode 02534 * @param ADCx ADC instance 02535 * @retval Returned value can be one of the following values: 02536 * @arg @ref LL_ADC_REG_CONV_SINGLE 02537 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS 02538 */ 02539 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) 02540 { 02541 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT)); 02542 } 02543 02544 /** 02545 * @brief Set ADC group regular conversion data transfer: no transfer or 02546 * transfer by DMA, and DMA requests mode. 02547 * @note If transfer by DMA selected, specifies the DMA requests 02548 * mode: 02549 * - Limited mode (One shot mode): DMA transfer requests are stopped 02550 * when number of DMA data transfers (number of 02551 * ADC conversions) is reached. 02552 * This ADC mode is intended to be used with DMA mode non-circular. 02553 * - Unlimited mode: DMA transfer requests are unlimited, 02554 * whatever number of DMA data transfers (number of 02555 * ADC conversions). 02556 * This ADC mode is intended to be used with DMA mode circular. 02557 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 02558 * mode non-circular: 02559 * when DMA transfers size will be reached, DMA will stop transfers of 02560 * ADC conversions data ADC will raise an overrun error 02561 * (overrun flag and interruption if enabled). 02562 * @note For devices with several ADC instances: ADC multimode DMA 02563 * settings are available using function @ref LL_ADC_SetMultiDMATransfer(). 02564 * @note To configure DMA source address (peripheral address), 02565 * use function @ref LL_ADC_DMA_GetRegAddr(). 02566 * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n 02567 * CR2 DDS LL_ADC_REG_SetDMATransfer 02568 * @param ADCx ADC instance 02569 * @param DMATransfer This parameter can be one of the following values: 02570 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE 02571 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED 02572 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED 02573 * @retval None 02574 */ 02575 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) 02576 { 02577 MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer); 02578 } 02579 02580 /** 02581 * @brief Get ADC group regular conversion data transfer: no transfer or 02582 * transfer by DMA, and DMA requests mode. 02583 * @note If transfer by DMA selected, specifies the DMA requests 02584 * mode: 02585 * - Limited mode (One shot mode): DMA transfer requests are stopped 02586 * when number of DMA data transfers (number of 02587 * ADC conversions) is reached. 02588 * This ADC mode is intended to be used with DMA mode non-circular. 02589 * - Unlimited mode: DMA transfer requests are unlimited, 02590 * whatever number of DMA data transfers (number of 02591 * ADC conversions). 02592 * This ADC mode is intended to be used with DMA mode circular. 02593 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 02594 * mode non-circular: 02595 * when DMA transfers size will be reached, DMA will stop transfers of 02596 * ADC conversions data ADC will raise an overrun error 02597 * (overrun flag and interruption if enabled). 02598 * @note For devices with several ADC instances: ADC multimode DMA 02599 * settings are available using function @ref LL_ADC_GetMultiDMATransfer(). 02600 * @note To configure DMA source address (peripheral address), 02601 * use function @ref LL_ADC_DMA_GetRegAddr(). 02602 * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n 02603 * CR2 DDS LL_ADC_REG_GetDMATransfer 02604 * @param ADCx ADC instance 02605 * @retval Returned value can be one of the following values: 02606 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE 02607 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED 02608 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED 02609 */ 02610 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) 02611 { 02612 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS)); 02613 } 02614 02615 /** 02616 * @brief Specify which ADC flag between EOC (end of unitary conversion) 02617 * or EOS (end of sequence conversions) is used to indicate 02618 * the end of conversion. 02619 * @note This feature is aimed to be set when using ADC with 02620 * programming model by polling or interruption 02621 * (programming model by DMA usually uses DMA interruptions 02622 * to indicate end of conversion and data transfer). 02623 * @note For ADC group injected, end of conversion (flag&IT) is raised 02624 * only at the end of the sequence. 02625 * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion 02626 * @param ADCx ADC instance 02627 * @param EocSelection This parameter can be one of the following values: 02628 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 02629 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV 02630 * @retval None 02631 */ 02632 __STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection) 02633 { 02634 MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection); 02635 } 02636 02637 /** 02638 * @brief Get which ADC flag between EOC (end of unitary conversion) 02639 * or EOS (end of sequence conversions) is used to indicate 02640 * the end of conversion. 02641 * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion 02642 * @param ADCx ADC instance 02643 * @retval Returned value can be one of the following values: 02644 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 02645 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV 02646 */ 02647 __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx) 02648 { 02649 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS)); 02650 } 02651 02652 /** 02653 * @} 02654 */ 02655 02656 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected 02657 * @{ 02658 */ 02659 02660 /** 02661 * @brief Set ADC group injected conversion trigger source: 02662 * internal (SW start) or from external IP (timer event, 02663 * external interrupt line). 02664 * @note On this STM32 serie, setting of external trigger edge is performed 02665 * using function @ref LL_ADC_INJ_StartConversionExtTrig(). 02666 * @note Availability of parameters of trigger sources from timer 02667 * depends on timers availability on the selected device. 02668 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n 02669 * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource 02670 * @param ADCx ADC instance 02671 * @param TriggerSource This parameter can be one of the following values: 02672 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE 02673 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 02674 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 02675 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 02676 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO 02677 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2 02678 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 02679 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1 02680 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2 02681 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 02682 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO 02683 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 02684 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO 02685 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 02686 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3 02687 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 02688 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 02689 * @retval None 02690 */ 02691 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 02692 { 02693 /* Note: On this STM32 serie, ADC group injected external trigger edge */ 02694 /* is used to perform a ADC conversion start. */ 02695 /* This function does not set external trigger edge. */ 02696 /* This feature is set using function */ 02697 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */ 02698 MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL)); 02699 } 02700 02701 /** 02702 * @brief Get ADC group injected conversion trigger source: 02703 * internal (SW start) or from external IP (timer event, 02704 * external interrupt line). 02705 * @note To determine whether group injected trigger source is 02706 * internal (SW start) or external, without detail 02707 * of which peripheral is selected as external trigger, 02708 * (equivalent to 02709 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") 02710 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. 02711 * @note Availability of parameters of trigger sources from timer 02712 * depends on timers availability on the selected device. 02713 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n 02714 * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource 02715 * @param ADCx ADC instance 02716 * @retval Returned value can be one of the following values: 02717 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE 02718 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 02719 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 02720 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 02721 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO 02722 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2 02723 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 02724 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1 02725 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2 02726 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 02727 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO 02728 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 02729 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO 02730 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 02731 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3 02732 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 02733 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 02734 */ 02735 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) 02736 { 02737 register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN); 02738 02739 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ 02740 /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */ 02741 register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U)); 02742 02743 /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */ 02744 /* to match with triggers literals definition. */ 02745 return ((TriggerSource 02746 & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL) 02747 | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN) 02748 ); 02749 } 02750 02751 /** 02752 * @brief Get ADC group injected conversion trigger source internal (SW start) 02753 or external 02754 * @note In case of group injected trigger source set to external trigger, 02755 * to determine which peripheral is selected as external trigger, 02756 * use function @ref LL_ADC_INJ_GetTriggerSource. 02757 * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart 02758 * @param ADCx ADC instance 02759 * @retval Value "0" if trigger source external trigger 02760 * Value "1" if trigger source SW start. 02761 */ 02762 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) 02763 { 02764 return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN)); 02765 } 02766 02767 /** 02768 * @brief Get ADC group injected conversion trigger polarity. 02769 * Applicable only for trigger source set to external trigger. 02770 * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge 02771 * @param ADCx ADC instance 02772 * @retval Returned value can be one of the following values: 02773 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING 02774 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING 02775 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING 02776 */ 02777 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) 02778 { 02779 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN)); 02780 } 02781 02782 /** 02783 * @brief Set ADC group injected sequencer length and scan direction. 02784 * @note This function performs configuration of: 02785 * - Sequence length: Number of ranks in the scan sequence. 02786 * - Sequence direction: Unless specified in parameters, sequencer 02787 * scan direction is forward (from rank 1 to rank n). 02788 * @note On this STM32 serie, group injected sequencer configuration 02789 * is conditioned to ADC instance sequencer mode. 02790 * If ADC instance sequencer mode is disabled, sequencers of 02791 * all groups (group regular, group injected) can be configured 02792 * but their execution is disabled (limited to rank 1). 02793 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 02794 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 02795 * ADC conversion on only 1 channel. 02796 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength 02797 * @param ADCx ADC instance 02798 * @param SequencerNbRanks This parameter can be one of the following values: 02799 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE 02800 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS 02801 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS 02802 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS 02803 * @retval None 02804 */ 02805 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) 02806 { 02807 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); 02808 } 02809 02810 /** 02811 * @brief Get ADC group injected sequencer length and scan direction. 02812 * @note This function retrieves: 02813 * - Sequence length: Number of ranks in the scan sequence. 02814 * - Sequence direction: Unless specified in parameters, sequencer 02815 * scan direction is forward (from rank 1 to rank n). 02816 * @note On this STM32 serie, group injected sequencer configuration 02817 * is conditioned to ADC instance sequencer mode. 02818 * If ADC instance sequencer mode is disabled, sequencers of 02819 * all groups (group regular, group injected) can be configured 02820 * but their execution is disabled (limited to rank 1). 02821 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 02822 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 02823 * ADC conversion on only 1 channel. 02824 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength 02825 * @param ADCx ADC instance 02826 * @retval Returned value can be one of the following values: 02827 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE 02828 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS 02829 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS 02830 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS 02831 */ 02832 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) 02833 { 02834 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); 02835 } 02836 02837 /** 02838 * @brief Set ADC group injected sequencer discontinuous mode: 02839 * sequence subdivided and scan conversions interrupted every selected 02840 * number of ranks. 02841 * @note It is not possible to enable both ADC group injected 02842 * auto-injected mode and sequencer discontinuous mode. 02843 * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont 02844 * @param ADCx ADC instance 02845 * @param SeqDiscont This parameter can be one of the following values: 02846 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE 02847 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK 02848 * @retval None 02849 */ 02850 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) 02851 { 02852 MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont); 02853 } 02854 02855 /** 02856 * @brief Get ADC group injected sequencer discontinuous mode: 02857 * sequence subdivided and scan conversions interrupted every selected 02858 * number of ranks. 02859 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont 02860 * @param ADCx ADC instance 02861 * @retval Returned value can be one of the following values: 02862 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE 02863 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK 02864 */ 02865 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) 02866 { 02867 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN)); 02868 } 02869 02870 /** 02871 * @brief Set ADC group injected sequence: channel on the selected 02872 * sequence rank. 02873 * @note Depending on devices and packages, some channels may not be available. 02874 * Refer to device datasheet for channels availability. 02875 * @note On this STM32 serie, to measure internal channels (VrefInt, 02876 * TempSensor, ...), measurement paths to internal channels must be 02877 * enabled separately. 02878 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). 02879 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n 02880 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n 02881 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n 02882 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks 02883 * @param ADCx ADC instance 02884 * @param Rank This parameter can be one of the following values: 02885 * @arg @ref LL_ADC_INJ_RANK_1 02886 * @arg @ref LL_ADC_INJ_RANK_2 02887 * @arg @ref LL_ADC_INJ_RANK_3 02888 * @arg @ref LL_ADC_INJ_RANK_4 02889 * @param Channel This parameter can be one of the following values: 02890 * @arg @ref LL_ADC_CHANNEL_0 02891 * @arg @ref LL_ADC_CHANNEL_1 02892 * @arg @ref LL_ADC_CHANNEL_2 02893 * @arg @ref LL_ADC_CHANNEL_3 02894 * @arg @ref LL_ADC_CHANNEL_4 02895 * @arg @ref LL_ADC_CHANNEL_5 02896 * @arg @ref LL_ADC_CHANNEL_6 02897 * @arg @ref LL_ADC_CHANNEL_7 02898 * @arg @ref LL_ADC_CHANNEL_8 02899 * @arg @ref LL_ADC_CHANNEL_9 02900 * @arg @ref LL_ADC_CHANNEL_10 02901 * @arg @ref LL_ADC_CHANNEL_11 02902 * @arg @ref LL_ADC_CHANNEL_12 02903 * @arg @ref LL_ADC_CHANNEL_13 02904 * @arg @ref LL_ADC_CHANNEL_14 02905 * @arg @ref LL_ADC_CHANNEL_15 02906 * @arg @ref LL_ADC_CHANNEL_16 02907 * @arg @ref LL_ADC_CHANNEL_17 02908 * @arg @ref LL_ADC_CHANNEL_18 02909 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 02910 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 02911 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 02912 * 02913 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 02914 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 02915 * @retval None 02916 */ 02917 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) 02918 { 02919 /* Set bits with content of parameter "Channel" with bits position */ 02920 /* in register depending on parameter "Rank". */ 02921 /* Parameters "Rank" and "Channel" are used with masks because containing */ 02922 /* other bits reserved for other purpose. */ 02923 register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; 02924 02925 MODIFY_REG(ADCx->JSQR, 02926 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))), 02927 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))); 02928 } 02929 02930 /** 02931 * @brief Get ADC group injected sequence: channel on the selected 02932 * sequence rank. 02933 * @note Depending on devices and packages, some channels may not be available. 02934 * Refer to device datasheet for channels availability. 02935 * @note Usage of the returned channel number: 02936 * - To reinject this channel into another function LL_ADC_xxx: 02937 * the returned channel number is only partly formatted on definition 02938 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 02939 * with parts of literals LL_ADC_CHANNEL_x or using 02940 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 02941 * Then the selected literal LL_ADC_CHANNEL_x can be used 02942 * as parameter for another function. 02943 * - To get the channel number in decimal format: 02944 * process the returned value with the helper macro 02945 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 02946 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n 02947 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n 02948 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n 02949 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks 02950 * @param ADCx ADC instance 02951 * @param Rank This parameter can be one of the following values: 02952 * @arg @ref LL_ADC_INJ_RANK_1 02953 * @arg @ref LL_ADC_INJ_RANK_2 02954 * @arg @ref LL_ADC_INJ_RANK_3 02955 * @arg @ref LL_ADC_INJ_RANK_4 02956 * @retval Returned value can be one of the following values: 02957 * @arg @ref LL_ADC_CHANNEL_0 02958 * @arg @ref LL_ADC_CHANNEL_1 02959 * @arg @ref LL_ADC_CHANNEL_2 02960 * @arg @ref LL_ADC_CHANNEL_3 02961 * @arg @ref LL_ADC_CHANNEL_4 02962 * @arg @ref LL_ADC_CHANNEL_5 02963 * @arg @ref LL_ADC_CHANNEL_6 02964 * @arg @ref LL_ADC_CHANNEL_7 02965 * @arg @ref LL_ADC_CHANNEL_8 02966 * @arg @ref LL_ADC_CHANNEL_9 02967 * @arg @ref LL_ADC_CHANNEL_10 02968 * @arg @ref LL_ADC_CHANNEL_11 02969 * @arg @ref LL_ADC_CHANNEL_12 02970 * @arg @ref LL_ADC_CHANNEL_13 02971 * @arg @ref LL_ADC_CHANNEL_14 02972 * @arg @ref LL_ADC_CHANNEL_15 02973 * @arg @ref LL_ADC_CHANNEL_16 02974 * @arg @ref LL_ADC_CHANNEL_17 02975 * @arg @ref LL_ADC_CHANNEL_18 02976 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 02977 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 02978 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 02979 * 02980 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 02981 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n 02982 * (1) For ADC channel read back from ADC register, 02983 * comparison with internal channel parameter to be done 02984 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 02985 */ 02986 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) 02987 { 02988 register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; 02989 02990 return (uint32_t)(READ_BIT(ADCx->JSQR, 02991 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))) 02992 >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))) 02993 ); 02994 } 02995 02996 /** 02997 * @brief Set ADC group injected conversion trigger: 02998 * independent or from ADC group regular. 02999 * @note This mode can be used to extend number of data registers 03000 * updated after one ADC conversion trigger and with data 03001 * permanently kept (not erased by successive conversions of scan of 03002 * ADC sequencer ranks), up to 5 data registers: 03003 * 1 data register on ADC group regular, 4 data registers 03004 * on ADC group injected. 03005 * @note If ADC group injected injected trigger source is set to an 03006 * external trigger, this feature must be must be set to 03007 * independent trigger. 03008 * ADC group injected automatic trigger is compliant only with 03009 * group injected trigger source set to SW start, without any 03010 * further action on ADC group injected conversion start or stop: 03011 * in this case, ADC group injected is controlled only 03012 * from ADC group regular. 03013 * @note It is not possible to enable both ADC group injected 03014 * auto-injected mode and sequencer discontinuous mode. 03015 * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto 03016 * @param ADCx ADC instance 03017 * @param TrigAuto This parameter can be one of the following values: 03018 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT 03019 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR 03020 * @retval None 03021 */ 03022 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) 03023 { 03024 MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto); 03025 } 03026 03027 /** 03028 * @brief Get ADC group injected conversion trigger: 03029 * independent or from ADC group regular. 03030 * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto 03031 * @param ADCx ADC instance 03032 * @retval Returned value can be one of the following values: 03033 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT 03034 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR 03035 */ 03036 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) 03037 { 03038 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO)); 03039 } 03040 03041 /** 03042 * @brief Set ADC group injected offset. 03043 * @note It sets: 03044 * - ADC group injected rank to which the offset programmed 03045 * will be applied 03046 * - Offset level (offset to be subtracted from the raw 03047 * converted data). 03048 * Caution: Offset format is dependent to ADC resolution: 03049 * offset has to be left-aligned on bit 11, the LSB (right bits) 03050 * are set to 0. 03051 * @note Offset cannot be enabled or disabled. 03052 * To emulate offset disabled, set an offset value equal to 0. 03053 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n 03054 * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n 03055 * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n 03056 * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset 03057 * @param ADCx ADC instance 03058 * @param Rank This parameter can be one of the following values: 03059 * @arg @ref LL_ADC_INJ_RANK_1 03060 * @arg @ref LL_ADC_INJ_RANK_2 03061 * @arg @ref LL_ADC_INJ_RANK_3 03062 * @arg @ref LL_ADC_INJ_RANK_4 03063 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF 03064 * @retval None 03065 */ 03066 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel) 03067 { 03068 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); 03069 03070 MODIFY_REG(*preg, 03071 ADC_JOFR1_JOFFSET1, 03072 OffsetLevel); 03073 } 03074 03075 /** 03076 * @brief Get ADC group injected offset. 03077 * @note It gives offset level (offset to be subtracted from the raw converted data). 03078 * Caution: Offset format is dependent to ADC resolution: 03079 * offset has to be left-aligned on bit 11, the LSB (right bits) 03080 * are set to 0. 03081 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n 03082 * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n 03083 * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n 03084 * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset 03085 * @param ADCx ADC instance 03086 * @param Rank This parameter can be one of the following values: 03087 * @arg @ref LL_ADC_INJ_RANK_1 03088 * @arg @ref LL_ADC_INJ_RANK_2 03089 * @arg @ref LL_ADC_INJ_RANK_3 03090 * @arg @ref LL_ADC_INJ_RANK_4 03091 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 03092 */ 03093 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) 03094 { 03095 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); 03096 03097 return (uint32_t)(READ_BIT(*preg, 03098 ADC_JOFR1_JOFFSET1) 03099 ); 03100 } 03101 03102 /** 03103 * @} 03104 */ 03105 03106 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels 03107 * @{ 03108 */ 03109 03110 /** 03111 * @brief Set sampling time of the selected ADC channel 03112 * Unit: ADC clock cycles. 03113 * @note On this device, sampling time is on channel scope: independently 03114 * of channel mapped on ADC group regular or injected. 03115 * @note In case of internal channel (VrefInt, TempSensor, ...) to be 03116 * converted: 03117 * sampling time constraints must be respected (sampling time can be 03118 * adjusted in function of ADC clock frequency and sampling time 03119 * setting). 03120 * Refer to device datasheet for timings values (parameters TS_vrefint, 03121 * TS_temp, ...). 03122 * @note Conversion time is the addition of sampling time and processing time. 03123 * Refer to reference manual for ADC processing time of 03124 * this STM32 serie. 03125 * @note In case of ADC conversion of internal channel (VrefInt, 03126 * temperature sensor, ...), a sampling time minimum value 03127 * is required. 03128 * Refer to device datasheet. 03129 * @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n 03130 * SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n 03131 * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n 03132 * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n 03133 * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n 03134 * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n 03135 * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n 03136 * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n 03137 * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n 03138 * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n 03139 * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n 03140 * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n 03141 * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n 03142 * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n 03143 * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n 03144 * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n 03145 * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n 03146 * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n 03147 * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime 03148 * @param ADCx ADC instance 03149 * @param Channel This parameter can be one of the following values: 03150 * @arg @ref LL_ADC_CHANNEL_0 03151 * @arg @ref LL_ADC_CHANNEL_1 03152 * @arg @ref LL_ADC_CHANNEL_2 03153 * @arg @ref LL_ADC_CHANNEL_3 03154 * @arg @ref LL_ADC_CHANNEL_4 03155 * @arg @ref LL_ADC_CHANNEL_5 03156 * @arg @ref LL_ADC_CHANNEL_6 03157 * @arg @ref LL_ADC_CHANNEL_7 03158 * @arg @ref LL_ADC_CHANNEL_8 03159 * @arg @ref LL_ADC_CHANNEL_9 03160 * @arg @ref LL_ADC_CHANNEL_10 03161 * @arg @ref LL_ADC_CHANNEL_11 03162 * @arg @ref LL_ADC_CHANNEL_12 03163 * @arg @ref LL_ADC_CHANNEL_13 03164 * @arg @ref LL_ADC_CHANNEL_14 03165 * @arg @ref LL_ADC_CHANNEL_15 03166 * @arg @ref LL_ADC_CHANNEL_16 03167 * @arg @ref LL_ADC_CHANNEL_17 03168 * @arg @ref LL_ADC_CHANNEL_18 03169 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 03170 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 03171 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 03172 * 03173 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 03174 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 03175 * @param SamplingTime This parameter can be one of the following values: 03176 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES 03177 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES 03178 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES 03179 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES 03180 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES 03181 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES 03182 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES 03183 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES 03184 * @retval None 03185 */ 03186 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) 03187 { 03188 /* Set bits with content of parameter "SamplingTime" with bits position */ 03189 /* in register and register position depending on parameter "Channel". */ 03190 /* Parameter "Channel" is used with masks because containing */ 03191 /* other bits reserved for other purpose. */ 03192 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); 03193 03194 MODIFY_REG(*preg, 03195 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), 03196 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); 03197 } 03198 03199 /** 03200 * @brief Get sampling time of the selected ADC channel 03201 * Unit: ADC clock cycles. 03202 * @note On this device, sampling time is on channel scope: independently 03203 * of channel mapped on ADC group regular or injected. 03204 * @note Conversion time is the addition of sampling time and processing time. 03205 * Refer to reference manual for ADC processing time of 03206 * this STM32 serie. 03207 * @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n 03208 * SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n 03209 * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n 03210 * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n 03211 * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n 03212 * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n 03213 * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n 03214 * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n 03215 * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n 03216 * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n 03217 * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n 03218 * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n 03219 * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n 03220 * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n 03221 * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n 03222 * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n 03223 * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n 03224 * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n 03225 * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime 03226 * @param ADCx ADC instance 03227 * @param Channel This parameter can be one of the following values: 03228 * @arg @ref LL_ADC_CHANNEL_0 03229 * @arg @ref LL_ADC_CHANNEL_1 03230 * @arg @ref LL_ADC_CHANNEL_2 03231 * @arg @ref LL_ADC_CHANNEL_3 03232 * @arg @ref LL_ADC_CHANNEL_4 03233 * @arg @ref LL_ADC_CHANNEL_5 03234 * @arg @ref LL_ADC_CHANNEL_6 03235 * @arg @ref LL_ADC_CHANNEL_7 03236 * @arg @ref LL_ADC_CHANNEL_8 03237 * @arg @ref LL_ADC_CHANNEL_9 03238 * @arg @ref LL_ADC_CHANNEL_10 03239 * @arg @ref LL_ADC_CHANNEL_11 03240 * @arg @ref LL_ADC_CHANNEL_12 03241 * @arg @ref LL_ADC_CHANNEL_13 03242 * @arg @ref LL_ADC_CHANNEL_14 03243 * @arg @ref LL_ADC_CHANNEL_15 03244 * @arg @ref LL_ADC_CHANNEL_16 03245 * @arg @ref LL_ADC_CHANNEL_17 03246 * @arg @ref LL_ADC_CHANNEL_18 03247 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 03248 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) 03249 * @arg @ref LL_ADC_CHANNEL_VBAT (1) 03250 * 03251 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 03252 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 03253 * @retval Returned value can be one of the following values: 03254 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES 03255 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES 03256 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES 03257 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES 03258 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES 03259 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES 03260 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES 03261 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES 03262 */ 03263 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) 03264 { 03265 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); 03266 03267 return (uint32_t)(READ_BIT(*preg, 03268 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) 03269 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) 03270 ); 03271 } 03272 03273 /** 03274 * @} 03275 */ 03276 03277 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog 03278 * @{ 03279 */ 03280 03281 /** 03282 * @brief Set ADC analog watchdog monitored channels: 03283 * a single channel or all channels, 03284 * on ADC groups regular and-or injected. 03285 * @note Once monitored channels are selected, analog watchdog 03286 * is enabled. 03287 * @note In case of need to define a single channel to monitor 03288 * with analog watchdog from sequencer channel definition, 03289 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). 03290 * @note On this STM32 serie, there is only 1 kind of analog watchdog 03291 * instance: 03292 * - AWD standard (instance AWD1): 03293 * - channels monitored: can monitor 1 channel or all channels. 03294 * - groups monitored: ADC groups regular and-or injected. 03295 * - resolution: resolution is not limited (corresponds to 03296 * ADC resolution configured). 03297 * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n 03298 * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n 03299 * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels 03300 * @param ADCx ADC instance 03301 * @param AWDChannelGroup This parameter can be one of the following values: 03302 * @arg @ref LL_ADC_AWD_DISABLE 03303 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG 03304 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ 03305 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 03306 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG 03307 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 03308 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 03309 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG 03310 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 03311 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 03312 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG 03313 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 03314 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 03315 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG 03316 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 03317 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 03318 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG 03319 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 03320 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 03321 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG 03322 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 03323 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 03324 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG 03325 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 03326 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 03327 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG 03328 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 03329 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 03330 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG 03331 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 03332 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 03333 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG 03334 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 03335 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 03336 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG 03337 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ 03338 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 03339 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG 03340 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ 03341 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 03342 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG 03343 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ 03344 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 03345 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG 03346 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ 03347 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 03348 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG 03349 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ 03350 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 03351 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG 03352 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ 03353 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 03354 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG 03355 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ 03356 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 03357 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG 03358 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ 03359 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 03360 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG 03361 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ 03362 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ 03363 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) 03364 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) 03365 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) 03366 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2) 03367 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2) 03368 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2) 03369 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1) 03370 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1) 03371 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) 03372 * 03373 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n 03374 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. 03375 * @retval None 03376 */ 03377 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup) 03378 { 03379 MODIFY_REG(ADCx->CR1, 03380 (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH), 03381 AWDChannelGroup); 03382 } 03383 03384 /** 03385 * @brief Get ADC analog watchdog monitored channel. 03386 * @note Usage of the returned channel number: 03387 * - To reinject this channel into another function LL_ADC_xxx: 03388 * the returned channel number is only partly formatted on definition 03389 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 03390 * with parts of literals LL_ADC_CHANNEL_x or using 03391 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 03392 * Then the selected literal LL_ADC_CHANNEL_x can be used 03393 * as parameter for another function. 03394 * - To get the channel number in decimal format: 03395 * process the returned value with the helper macro 03396 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 03397 * Applicable only when the analog watchdog is set to monitor 03398 * one channel. 03399 * @note On this STM32 serie, there is only 1 kind of analog watchdog 03400 * instance: 03401 * - AWD standard (instance AWD1): 03402 * - channels monitored: can monitor 1 channel or all channels. 03403 * - groups monitored: ADC groups regular and-or injected. 03404 * - resolution: resolution is not limited (corresponds to 03405 * ADC resolution configured). 03406 * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n 03407 * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n 03408 * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels 03409 * @param ADCx ADC instance 03410 * @retval Returned value can be one of the following values: 03411 * @arg @ref LL_ADC_AWD_DISABLE 03412 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG 03413 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ 03414 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 03415 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG 03416 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 03417 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 03418 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG 03419 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 03420 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 03421 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG 03422 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 03423 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 03424 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG 03425 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 03426 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 03427 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG 03428 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 03429 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 03430 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG 03431 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 03432 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 03433 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG 03434 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 03435 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 03436 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG 03437 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 03438 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 03439 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG 03440 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 03441 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 03442 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG 03443 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 03444 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 03445 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG 03446 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ 03447 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 03448 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG 03449 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ 03450 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 03451 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG 03452 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ 03453 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 03454 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG 03455 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ 03456 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 03457 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG 03458 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ 03459 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 03460 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG 03461 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ 03462 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 03463 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG 03464 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ 03465 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 03466 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG 03467 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ 03468 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 03469 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG 03470 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ 03471 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ 03472 */ 03473 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) 03474 { 03475 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH))); 03476 } 03477 03478 /** 03479 * @brief Set ADC analog watchdog threshold value of threshold 03480 * high or low. 03481 * @note In case of ADC resolution different of 12 bits, 03482 * analog watchdog thresholds data require a specific shift. 03483 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). 03484 * @note On this STM32 serie, there is only 1 kind of analog watchdog 03485 * instance: 03486 * - AWD standard (instance AWD1): 03487 * - channels monitored: can monitor 1 channel or all channels. 03488 * - groups monitored: ADC groups regular and-or injected. 03489 * - resolution: resolution is not limited (corresponds to 03490 * ADC resolution configured). 03491 * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n 03492 * LTR LT LL_ADC_SetAnalogWDThresholds 03493 * @param ADCx ADC instance 03494 * @param AWDThresholdsHighLow This parameter can be one of the following values: 03495 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH 03496 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW 03497 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF 03498 * @retval None 03499 */ 03500 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) 03501 { 03502 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); 03503 03504 MODIFY_REG(*preg, 03505 ADC_HTR_HT, 03506 AWDThresholdValue); 03507 } 03508 03509 /** 03510 * @brief Get ADC analog watchdog threshold value of threshold high or 03511 * threshold low. 03512 * @note In case of ADC resolution different of 12 bits, 03513 * analog watchdog thresholds data require a specific shift. 03514 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). 03515 * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n 03516 * LTR LT LL_ADC_GetAnalogWDThresholds 03517 * @param ADCx ADC instance 03518 * @param AWDThresholdsHighLow This parameter can be one of the following values: 03519 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH 03520 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW 03521 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 03522 */ 03523 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) 03524 { 03525 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); 03526 03527 return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT)); 03528 } 03529 03530 /** 03531 * @} 03532 */ 03533 03534 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode 03535 * @{ 03536 */ 03537 03538 #if defined(ADC_MULTIMODE_SUPPORT) 03539 /** 03540 * @brief Set ADC multimode configuration to operate in independent mode 03541 * or multimode (for devices with several ADC instances). 03542 * @note If multimode configuration: the selected ADC instance is 03543 * either master or slave depending on hardware. 03544 * Refer to reference manual. 03545 * @rmtoll CCR MULTI LL_ADC_SetMultimode 03546 * @param ADCxy_COMMON ADC common instance 03547 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03548 * @param Multimode This parameter can be one of the following values: 03549 * @arg @ref LL_ADC_MULTI_INDEPENDENT 03550 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT 03551 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL 03552 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT 03553 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN 03554 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM 03555 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT 03556 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM 03557 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM 03558 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT 03559 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT 03560 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT 03561 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL 03562 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN 03563 * @retval None 03564 */ 03565 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) 03566 { 03567 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode); 03568 } 03569 03570 /** 03571 * @brief Get ADC multimode configuration to operate in independent mode 03572 * or multimode (for devices with several ADC instances). 03573 * @note If multimode configuration: the selected ADC instance is 03574 * either master or slave depending on hardware. 03575 * Refer to reference manual. 03576 * @rmtoll CCR MULTI LL_ADC_GetMultimode 03577 * @param ADCxy_COMMON ADC common instance 03578 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03579 * @retval Returned value can be one of the following values: 03580 * @arg @ref LL_ADC_MULTI_INDEPENDENT 03581 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT 03582 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL 03583 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT 03584 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN 03585 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM 03586 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT 03587 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM 03588 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM 03589 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT 03590 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT 03591 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT 03592 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL 03593 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN 03594 */ 03595 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) 03596 { 03597 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI)); 03598 } 03599 03600 /** 03601 * @brief Set ADC multimode conversion data transfer: no transfer 03602 * or transfer by DMA. 03603 * @note If ADC multimode transfer by DMA is not selected: 03604 * each ADC uses its own DMA channel, with its individual 03605 * DMA transfer settings. 03606 * If ADC multimode transfer by DMA is selected: 03607 * One DMA channel is used for both ADC (DMA of ADC master) 03608 * Specifies the DMA requests mode: 03609 * - Limited mode (One shot mode): DMA transfer requests are stopped 03610 * when number of DMA data transfers (number of 03611 * ADC conversions) is reached. 03612 * This ADC mode is intended to be used with DMA mode non-circular. 03613 * - Unlimited mode: DMA transfer requests are unlimited, 03614 * whatever number of DMA data transfers (number of 03615 * ADC conversions). 03616 * This ADC mode is intended to be used with DMA mode circular. 03617 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 03618 * mode non-circular: 03619 * when DMA transfers size will be reached, DMA will stop transfers of 03620 * ADC conversions data ADC will raise an overrun error 03621 * (overrun flag and interruption if enabled). 03622 * @note How to retrieve multimode conversion data: 03623 * Whatever multimode transfer by DMA setting: using function 03624 * @ref LL_ADC_REG_ReadMultiConversionData32(). 03625 * If ADC multimode transfer by DMA is selected: conversion data 03626 * is a raw data with ADC master and slave concatenated. 03627 * A macro is available to get the conversion data of 03628 * ADC master or ADC slave: see helper macro 03629 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 03630 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n 03631 * CCR DDS LL_ADC_SetMultiDMATransfer 03632 * @param ADCxy_COMMON ADC common instance 03633 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03634 * @param MultiDMATransfer This parameter can be one of the following values: 03635 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC 03636 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1 03637 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2 03638 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3 03639 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1 03640 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2 03641 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3 03642 * @retval None 03643 */ 03644 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer) 03645 { 03646 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer); 03647 } 03648 03649 /** 03650 * @brief Get ADC multimode conversion data transfer: no transfer 03651 * or transfer by DMA. 03652 * @note If ADC multimode transfer by DMA is not selected: 03653 * each ADC uses its own DMA channel, with its individual 03654 * DMA transfer settings. 03655 * If ADC multimode transfer by DMA is selected: 03656 * One DMA channel is used for both ADC (DMA of ADC master) 03657 * Specifies the DMA requests mode: 03658 * - Limited mode (One shot mode): DMA transfer requests are stopped 03659 * when number of DMA data transfers (number of 03660 * ADC conversions) is reached. 03661 * This ADC mode is intended to be used with DMA mode non-circular. 03662 * - Unlimited mode: DMA transfer requests are unlimited, 03663 * whatever number of DMA data transfers (number of 03664 * ADC conversions). 03665 * This ADC mode is intended to be used with DMA mode circular. 03666 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 03667 * mode non-circular: 03668 * when DMA transfers size will be reached, DMA will stop transfers of 03669 * ADC conversions data ADC will raise an overrun error 03670 * (overrun flag and interruption if enabled). 03671 * @note How to retrieve multimode conversion data: 03672 * Whatever multimode transfer by DMA setting: using function 03673 * @ref LL_ADC_REG_ReadMultiConversionData32(). 03674 * If ADC multimode transfer by DMA is selected: conversion data 03675 * is a raw data with ADC master and slave concatenated. 03676 * A macro is available to get the conversion data of 03677 * ADC master or ADC slave: see helper macro 03678 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 03679 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n 03680 * CCR DDS LL_ADC_GetMultiDMATransfer 03681 * @param ADCxy_COMMON ADC common instance 03682 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03683 * @retval Returned value can be one of the following values: 03684 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC 03685 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1 03686 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2 03687 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3 03688 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1 03689 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2 03690 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3 03691 */ 03692 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON) 03693 { 03694 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS)); 03695 } 03696 03697 /** 03698 * @brief Set ADC multimode delay between 2 sampling phases. 03699 * @note The sampling delay range depends on ADC resolution: 03700 * - ADC resolution 12 bits can have maximum delay of 12 cycles. 03701 * - ADC resolution 10 bits can have maximum delay of 10 cycles. 03702 * - ADC resolution 8 bits can have maximum delay of 8 cycles. 03703 * - ADC resolution 6 bits can have maximum delay of 6 cycles. 03704 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay 03705 * @param ADCxy_COMMON ADC common instance 03706 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03707 * @param MultiTwoSamplingDelay This parameter can be one of the following values: 03708 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 03709 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES 03710 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES 03711 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES 03712 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES 03713 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES 03714 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES 03715 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES 03716 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES 03717 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES 03718 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES 03719 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES 03720 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES 03721 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES 03722 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES 03723 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES 03724 * @retval None 03725 */ 03726 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay) 03727 { 03728 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay); 03729 } 03730 03731 /** 03732 * @brief Get ADC multimode delay between 2 sampling phases. 03733 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay 03734 * @param ADCxy_COMMON ADC common instance 03735 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03736 * @retval Returned value can be one of the following values: 03737 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 03738 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES 03739 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES 03740 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES 03741 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES 03742 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES 03743 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES 03744 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES 03745 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES 03746 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES 03747 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES 03748 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES 03749 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES 03750 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES 03751 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES 03752 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES 03753 */ 03754 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON) 03755 { 03756 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); 03757 } 03758 #endif /* ADC_MULTIMODE_SUPPORT */ 03759 03760 /** 03761 * @} 03762 */ 03763 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance 03764 * @{ 03765 */ 03766 03767 /** 03768 * @brief Enable the selected ADC instance. 03769 * @note On this STM32 serie, after ADC enable, a delay for 03770 * ADC internal analog stabilization is required before performing a 03771 * ADC conversion start. 03772 * Refer to device datasheet, parameter tSTAB. 03773 * @rmtoll CR2 ADON LL_ADC_Enable 03774 * @param ADCx ADC instance 03775 * @retval None 03776 */ 03777 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) 03778 { 03779 SET_BIT(ADCx->CR2, ADC_CR2_ADON); 03780 } 03781 03782 /** 03783 * @brief Disable the selected ADC instance. 03784 * @rmtoll CR2 ADON LL_ADC_Disable 03785 * @param ADCx ADC instance 03786 * @retval None 03787 */ 03788 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) 03789 { 03790 CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON); 03791 } 03792 03793 /** 03794 * @brief Get the selected ADC instance enable state. 03795 * @rmtoll CR2 ADON LL_ADC_IsEnabled 03796 * @param ADCx ADC instance 03797 * @retval 0: ADC is disabled, 1: ADC is enabled. 03798 */ 03799 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) 03800 { 03801 return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON)); 03802 } 03803 03804 /** 03805 * @} 03806 */ 03807 03808 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular 03809 * @{ 03810 */ 03811 03812 /** 03813 * @brief Start ADC group regular conversion. 03814 * @note On this STM32 serie, this function is relevant only for 03815 * internal trigger (SW start), not for external trigger: 03816 * - If ADC trigger has been set to software start, ADC conversion 03817 * starts immediately. 03818 * - If ADC trigger has been set to external trigger, ADC conversion 03819 * start must be performed using function 03820 * @ref LL_ADC_REG_StartConversionExtTrig(). 03821 * (if external trigger edge would have been set during ADC other 03822 * settings, ADC conversion would start at trigger event 03823 * as soon as ADC is enabled). 03824 * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart 03825 * @param ADCx ADC instance 03826 * @retval None 03827 */ 03828 __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx) 03829 { 03830 SET_BIT(ADCx->CR2, ADC_CR2_SWSTART); 03831 } 03832 03833 /** 03834 * @brief Start ADC group regular conversion from external trigger. 03835 * @note ADC conversion will start at next trigger event (on the selected 03836 * trigger edge) following the ADC start conversion command. 03837 * @note On this STM32 serie, this function is relevant for 03838 * ADC conversion start from external trigger. 03839 * If internal trigger (SW start) is needed, perform ADC conversion 03840 * start using function @ref LL_ADC_REG_StartConversionSWStart(). 03841 * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig 03842 * @param ExternalTriggerEdge This parameter can be one of the following values: 03843 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING 03844 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING 03845 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING 03846 * @param ADCx ADC instance 03847 * @retval None 03848 */ 03849 __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) 03850 { 03851 SET_BIT(ADCx->CR2, ExternalTriggerEdge); 03852 } 03853 03854 /** 03855 * @brief Stop ADC group regular conversion from external trigger. 03856 * @note No more ADC conversion will start at next trigger event 03857 * following the ADC stop conversion command. 03858 * If a conversion is on-going, it will be completed. 03859 * @note On this STM32 serie, there is no specific command 03860 * to stop a conversion on-going or to stop ADC converting 03861 * in continuous mode. These actions can be performed 03862 * using function @ref LL_ADC_Disable(). 03863 * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig 03864 * @param ADCx ADC instance 03865 * @retval None 03866 */ 03867 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx) 03868 { 03869 CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN); 03870 } 03871 03872 /** 03873 * @brief Get ADC group regular conversion data, range fit for 03874 * all ADC configurations: all ADC resolutions and 03875 * all oversampling increased data width (for devices 03876 * with feature oversampling). 03877 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 03878 * @param ADCx ADC instance 03879 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 03880 */ 03881 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) 03882 { 03883 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 03884 } 03885 03886 /** 03887 * @brief Get ADC group regular conversion data, range fit for 03888 * ADC resolution 12 bits. 03889 * @note For devices with feature oversampling: Oversampling 03890 * can increase data width, function for extended range 03891 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 03892 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 03893 * @param ADCx ADC instance 03894 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 03895 */ 03896 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) 03897 { 03898 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 03899 } 03900 03901 /** 03902 * @brief Get ADC group regular conversion data, range fit for 03903 * ADC resolution 10 bits. 03904 * @note For devices with feature oversampling: Oversampling 03905 * can increase data width, function for extended range 03906 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 03907 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10 03908 * @param ADCx ADC instance 03909 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 03910 */ 03911 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) 03912 { 03913 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 03914 } 03915 03916 /** 03917 * @brief Get ADC group regular conversion data, range fit for 03918 * ADC resolution 8 bits. 03919 * @note For devices with feature oversampling: Oversampling 03920 * can increase data width, function for extended range 03921 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 03922 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8 03923 * @param ADCx ADC instance 03924 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 03925 */ 03926 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) 03927 { 03928 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 03929 } 03930 03931 /** 03932 * @brief Get ADC group regular conversion data, range fit for 03933 * ADC resolution 6 bits. 03934 * @note For devices with feature oversampling: Oversampling 03935 * can increase data width, function for extended range 03936 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 03937 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6 03938 * @param ADCx ADC instance 03939 * @retval Value between Min_Data=0x00 and Max_Data=0x3F 03940 */ 03941 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) 03942 { 03943 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 03944 } 03945 03946 #if defined(ADC_MULTIMODE_SUPPORT) 03947 /** 03948 * @brief Get ADC multimode conversion data of ADC master, ADC slave 03949 * or raw data with ADC master and slave concatenated. 03950 * @note If raw data with ADC master and slave concatenated is retrieved, 03951 * a macro is available to get the conversion data of 03952 * ADC master or ADC slave: see helper macro 03953 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 03954 * (however this macro is mainly intended for multimode 03955 * transfer by DMA, because this function can do the same 03956 * by getting multimode conversion data of ADC master or ADC slave 03957 * separately). 03958 * @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n 03959 * CDR DATA2 LL_ADC_REG_ReadMultiConversionData32 03960 * @param ADCxy_COMMON ADC common instance 03961 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 03962 * @param ConversionData This parameter can be one of the following values: 03963 * @arg @ref LL_ADC_MULTI_MASTER 03964 * @arg @ref LL_ADC_MULTI_SLAVE 03965 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE 03966 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 03967 */ 03968 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) 03969 { 03970 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, 03971 ADC_DR_ADC2DATA) 03972 >> POSITION_VAL(ConversionData) 03973 ); 03974 } 03975 #endif /* ADC_MULTIMODE_SUPPORT */ 03976 03977 /** 03978 * @} 03979 */ 03980 03981 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected 03982 * @{ 03983 */ 03984 03985 /** 03986 * @brief Start ADC group injected conversion. 03987 * @note On this STM32 serie, this function is relevant only for 03988 * internal trigger (SW start), not for external trigger: 03989 * - If ADC trigger has been set to software start, ADC conversion 03990 * starts immediately. 03991 * - If ADC trigger has been set to external trigger, ADC conversion 03992 * start must be performed using function 03993 * @ref LL_ADC_INJ_StartConversionExtTrig(). 03994 * (if external trigger edge would have been set during ADC other 03995 * settings, ADC conversion would start at trigger event 03996 * as soon as ADC is enabled). 03997 * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart 03998 * @param ADCx ADC instance 03999 * @retval None 04000 */ 04001 __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx) 04002 { 04003 SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART); 04004 } 04005 04006 /** 04007 * @brief Start ADC group injected conversion from external trigger. 04008 * @note ADC conversion will start at next trigger event (on the selected 04009 * trigger edge) following the ADC start conversion command. 04010 * @note On this STM32 serie, this function is relevant for 04011 * ADC conversion start from external trigger. 04012 * If internal trigger (SW start) is needed, perform ADC conversion 04013 * start using function @ref LL_ADC_INJ_StartConversionSWStart(). 04014 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig 04015 * @param ExternalTriggerEdge This parameter can be one of the following values: 04016 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING 04017 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING 04018 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING 04019 * @param ADCx ADC instance 04020 * @retval None 04021 */ 04022 __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) 04023 { 04024 SET_BIT(ADCx->CR2, ExternalTriggerEdge); 04025 } 04026 04027 /** 04028 * @brief Stop ADC group injected conversion from external trigger. 04029 * @note No more ADC conversion will start at next trigger event 04030 * following the ADC stop conversion command. 04031 * If a conversion is on-going, it will be completed. 04032 * @note On this STM32 serie, there is no specific command 04033 * to stop a conversion on-going or to stop ADC converting 04034 * in continuous mode. These actions can be performed 04035 * using function @ref LL_ADC_Disable(). 04036 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig 04037 * @param ADCx ADC instance 04038 * @retval None 04039 */ 04040 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx) 04041 { 04042 CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN); 04043 } 04044 04045 /** 04046 * @brief Get ADC group regular conversion data, range fit for 04047 * all ADC configurations: all ADC resolutions and 04048 * all oversampling increased data width (for devices 04049 * with feature oversampling). 04050 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n 04051 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n 04052 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n 04053 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 04054 * @param ADCx ADC instance 04055 * @param Rank This parameter can be one of the following values: 04056 * @arg @ref LL_ADC_INJ_RANK_1 04057 * @arg @ref LL_ADC_INJ_RANK_2 04058 * @arg @ref LL_ADC_INJ_RANK_3 04059 * @arg @ref LL_ADC_INJ_RANK_4 04060 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 04061 */ 04062 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) 04063 { 04064 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 04065 04066 return (uint32_t)(READ_BIT(*preg, 04067 ADC_JDR1_JDATA) 04068 ); 04069 } 04070 04071 /** 04072 * @brief Get ADC group injected conversion data, range fit for 04073 * ADC resolution 12 bits. 04074 * @note For devices with feature oversampling: Oversampling 04075 * can increase data width, function for extended range 04076 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 04077 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n 04078 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n 04079 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n 04080 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 04081 * @param ADCx ADC instance 04082 * @param Rank This parameter can be one of the following values: 04083 * @arg @ref LL_ADC_INJ_RANK_1 04084 * @arg @ref LL_ADC_INJ_RANK_2 04085 * @arg @ref LL_ADC_INJ_RANK_3 04086 * @arg @ref LL_ADC_INJ_RANK_4 04087 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 04088 */ 04089 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) 04090 { 04091 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 04092 04093 return (uint16_t)(READ_BIT(*preg, 04094 ADC_JDR1_JDATA) 04095 ); 04096 } 04097 04098 /** 04099 * @brief Get ADC group injected conversion data, range fit for 04100 * ADC resolution 10 bits. 04101 * @note For devices with feature oversampling: Oversampling 04102 * can increase data width, function for extended range 04103 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 04104 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n 04105 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n 04106 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n 04107 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10 04108 * @param ADCx ADC instance 04109 * @param Rank This parameter can be one of the following values: 04110 * @arg @ref LL_ADC_INJ_RANK_1 04111 * @arg @ref LL_ADC_INJ_RANK_2 04112 * @arg @ref LL_ADC_INJ_RANK_3 04113 * @arg @ref LL_ADC_INJ_RANK_4 04114 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 04115 */ 04116 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) 04117 { 04118 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 04119 04120 return (uint16_t)(READ_BIT(*preg, 04121 ADC_JDR1_JDATA) 04122 ); 04123 } 04124 04125 /** 04126 * @brief Get ADC group injected conversion data, range fit for 04127 * ADC resolution 8 bits. 04128 * @note For devices with feature oversampling: Oversampling 04129 * can increase data width, function for extended range 04130 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 04131 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n 04132 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n 04133 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n 04134 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8 04135 * @param ADCx ADC instance 04136 * @param Rank This parameter can be one of the following values: 04137 * @arg @ref LL_ADC_INJ_RANK_1 04138 * @arg @ref LL_ADC_INJ_RANK_2 04139 * @arg @ref LL_ADC_INJ_RANK_3 04140 * @arg @ref LL_ADC_INJ_RANK_4 04141 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 04142 */ 04143 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) 04144 { 04145 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 04146 04147 return (uint8_t)(READ_BIT(*preg, 04148 ADC_JDR1_JDATA) 04149 ); 04150 } 04151 04152 /** 04153 * @brief Get ADC group injected conversion data, range fit for 04154 * ADC resolution 6 bits. 04155 * @note For devices with feature oversampling: Oversampling 04156 * can increase data width, function for extended range 04157 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 04158 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n 04159 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n 04160 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n 04161 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6 04162 * @param ADCx ADC instance 04163 * @param Rank This parameter can be one of the following values: 04164 * @arg @ref LL_ADC_INJ_RANK_1 04165 * @arg @ref LL_ADC_INJ_RANK_2 04166 * @arg @ref LL_ADC_INJ_RANK_3 04167 * @arg @ref LL_ADC_INJ_RANK_4 04168 * @retval Value between Min_Data=0x00 and Max_Data=0x3F 04169 */ 04170 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) 04171 { 04172 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 04173 04174 return (uint8_t)(READ_BIT(*preg, 04175 ADC_JDR1_JDATA) 04176 ); 04177 } 04178 04179 /** 04180 * @} 04181 */ 04182 04183 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management 04184 * @{ 04185 */ 04186 04187 /** 04188 * @brief Get flag ADC group regular end of unitary conversion 04189 * or end of sequence conversions, depending on 04190 * ADC configuration. 04191 * @note To configure flag of end of conversion, 04192 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 04193 * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS 04194 * @param ADCx ADC instance 04195 * @retval State of bit (1 or 0). 04196 */ 04197 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx) 04198 { 04199 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS)); 04200 } 04201 04202 /** 04203 * @brief Get flag ADC group regular overrun. 04204 * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR 04205 * @param ADCx ADC instance 04206 * @retval State of bit (1 or 0). 04207 */ 04208 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) 04209 { 04210 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)); 04211 } 04212 04213 04214 /** 04215 * @brief Get flag ADC group injected end of sequence conversions. 04216 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS 04217 * @param ADCx ADC instance 04218 * @retval State of bit (1 or 0). 04219 */ 04220 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) 04221 { 04222 /* Note: on this STM32 serie, there is no flag ADC group injected */ 04223 /* end of unitary conversion. */ 04224 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 04225 /* in other STM32 families). */ 04226 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); 04227 } 04228 04229 /** 04230 * @brief Get flag ADC analog watchdog 1 flag 04231 * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1 04232 * @param ADCx ADC instance 04233 * @retval State of bit (1 or 0). 04234 */ 04235 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) 04236 { 04237 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); 04238 } 04239 04240 /** 04241 * @brief Clear flag ADC group regular end of unitary conversion 04242 * or end of sequence conversions, depending on 04243 * ADC configuration. 04244 * @note To configure flag of end of conversion, 04245 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 04246 * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS 04247 * @param ADCx ADC instance 04248 * @retval None 04249 */ 04250 __STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx) 04251 { 04252 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS); 04253 } 04254 04255 /** 04256 * @brief Clear flag ADC group regular overrun. 04257 * @rmtoll SR OVR LL_ADC_ClearFlag_OVR 04258 * @param ADCx ADC instance 04259 * @retval None 04260 */ 04261 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) 04262 { 04263 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR); 04264 } 04265 04266 04267 /** 04268 * @brief Clear flag ADC group injected end of sequence conversions. 04269 * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS 04270 * @param ADCx ADC instance 04271 * @retval None 04272 */ 04273 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) 04274 { 04275 /* Note: on this STM32 serie, there is no flag ADC group injected */ 04276 /* end of unitary conversion. */ 04277 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 04278 /* in other STM32 families). */ 04279 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS); 04280 } 04281 04282 /** 04283 * @brief Clear flag ADC analog watchdog 1. 04284 * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1 04285 * @param ADCx ADC instance 04286 * @retval None 04287 */ 04288 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) 04289 { 04290 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1); 04291 } 04292 04293 #if defined(ADC_MULTIMODE_SUPPORT) 04294 /** 04295 * @brief Get flag multimode ADC group regular end of unitary conversion 04296 * or end of sequence conversions, depending on 04297 * ADC configuration, of the ADC master. 04298 * @note To configure flag of end of conversion, 04299 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 04300 * @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS 04301 * @param ADCxy_COMMON ADC common instance 04302 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04303 * @retval State of bit (1 or 0). 04304 */ 04305 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) 04306 { 04307 return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS)); 04308 } 04309 04310 /** 04311 * @brief Get flag multimode ADC group regular end of unitary conversion 04312 * or end of sequence conversions, depending on 04313 * ADC configuration, of the ADC slave 1. 04314 * @note To configure flag of end of conversion, 04315 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 04316 * @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS 04317 * @param ADCxy_COMMON ADC common instance 04318 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04319 * @retval State of bit (1 or 0). 04320 */ 04321 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) 04322 { 04323 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1)); 04324 } 04325 04326 /** 04327 * @brief Get flag multimode ADC group regular end of unitary conversion 04328 * or end of sequence conversions, depending on 04329 * ADC configuration, of the ADC slave 2. 04330 * @note To configure flag of end of conversion, 04331 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 04332 * @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS 04333 * @param ADCxy_COMMON ADC common instance 04334 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04335 * @retval State of bit (1 or 0). 04336 */ 04337 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) 04338 { 04339 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2)); 04340 } 04341 /** 04342 * @brief Get flag multimode ADC group regular overrun of the ADC master. 04343 * @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR 04344 * @param ADCxy_COMMON ADC common instance 04345 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04346 * @retval State of bit (1 or 0). 04347 */ 04348 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) 04349 { 04350 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)); 04351 } 04352 04353 /** 04354 * @brief Get flag multimode ADC group regular overrun of the ADC slave 1. 04355 * @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR 04356 * @param ADCxy_COMMON ADC common instance 04357 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04358 * @retval State of bit (1 or 0). 04359 */ 04360 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON) 04361 { 04362 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1)); 04363 } 04364 04365 /** 04366 * @brief Get flag multimode ADC group regular overrun of the ADC slave 2. 04367 * @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR 04368 * @param ADCxy_COMMON ADC common instance 04369 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04370 * @retval State of bit (1 or 0). 04371 */ 04372 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON) 04373 { 04374 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2)); 04375 } 04376 04377 04378 /** 04379 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. 04380 * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_EOCS 04381 * @param ADCxy_COMMON ADC common instance 04382 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04383 * @retval State of bit (1 or 0). 04384 */ 04385 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) 04386 { 04387 /* Note: on this STM32 serie, there is no flag ADC group injected */ 04388 /* end of unitary conversion. */ 04389 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 04390 /* in other STM32 families). */ 04391 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1)); 04392 } 04393 04394 /** 04395 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1. 04396 * @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS 04397 * @param ADCxy_COMMON ADC common instance 04398 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04399 * @retval State of bit (1 or 0). 04400 */ 04401 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) 04402 { 04403 /* Note: on this STM32 serie, there is no flag ADC group injected */ 04404 /* end of unitary conversion. */ 04405 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 04406 /* in other STM32 families). */ 04407 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2)); 04408 } 04409 04410 /** 04411 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2. 04412 * @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS 04413 * @param ADCxy_COMMON ADC common instance 04414 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04415 * @retval State of bit (1 or 0). 04416 */ 04417 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) 04418 { 04419 /* Note: on this STM32 serie, there is no flag ADC group injected */ 04420 /* end of unitary conversion. */ 04421 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 04422 /* in other STM32 families). */ 04423 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3)); 04424 } 04425 04426 /** 04427 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. 04428 * @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1 04429 * @param ADCxy_COMMON ADC common instance 04430 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04431 * @retval State of bit (1 or 0). 04432 */ 04433 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) 04434 { 04435 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)); 04436 } 04437 04438 /** 04439 * @brief Get flag multimode analog watchdog 1 of the ADC slave 1. 04440 * @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1 04441 * @param ADCxy_COMMON ADC common instance 04442 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04443 * @retval State of bit (1 or 0). 04444 */ 04445 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) 04446 { 04447 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1)); 04448 } 04449 04450 /** 04451 * @brief Get flag multimode analog watchdog 1 of the ADC slave 2. 04452 * @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1 04453 * @param ADCxy_COMMON ADC common instance 04454 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 04455 * @retval State of bit (1 or 0). 04456 */ 04457 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) 04458 { 04459 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2)); 04460 } 04461 04462 #endif /* ADC_MULTIMODE_SUPPORT */ 04463 04464 /** 04465 * @} 04466 */ 04467 04468 /** @defgroup ADC_LL_EF_IT_Management ADC IT management 04469 * @{ 04470 */ 04471 04472 /** 04473 * @brief Enable interruption ADC group regular end of unitary conversion 04474 * or end of sequence conversions, depending on 04475 * ADC configuration. 04476 * @note To configure flag of end of conversion, 04477 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 04478 * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS 04479 * @param ADCx ADC instance 04480 * @retval None 04481 */ 04482 __STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx) 04483 { 04484 SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS); 04485 } 04486 04487 /** 04488 * @brief Enable ADC group regular interruption overrun. 04489 * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR 04490 * @param ADCx ADC instance 04491 * @retval None 04492 */ 04493 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) 04494 { 04495 SET_BIT(ADCx->CR1, LL_ADC_IT_OVR); 04496 } 04497 04498 04499 /** 04500 * @brief Enable interruption ADC group injected end of sequence conversions. 04501 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS 04502 * @param ADCx ADC instance 04503 * @retval None 04504 */ 04505 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) 04506 { 04507 /* Note: on this STM32 serie, there is no flag ADC group injected */ 04508 /* end of unitary conversion. */ 04509 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 04510 /* in other STM32 families). */ 04511 SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS); 04512 } 04513 04514 /** 04515 * @brief Enable interruption ADC analog watchdog 1. 04516 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 04517 * @param ADCx ADC instance 04518 * @retval None 04519 */ 04520 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) 04521 { 04522 SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1); 04523 } 04524 04525 /** 04526 * @brief Disable interruption ADC group regular end of unitary conversion 04527 * or end of sequence conversions, depending on 04528 * ADC configuration. 04529 * @note To configure flag of end of conversion, 04530 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 04531 * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS 04532 * @param ADCx ADC instance 04533 * @retval None 04534 */ 04535 __STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx) 04536 { 04537 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS); 04538 } 04539 04540 /** 04541 * @brief Disable interruption ADC group regular overrun. 04542 * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR 04543 * @param ADCx ADC instance 04544 * @retval None 04545 */ 04546 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) 04547 { 04548 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR); 04549 } 04550 04551 04552 /** 04553 * @brief Disable interruption ADC group injected end of sequence conversions. 04554 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS 04555 * @param ADCx ADC instance 04556 * @retval None 04557 */ 04558 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) 04559 { 04560 /* Note: on this STM32 serie, there is no flag ADC group injected */ 04561 /* end of unitary conversion. */ 04562 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 04563 /* in other STM32 families). */ 04564 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS); 04565 } 04566 04567 /** 04568 * @brief Disable interruption ADC analog watchdog 1. 04569 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 04570 * @param ADCx ADC instance 04571 * @retval None 04572 */ 04573 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) 04574 { 04575 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1); 04576 } 04577 04578 /** 04579 * @brief Get state of interruption ADC group regular end of unitary conversion 04580 * or end of sequence conversions, depending on 04581 * ADC configuration. 04582 * @note To configure flag of end of conversion, 04583 * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). 04584 * (0: interrupt disabled, 1: interrupt enabled) 04585 * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS 04586 * @param ADCx ADC instance 04587 * @retval State of bit (1 or 0). 04588 */ 04589 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx) 04590 { 04591 return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS)); 04592 } 04593 04594 /** 04595 * @brief Get state of interruption ADC group regular overrun 04596 * (0: interrupt disabled, 1: interrupt enabled). 04597 * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR 04598 * @param ADCx ADC instance 04599 * @retval State of bit (1 or 0). 04600 */ 04601 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) 04602 { 04603 return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)); 04604 } 04605 04606 04607 /** 04608 * @brief Get state of interruption ADC group injected end of sequence conversions 04609 * (0: interrupt disabled, 1: interrupt enabled). 04610 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS 04611 * @param ADCx ADC instance 04612 * @retval State of bit (1 or 0). 04613 */ 04614 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) 04615 { 04616 /* Note: on this STM32 serie, there is no flag ADC group injected */ 04617 /* end of unitary conversion. */ 04618 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 04619 /* in other STM32 families). */ 04620 return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); 04621 } 04622 04623 /** 04624 * @brief Get state of interruption ADC analog watchdog 1 04625 * (0: interrupt disabled, 1: interrupt enabled). 04626 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 04627 * @param ADCx ADC instance 04628 * @retval State of bit (1 or 0). 04629 */ 04630 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) 04631 { 04632 return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); 04633 } 04634 04635 /** 04636 * @} 04637 */ 04638 04639 #if defined(USE_FULL_LL_DRIVER) 04640 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions 04641 * @{ 04642 */ 04643 04644 /* Initialization of some features of ADC common parameters and multimode */ 04645 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); 04646 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); 04647 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); 04648 04649 /* De-initialization of ADC instance, ADC group regular and ADC group injected */ 04650 /* (availability of ADC group injected depends on STM32 families) */ 04651 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); 04652 04653 /* Initialization of some features of ADC instance */ 04654 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); 04655 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); 04656 04657 /* Initialization of some features of ADC instance and ADC group regular */ 04658 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); 04659 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); 04660 04661 /* Initialization of some features of ADC instance and ADC group injected */ 04662 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); 04663 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); 04664 04665 /** 04666 * @} 04667 */ 04668 #endif /* USE_FULL_LL_DRIVER */ 04669 04670 /** 04671 * @} 04672 */ 04673 04674 /** 04675 * @} 04676 */ 04677 04678 #endif /* ADC1 || ADC2 || ADC3 */ 04679 04680 /** 04681 * @} 04682 */ 04683 04684 #ifdef __cplusplus 04685 } 04686 #endif 04687 04688 #endif /* __STM32F4xx_LL_ADC_H */ 04689 04690 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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