STM32F439xx HAL User Manual
Defines
Multimode - DMA transfer
ADC Exported Constants

Defines

#define LL_ADC_MULTI_REG_DMA_EACH_ADC   0x00000000U
#define LL_ADC_MULTI_REG_DMA_LIMIT_1   ( ADC_CCR_DMA_0)
#define LL_ADC_MULTI_REG_DMA_LIMIT_2   ( ADC_CCR_DMA_1 )
#define LL_ADC_MULTI_REG_DMA_LIMIT_3   ( ADC_CCR_DMA_0 | ADC_CCR_DMA_0)
#define LL_ADC_MULTI_REG_DMA_UNLMT_1   (ADC_CCR_DDS | ADC_CCR_DMA_0)
#define LL_ADC_MULTI_REG_DMA_UNLMT_2   (ADC_CCR_DDS | ADC_CCR_DMA_1 )
#define LL_ADC_MULTI_REG_DMA_UNLMT_3   (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0)

Define Documentation

#define LL_ADC_MULTI_REG_DMA_EACH_ADC   0x00000000U

ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings

Definition at line 999 of file stm32f4xx_ll_adc.h.

Referenced by LL_ADC_CommonStructInit().

#define LL_ADC_MULTI_REG_DMA_LIMIT_1   ( ADC_CCR_DMA_0)

ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3.

Definition at line 1000 of file stm32f4xx_ll_adc.h.

#define LL_ADC_MULTI_REG_DMA_LIMIT_2   ( ADC_CCR_DMA_1 )

ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2.

Definition at line 1001 of file stm32f4xx_ll_adc.h.

#define LL_ADC_MULTI_REG_DMA_LIMIT_3   ( ADC_CCR_DMA_0 | ADC_CCR_DMA_0)

ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2.

Definition at line 1002 of file stm32f4xx_ll_adc.h.

#define LL_ADC_MULTI_REG_DMA_UNLMT_1   (ADC_CCR_DDS | ADC_CCR_DMA_0)

ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3.

Definition at line 1003 of file stm32f4xx_ll_adc.h.

#define LL_ADC_MULTI_REG_DMA_UNLMT_2   (ADC_CCR_DDS | ADC_CCR_DMA_1 )

ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2.

Definition at line 1004 of file stm32f4xx_ll_adc.h.

#define LL_ADC_MULTI_REG_DMA_UNLMT_3   (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0)

ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2.

Definition at line 1005 of file stm32f4xx_ll_adc.h.