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STM32F439xx HAL User Manual
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Defines | |
| #define | ADC_SQR1_REGOFFSET 0x00000000U |
| #define | ADC_SQR2_REGOFFSET 0x00000100U |
| #define | ADC_SQR3_REGOFFSET 0x00000200U |
| #define | ADC_SQR4_REGOFFSET 0x00000300U |
| #define | ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) |
| #define | ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) |
| #define | ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */ |
| #define | ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */ |
| #define | ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */ |
| #define | ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */ |
| #define | ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */ |
| #define | ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */ |
| #define | ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ |
| #define | ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ |
| #define | ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ |
| #define | ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */ |
| #define | ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */ |
| #define | ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */ |
| #define | ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */ |
| #define | ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */ |
| #define | ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */ |
| #define | ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */ |
| #define | ADC_JDR1_REGOFFSET 0x00000000U |
| #define | ADC_JDR2_REGOFFSET 0x00000100U |
| #define | ADC_JDR3_REGOFFSET 0x00000200U |
| #define | ADC_JDR4_REGOFFSET 0x00000300U |
| #define | ADC_JOFR1_REGOFFSET 0x00000000U |
| #define | ADC_JOFR2_REGOFFSET 0x00001000U |
| #define | ADC_JOFR3_REGOFFSET 0x00002000U |
| #define | ADC_JOFR4_REGOFFSET 0x00003000U |
| #define | ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) |
| #define | ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET) |
| #define | ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) |
| #define | ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ |
| #define | ADC_REG_TRIG_SOURCE_MASK |
| #define | ADC_REG_TRIG_EDGE_MASK |
| #define | ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */ |
| #define | ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */ |
| #define | ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ |
| #define | ADC_INJ_TRIG_SOURCE_MASK |
| #define | ADC_INJ_TRIG_EDGE_MASK |
| #define | ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */ |
| #define | ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */ |
| #define | ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH) |
| #define | ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ |
| #define | ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) |
| #define | ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ |
| #define | ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */ |
| #define | ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ |
| #define | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */ |
| #define | ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) |
| #define | ADC_SMPR1_REGOFFSET 0x00000000U |
| #define | ADC_SMPR2_REGOFFSET 0x02000000U |
| #define | ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) |
| #define | ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U |
| #define | ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ |
| #define | ADC_CHANNEL_0_NUMBER 0x00000000U |
| #define | ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0) |
| #define | ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 ) |
| #define | ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) |
| #define | ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 ) |
| #define | ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) |
| #define | ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) |
| #define | ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) |
| #define | ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 ) |
| #define | ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0) |
| #define | ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 ) |
| #define | ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) |
| #define | ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 ) |
| #define | ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) |
| #define | ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) |
| #define | ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) |
| #define | ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 ) |
| #define | ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0) |
| #define | ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 ) |
| #define | ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */ |
| #define | ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */ |
| #define | ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */ |
| #define | ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */ |
| #define | ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */ |
| #define | ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */ |
| #define | ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */ |
| #define | ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */ |
| #define | ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */ |
| #define | ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */ |
| #define | ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */ |
| #define | ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */ |
| #define | ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */ |
| #define | ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */ |
| #define | ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */ |
| #define | ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */ |
| #define | ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */ |
| #define | ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */ |
| #define | ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */ |
| #define | ADC_AWD_CR1_REGOFFSET 0x00000000U |
| #define | ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) |
| #define | ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) |
| #define | ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) |
| #define | ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U |
| #define | ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U |
| #define | ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET) |
| #define | ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */ |
| #define | ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */ |
| #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) |
Definition at line 261 of file stm32f4xx_ll_adc.h.
| #define ADC_AWD_CR1_REGOFFSET 0x00000000U |
Definition at line 257 of file stm32f4xx_ll_adc.h.
Definition at line 262 of file stm32f4xx_ll_adc.h.
Definition at line 259 of file stm32f4xx_ll_adc.h.
| #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U |
Definition at line 265 of file stm32f4xx_ll_adc.h.
| #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U |
Definition at line 266 of file stm32f4xx_ll_adc.h.
Definition at line 267 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_0_NUMBER 0x00000000U |
Definition at line 207 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */ |
Definition at line 229 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 ) |
Definition at line 217 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */ |
Definition at line 239 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) |
Definition at line 218 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */ |
Definition at line 240 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 ) |
Definition at line 219 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */ |
Definition at line 241 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) |
Definition at line 220 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */ |
Definition at line 242 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) |
Definition at line 221 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */ |
Definition at line 243 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) |
Definition at line 222 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */ |
Definition at line 244 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 ) |
Definition at line 223 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */ |
Definition at line 245 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0) |
Definition at line 224 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */ |
Definition at line 246 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 ) |
Definition at line 225 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */ |
Definition at line 247 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0) |
Definition at line 208 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */ |
Definition at line 230 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 ) |
Definition at line 209 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */ |
Definition at line 231 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) |
Definition at line 210 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */ |
Definition at line 232 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 ) |
Definition at line 211 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */ |
Definition at line 233 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) |
Definition at line 212 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */ |
Definition at line 234 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) |
Definition at line 213 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */ |
Definition at line 235 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) |
Definition at line 214 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */ |
Definition at line 236 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 ) |
Definition at line 215 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */ |
Definition at line 237 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0) |
Definition at line 216 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */ |
Definition at line 238 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */ |
Definition at line 193 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */ |
Definition at line 191 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ |
Definition at line 192 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) |
Definition at line 194 of file stm32f4xx_ll_adc.h.
Definition at line 186 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ |
Definition at line 185 of file stm32f4xx_ll_adc.h.
| #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH) |
Definition at line 184 of file stm32f4xx_ll_adc.h.
Referenced by LL_ADC_INJ_GetSequencerRanks(), LL_ADC_INJ_SetSequencerRanks(), LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().
| #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ |
Definition at line 188 of file stm32f4xx_ll_adc.h.
Definition at line 200 of file stm32f4xx_ll_adc.h.
Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().
| #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U |
Definition at line 202 of file stm32f4xx_ll_adc.h.
Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().
| #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ |
Definition at line 203 of file stm32f4xx_ll_adc.h.
| #define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */ |
Definition at line 270 of file stm32f4xx_ll_adc.h.
| #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) |
Definition at line 119 of file stm32f4xx_ll_adc.h.
Referenced by LL_ADC_INJ_ReadConversionData10(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData32(), LL_ADC_INJ_ReadConversionData6(), and LL_ADC_INJ_ReadConversionData8().
| #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET) |
Definition at line 120 of file stm32f4xx_ll_adc.h.
Referenced by LL_ADC_INJ_GetOffset(), and LL_ADC_INJ_SetOffset().
Definition at line 121 of file stm32f4xx_ll_adc.h.
| #define ADC_INJ_TRIG_EDGE_MASK |
(((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
Definition at line 168 of file stm32f4xx_ll_adc.h.
Referenced by LL_ADC_INJ_GetTriggerSource().
| #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ |
Definition at line 155 of file stm32f4xx_ll_adc.h.
| #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */ |
Definition at line 175 of file stm32f4xx_ll_adc.h.
Referenced by LL_ADC_INJ_GetTriggerSource().
| #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */ |
Definition at line 174 of file stm32f4xx_ll_adc.h.
| #define ADC_INJ_TRIG_SOURCE_MASK |
(((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \ ((ADC_CR2_JEXTSEL) >> (4U * 1U)) | \ ((ADC_CR2_JEXTSEL) >> (4U * 2U)) | \ ((ADC_CR2_JEXTSEL) >> (4U * 3U)))
Definition at line 160 of file stm32f4xx_ll_adc.h.
Referenced by LL_ADC_INJ_GetTriggerSource().
| #define ADC_JDR1_REGOFFSET 0x00000000U |
Definition at line 107 of file stm32f4xx_ll_adc.h.
| #define ADC_JDR2_REGOFFSET 0x00000100U |
Definition at line 108 of file stm32f4xx_ll_adc.h.
| #define ADC_JDR3_REGOFFSET 0x00000200U |
Definition at line 109 of file stm32f4xx_ll_adc.h.
| #define ADC_JDR4_REGOFFSET 0x00000300U |
Definition at line 110 of file stm32f4xx_ll_adc.h.
| #define ADC_JOFR1_REGOFFSET 0x00000000U |
Definition at line 114 of file stm32f4xx_ll_adc.h.
| #define ADC_JOFR2_REGOFFSET 0x00001000U |
Definition at line 115 of file stm32f4xx_ll_adc.h.
| #define ADC_JOFR3_REGOFFSET 0x00002000U |
Definition at line 116 of file stm32f4xx_ll_adc.h.
| #define ADC_JOFR4_REGOFFSET 0x00003000U |
Definition at line 117 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */ |
Definition at line 91 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */ |
Definition at line 92 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */ |
Definition at line 93 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */ |
Definition at line 94 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */ |
Definition at line 95 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */ |
Definition at line 96 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */ |
Definition at line 97 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */ |
Definition at line 82 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */ |
Definition at line 83 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */ |
Definition at line 84 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */ |
Definition at line 85 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */ |
Definition at line 86 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */ |
Definition at line 87 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ |
Definition at line 88 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ |
Definition at line 89 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ |
Definition at line 90 of file stm32f4xx_ll_adc.h.
Definition at line 78 of file stm32f4xx_ll_adc.h.
Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().
| #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) |
Definition at line 77 of file stm32f4xx_ll_adc.h.
Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().
| #define ADC_REG_TRIG_EDGE_MASK |
(((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
Definition at line 140 of file stm32f4xx_ll_adc.h.
Referenced by LL_ADC_REG_GetTriggerSource().
| #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ |
Definition at line 127 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */ |
Definition at line 147 of file stm32f4xx_ll_adc.h.
Referenced by LL_ADC_REG_GetTriggerSource().
| #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */ |
Definition at line 146 of file stm32f4xx_ll_adc.h.
| #define ADC_REG_TRIG_SOURCE_MASK |
(((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \ ((ADC_CR2_EXTSEL) >> (4U * 1U)) | \ ((ADC_CR2_EXTSEL) >> (4U * 2U)) | \ ((ADC_CR2_EXTSEL) >> (4U * 3U)))
Definition at line 132 of file stm32f4xx_ll_adc.h.
Referenced by LL_ADC_REG_GetTriggerSource().
| #define ADC_SMPR1_REGOFFSET 0x00000000U |
Definition at line 198 of file stm32f4xx_ll_adc.h.
| #define ADC_SMPR2_REGOFFSET 0x02000000U |
Definition at line 199 of file stm32f4xx_ll_adc.h.
| #define ADC_SQR1_REGOFFSET 0x00000000U |
Definition at line 72 of file stm32f4xx_ll_adc.h.
| #define ADC_SQR2_REGOFFSET 0x00000100U |
Definition at line 73 of file stm32f4xx_ll_adc.h.
| #define ADC_SQR3_REGOFFSET 0x00000200U |
Definition at line 74 of file stm32f4xx_ll_adc.h.
| #define ADC_SQR4_REGOFFSET 0x00000300U |
Definition at line 75 of file stm32f4xx_ll_adc.h.
| #define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */ |
Definition at line 271 of file stm32f4xx_ll_adc.h.
1.7.6.1