STM32F439xx HAL User Manual
Defines
Calculate frequencies
RCC Exported Macros

Defines

#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)
 Helper macro to calculate the PLLCLK frequency on system domain.
#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)
 Helper macro to calculate the PLLCLK frequency used on 48M domain.
#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__)
 Helper macro to calculate the PLLSAI frequency used for SAI domain.
#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__)
 Helper macro to calculate the PLLSAI frequency used for LTDC domain.
#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__)
 Helper macro to calculate the PLLI2S frequency used for SAI domain.
#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__)
 Helper macro to calculate the PLLI2S frequency used for I2S domain.
#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__)   ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
 Helper macro to calculate the HCLK frequency.
#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__)   ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
 Helper macro to calculate the PCLK1 frequency (ABP1)
#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__)   ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
 Helper macro to calculate the PCLK2 frequency (ABP2)

Define Documentation

#define __LL_RCC_CALC_HCLK_FREQ (   __SYSCLKFREQ__,
  __AHBPRESCALER__ 
)    ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])

Helper macro to calculate the HCLK frequency.

Parameters:
__SYSCLKFREQ__SYSCLK frequency (based on HSE/HSI/PLLCLK)
__AHBPRESCALER__This parameter can be one of the following values:
Return values:
HCLKclock frequency (in Hz)

Definition at line 2887 of file stm32f4xx_ll_rcc.h.

Referenced by RCC_GetHCLKClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

#define __LL_RCC_CALC_PCLK1_FREQ (   __HCLKFREQ__,
  __APB1PRESCALER__ 
)    ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])

Helper macro to calculate the PCLK1 frequency (ABP1)

Parameters:
__HCLKFREQ__HCLK frequency
__APB1PRESCALER__This parameter can be one of the following values:
Return values:
PCLK1clock frequency (in Hz)

Definition at line 2900 of file stm32f4xx_ll_rcc.h.

Referenced by RCC_GetPCLK1ClockFreq().

#define __LL_RCC_CALC_PCLK2_FREQ (   __HCLKFREQ__,
  __APB2PRESCALER__ 
)    ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])

Helper macro to calculate the PCLK2 frequency (ABP2)

Parameters:
__HCLKFREQ__HCLK frequency
__APB2PRESCALER__This parameter can be one of the following values:
Return values:
PCLK2clock frequency (in Hz)

Definition at line 2913 of file stm32f4xx_ll_rcc.h.

Referenced by RCC_GetPCLK2ClockFreq().

#define __LL_RCC_CALC_PLLCLK_48M_FREQ (   __INPUTFREQ__,
  __PLLM__,
  __PLLN__,
  __PLLQ__ 
)
Value:
((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
                   ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))

Helper macro to calculate the PLLCLK frequency used on 48M domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetQ ());
Parameters:
__INPUTFREQ__PLL Input frequency (based on HSE/HSI)
__PLLM__This parameter can be one of the following values:
__PLLN__Between 50/192(*) and 432

(*) value not defined in all devices.

Parameters:
__PLLQ__This parameter can be one of the following values:
Return values:
PLLclock frequency (in Hz)

Definition at line 1767 of file stm32f4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_48M().

#define __LL_RCC_CALC_PLLCLK_FREQ (   __INPUTFREQ__,
  __PLLM__,
  __PLLN__,
  __PLLP__ 
)
Value:
((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
                   ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))

Helper macro to calculate the PLLCLK frequency on system domain.

Note:
ex: __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,LL_RCC_PLL_GetDivider (), LL_RCC_PLL_GetN (), LL_RCC_PLL_GetP ());
Parameters:
__INPUTFREQ__PLL Input frequency (based on HSE/HSI)
__PLLM__This parameter can be one of the following values:
__PLLN__Between 50/192(*) and 432

(*) value not defined in all devices.

Parameters:
__PLLP__This parameter can be one of the following values:
Return values:
PLLclock frequency (in Hz)

Definition at line 1592 of file stm32f4xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SYS().

#define __LL_RCC_CALC_PLLI2S_I2S_FREQ (   __INPUTFREQ__,
  __PLLM__,
  __PLLI2SN__,
  __PLLI2SR__ 
)
Value:
(((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
                   ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))

Helper macro to calculate the PLLI2S frequency used for I2S domain.

Note:
ex: __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,LL_RCC_PLLI2S_GetDivider (), LL_RCC_PLLI2S_GetN (), LL_RCC_PLLI2S_GetR ());
Parameters:
__INPUTFREQ__PLL Input frequency (based on HSE/HSI)
__PLLM__This parameter can be one of the following values:
__PLLI2SN__Between 50/192(*) and 432

(*) value not defined in all devices.

Parameters:
__PLLI2SR__This parameter can be one of the following values:
Return values:
PLLI2Sclock frequency (in Hz)

Definition at line 2776 of file stm32f4xx_ll_rcc.h.

Referenced by RCC_PLLI2S_GetFreqDomain_I2S().

#define __LL_RCC_CALC_PLLI2S_SAI_FREQ (   __INPUTFREQ__,
  __PLLM__,
  __PLLI2SN__,
  __PLLI2SQ_R__,
  __PLLI2SDIVQ_R__ 
)
Value:
(((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
                   (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U)))

Helper macro to calculate the PLLI2S frequency used for SAI domain.

Note:
ex: __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,LL_RCC_PLLI2S_GetDivider (), LL_RCC_PLLI2S_GetN (), LL_RCC_PLLI2S_GetQ (), LL_RCC_PLLI2S_GetDIVQ ());
Parameters:
__INPUTFREQ__PLL Input frequency (based on HSE/HSI)
__PLLM__This parameter can be one of the following values:
__PLLI2SN__Between 50/192(*) and 432

(*) value not defined in all devices.

Parameters:
__PLLI2SQ_R__This parameter can be one of the following values: (*) value not defined in all devices.
__PLLI2SDIVQ_R__This parameter can be one of the following values: (*) value not defined in all devices.
Return values:
PLLI2Sclock frequency (in Hz)

Definition at line 2605 of file stm32f4xx_ll_rcc.h.

Referenced by RCC_PLLI2S_GetFreqDomain_SAI().

#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ (   __INPUTFREQ__,
  __PLLM__,
  __PLLSAIN__,
  __PLLSAIR__,
  __PLLSAIDIVR__ 
)
Value:
(((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
                   (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos])))

Helper macro to calculate the PLLSAI frequency used for LTDC domain.

Note:
ex: __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,LL_RCC_PLLSAI_GetDivider (), LL_RCC_PLLSAI_GetN (), LL_RCC_PLLSAI_GetR (), LL_RCC_PLLSAI_GetDIVR ());
Parameters:
__INPUTFREQ__PLL Input frequency (based on HSE/HSI)
__PLLM__This parameter can be one of the following values:
__PLLSAIN__Between 49/50(*) and 432

(*) value not defined in all devices.

Parameters:
__PLLSAIR__This parameter can be one of the following values:
__PLLSAIDIVR__This parameter can be one of the following values:
Return values:
PLLSAIclock frequency (in Hz)

Definition at line 2435 of file stm32f4xx_ll_rcc.h.

Referenced by RCC_PLLSAI_GetFreqDomain_LTDC().

#define __LL_RCC_CALC_PLLSAI_SAI_FREQ (   __INPUTFREQ__,
  __PLLM__,
  __PLLSAIN__,
  __PLLSAIQ__,
  __PLLSAIDIVQ__ 
)
Value:
(((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
                   (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U)))

Helper macro to calculate the PLLSAI frequency used for SAI domain.

Note:
ex: __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,LL_RCC_PLLSAI_GetDivider (), LL_RCC_PLLSAI_GetN (), LL_RCC_PLLSAI_GetQ (), LL_RCC_PLLSAI_GetDIVQ ());
Parameters:
__INPUTFREQ__PLL Input frequency (based on HSE/HSI)
__PLLM__This parameter can be one of the following values:
__PLLSAIN__Between 49/50(*) and 432

(*) value not defined in all devices.

Parameters:
__PLLSAIQ__This parameter can be one of the following values:
__PLLSAIDIVQ__This parameter can be one of the following values:
Return values:
PLLSAIclock frequency (in Hz)

Definition at line 2265 of file stm32f4xx_ll_rcc.h.

Referenced by RCC_PLLSAI_GetFreqDomain_SAI().

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