STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_utils.c 00004 * @author MCD Application Team 00005 * @brief UTILS LL module driver. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 /* Includes ------------------------------------------------------------------*/ 00036 #include "stm32f4xx_ll_utils.h" 00037 #include "stm32f4xx_ll_rcc.h" 00038 #include "stm32f4xx_ll_system.h" 00039 #include "stm32f4xx_ll_pwr.h" 00040 #ifdef USE_FULL_ASSERT 00041 #include "stm32_assert.h" 00042 #else 00043 #define assert_param(expr) ((void)0U) 00044 #endif /* USE_FULL_ASSERT */ 00045 00046 /** @addtogroup STM32F4xx_LL_Driver 00047 * @{ 00048 */ 00049 00050 /** @addtogroup UTILS_LL 00051 * @{ 00052 */ 00053 00054 /* Private types -------------------------------------------------------------*/ 00055 /* Private variables ---------------------------------------------------------*/ 00056 /* Private constants ---------------------------------------------------------*/ 00057 /** @addtogroup UTILS_LL_Private_Constants 00058 * @{ 00059 */ 00060 #if defined(RCC_MAX_FREQUENCY_SCALE1) 00061 #define UTILS_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */ 00062 #endif /*RCC_MAX_FREQUENCY_SCALE1 */ 00063 #define UTILS_MAX_FREQUENCY_SCALE2 RCC_MAX_FREQUENCY_SCALE2 /*!< Maximum frequency for system clock at power scale2, in Hz */ 00064 #if defined(RCC_MAX_FREQUENCY_SCALE3) 00065 #define UTILS_MAX_FREQUENCY_SCALE3 RCC_MAX_FREQUENCY_SCALE3 /*!< Maximum frequency for system clock at power scale3, in Hz */ 00066 #endif /* MAX_FREQUENCY_SCALE3 */ 00067 00068 /* Defines used for PLL range */ 00069 #define UTILS_PLLVCO_INPUT_MIN RCC_PLLVCO_INPUT_MIN /*!< Frequency min for PLLVCO input, in Hz */ 00070 #define UTILS_PLLVCO_INPUT_MAX RCC_PLLVCO_INPUT_MAX /*!< Frequency max for PLLVCO input, in Hz */ 00071 #define UTILS_PLLVCO_OUTPUT_MIN RCC_PLLVCO_OUTPUT_MIN /*!< Frequency min for PLLVCO output, in Hz */ 00072 #define UTILS_PLLVCO_OUTPUT_MAX RCC_PLLVCO_OUTPUT_MAX /*!< Frequency max for PLLVCO output, in Hz */ 00073 00074 /* Defines used for HSE range */ 00075 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ 00076 #define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */ 00077 00078 /* Defines used for FLASH latency according to HCLK Frequency */ 00079 #if defined(FLASH_SCALE1_LATENCY1_FREQ) 00080 #define UTILS_SCALE1_LATENCY1_FREQ FLASH_SCALE1_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ 00081 #endif 00082 #if defined(FLASH_SCALE1_LATENCY2_FREQ) 00083 #define UTILS_SCALE1_LATENCY2_FREQ FLASH_SCALE1_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ 00084 #endif 00085 #if defined(FLASH_SCALE1_LATENCY3_FREQ) 00086 #define UTILS_SCALE1_LATENCY3_FREQ FLASH_SCALE1_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ 00087 #endif 00088 #if defined(FLASH_SCALE1_LATENCY4_FREQ) 00089 #define UTILS_SCALE1_LATENCY4_FREQ FLASH_SCALE1_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ 00090 #endif 00091 #if defined(FLASH_SCALE1_LATENCY5_FREQ) 00092 #define UTILS_SCALE1_LATENCY5_FREQ FLASH_SCALE1_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */ 00093 #endif 00094 #define UTILS_SCALE2_LATENCY1_FREQ FLASH_SCALE2_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ 00095 #define UTILS_SCALE2_LATENCY2_FREQ FLASH_SCALE2_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ 00096 #if defined(FLASH_SCALE2_LATENCY3_FREQ) 00097 #define UTILS_SCALE2_LATENCY3_FREQ FLASH_SCALE2_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ 00098 #endif 00099 #if defined(FLASH_SCALE2_LATENCY4_FREQ) 00100 #define UTILS_SCALE2_LATENCY4_FREQ FLASH_SCALE2_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */ 00101 #endif 00102 #if defined(FLASH_SCALE2_LATENCY5_FREQ) 00103 #define UTILS_SCALE2_LATENCY5_FREQ FLASH_SCALE2_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */ 00104 #endif 00105 #if defined(FLASH_SCALE3_LATENCY1_FREQ) 00106 #define UTILS_SCALE3_LATENCY1_FREQ FLASH_SCALE3_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ 00107 #endif 00108 #if defined(FLASH_SCALE3_LATENCY2_FREQ) 00109 #define UTILS_SCALE3_LATENCY2_FREQ FLASH_SCALE3_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */ 00110 #endif 00111 #if defined(FLASH_SCALE3_LATENCY3_FREQ) 00112 #define UTILS_SCALE3_LATENCY3_FREQ FLASH_SCALE3_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */ 00113 #endif 00114 #if defined(FLASH_SCALE3_LATENCY4_FREQ) 00115 #define UTILS_SCALE3_LATENCY4_FREQ FLASH_SCALE3_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */ 00116 #endif 00117 #if defined(FLASH_SCALE3_LATENCY5_FREQ) 00118 #define UTILS_SCALE3_LATENCY5_FREQ FLASH_SCALE3_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 3 */ 00119 #endif 00120 /** 00121 * @} 00122 */ 00123 00124 /* Private macros ------------------------------------------------------------*/ 00125 /** @addtogroup UTILS_LL_Private_Macros 00126 * @{ 00127 */ 00128 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ 00129 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ 00130 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ 00131 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ 00132 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ 00133 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ 00134 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ 00135 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ 00136 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) 00137 00138 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ 00139 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ 00140 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ 00141 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ 00142 || ((__VALUE__) == LL_RCC_APB1_DIV_16)) 00143 00144 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ 00145 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ 00146 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ 00147 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ 00148 || ((__VALUE__) == LL_RCC_APB2_DIV_16)) 00149 00150 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \ 00151 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \ 00152 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \ 00153 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \ 00154 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \ 00155 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \ 00156 || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \ 00157 || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \ 00158 || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \ 00159 || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \ 00160 || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \ 00161 || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \ 00162 || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \ 00163 || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \ 00164 || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \ 00165 || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \ 00166 || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \ 00167 || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \ 00168 || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \ 00169 || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \ 00170 || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \ 00171 || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \ 00172 || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \ 00173 || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \ 00174 || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \ 00175 || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \ 00176 || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \ 00177 || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \ 00178 || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \ 00179 || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \ 00180 || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \ 00181 || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \ 00182 || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \ 00183 || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \ 00184 || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \ 00185 || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \ 00186 || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \ 00187 || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \ 00188 || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \ 00189 || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \ 00190 || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \ 00191 || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \ 00192 || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \ 00193 || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \ 00194 || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \ 00195 || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \ 00196 || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \ 00197 || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \ 00198 || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \ 00199 || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \ 00200 || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \ 00201 || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \ 00202 || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \ 00203 || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \ 00204 || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \ 00205 || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \ 00206 || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \ 00207 || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \ 00208 || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \ 00209 || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \ 00210 || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \ 00211 || ((__VALUE__) == LL_RCC_PLLM_DIV_63)) 00212 00213 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((RCC_PLLN_MIN_VALUE <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLN_MAX_VALUE)) 00214 00215 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \ 00216 || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \ 00217 || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \ 00218 || ((__VALUE__) == LL_RCC_PLLP_DIV_8)) 00219 00220 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX)) 00221 00222 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX)) 00223 00224 #if !defined(RCC_MAX_FREQUENCY_SCALE1) 00225 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \ 00226 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3)) 00227 00228 #elif defined(RCC_MAX_FREQUENCY_SCALE3) 00229 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ 00230 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \ 00231 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3)) 00232 00233 #else 00234 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ 00235 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2)) 00236 00237 #endif /* RCC_MAX_FREQUENCY_SCALE1*/ 00238 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ 00239 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) 00240 00241 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) 00242 /** 00243 * @} 00244 */ 00245 /* Private function prototypes -----------------------------------------------*/ 00246 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions 00247 * @{ 00248 */ 00249 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, 00250 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); 00251 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency); 00252 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); 00253 static ErrorStatus UTILS_PLL_IsBusy(void); 00254 /** 00255 * @} 00256 */ 00257 00258 /* Exported functions --------------------------------------------------------*/ 00259 /** @addtogroup UTILS_LL_Exported_Functions 00260 * @{ 00261 */ 00262 00263 /** @addtogroup UTILS_LL_EF_DELAY 00264 * @{ 00265 */ 00266 00267 /** 00268 * @brief This function configures the Cortex-M SysTick source to have 1ms time base. 00269 * @note When a RTOS is used, it is recommended to avoid changing the Systick 00270 * configuration by calling this function, for a delay use rather osDelay RTOS service. 00271 * @param HCLKFrequency HCLK frequency in Hz 00272 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq 00273 * @retval None 00274 */ 00275 void LL_Init1msTick(uint32_t HCLKFrequency) 00276 { 00277 /* Use frequency provided in argument */ 00278 LL_InitTick(HCLKFrequency, 1000U); 00279 } 00280 00281 /** 00282 * @brief This function provides accurate delay (in milliseconds) based 00283 * on SysTick counter flag 00284 * @note When a RTOS is used, it is recommended to avoid using blocking delay 00285 * and use rather osDelay service. 00286 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which 00287 * will configure Systick to 1ms 00288 * @param Delay specifies the delay time length, in milliseconds. 00289 * @retval None 00290 */ 00291 void LL_mDelay(uint32_t Delay) 00292 { 00293 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ 00294 /* Add this code to indicate that local variable is not used */ 00295 ((void)tmp); 00296 00297 /* Add a period to guaranty minimum wait */ 00298 if(Delay < LL_MAX_DELAY) 00299 { 00300 Delay++; 00301 } 00302 00303 while (Delay) 00304 { 00305 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) 00306 { 00307 Delay--; 00308 } 00309 } 00310 } 00311 00312 /** 00313 * @} 00314 */ 00315 00316 /** @addtogroup UTILS_EF_SYSTEM 00317 * @brief System Configuration functions 00318 * 00319 @verbatim 00320 =============================================================================== 00321 ##### System Configuration functions ##### 00322 =============================================================================== 00323 [..] 00324 System, AHB and APB buses clocks configuration 00325 00326 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 180000000 Hz. 00327 @endverbatim 00328 @internal 00329 Depending on the device voltage range, the maximum frequency should be 00330 adapted accordingly to the Refenece manual. 00331 @endinternal 00332 * @{ 00333 */ 00334 00335 /** 00336 * @brief This function sets directly SystemCoreClock CMSIS variable. 00337 * @note Variable can be calculated also through SystemCoreClockUpdate function. 00338 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) 00339 * @retval None 00340 */ 00341 void LL_SetSystemCoreClock(uint32_t HCLKFrequency) 00342 { 00343 /* HCLK clock frequency */ 00344 SystemCoreClock = HCLKFrequency; 00345 } 00346 00347 /** 00348 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL 00349 * @note The application need to ensure that PLL is disabled. 00350 * @note Function is based on the following formula: 00351 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP) 00352 * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM) 00353 * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN) 00354 * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP) 00355 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains 00356 * the configuration information for the PLL. 00357 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains 00358 * the configuration information for the BUS prescalers. 00359 * @retval An ErrorStatus enumeration value: 00360 * - SUCCESS: Max frequency configuration done 00361 * - ERROR: Max frequency configuration not done 00362 */ 00363 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, 00364 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) 00365 { 00366 ErrorStatus status = SUCCESS; 00367 uint32_t pllfreq = 0U; 00368 00369 /* Check if one of the PLL is enabled */ 00370 if(UTILS_PLL_IsBusy() == SUCCESS) 00371 { 00372 /* Calculate the new PLL output frequency */ 00373 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); 00374 00375 /* Enable HSI if not enabled */ 00376 if(LL_RCC_HSI_IsReady() != 1U) 00377 { 00378 LL_RCC_HSI_Enable(); 00379 while (LL_RCC_HSI_IsReady() != 1U) 00380 { 00381 /* Wait for HSI ready */ 00382 } 00383 } 00384 00385 /* Configure PLL */ 00386 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, 00387 UTILS_PLLInitStruct->PLLP); 00388 00389 /* Enable PLL and switch system clock to PLL */ 00390 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); 00391 } 00392 else 00393 { 00394 /* Current PLL configuration cannot be modified */ 00395 status = ERROR; 00396 } 00397 00398 return status; 00399 } 00400 00401 /** 00402 * @brief This function configures system clock with HSE as clock source of the PLL 00403 * @note The application need to ensure that PLL is disabled. 00404 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP) 00405 * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM) 00406 * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN) 00407 * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP) 00408 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000 00409 * @param HSEBypass This parameter can be one of the following values: 00410 * @arg @ref LL_UTILS_HSEBYPASS_ON 00411 * @arg @ref LL_UTILS_HSEBYPASS_OFF 00412 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains 00413 * the configuration information for the PLL. 00414 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains 00415 * the configuration information for the BUS prescalers. 00416 * @retval An ErrorStatus enumeration value: 00417 * - SUCCESS: Max frequency configuration done 00418 * - ERROR: Max frequency configuration not done 00419 */ 00420 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, 00421 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) 00422 { 00423 ErrorStatus status = SUCCESS; 00424 uint32_t pllfreq = 0U; 00425 00426 /* Check the parameters */ 00427 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); 00428 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); 00429 00430 /* Check if one of the PLL is enabled */ 00431 if(UTILS_PLL_IsBusy() == SUCCESS) 00432 { 00433 /* Calculate the new PLL output frequency */ 00434 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); 00435 00436 /* Enable HSE if not enabled */ 00437 if(LL_RCC_HSE_IsReady() != 1U) 00438 { 00439 /* Check if need to enable HSE bypass feature or not */ 00440 if(HSEBypass == LL_UTILS_HSEBYPASS_ON) 00441 { 00442 LL_RCC_HSE_EnableBypass(); 00443 } 00444 else 00445 { 00446 LL_RCC_HSE_DisableBypass(); 00447 } 00448 00449 /* Enable HSE */ 00450 LL_RCC_HSE_Enable(); 00451 while (LL_RCC_HSE_IsReady() != 1U) 00452 { 00453 /* Wait for HSE ready */ 00454 } 00455 } 00456 00457 /* Configure PLL */ 00458 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, 00459 UTILS_PLLInitStruct->PLLP); 00460 00461 /* Enable PLL and switch system clock to PLL */ 00462 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); 00463 } 00464 else 00465 { 00466 /* Current PLL configuration cannot be modified */ 00467 status = ERROR; 00468 } 00469 00470 return status; 00471 } 00472 00473 /** 00474 * @} 00475 */ 00476 00477 /** 00478 * @} 00479 */ 00480 00481 /** @addtogroup UTILS_LL_Private_Functions 00482 * @{ 00483 */ 00484 /** 00485 * @brief Update number of Flash wait states in line with new frequency and current 00486 voltage range. 00487 * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V 00488 * @param HCLK_Frequency HCLK frequency 00489 * @retval An ErrorStatus enumeration value: 00490 * - SUCCESS: Latency has been modified 00491 * - ERROR: Latency cannot be modified 00492 */ 00493 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) 00494 { 00495 ErrorStatus status = SUCCESS; 00496 00497 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ 00498 00499 /* Frequency cannot be equal to 0 */ 00500 if(HCLK_Frequency == 0U) 00501 { 00502 status = ERROR; 00503 } 00504 else 00505 { 00506 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) 00507 { 00508 #if defined (UTILS_SCALE1_LATENCY5_FREQ) 00509 if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0)) 00510 { 00511 latency = LL_FLASH_LATENCY_5; 00512 } 00513 #endif /*UTILS_SCALE1_LATENCY5_FREQ */ 00514 #if defined (UTILS_SCALE1_LATENCY4_FREQ) 00515 if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0)) 00516 { 00517 latency = LL_FLASH_LATENCY_4; 00518 } 00519 #endif /* UTILS_SCALE1_LATENCY4_FREQ */ 00520 #if defined (UTILS_SCALE1_LATENCY3_FREQ) 00521 if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0)) 00522 { 00523 latency = LL_FLASH_LATENCY_3; 00524 } 00525 #endif /* UTILS_SCALE1_LATENCY3_FREQ */ 00526 #if defined (UTILS_SCALE1_LATENCY2_FREQ) 00527 if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0)) 00528 { 00529 latency = LL_FLASH_LATENCY_2; 00530 } 00531 else 00532 { 00533 if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0)) 00534 { 00535 latency = LL_FLASH_LATENCY_1; 00536 } 00537 } 00538 #endif /* UTILS_SCALE1_LATENCY2_FREQ */ 00539 } 00540 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) 00541 { 00542 #if defined (UTILS_SCALE2_LATENCY5_FREQ) 00543 if((HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0)) 00544 { 00545 latency = LL_FLASH_LATENCY_5; 00546 } 00547 #endif /*UTILS_SCALE1_LATENCY5_FREQ */ 00548 #if defined (UTILS_SCALE2_LATENCY4_FREQ) 00549 if((HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0)) 00550 { 00551 latency = LL_FLASH_LATENCY_4; 00552 } 00553 #endif /*UTILS_SCALE1_LATENCY4_FREQ */ 00554 #if defined (UTILS_SCALE2_LATENCY3_FREQ) 00555 if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0)) 00556 { 00557 latency = LL_FLASH_LATENCY_3; 00558 } 00559 #endif /*UTILS_SCALE1_LATENCY3_FREQ */ 00560 if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0)) 00561 { 00562 latency = LL_FLASH_LATENCY_2; 00563 } 00564 else 00565 { 00566 if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0)) 00567 { 00568 latency = LL_FLASH_LATENCY_1; 00569 } 00570 } 00571 } 00572 #if defined (LL_PWR_REGU_VOLTAGE_SCALE3) 00573 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3) 00574 { 00575 #if defined (UTILS_SCALE3_LATENCY3_FREQ) 00576 if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0)) 00577 { 00578 latency = LL_FLASH_LATENCY_3; 00579 } 00580 #endif /*UTILS_SCALE1_LATENCY3_FREQ */ 00581 #if defined (UTILS_SCALE3_LATENCY2_FREQ) 00582 if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0)) 00583 { 00584 latency = LL_FLASH_LATENCY_2; 00585 } 00586 else 00587 { 00588 if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0)) 00589 { 00590 latency = LL_FLASH_LATENCY_1; 00591 } 00592 } 00593 } 00594 #endif /*UTILS_SCALE1_LATENCY2_FREQ */ 00595 #endif /* LL_PWR_REGU_VOLTAGE_SCALE3 */ 00596 00597 LL_FLASH_SetLatency(latency); 00598 00599 /* Check that the new number of wait states is taken into account to access the Flash 00600 memory by reading the FLASH_ACR register */ 00601 if(LL_FLASH_GetLatency() != latency) 00602 { 00603 status = ERROR; 00604 } 00605 } 00606 return status; 00607 } 00608 00609 /** 00610 * @brief Function to check that PLL can be modified 00611 * @param PLL_InputFrequency PLL input frequency (in Hz) 00612 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains 00613 * the configuration information for the PLL. 00614 * @retval PLL output frequency (in Hz) 00615 */ 00616 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) 00617 { 00618 uint32_t pllfreq = 0U; 00619 00620 /* Check the parameters */ 00621 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); 00622 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); 00623 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP)); 00624 00625 /* Check different PLL parameters according to RM */ 00626 /* - PLLM: ensure that the VCO input frequency ranges from @ref UTILS_PLLVCO_INPUT_MIN to @ref UTILS_PLLVCO_INPUT_MAX MHz. */ 00627 pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos)); 00628 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq)); 00629 00630 /* - PLLN: ensure that the VCO output frequency is between @ref UTILS_PLLVCO_OUTPUT_MIN and @ref UTILS_PLLVCO_OUTPUT_MAX .*/ 00631 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos)); 00632 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); 00633 00634 /* - PLLP: ensure that max frequency at @ref RCC_MAX_FREQUENCY Hz is reached */ 00635 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); 00636 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); 00637 00638 return pllfreq; 00639 } 00640 00641 /** 00642 * @brief Function to check that PLL can be modified 00643 * @retval An ErrorStatus enumeration value: 00644 * - SUCCESS: PLL modification can be done 00645 * - ERROR: PLL is busy 00646 */ 00647 static ErrorStatus UTILS_PLL_IsBusy(void) 00648 { 00649 ErrorStatus status = SUCCESS; 00650 00651 /* Check if PLL is busy*/ 00652 if(LL_RCC_PLL_IsReady() != 0U) 00653 { 00654 /* PLL configuration cannot be modified */ 00655 status = ERROR; 00656 } 00657 00658 #if defined(RCC_PLLSAI_SUPPORT) 00659 /* Check if PLLSAI is busy*/ 00660 if(LL_RCC_PLLSAI_IsReady() != 0U) 00661 { 00662 /* PLLSAI1 configuration cannot be modified */ 00663 status = ERROR; 00664 } 00665 #endif /*RCC_PLLSAI_SUPPORT*/ 00666 #if defined(RCC_PLLI2S_SUPPORT) 00667 /* Check if PLLI2S is busy*/ 00668 if(LL_RCC_PLLI2S_IsReady() != 0U) 00669 { 00670 /* PLLI2S configuration cannot be modified */ 00671 status = ERROR; 00672 } 00673 #endif /*RCC_PLLI2S_SUPPORT*/ 00674 return status; 00675 } 00676 00677 /** 00678 * @brief Function to enable PLL and switch system clock to PLL 00679 * @param SYSCLK_Frequency SYSCLK frequency 00680 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains 00681 * the configuration information for the BUS prescalers. 00682 * @retval An ErrorStatus enumeration value: 00683 * - SUCCESS: No problem to switch system to PLL 00684 * - ERROR: Problem to switch system to PLL 00685 */ 00686 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) 00687 { 00688 ErrorStatus status = SUCCESS; 00689 uint32_t hclk_frequency = 0U; 00690 00691 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); 00692 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); 00693 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); 00694 00695 /* Calculate HCLK frequency */ 00696 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider); 00697 00698 /* Increasing the number of wait states because of higher CPU frequency */ 00699 if(SystemCoreClock < hclk_frequency) 00700 { 00701 /* Set FLASH latency to highest latency */ 00702 status = UTILS_SetFlashLatency(hclk_frequency); 00703 } 00704 00705 /* Update system clock configuration */ 00706 if(status == SUCCESS) 00707 { 00708 /* Enable PLL */ 00709 LL_RCC_PLL_Enable(); 00710 while (LL_RCC_PLL_IsReady() != 1U) 00711 { 00712 /* Wait for PLL ready */ 00713 } 00714 00715 /* Sysclk activation on the main PLL */ 00716 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); 00717 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); 00718 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) 00719 { 00720 /* Wait for system clock switch to PLL */ 00721 } 00722 00723 /* Set APB1 & APB2 prescaler*/ 00724 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); 00725 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); 00726 } 00727 00728 /* Decreasing the number of wait states because of lower CPU frequency */ 00729 if(SystemCoreClock > hclk_frequency) 00730 { 00731 /* Set FLASH latency to lowest latency */ 00732 status = UTILS_SetFlashLatency(hclk_frequency); 00733 } 00734 00735 /* Update SystemCoreClock variable */ 00736 if(status == SUCCESS) 00737 { 00738 LL_SetSystemCoreClock(hclk_frequency); 00739 } 00740 00741 return status; 00742 } 00743 00744 /** 00745 * @} 00746 */ 00747 00748 /** 00749 * @} 00750 */ 00751 00752 /** 00753 * @} 00754 */ 00755 00756 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/