STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_rcc.c 00004 * @author MCD Application Team 00005 * @brief RCC LL module driver. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 #if defined(USE_FULL_LL_DRIVER) 00036 00037 /* Includes ------------------------------------------------------------------*/ 00038 #include "stm32f4xx_ll_rcc.h" 00039 #ifdef USE_FULL_ASSERT 00040 #include "stm32_assert.h" 00041 #else 00042 #define assert_param(expr) ((void)0U) 00043 #endif 00044 /** @addtogroup STM32F4xx_LL_Driver 00045 * @{ 00046 */ 00047 00048 #if defined(RCC) 00049 00050 /** @addtogroup RCC_LL 00051 * @{ 00052 */ 00053 00054 /* Private types -------------------------------------------------------------*/ 00055 /* Private variables ---------------------------------------------------------*/ 00056 /* Private constants ---------------------------------------------------------*/ 00057 /* Private macros ------------------------------------------------------------*/ 00058 /** @addtogroup RCC_LL_Private_Macros 00059 * @{ 00060 */ 00061 #if defined(FMPI2C1) 00062 #define IS_LL_RCC_FMPI2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_FMPI2C1_CLKSOURCE) 00063 #endif /* FMPI2C1 */ 00064 00065 #if defined(LPTIM1) 00066 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE)) 00067 #endif /* LPTIM1 */ 00068 00069 #if defined(SAI1) 00070 #if defined(RCC_DCKCFGR_SAI1SRC) 00071 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \ 00072 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE)) 00073 #elif defined(RCC_DCKCFGR_SAI1ASRC) 00074 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_A_CLKSOURCE) \ 00075 || ((__VALUE__) == LL_RCC_SAI1_B_CLKSOURCE)) 00076 #endif /* RCC_DCKCFGR_SAI1SRC */ 00077 #endif /* SAI1 */ 00078 00079 #if defined(SDIO) 00080 #define IS_LL_RCC_SDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDIO_CLKSOURCE)) 00081 #endif /* SDIO */ 00082 00083 #if defined(RNG) 00084 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE)) 00085 #endif /* RNG */ 00086 00087 #if defined(USB_OTG_FS) || defined(USB_OTG_HS) 00088 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) 00089 #endif /* USB_OTG_FS || USB_OTG_HS */ 00090 00091 #if defined(DFSDM2_Channel0) 00092 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE)) 00093 00094 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE) \ 00095 || ((__VALUE__) == LL_RCC_DFSDM2_AUDIO_CLKSOURCE)) 00096 #elif defined(DFSDM1_Channel0) 00097 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE)) 00098 00099 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE)) 00100 #endif /* DFSDM2_Channel0 */ 00101 00102 #if defined(RCC_DCKCFGR_I2S2SRC) 00103 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \ 00104 || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE)) 00105 #else 00106 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE)) 00107 #endif /* RCC_DCKCFGR_I2S2SRC */ 00108 00109 #if defined(CEC) 00110 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE)) 00111 #endif /* CEC */ 00112 00113 #if defined(DSI) 00114 #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE)) 00115 #endif /* DSI */ 00116 00117 #if defined(LTDC) 00118 #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE)) 00119 #endif /* LTDC */ 00120 00121 #if defined(SPDIFRX) 00122 #define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE)) 00123 #endif /* SPDIFRX */ 00124 /** 00125 * @} 00126 */ 00127 00128 /* Private function prototypes -----------------------------------------------*/ 00129 /** @defgroup RCC_LL_Private_Functions RCC Private functions 00130 * @{ 00131 */ 00132 uint32_t RCC_GetSystemClockFreq(void); 00133 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); 00134 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); 00135 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); 00136 uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source); 00137 uint32_t RCC_PLL_GetFreqDomain_48M(void); 00138 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC) 00139 uint32_t RCC_PLL_GetFreqDomain_I2S(void); 00140 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */ 00141 #if defined(SPDIFRX) 00142 uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void); 00143 #endif /* SPDIFRX */ 00144 #if defined(RCC_PLLCFGR_PLLR) 00145 #if defined(SAI1) 00146 uint32_t RCC_PLL_GetFreqDomain_SAI(void); 00147 #endif /* SAI1 */ 00148 #endif /* RCC_PLLCFGR_PLLR */ 00149 #if defined(DSI) 00150 uint32_t RCC_PLL_GetFreqDomain_DSI(void); 00151 #endif /* DSI */ 00152 #if defined(RCC_PLLSAI_SUPPORT) 00153 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void); 00154 #if defined(RCC_PLLSAICFGR_PLLSAIP) 00155 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void); 00156 #endif /* RCC_PLLSAICFGR_PLLSAIP */ 00157 #if defined(LTDC) 00158 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void); 00159 #endif /* LTDC */ 00160 #endif /* RCC_PLLSAI_SUPPORT */ 00161 #if defined(RCC_PLLI2S_SUPPORT) 00162 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void); 00163 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) 00164 uint32_t RCC_PLLI2S_GetFreqDomain_48M(void); 00165 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ 00166 #if defined(SAI1) 00167 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void); 00168 #endif /* SAI1 */ 00169 #if defined(SPDIFRX) 00170 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void); 00171 #endif /* SPDIFRX */ 00172 #endif /* RCC_PLLI2S_SUPPORT */ 00173 /** 00174 * @} 00175 */ 00176 00177 00178 /* Exported functions --------------------------------------------------------*/ 00179 /** @addtogroup RCC_LL_Exported_Functions 00180 * @{ 00181 */ 00182 00183 /** @addtogroup RCC_LL_EF_Init 00184 * @{ 00185 */ 00186 00187 /** 00188 * @brief Reset the RCC clock configuration to the default reset state. 00189 * @note The default reset state of the clock configuration is given below: 00190 * - HSI ON and used as system clock source 00191 * - HSE and PLL OFF 00192 * - AHB, APB1 and APB2 prescaler set to 1. 00193 * - CSS, MCO OFF 00194 * - All interrupts disabled 00195 * @note This function doesn't modify the configuration of the 00196 * - Peripheral clocks 00197 * - LSI, LSE and RTC clocks 00198 * @retval An ErrorStatus enumeration value: 00199 * - SUCCESS: RCC registers are de-initialized 00200 * - ERROR: not applicable 00201 */ 00202 ErrorStatus LL_RCC_DeInit(void) 00203 { 00204 uint32_t vl_mask = 0U; 00205 00206 /* Set HSION bit */ 00207 LL_RCC_HSI_Enable(); 00208 00209 /* Wait for HSI READY bit */ 00210 while(LL_RCC_HSI_IsReady() != 1U) 00211 {} 00212 00213 /* Reset CFGR register */ 00214 LL_RCC_WriteReg(CFGR, 0x00000000U); 00215 00216 vl_mask = 0xFFFFFFFFU; 00217 00218 /* Reset HSEON, PLLSYSON bits */ 00219 CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON)); 00220 00221 #if defined(RCC_PLLSAI_SUPPORT) 00222 /* Reset PLLSAION bit */ 00223 CLEAR_BIT(vl_mask, RCC_CR_PLLSAION); 00224 #endif /* RCC_PLLSAI_SUPPORT */ 00225 00226 #if defined(RCC_PLLI2S_SUPPORT) 00227 /* Reset PLLI2SON bit */ 00228 CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON); 00229 #endif /* RCC_PLLI2S_SUPPORT */ 00230 00231 /* Write new mask in CR register */ 00232 LL_RCC_WriteReg(CR, vl_mask); 00233 00234 /* Set HSITRIM bits to the reset value*/ 00235 LL_RCC_HSI_SetCalibTrimming(0x10U); 00236 00237 /* Wait for PLL READY bit to be reset */ 00238 while(LL_RCC_PLL_IsReady() != 0U) 00239 {} 00240 00241 /* Reset PLLCFGR register */ 00242 LL_RCC_WriteReg(PLLCFGR, RCC_PLLCFGR_RST_VALUE); 00243 00244 #if defined(RCC_PLLI2S_SUPPORT) 00245 /* Reset PLLI2SCFGR register */ 00246 LL_RCC_WriteReg(PLLI2SCFGR, RCC_PLLI2SCFGR_RST_VALUE); 00247 #endif /* RCC_PLLI2S_SUPPORT */ 00248 00249 #if defined(RCC_PLLSAI_SUPPORT) 00250 /* Reset PLLSAICFGR register */ 00251 LL_RCC_WriteReg(PLLSAICFGR, RCC_PLLSAICFGR_RST_VALUE); 00252 #endif /* RCC_PLLSAI_SUPPORT */ 00253 00254 /* Disable all interrupts */ 00255 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE); 00256 00257 #if defined(RCC_CIR_PLLI2SRDYIE) 00258 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); 00259 #endif /* RCC_CIR_PLLI2SRDYIE */ 00260 00261 #if defined(RCC_CIR_PLLSAIRDYIE) 00262 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); 00263 #endif /* RCC_CIR_PLLSAIRDYIE */ 00264 00265 /* Clear all interrupt flags */ 00266 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC); 00267 00268 #if defined(RCC_CIR_PLLI2SRDYC) 00269 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); 00270 #endif /* RCC_CIR_PLLI2SRDYC */ 00271 00272 #if defined(RCC_CIR_PLLSAIRDYC) 00273 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); 00274 #endif /* RCC_CIR_PLLSAIRDYC */ 00275 00276 /* Clear LSION bit */ 00277 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); 00278 00279 /* Reset all CSR flags */ 00280 SET_BIT(RCC->CSR, RCC_CSR_RMVF); 00281 00282 return SUCCESS; 00283 } 00284 00285 /** 00286 * @} 00287 */ 00288 00289 /** @addtogroup RCC_LL_EF_Get_Freq 00290 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks 00291 * and different peripheral clocks available on the device. 00292 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) 00293 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) 00294 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***) 00295 * or HSI_VALUE(**) multiplied/divided by the PLL factors. 00296 * @note (**) HSI_VALUE is a constant defined in this file (default value 00297 * 16 MHz) but the real value may vary depending on the variations 00298 * in voltage and temperature. 00299 * @note (***) HSE_VALUE is a constant defined in this file (default value 00300 * 25 MHz), user has to ensure that HSE_VALUE is same as the real 00301 * frequency of the crystal used. Otherwise, this function may 00302 * have wrong result. 00303 * @note The result of this function could be incorrect when using fractional 00304 * value for HSE crystal. 00305 * @note This function can be used by the user application to compute the 00306 * baud-rate for the communication peripherals or configure other parameters. 00307 * @{ 00308 */ 00309 00310 /** 00311 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks 00312 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function 00313 * must be called to update structure fields. Otherwise, any 00314 * configuration based on this function will be incorrect. 00315 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies 00316 * @retval None 00317 */ 00318 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) 00319 { 00320 /* Get SYSCLK frequency */ 00321 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); 00322 00323 /* HCLK clock frequency */ 00324 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); 00325 00326 /* PCLK1 clock frequency */ 00327 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); 00328 00329 /* PCLK2 clock frequency */ 00330 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency); 00331 } 00332 00333 #if defined(FMPI2C1) 00334 /** 00335 * @brief Return FMPI2Cx clock frequency 00336 * @param FMPI2CxSource This parameter can be one of the following values: 00337 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE 00338 * @retval FMPI2C clock frequency (in Hz) 00339 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready 00340 */ 00341 uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource) 00342 { 00343 uint32_t FMPI2C_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00344 00345 /* Check parameter */ 00346 assert_param(IS_LL_RCC_FMPI2C_CLKSOURCE(FMPI2CxSource)); 00347 00348 if (FMPI2CxSource == LL_RCC_FMPI2C1_CLKSOURCE) 00349 { 00350 /* FMPI2C1 CLK clock frequency */ 00351 switch (LL_RCC_GetFMPI2CClockSource(FMPI2CxSource)) 00352 { 00353 case LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK: /* FMPI2C1 Clock is System Clock */ 00354 FMPI2C_frequency = RCC_GetSystemClockFreq(); 00355 break; 00356 00357 case LL_RCC_FMPI2C1_CLKSOURCE_HSI: /* FMPI2C1 Clock is HSI Osc. */ 00358 if (LL_RCC_HSI_IsReady()) 00359 { 00360 FMPI2C_frequency = HSI_VALUE; 00361 } 00362 break; 00363 00364 case LL_RCC_FMPI2C1_CLKSOURCE_PCLK1: /* FMPI2C1 Clock is PCLK1 */ 00365 default: 00366 FMPI2C_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 00367 break; 00368 } 00369 } 00370 00371 return FMPI2C_frequency; 00372 } 00373 #endif /* FMPI2C1 */ 00374 00375 /** 00376 * @brief Return I2Sx clock frequency 00377 * @param I2SxSource This parameter can be one of the following values: 00378 * @arg @ref LL_RCC_I2S1_CLKSOURCE 00379 * @arg @ref LL_RCC_I2S2_CLKSOURCE (*) 00380 * 00381 * (*) value not defined in all devices. 00382 * @retval I2S clock frequency (in Hz) 00383 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready 00384 */ 00385 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) 00386 { 00387 uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00388 00389 /* Check parameter */ 00390 assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource)); 00391 00392 if (I2SxSource == LL_RCC_I2S1_CLKSOURCE) 00393 { 00394 /* I2S1 CLK clock frequency */ 00395 switch (LL_RCC_GetI2SClockSource(I2SxSource)) 00396 { 00397 #if defined(RCC_PLLI2S_SUPPORT) 00398 case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */ 00399 if (LL_RCC_PLLI2S_IsReady()) 00400 { 00401 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S(); 00402 } 00403 break; 00404 #endif /* RCC_PLLI2S_SUPPORT */ 00405 00406 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC) 00407 case LL_RCC_I2S1_CLKSOURCE_PLL: /* I2S1 Clock is PLL */ 00408 if (LL_RCC_PLL_IsReady()) 00409 { 00410 i2s_frequency = RCC_PLL_GetFreqDomain_I2S(); 00411 } 00412 break; 00413 00414 case LL_RCC_I2S1_CLKSOURCE_PLLSRC: /* I2S1 Clock is PLL Main source */ 00415 switch (LL_RCC_PLL_GetMainSource()) 00416 { 00417 case LL_RCC_PLLSOURCE_HSE: /* I2S1 Clock is HSE Osc. */ 00418 if (LL_RCC_HSE_IsReady()) 00419 { 00420 i2s_frequency = HSE_VALUE; 00421 } 00422 break; 00423 00424 case LL_RCC_PLLSOURCE_HSI: /* I2S1 Clock is HSI Osc. */ 00425 default: 00426 if (LL_RCC_HSI_IsReady()) 00427 { 00428 i2s_frequency = HSI_VALUE; 00429 } 00430 break; 00431 } 00432 break; 00433 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */ 00434 00435 case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */ 00436 default: 00437 i2s_frequency = EXTERNAL_CLOCK_VALUE; 00438 break; 00439 } 00440 } 00441 #if defined(RCC_DCKCFGR_I2S2SRC) 00442 else 00443 { 00444 /* I2S2 CLK clock frequency */ 00445 switch (LL_RCC_GetI2SClockSource(I2SxSource)) 00446 { 00447 case LL_RCC_I2S2_CLKSOURCE_PLLI2S: /* I2S2 Clock is PLLI2S */ 00448 if (LL_RCC_PLLI2S_IsReady()) 00449 { 00450 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S(); 00451 } 00452 break; 00453 00454 case LL_RCC_I2S2_CLKSOURCE_PLL: /* I2S2 Clock is PLL */ 00455 if (LL_RCC_PLL_IsReady()) 00456 { 00457 i2s_frequency = RCC_PLL_GetFreqDomain_I2S(); 00458 } 00459 break; 00460 00461 case LL_RCC_I2S2_CLKSOURCE_PLLSRC: /* I2S2 Clock is PLL Main source */ 00462 switch (LL_RCC_PLL_GetMainSource()) 00463 { 00464 case LL_RCC_PLLSOURCE_HSE: /* I2S2 Clock is HSE Osc. */ 00465 if (LL_RCC_HSE_IsReady()) 00466 { 00467 i2s_frequency = HSE_VALUE; 00468 } 00469 break; 00470 00471 case LL_RCC_PLLSOURCE_HSI: /* I2S2 Clock is HSI Osc. */ 00472 default: 00473 if (LL_RCC_HSI_IsReady()) 00474 { 00475 i2s_frequency = HSI_VALUE; 00476 } 00477 break; 00478 } 00479 break; 00480 00481 case LL_RCC_I2S2_CLKSOURCE_PIN: /* I2S2 Clock is External clock */ 00482 default: 00483 i2s_frequency = EXTERNAL_CLOCK_VALUE; 00484 break; 00485 } 00486 } 00487 #endif /* RCC_DCKCFGR_I2S2SRC */ 00488 00489 return i2s_frequency; 00490 } 00491 00492 #if defined(LPTIM1) 00493 /** 00494 * @brief Return LPTIMx clock frequency 00495 * @param LPTIMxSource This parameter can be one of the following values: 00496 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE 00497 * @retval LPTIM clock frequency (in Hz) 00498 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready 00499 */ 00500 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) 00501 { 00502 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00503 00504 /* Check parameter */ 00505 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource)); 00506 00507 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE) 00508 { 00509 /* LPTIM1CLK clock frequency */ 00510 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) 00511 { 00512 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ 00513 if (LL_RCC_LSI_IsReady()) 00514 { 00515 lptim_frequency = LSI_VALUE; 00516 } 00517 break; 00518 00519 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */ 00520 if (LL_RCC_HSI_IsReady()) 00521 { 00522 lptim_frequency = HSI_VALUE; 00523 } 00524 break; 00525 00526 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ 00527 if (LL_RCC_LSE_IsReady()) 00528 { 00529 lptim_frequency = LSE_VALUE; 00530 } 00531 break; 00532 00533 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */ 00534 default: 00535 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 00536 break; 00537 } 00538 } 00539 00540 return lptim_frequency; 00541 } 00542 #endif /* LPTIM1 */ 00543 00544 #if defined(SAI1) 00545 /** 00546 * @brief Return SAIx clock frequency 00547 * @param SAIxSource This parameter can be one of the following values: 00548 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*) 00549 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) 00550 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*) 00551 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*) 00552 * 00553 * (*) value not defined in all devices. 00554 * @retval SAI clock frequency (in Hz) 00555 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready 00556 */ 00557 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) 00558 { 00559 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00560 00561 /* Check parameter */ 00562 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource)); 00563 00564 #if defined(RCC_DCKCFGR_SAI1SRC) 00565 if ((SAIxSource == LL_RCC_SAI1_CLKSOURCE) || (SAIxSource == LL_RCC_SAI2_CLKSOURCE)) 00566 { 00567 /* SAI1CLK clock frequency */ 00568 switch (LL_RCC_GetSAIClockSource(SAIxSource)) 00569 { 00570 case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */ 00571 case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */ 00572 if (LL_RCC_PLLSAI_IsReady()) 00573 { 00574 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI(); 00575 } 00576 break; 00577 00578 case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */ 00579 case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */ 00580 if (LL_RCC_PLLI2S_IsReady()) 00581 { 00582 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI(); 00583 } 00584 break; 00585 00586 case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */ 00587 case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */ 00588 if (LL_RCC_PLL_IsReady()) 00589 { 00590 sai_frequency = RCC_PLL_GetFreqDomain_SAI(); 00591 } 00592 break; 00593 00594 case LL_RCC_SAI2_CLKSOURCE_PLLSRC: 00595 switch (LL_RCC_PLL_GetMainSource()) 00596 { 00597 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */ 00598 if (LL_RCC_HSE_IsReady()) 00599 { 00600 sai_frequency = HSE_VALUE; 00601 } 00602 break; 00603 00604 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */ 00605 default: 00606 if (LL_RCC_HSI_IsReady()) 00607 { 00608 sai_frequency = HSI_VALUE; 00609 } 00610 break; 00611 } 00612 break; 00613 00614 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */ 00615 default: 00616 sai_frequency = EXTERNAL_CLOCK_VALUE; 00617 break; 00618 } 00619 } 00620 #endif /* RCC_DCKCFGR_SAI1SRC */ 00621 #if defined(RCC_DCKCFGR_SAI1ASRC) 00622 if ((SAIxSource == LL_RCC_SAI1_A_CLKSOURCE) || (SAIxSource == LL_RCC_SAI1_B_CLKSOURCE)) 00623 { 00624 /* SAI1CLK clock frequency */ 00625 switch (LL_RCC_GetSAIClockSource(SAIxSource)) 00626 { 00627 #if defined(RCC_PLLSAI_SUPPORT) 00628 case LL_RCC_SAI1_A_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block A clock source */ 00629 case LL_RCC_SAI1_B_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block B clock source */ 00630 if (LL_RCC_PLLSAI_IsReady()) 00631 { 00632 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI(); 00633 } 00634 break; 00635 #endif /* RCC_PLLSAI_SUPPORT */ 00636 00637 case LL_RCC_SAI1_A_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block A clock source */ 00638 case LL_RCC_SAI1_B_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block B clock source */ 00639 if (LL_RCC_PLLI2S_IsReady()) 00640 { 00641 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI(); 00642 } 00643 break; 00644 00645 #if defined(RCC_SAI1A_PLLSOURCE_SUPPORT) 00646 case LL_RCC_SAI1_A_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block A clock source */ 00647 case LL_RCC_SAI1_B_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block B clock source */ 00648 if (LL_RCC_PLL_IsReady()) 00649 { 00650 sai_frequency = RCC_PLL_GetFreqDomain_SAI(); 00651 } 00652 break; 00653 00654 case LL_RCC_SAI1_A_CLKSOURCE_PLLSRC: 00655 case LL_RCC_SAI1_B_CLKSOURCE_PLLSRC: 00656 switch (LL_RCC_PLL_GetMainSource()) 00657 { 00658 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 Block A or B clock source */ 00659 if (LL_RCC_HSE_IsReady()) 00660 { 00661 sai_frequency = HSE_VALUE; 00662 } 00663 break; 00664 00665 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 Block A or B clock source */ 00666 default: 00667 if (LL_RCC_HSI_IsReady()) 00668 { 00669 sai_frequency = HSI_VALUE; 00670 } 00671 break; 00672 } 00673 break; 00674 #endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */ 00675 00676 case LL_RCC_SAI1_A_CLKSOURCE_PIN: /* External input clock used as SAI1 Block A clock source */ 00677 case LL_RCC_SAI1_B_CLKSOURCE_PIN: /* External input clock used as SAI1 Block B clock source */ 00678 default: 00679 sai_frequency = EXTERNAL_CLOCK_VALUE; 00680 break; 00681 } 00682 } 00683 #endif /* RCC_DCKCFGR_SAI1ASRC */ 00684 00685 return sai_frequency; 00686 } 00687 #endif /* SAI1 */ 00688 00689 #if defined(SDIO) 00690 /** 00691 * @brief Return SDIOx clock frequency 00692 * @param SDIOxSource This parameter can be one of the following values: 00693 * @arg @ref LL_RCC_SDIO_CLKSOURCE 00694 * @retval SDIO clock frequency (in Hz) 00695 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready 00696 */ 00697 uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource) 00698 { 00699 uint32_t SDIO_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00700 00701 /* Check parameter */ 00702 assert_param(IS_LL_RCC_SDIO_CLKSOURCE(SDIOxSource)); 00703 00704 if (SDIOxSource == LL_RCC_SDIO_CLKSOURCE) 00705 { 00706 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) 00707 /* SDIOCLK clock frequency */ 00708 switch (LL_RCC_GetSDIOClockSource(SDIOxSource)) 00709 { 00710 case LL_RCC_SDIO_CLKSOURCE_PLL48CLK: /* PLL48M clock used as SDIO clock source */ 00711 switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE)) 00712 { 00713 case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */ 00714 if (LL_RCC_PLL_IsReady()) 00715 { 00716 SDIO_frequency = RCC_PLL_GetFreqDomain_48M(); 00717 } 00718 break; 00719 00720 #if defined(RCC_PLLSAI_SUPPORT) 00721 case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */ 00722 default: 00723 if (LL_RCC_PLLSAI_IsReady()) 00724 { 00725 SDIO_frequency = RCC_PLLSAI_GetFreqDomain_48M(); 00726 } 00727 break; 00728 #endif /* RCC_PLLSAI_SUPPORT */ 00729 00730 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) 00731 case LL_RCC_CK48M_CLKSOURCE_PLLI2S: /* PLLI2S clock used as 48Mhz domain clock */ 00732 default: 00733 if (LL_RCC_PLLI2S_IsReady()) 00734 { 00735 SDIO_frequency = RCC_PLLI2S_GetFreqDomain_48M(); 00736 } 00737 break; 00738 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ 00739 } 00740 break; 00741 00742 case LL_RCC_SDIO_CLKSOURCE_SYSCLK: /* PLL clock used as SDIO clock source */ 00743 default: 00744 SDIO_frequency = RCC_GetSystemClockFreq(); 00745 break; 00746 } 00747 #else 00748 /* PLL clock used as 48Mhz domain clock */ 00749 if (LL_RCC_PLL_IsReady()) 00750 { 00751 SDIO_frequency = RCC_PLL_GetFreqDomain_48M(); 00752 } 00753 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ 00754 } 00755 00756 return SDIO_frequency; 00757 } 00758 #endif /* SDIO */ 00759 00760 #if defined(RNG) 00761 /** 00762 * @brief Return RNGx clock frequency 00763 * @param RNGxSource This parameter can be one of the following values: 00764 * @arg @ref LL_RCC_RNG_CLKSOURCE 00765 * @retval RNG clock frequency (in Hz) 00766 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready 00767 */ 00768 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) 00769 { 00770 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00771 00772 /* Check parameter */ 00773 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource)); 00774 00775 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) 00776 /* RNGCLK clock frequency */ 00777 switch (LL_RCC_GetRNGClockSource(RNGxSource)) 00778 { 00779 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) 00780 case LL_RCC_RNG_CLKSOURCE_PLLI2S: /* PLLI2S clock used as RNG clock source */ 00781 if (LL_RCC_PLLI2S_IsReady()) 00782 { 00783 rng_frequency = RCC_PLLI2S_GetFreqDomain_48M(); 00784 } 00785 break; 00786 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ 00787 00788 #if defined(RCC_PLLSAI_SUPPORT) 00789 case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */ 00790 if (LL_RCC_PLLSAI_IsReady()) 00791 { 00792 rng_frequency = RCC_PLLSAI_GetFreqDomain_48M(); 00793 } 00794 break; 00795 #endif /* RCC_PLLSAI_SUPPORT */ 00796 00797 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */ 00798 default: 00799 if (LL_RCC_PLL_IsReady()) 00800 { 00801 rng_frequency = RCC_PLL_GetFreqDomain_48M(); 00802 } 00803 break; 00804 } 00805 #else 00806 /* PLL clock used as RNG clock source */ 00807 if (LL_RCC_PLL_IsReady()) 00808 { 00809 rng_frequency = RCC_PLL_GetFreqDomain_48M(); 00810 } 00811 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ 00812 00813 return rng_frequency; 00814 } 00815 #endif /* RNG */ 00816 00817 #if defined(CEC) 00818 /** 00819 * @brief Return CEC clock frequency 00820 * @param CECxSource This parameter can be one of the following values: 00821 * @arg @ref LL_RCC_CEC_CLKSOURCE 00822 * @retval CEC clock frequency (in Hz) 00823 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready 00824 */ 00825 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource) 00826 { 00827 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00828 00829 /* Check parameter */ 00830 assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource)); 00831 00832 /* CECCLK clock frequency */ 00833 switch (LL_RCC_GetCECClockSource(CECxSource)) 00834 { 00835 case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */ 00836 if (LL_RCC_LSE_IsReady()) 00837 { 00838 cec_frequency = LSE_VALUE; 00839 } 00840 break; 00841 00842 case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */ 00843 default: 00844 if (LL_RCC_HSI_IsReady()) 00845 { 00846 cec_frequency = HSI_VALUE/488U; 00847 } 00848 break; 00849 } 00850 00851 return cec_frequency; 00852 } 00853 #endif /* CEC */ 00854 00855 #if defined(USB_OTG_FS) || defined(USB_OTG_HS) 00856 /** 00857 * @brief Return USBx clock frequency 00858 * @param USBxSource This parameter can be one of the following values: 00859 * @arg @ref LL_RCC_USB_CLKSOURCE 00860 * @retval USB clock frequency (in Hz) 00861 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready 00862 */ 00863 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) 00864 { 00865 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00866 00867 /* Check parameter */ 00868 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); 00869 00870 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) 00871 /* USBCLK clock frequency */ 00872 switch (LL_RCC_GetUSBClockSource(USBxSource)) 00873 { 00874 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) 00875 case LL_RCC_USB_CLKSOURCE_PLLI2S: /* PLLI2S clock used as USB clock source */ 00876 if (LL_RCC_PLLI2S_IsReady()) 00877 { 00878 usb_frequency = RCC_PLLI2S_GetFreqDomain_48M(); 00879 } 00880 break; 00881 00882 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ 00883 00884 #if defined(RCC_PLLSAI_SUPPORT) 00885 case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */ 00886 if (LL_RCC_PLLSAI_IsReady()) 00887 { 00888 usb_frequency = RCC_PLLSAI_GetFreqDomain_48M(); 00889 } 00890 break; 00891 #endif /* RCC_PLLSAI_SUPPORT */ 00892 00893 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ 00894 default: 00895 if (LL_RCC_PLL_IsReady()) 00896 { 00897 usb_frequency = RCC_PLL_GetFreqDomain_48M(); 00898 } 00899 break; 00900 } 00901 #else 00902 /* PLL clock used as USB clock source */ 00903 if (LL_RCC_PLL_IsReady()) 00904 { 00905 usb_frequency = RCC_PLL_GetFreqDomain_48M(); 00906 } 00907 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ 00908 00909 return usb_frequency; 00910 } 00911 #endif /* USB_OTG_FS || USB_OTG_HS */ 00912 00913 #if defined(DFSDM1_Channel0) 00914 /** 00915 * @brief Return DFSDMx clock frequency 00916 * @param DFSDMxSource This parameter can be one of the following values: 00917 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE 00918 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*) 00919 * 00920 * (*) value not defined in all devices. 00921 * @retval DFSDM clock frequency (in Hz) 00922 */ 00923 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource) 00924 { 00925 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00926 00927 /* Check parameter */ 00928 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource)); 00929 00930 if (DFSDMxSource == LL_RCC_DFSDM1_CLKSOURCE) 00931 { 00932 /* DFSDM1CLK clock frequency */ 00933 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource)) 00934 { 00935 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */ 00936 dfsdm_frequency = RCC_GetSystemClockFreq(); 00937 break; 00938 00939 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */ 00940 default: 00941 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 00942 break; 00943 } 00944 } 00945 #if defined(DFSDM2_Channel0) 00946 else 00947 { 00948 /* DFSDM2CLK clock frequency */ 00949 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource)) 00950 { 00951 case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK: /* DFSDM2 Clock is SYSCLK */ 00952 dfsdm_frequency = RCC_GetSystemClockFreq(); 00953 break; 00954 00955 case LL_RCC_DFSDM2_CLKSOURCE_PCLK2: /* DFSDM2 Clock is PCLK2 */ 00956 default: 00957 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 00958 break; 00959 } 00960 } 00961 #endif /* DFSDM2_Channel0 */ 00962 00963 return dfsdm_frequency; 00964 } 00965 00966 /** 00967 * @brief Return DFSDMx Audio clock frequency 00968 * @param DFSDMxSource This parameter can be one of the following values: 00969 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE 00970 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*) 00971 * 00972 * (*) value not defined in all devices. 00973 * @retval DFSDM clock frequency (in Hz) 00974 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready 00975 */ 00976 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource) 00977 { 00978 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00979 00980 /* Check parameter */ 00981 assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource)); 00982 00983 if (DFSDMxSource == LL_RCC_DFSDM1_AUDIO_CLKSOURCE) 00984 { 00985 /* DFSDM1CLK clock frequency */ 00986 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource)) 00987 { 00988 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM1 clock */ 00989 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE); 00990 break; 00991 00992 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM1 clock */ 00993 default: 00994 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE); 00995 break; 00996 } 00997 } 00998 #if defined(DFSDM2_Channel0) 00999 else 01000 { 01001 /* DFSDM2CLK clock frequency */ 01002 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource)) 01003 { 01004 case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM2 clock */ 01005 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE); 01006 break; 01007 01008 case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM2 clock */ 01009 default: 01010 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE); 01011 break; 01012 } 01013 } 01014 #endif /* DFSDM2_Channel0 */ 01015 01016 return dfsdm_frequency; 01017 } 01018 #endif /* DFSDM1_Channel0 */ 01019 01020 #if defined(DSI) 01021 /** 01022 * @brief Return DSI clock frequency 01023 * @param DSIxSource This parameter can be one of the following values: 01024 * @arg @ref LL_RCC_DSI_CLKSOURCE 01025 * @retval DSI clock frequency (in Hz) 01026 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready 01027 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used 01028 */ 01029 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource) 01030 { 01031 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 01032 01033 /* Check parameter */ 01034 assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource)); 01035 01036 /* DSICLK clock frequency */ 01037 switch (LL_RCC_GetDSIClockSource(DSIxSource)) 01038 { 01039 case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */ 01040 if (LL_RCC_PLL_IsReady()) 01041 { 01042 dsi_frequency = RCC_PLL_GetFreqDomain_DSI(); 01043 } 01044 break; 01045 01046 case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */ 01047 default: 01048 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA; 01049 break; 01050 } 01051 01052 return dsi_frequency; 01053 } 01054 #endif /* DSI */ 01055 01056 #if defined(LTDC) 01057 /** 01058 * @brief Return LTDC clock frequency 01059 * @param LTDCxSource This parameter can be one of the following values: 01060 * @arg @ref LL_RCC_LTDC_CLKSOURCE 01061 * @retval LTDC clock frequency (in Hz) 01062 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready 01063 */ 01064 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource) 01065 { 01066 uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 01067 01068 /* Check parameter */ 01069 assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource)); 01070 01071 if (LL_RCC_PLLSAI_IsReady()) 01072 { 01073 ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC(); 01074 } 01075 01076 return ltdc_frequency; 01077 } 01078 #endif /* LTDC */ 01079 01080 #if defined(SPDIFRX) 01081 /** 01082 * @brief Return SPDIFRX clock frequency 01083 * @param SPDIFRXxSource This parameter can be one of the following values: 01084 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE 01085 * @retval SPDIFRX clock frequency (in Hz) 01086 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready 01087 */ 01088 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource) 01089 { 01090 uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 01091 01092 /* Check parameter */ 01093 assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource)); 01094 01095 /* SPDIFRX1CLK clock frequency */ 01096 switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource)) 01097 { 01098 case LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S: /* SPDIFRX Clock is PLLI2S Osc. */ 01099 if (LL_RCC_PLLI2S_IsReady()) 01100 { 01101 spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX(); 01102 } 01103 break; 01104 01105 case LL_RCC_SPDIFRX1_CLKSOURCE_PLL: /* SPDIFRX Clock is PLL Osc. */ 01106 default: 01107 if (LL_RCC_PLL_IsReady()) 01108 { 01109 spdifrx_frequency = RCC_PLL_GetFreqDomain_SPDIFRX(); 01110 } 01111 break; 01112 } 01113 01114 return spdifrx_frequency; 01115 } 01116 #endif /* SPDIFRX */ 01117 01118 /** 01119 * @} 01120 */ 01121 01122 /** 01123 * @} 01124 */ 01125 01126 /** @addtogroup RCC_LL_Private_Functions 01127 * @{ 01128 */ 01129 01130 /** 01131 * @brief Return SYSTEM clock frequency 01132 * @retval SYSTEM clock frequency (in Hz) 01133 */ 01134 uint32_t RCC_GetSystemClockFreq(void) 01135 { 01136 uint32_t frequency = 0U; 01137 01138 /* Get SYSCLK source -------------------------------------------------------*/ 01139 switch (LL_RCC_GetSysClkSource()) 01140 { 01141 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ 01142 frequency = HSI_VALUE; 01143 break; 01144 01145 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ 01146 frequency = HSE_VALUE; 01147 break; 01148 01149 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ 01150 frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLL); 01151 break; 01152 01153 #if defined(RCC_PLLR_SYSCLK_SUPPORT) 01154 case LL_RCC_SYS_CLKSOURCE_STATUS_PLLR: /* PLLR used as system clock source */ 01155 frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLLR); 01156 break; 01157 #endif /* RCC_PLLR_SYSCLK_SUPPORT */ 01158 01159 default: 01160 frequency = HSI_VALUE; 01161 break; 01162 } 01163 01164 return frequency; 01165 } 01166 01167 /** 01168 * @brief Return HCLK clock frequency 01169 * @param SYSCLK_Frequency SYSCLK clock frequency 01170 * @retval HCLK clock frequency (in Hz) 01171 */ 01172 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) 01173 { 01174 /* HCLK clock frequency */ 01175 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); 01176 } 01177 01178 /** 01179 * @brief Return PCLK1 clock frequency 01180 * @param HCLK_Frequency HCLK clock frequency 01181 * @retval PCLK1 clock frequency (in Hz) 01182 */ 01183 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) 01184 { 01185 /* PCLK1 clock frequency */ 01186 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); 01187 } 01188 01189 /** 01190 * @brief Return PCLK2 clock frequency 01191 * @param HCLK_Frequency HCLK clock frequency 01192 * @retval PCLK2 clock frequency (in Hz) 01193 */ 01194 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) 01195 { 01196 /* PCLK2 clock frequency */ 01197 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); 01198 } 01199 01200 /** 01201 * @brief Return PLL clock frequency used for system domain 01202 * @param SYSCLK_Source System clock source 01203 * @retval PLL clock frequency (in Hz) 01204 */ 01205 uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source) 01206 { 01207 uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U; 01208 01209 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN 01210 SYSCLK = PLL_VCO / (PLLP or PLLR) 01211 */ 01212 pllsource = LL_RCC_PLL_GetMainSource(); 01213 01214 switch (pllsource) 01215 { 01216 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ 01217 pllinputfreq = HSI_VALUE; 01218 break; 01219 01220 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ 01221 pllinputfreq = HSE_VALUE; 01222 break; 01223 01224 default: 01225 pllinputfreq = HSI_VALUE; 01226 break; 01227 } 01228 01229 if (SYSCLK_Source == LL_RCC_SYS_CLKSOURCE_STATUS_PLL) 01230 { 01231 plloutputfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), 01232 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); 01233 } 01234 #if defined(RCC_PLLR_SYSCLK_SUPPORT) 01235 else 01236 { 01237 plloutputfreq = __LL_RCC_CALC_PLLRCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), 01238 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); 01239 } 01240 #endif /* RCC_PLLR_SYSCLK_SUPPORT */ 01241 01242 return plloutputfreq; 01243 } 01244 01245 /** 01246 * @brief Return PLL clock frequency used for 48 MHz domain 01247 * @retval PLL clock frequency (in Hz) 01248 */ 01249 uint32_t RCC_PLL_GetFreqDomain_48M(void) 01250 { 01251 uint32_t pllinputfreq = 0U, pllsource = 0U; 01252 01253 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN 01254 48M Domain clock = PLL_VCO / PLLQ 01255 */ 01256 pllsource = LL_RCC_PLL_GetMainSource(); 01257 01258 switch (pllsource) 01259 { 01260 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ 01261 pllinputfreq = HSI_VALUE; 01262 break; 01263 01264 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ 01265 pllinputfreq = HSE_VALUE; 01266 break; 01267 01268 default: 01269 pllinputfreq = HSI_VALUE; 01270 break; 01271 } 01272 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), 01273 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); 01274 } 01275 01276 #if defined(DSI) 01277 /** 01278 * @brief Return PLL clock frequency used for DSI clock 01279 * @retval PLL clock frequency (in Hz) 01280 */ 01281 uint32_t RCC_PLL_GetFreqDomain_DSI(void) 01282 { 01283 uint32_t pllinputfreq = 0U, pllsource = 0U; 01284 01285 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN 01286 DSICLK = PLL_VCO / PLLR 01287 */ 01288 pllsource = LL_RCC_PLL_GetMainSource(); 01289 01290 switch (pllsource) 01291 { 01292 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ 01293 pllinputfreq = HSE_VALUE; 01294 break; 01295 01296 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ 01297 default: 01298 pllinputfreq = HSI_VALUE; 01299 break; 01300 } 01301 return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), 01302 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); 01303 } 01304 #endif /* DSI */ 01305 01306 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC) 01307 /** 01308 * @brief Return PLL clock frequency used for I2S clock 01309 * @retval PLL clock frequency (in Hz) 01310 */ 01311 uint32_t RCC_PLL_GetFreqDomain_I2S(void) 01312 { 01313 uint32_t pllinputfreq = 0U, pllsource = 0U; 01314 01315 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN 01316 I2SCLK = PLL_VCO / PLLR 01317 */ 01318 pllsource = LL_RCC_PLL_GetMainSource(); 01319 01320 switch (pllsource) 01321 { 01322 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ 01323 pllinputfreq = HSE_VALUE; 01324 break; 01325 01326 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ 01327 default: 01328 pllinputfreq = HSI_VALUE; 01329 break; 01330 } 01331 return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), 01332 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); 01333 } 01334 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */ 01335 01336 #if defined(SPDIFRX) 01337 /** 01338 * @brief Return PLL clock frequency used for SPDIFRX clock 01339 * @retval PLL clock frequency (in Hz) 01340 */ 01341 uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void) 01342 { 01343 uint32_t pllinputfreq = 0U, pllsource = 0U; 01344 01345 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN 01346 SPDIFRXCLK = PLL_VCO / PLLR 01347 */ 01348 pllsource = LL_RCC_PLL_GetMainSource(); 01349 01350 switch (pllsource) 01351 { 01352 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ 01353 pllinputfreq = HSE_VALUE; 01354 break; 01355 01356 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ 01357 default: 01358 pllinputfreq = HSI_VALUE; 01359 break; 01360 } 01361 return __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), 01362 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); 01363 } 01364 #endif /* SPDIFRX */ 01365 01366 #if defined(RCC_PLLCFGR_PLLR) 01367 #if defined(SAI1) 01368 /** 01369 * @brief Return PLL clock frequency used for SAI clock 01370 * @retval PLL clock frequency (in Hz) 01371 */ 01372 uint32_t RCC_PLL_GetFreqDomain_SAI(void) 01373 { 01374 uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U; 01375 01376 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN 01377 SAICLK = (PLL_VCO / PLLR) / PLLDIVR 01378 or 01379 SAICLK = PLL_VCO / PLLR 01380 */ 01381 pllsource = LL_RCC_PLL_GetMainSource(); 01382 01383 switch (pllsource) 01384 { 01385 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ 01386 pllinputfreq = HSE_VALUE; 01387 break; 01388 01389 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ 01390 default: 01391 pllinputfreq = HSI_VALUE; 01392 break; 01393 } 01394 01395 #if defined(RCC_DCKCFGR_PLLDIVR) 01396 plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), 01397 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR(), LL_RCC_PLL_GetDIVR()); 01398 #else 01399 plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), 01400 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); 01401 #endif /* RCC_DCKCFGR_PLLDIVR */ 01402 01403 return plloutputfreq; 01404 } 01405 #endif /* SAI1 */ 01406 #endif /* RCC_PLLCFGR_PLLR */ 01407 01408 #if defined(RCC_PLLSAI_SUPPORT) 01409 /** 01410 * @brief Return PLLSAI clock frequency used for SAI domain 01411 * @retval PLLSAI clock frequency (in Hz) 01412 */ 01413 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void) 01414 { 01415 uint32_t pllinputfreq = 0U, pllsource = 0U; 01416 01417 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN 01418 SAI domain clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ 01419 */ 01420 pllsource = LL_RCC_PLL_GetMainSource(); 01421 01422 switch (pllsource) 01423 { 01424 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */ 01425 pllinputfreq = HSI_VALUE; 01426 break; 01427 01428 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */ 01429 pllinputfreq = HSE_VALUE; 01430 break; 01431 01432 default: 01433 pllinputfreq = HSI_VALUE; 01434 break; 01435 } 01436 return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(), 01437 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ()); 01438 } 01439 01440 #if defined(RCC_PLLSAICFGR_PLLSAIP) 01441 /** 01442 * @brief Return PLLSAI clock frequency used for 48Mhz domain 01443 * @retval PLLSAI clock frequency (in Hz) 01444 */ 01445 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void) 01446 { 01447 uint32_t pllinputfreq = 0U, pllsource = 0U; 01448 01449 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN 01450 48M Domain clock = PLLSAI_VCO / PLLSAIP 01451 */ 01452 pllsource = LL_RCC_PLL_GetMainSource(); 01453 01454 switch (pllsource) 01455 { 01456 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */ 01457 pllinputfreq = HSI_VALUE; 01458 break; 01459 01460 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */ 01461 pllinputfreq = HSE_VALUE; 01462 break; 01463 01464 default: 01465 pllinputfreq = HSI_VALUE; 01466 break; 01467 } 01468 return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(), 01469 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP()); 01470 } 01471 #endif /* RCC_PLLSAICFGR_PLLSAIP */ 01472 01473 #if defined(LTDC) 01474 /** 01475 * @brief Return PLLSAI clock frequency used for LTDC domain 01476 * @retval PLLSAI clock frequency (in Hz) 01477 */ 01478 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void) 01479 { 01480 uint32_t pllinputfreq = 0U, pllsource = 0U; 01481 01482 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN 01483 LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR 01484 */ 01485 pllsource = LL_RCC_PLL_GetMainSource(); 01486 01487 switch (pllsource) 01488 { 01489 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */ 01490 pllinputfreq = HSI_VALUE; 01491 break; 01492 01493 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */ 01494 pllinputfreq = HSE_VALUE; 01495 break; 01496 01497 default: 01498 pllinputfreq = HSI_VALUE; 01499 break; 01500 } 01501 return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(), 01502 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR()); 01503 } 01504 #endif /* LTDC */ 01505 #endif /* RCC_PLLSAI_SUPPORT */ 01506 01507 #if defined(RCC_PLLI2S_SUPPORT) 01508 #if defined(SAI1) 01509 /** 01510 * @brief Return PLLI2S clock frequency used for SAI domains 01511 * @retval PLLI2S clock frequency (in Hz) 01512 */ 01513 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void) 01514 { 01515 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U; 01516 01517 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN 01518 SAI domain clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ 01519 or 01520 SAI domain clock = (PLLI2S_VCO / PLLI2SR) / PLLI2SDIVR 01521 */ 01522 plli2ssource = LL_RCC_PLLI2S_GetMainSource(); 01523 01524 switch (plli2ssource) 01525 { 01526 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */ 01527 plli2sinputfreq = HSE_VALUE; 01528 break; 01529 01530 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC) 01531 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */ 01532 plli2sinputfreq = EXTERNAL_CLOCK_VALUE; 01533 break; 01534 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */ 01535 01536 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */ 01537 default: 01538 plli2sinputfreq = HSI_VALUE; 01539 break; 01540 } 01541 01542 #if defined(RCC_DCKCFGR_PLLI2SDIVQ) 01543 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(), 01544 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ()); 01545 #else 01546 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(), 01547 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR(), LL_RCC_PLLI2S_GetDIVR()); 01548 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */ 01549 01550 return plli2soutputfreq; 01551 } 01552 #endif /* SAI1 */ 01553 01554 #if defined(SPDIFRX) 01555 /** 01556 * @brief Return PLLI2S clock frequency used for SPDIFRX domain 01557 * @retval PLLI2S clock frequency (in Hz) 01558 */ 01559 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void) 01560 { 01561 uint32_t pllinputfreq = 0U, pllsource = 0U; 01562 01563 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN 01564 SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP 01565 */ 01566 pllsource = LL_RCC_PLLI2S_GetMainSource(); 01567 01568 switch (pllsource) 01569 { 01570 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */ 01571 pllinputfreq = HSE_VALUE; 01572 break; 01573 01574 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */ 01575 default: 01576 pllinputfreq = HSI_VALUE; 01577 break; 01578 } 01579 01580 return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLLI2S_GetDivider(), 01581 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP()); 01582 } 01583 #endif /* SPDIFRX */ 01584 01585 /** 01586 * @brief Return PLLI2S clock frequency used for I2S domain 01587 * @retval PLLI2S clock frequency (in Hz) 01588 */ 01589 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void) 01590 { 01591 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U; 01592 01593 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN 01594 I2S Domain clock = PLLI2S_VCO / PLLI2SR 01595 */ 01596 plli2ssource = LL_RCC_PLLI2S_GetMainSource(); 01597 01598 switch (plli2ssource) 01599 { 01600 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */ 01601 plli2sinputfreq = HSE_VALUE; 01602 break; 01603 01604 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC) 01605 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */ 01606 plli2sinputfreq = EXTERNAL_CLOCK_VALUE; 01607 break; 01608 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */ 01609 01610 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */ 01611 default: 01612 plli2sinputfreq = HSI_VALUE; 01613 break; 01614 } 01615 01616 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_I2S_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(), 01617 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR()); 01618 01619 return plli2soutputfreq; 01620 } 01621 01622 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) 01623 /** 01624 * @brief Return PLLI2S clock frequency used for 48Mhz domain 01625 * @retval PLLI2S clock frequency (in Hz) 01626 */ 01627 uint32_t RCC_PLLI2S_GetFreqDomain_48M(void) 01628 { 01629 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U; 01630 01631 /* PLL48M_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN 01632 48M Domain clock = PLLI2S_VCO / PLLI2SQ 01633 */ 01634 plli2ssource = LL_RCC_PLLI2S_GetMainSource(); 01635 01636 switch (plli2ssource) 01637 { 01638 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */ 01639 plli2sinputfreq = HSE_VALUE; 01640 break; 01641 01642 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC) 01643 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */ 01644 plli2sinputfreq = EXTERNAL_CLOCK_VALUE; 01645 break; 01646 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */ 01647 01648 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */ 01649 default: 01650 plli2sinputfreq = HSI_VALUE; 01651 break; 01652 } 01653 01654 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_48M_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(), 01655 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ()); 01656 01657 return plli2soutputfreq; 01658 } 01659 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ 01660 #endif /* RCC_PLLI2S_SUPPORT */ 01661 /** 01662 * @} 01663 */ 01664 01665 /** 01666 * @} 01667 */ 01668 01669 #endif /* defined(RCC) */ 01670 01671 /** 01672 * @} 01673 */ 01674 01675 #endif /* USE_FULL_LL_DRIVER */ 01676 01677 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/