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STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_rcc.h 00004 * @author MCD Application Team 00005 * @brief Header file of RCC LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32F4xx_LL_RCC_H 00038 #define __STM32F4xx_LL_RCC_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32f4xx.h" 00046 00047 /** @addtogroup STM32F4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined(RCC) 00052 00053 /** @defgroup RCC_LL RCC 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 /** @defgroup RCC_LL_Private_Variables RCC Private Variables 00060 * @{ 00061 */ 00062 00063 #if defined(RCC_DCKCFGR_PLLSAIDIVR) 00064 static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16}; 00065 #endif /* RCC_DCKCFGR_PLLSAIDIVR */ 00066 00067 /** 00068 * @} 00069 */ 00070 /* Private constants ---------------------------------------------------------*/ 00071 /* Private macros ------------------------------------------------------------*/ 00072 #if defined(USE_FULL_LL_DRIVER) 00073 /** @defgroup RCC_LL_Private_Macros RCC Private Macros 00074 * @{ 00075 */ 00076 /** 00077 * @} 00078 */ 00079 #endif /*USE_FULL_LL_DRIVER*/ 00080 /* Exported types ------------------------------------------------------------*/ 00081 #if defined(USE_FULL_LL_DRIVER) 00082 /** @defgroup RCC_LL_Exported_Types RCC Exported Types 00083 * @{ 00084 */ 00085 00086 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure 00087 * @{ 00088 */ 00089 00090 /** 00091 * @brief RCC Clocks Frequency Structure 00092 */ 00093 typedef struct 00094 { 00095 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ 00096 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ 00097 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ 00098 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ 00099 } LL_RCC_ClocksTypeDef; 00100 00101 /** 00102 * @} 00103 */ 00104 00105 /** 00106 * @} 00107 */ 00108 #endif /* USE_FULL_LL_DRIVER */ 00109 00110 /* Exported constants --------------------------------------------------------*/ 00111 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants 00112 * @{ 00113 */ 00114 00115 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation 00116 * @brief Defines used to adapt values of different oscillators 00117 * @note These values could be modified in the user environment according to 00118 * HW set-up. 00119 * @{ 00120 */ 00121 #if !defined (HSE_VALUE) 00122 #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */ 00123 #endif /* HSE_VALUE */ 00124 00125 #if !defined (HSI_VALUE) 00126 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ 00127 #endif /* HSI_VALUE */ 00128 00129 #if !defined (LSE_VALUE) 00130 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ 00131 #endif /* LSE_VALUE */ 00132 00133 #if !defined (LSI_VALUE) 00134 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ 00135 #endif /* LSI_VALUE */ 00136 00137 #if !defined (EXTERNAL_CLOCK_VALUE) 00138 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ 00139 #endif /* EXTERNAL_CLOCK_VALUE */ 00140 /** 00141 * @} 00142 */ 00143 00144 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines 00145 * @brief Flags defines which can be used with LL_RCC_WriteReg function 00146 * @{ 00147 */ 00148 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ 00149 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ 00150 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ 00151 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ 00152 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ 00153 #if defined(RCC_PLLI2S_SUPPORT) 00154 #define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */ 00155 #endif /* RCC_PLLI2S_SUPPORT */ 00156 #if defined(RCC_PLLSAI_SUPPORT) 00157 #define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */ 00158 #endif /* RCC_PLLSAI_SUPPORT */ 00159 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ 00160 /** 00161 * @} 00162 */ 00163 00164 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines 00165 * @brief Flags defines which can be used with LL_RCC_ReadReg function 00166 * @{ 00167 */ 00168 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ 00169 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ 00170 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ 00171 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ 00172 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ 00173 #if defined(RCC_PLLI2S_SUPPORT) 00174 #define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */ 00175 #endif /* RCC_PLLI2S_SUPPORT */ 00176 #if defined(RCC_PLLSAI_SUPPORT) 00177 #define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */ 00178 #endif /* RCC_PLLSAI_SUPPORT */ 00179 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ 00180 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ 00181 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ 00182 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ 00183 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ 00184 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 00185 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 00186 #if defined(RCC_CSR_BORRSTF) 00187 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ 00188 #endif /* RCC_CSR_BORRSTF */ 00189 /** 00190 * @} 00191 */ 00192 00193 /** @defgroup RCC_LL_EC_IT IT Defines 00194 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions 00195 * @{ 00196 */ 00197 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ 00198 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ 00199 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ 00200 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ 00201 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ 00202 #if defined(RCC_PLLI2S_SUPPORT) 00203 #define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */ 00204 #endif /* RCC_PLLI2S_SUPPORT */ 00205 #if defined(RCC_PLLSAI_SUPPORT) 00206 #define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */ 00207 #endif /* RCC_PLLSAI_SUPPORT */ 00208 /** 00209 * @} 00210 */ 00211 00212 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch 00213 * @{ 00214 */ 00215 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ 00216 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ 00217 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ 00218 #if defined(RCC_CFGR_SW_PLLR) 00219 #define LL_RCC_SYS_CLKSOURCE_PLLR RCC_CFGR_SW_PLLR /*!< PLLR selection as system clock */ 00220 #endif /* RCC_CFGR_SW_PLLR */ 00221 /** 00222 * @} 00223 */ 00224 00225 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status 00226 * @{ 00227 */ 00228 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 00229 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 00230 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 00231 #if defined(RCC_PLLR_SYSCLK_SUPPORT) 00232 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR RCC_CFGR_SWS_PLLR /*!< PLLR used as system clock */ 00233 #endif /* RCC_PLLR_SYSCLK_SUPPORT */ 00234 /** 00235 * @} 00236 */ 00237 00238 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler 00239 * @{ 00240 */ 00241 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 00242 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 00243 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 00244 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 00245 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 00246 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 00247 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 00248 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 00249 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 00250 /** 00251 * @} 00252 */ 00253 00254 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) 00255 * @{ 00256 */ 00257 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 00258 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 00259 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 00260 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 00261 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 00262 /** 00263 * @} 00264 */ 00265 00266 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) 00267 * @{ 00268 */ 00269 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ 00270 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ 00271 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ 00272 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ 00273 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ 00274 /** 00275 * @} 00276 */ 00277 00278 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection 00279 * @{ 00280 */ 00281 #define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */ 00282 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */ 00283 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */ 00284 #define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */ 00285 #if defined(RCC_CFGR_MCO2) 00286 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */ 00287 #define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */ 00288 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */ 00289 #define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */ 00290 #endif /* RCC_CFGR_MCO2 */ 00291 /** 00292 * @} 00293 */ 00294 00295 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler 00296 * @{ 00297 */ 00298 #define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */ 00299 #define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */ 00300 #define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */ 00301 #define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */ 00302 #define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */ 00303 #if defined(RCC_CFGR_MCO2PRE) 00304 #define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */ 00305 #define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */ 00306 #define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */ 00307 #define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */ 00308 #define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */ 00309 #endif /* RCC_CFGR_MCO2PRE */ 00310 /** 00311 * @} 00312 */ 00313 00314 /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock 00315 * @{ 00316 */ 00317 #define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */ 00318 #define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */ 00319 #define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */ 00320 #define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */ 00321 #define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */ 00322 #define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */ 00323 #define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */ 00324 #define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */ 00325 #define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */ 00326 #define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */ 00327 #define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */ 00328 #define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */ 00329 #define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */ 00330 #define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */ 00331 #define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */ 00332 #define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */ 00333 #define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */ 00334 #define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */ 00335 #define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */ 00336 #define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */ 00337 #define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */ 00338 #define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */ 00339 #define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */ 00340 #define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */ 00341 #define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */ 00342 #define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */ 00343 #define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */ 00344 #define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */ 00345 #define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */ 00346 #define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */ 00347 #define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */ 00348 /** 00349 * @} 00350 */ 00351 00352 #if defined(USE_FULL_LL_DRIVER) 00353 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency 00354 * @{ 00355 */ 00356 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ 00357 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ 00358 /** 00359 * @} 00360 */ 00361 #endif /* USE_FULL_LL_DRIVER */ 00362 00363 #if defined(FMPI2C1) 00364 /** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE Peripheral FMPI2C clock source selection 00365 * @{ 00366 */ 00367 #define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as FMPI2C1 clock source */ 00368 #define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK RCC_DCKCFGR2_FMPI2C1SEL_0 /*!< SYSCLK clock used as FMPI2C1 clock source */ 00369 #define LL_RCC_FMPI2C1_CLKSOURCE_HSI RCC_DCKCFGR2_FMPI2C1SEL_1 /*!< HSI clock used as FMPI2C1 clock source */ 00370 /** 00371 * @} 00372 */ 00373 #endif /* FMPI2C1 */ 00374 00375 #if defined(LPTIM1) 00376 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection 00377 * @{ 00378 */ 00379 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */ 00380 #define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */ 00381 #define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */ 00382 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */ 00383 /** 00384 * @} 00385 */ 00386 #endif /* LPTIM1 */ 00387 00388 #if defined(SAI1) 00389 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection 00390 * @{ 00391 */ 00392 #if defined(RCC_DCKCFGR_SAI1SRC) 00393 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */ 00394 #define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 clock source */ 00395 #define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16)) /*!< PLL clock used as SAI1 clock source */ 00396 #define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16)) /*!< External pin clock used as SAI1 clock source */ 00397 #endif /* RCC_DCKCFGR_SAI1SRC */ 00398 #if defined(RCC_DCKCFGR_SAI2SRC) 00399 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */ 00400 #define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16)) /*!< PLLI2S clock used as SAI2 clock source */ 00401 #define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16)) /*!< PLL clock used as SAI2 clock source */ 00402 #define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16)) /*!< PLL Main clock used as SAI2 clock source */ 00403 #endif /* RCC_DCKCFGR_SAI2SRC */ 00404 #if defined(RCC_DCKCFGR_SAI1ASRC) 00405 #if defined(RCC_SAI1A_PLLSOURCE_SUPPORT) 00406 #define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block A clock source */ 00407 #define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< External pin used as SAI1 block A clock source */ 00408 #define LL_RCC_SAI1_A_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< PLL clock used as SAI1 block A clock source */ 00409 #define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16)) /*!< PLL Main clock used as SAI1 block A clock source */ 00410 #else 00411 #define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block A clock source */ 00412 #define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block A clock source */ 00413 #define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< External pin clock used as SAI1 block A clock source */ 00414 #endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */ 00415 #endif /* RCC_DCKCFGR_SAI1ASRC */ 00416 #if defined(RCC_DCKCFGR_SAI1BSRC) 00417 #if defined(RCC_SAI1B_PLLSOURCE_SUPPORT) 00418 #define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block B clock source */ 00419 #define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< External pin used as SAI1 block B clock source */ 00420 #define LL_RCC_SAI1_B_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< PLL clock used as SAI1 block B clock source */ 00421 #define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16)) /*!< PLL Main clock used as SAI1 block B clock source */ 00422 #else 00423 #define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block B clock source */ 00424 #define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block B clock source */ 00425 #define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< External pin clock used as SAI1 block B clock source */ 00426 #endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */ 00427 #endif /* RCC_DCKCFGR_SAI1BSRC */ 00428 /** 00429 * @} 00430 */ 00431 #endif /* SAI1 */ 00432 00433 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) 00434 /** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE Peripheral SDIO clock source selection 00435 * @{ 00436 */ 00437 #define LL_RCC_SDIO_CLKSOURCE_PLL48CLK 0x00000000U /*!< PLL 48M domain clock used as SDIO clock */ 00438 #if defined(RCC_DCKCFGR_SDIOSEL) 00439 #define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR_SDIOSEL /*!< System clock clock used as SDIO clock */ 00440 #else 00441 #define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDIOSEL /*!< System clock clock used as SDIO clock */ 00442 #endif /* RCC_DCKCFGR_SDIOSEL */ 00443 /** 00444 * @} 00445 */ 00446 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ 00447 00448 #if defined(DSI) 00449 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection 00450 * @{ 00451 */ 00452 #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */ 00453 #define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR_DSISEL /*!< PLL clock used as DSI byte lane clock source */ 00454 /** 00455 * @} 00456 */ 00457 #endif /* DSI */ 00458 00459 #if defined(CEC) 00460 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection 00461 * @{ 00462 */ 00463 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as CEC clock */ 00464 #define LL_RCC_CEC_CLKSOURCE_LSE RCC_DCKCFGR2_CECSEL /*!< LSE oscillator clock used as CEC clock */ 00465 /** 00466 * @} 00467 */ 00468 #endif /* CEC */ 00469 00470 /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection 00471 * @{ 00472 */ 00473 #if defined(RCC_CFGR_I2SSRC) 00474 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */ 00475 #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */ 00476 #endif /* RCC_CFGR_I2SSRC */ 00477 #if defined(RCC_DCKCFGR_I2SSRC) 00478 #define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U) /*!< PLL clock used as I2S1 clock source */ 00479 #define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16)) /*!< External pin used as I2S1 clock source */ 00480 #define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16)) /*!< PLL Main clock used as I2S1 clock source */ 00481 #endif /* RCC_DCKCFGR_I2SSRC */ 00482 #if defined(RCC_DCKCFGR_I2S1SRC) 00483 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U) /*!< PLLI2S clock used as I2S1 clock source */ 00484 #define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /*!< External pin used as I2S1 clock source */ 00485 #define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /*!< PLL clock used as I2S1 clock source */ 00486 #define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16)) /*!< PLL Main clock used as I2S1 clock source */ 00487 #endif /* RCC_DCKCFGR_I2S1SRC */ 00488 #if defined(RCC_DCKCFGR_I2S2SRC) 00489 #define LL_RCC_I2S2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U) /*!< PLLI2S clock used as I2S2 clock source */ 00490 #define LL_RCC_I2S2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /*!< External pin used as I2S2 clock source */ 00491 #define LL_RCC_I2S2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /*!< PLL clock used as I2S2 clock source */ 00492 #define LL_RCC_I2S2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16)) /*!< PLL Main clock used as I2S2 clock source */ 00493 #endif /* RCC_DCKCFGR_I2S2SRC */ 00494 /** 00495 * @} 00496 */ 00497 00498 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) 00499 /** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection 00500 * @{ 00501 */ 00502 #if defined(RCC_DCKCFGR_CK48MSEL) 00503 #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */ 00504 #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */ 00505 #endif /* RCC_DCKCFGR_CK48MSEL */ 00506 #if defined(RCC_DCKCFGR2_CK48MSEL) 00507 #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */ 00508 #if defined(RCC_PLLSAI_SUPPORT) 00509 #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */ 00510 #endif /* RCC_PLLSAI_SUPPORT */ 00511 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) 00512 #define LL_RCC_CK48M_CLKSOURCE_PLLI2S RCC_DCKCFGR2_CK48MSEL /*!< PLLI2S oscillator clock used as 48Mhz domain clock */ 00513 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ 00514 #endif /* RCC_DCKCFGR2_CK48MSEL */ 00515 /** 00516 * @} 00517 */ 00518 00519 #if defined(RNG) 00520 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection 00521 * @{ 00522 */ 00523 #define LL_RCC_RNG_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as RNG clock source */ 00524 #if defined(RCC_PLLSAI_SUPPORT) 00525 #define LL_RCC_RNG_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as RNG clock source */ 00526 #endif /* RCC_PLLSAI_SUPPORT */ 00527 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) 00528 #define LL_RCC_RNG_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as RNG clock source */ 00529 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ 00530 /** 00531 * @} 00532 */ 00533 #endif /* RNG */ 00534 00535 #if defined(USB_OTG_FS) || defined(USB_OTG_HS) 00536 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection 00537 * @{ 00538 */ 00539 #define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as USB clock source */ 00540 #if defined(RCC_PLLSAI_SUPPORT) 00541 #define LL_RCC_USB_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as USB clock source */ 00542 #endif /* RCC_PLLSAI_SUPPORT */ 00543 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) 00544 #define LL_RCC_USB_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as USB clock source */ 00545 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ 00546 /** 00547 * @} 00548 */ 00549 #endif /* USB_OTG_FS || USB_OTG_HS */ 00550 00551 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ 00552 00553 #if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0) 00554 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection 00555 * @{ 00556 */ 00557 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM1 Audio clock source */ 00558 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /*!< I2S2 clock used as DFSDM1 Audio clock source */ 00559 #if defined(DFSDM2_Channel0) 00560 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM2 Audio clock source */ 00561 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /*!< I2S2 clock used as DFSDM2 Audio clock source */ 00562 #endif /* DFSDM2_Channel0 */ 00563 /** 00564 * @} 00565 */ 00566 00567 /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection 00568 * @{ 00569 */ 00570 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */ 00571 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM1 clock */ 00572 #if defined(DFSDM2_Channel0) 00573 #define LL_RCC_DFSDM2_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM2 clock */ 00574 #define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM2 clock */ 00575 #endif /* DFSDM2_Channel0 */ 00576 /** 00577 * @} 00578 */ 00579 #endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */ 00580 00581 #if defined(FMPI2C1) 00582 /** @defgroup RCC_LL_EC_FMPI2C1 Peripheral FMPI2C get clock source 00583 * @{ 00584 */ 00585 #define LL_RCC_FMPI2C1_CLKSOURCE RCC_DCKCFGR2_FMPI2C1SEL /*!< FMPI2C1 Clock source selection */ 00586 /** 00587 * @} 00588 */ 00589 #endif /* FMPI2C1 */ 00590 00591 #if defined(SPDIFRX) 00592 /** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection 00593 * @{ 00594 */ 00595 #define LL_RCC_SPDIFRX1_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as SPDIFRX clock source */ 00596 #define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S RCC_DCKCFGR2_SPDIFRXSEL /*!< PLLI2S clock used as SPDIFRX clock source */ 00597 /** 00598 * @} 00599 */ 00600 #endif /* SPDIFRX */ 00601 00602 #if defined(LPTIM1) 00603 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source 00604 * @{ 00605 */ 00606 #define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */ 00607 /** 00608 * @} 00609 */ 00610 #endif /* LPTIM1 */ 00611 00612 #if defined(SAI1) 00613 /** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source 00614 * @{ 00615 */ 00616 #if defined(RCC_DCKCFGR_SAI1ASRC) 00617 #define LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC /*!< SAI1 block A Clock source selection */ 00618 #endif /* RCC_DCKCFGR_SAI1ASRC */ 00619 #if defined(RCC_DCKCFGR_SAI1BSRC) 00620 #define LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC /*!< SAI1 block B Clock source selection */ 00621 #endif /* RCC_DCKCFGR_SAI1BSRC */ 00622 #if defined(RCC_DCKCFGR_SAI1SRC) 00623 #define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR_SAI1SRC /*!< SAI1 Clock source selection */ 00624 #endif /* RCC_DCKCFGR_SAI1SRC */ 00625 #if defined(RCC_DCKCFGR_SAI2SRC) 00626 #define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR_SAI2SRC /*!< SAI2 Clock source selection */ 00627 #endif /* RCC_DCKCFGR_SAI2SRC */ 00628 /** 00629 * @} 00630 */ 00631 #endif /* SAI1 */ 00632 00633 #if defined(SDIO) 00634 /** @defgroup RCC_LL_EC_SDIOx Peripheral SDIO get clock source 00635 * @{ 00636 */ 00637 #if defined(RCC_DCKCFGR_SDIOSEL) 00638 #define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR_SDIOSEL /*!< SDIO Clock source selection */ 00639 #elif defined(RCC_DCKCFGR2_SDIOSEL) 00640 #define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR2_SDIOSEL /*!< SDIO Clock source selection */ 00641 #else 00642 #define LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< SDIO Clock source selection */ 00643 #endif 00644 /** 00645 * @} 00646 */ 00647 #endif /* SDIO */ 00648 00649 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) 00650 /** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source 00651 * @{ 00652 */ 00653 #if defined(RCC_DCKCFGR_CK48MSEL) 00654 #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR_CK48MSEL /*!< CK48M Domain clock source selection */ 00655 #endif /* RCC_DCKCFGR_CK48MSEL */ 00656 #if defined(RCC_DCKCFGR2_CK48MSEL) 00657 #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */ 00658 #endif /* RCC_DCKCFGR_CK48MSEL */ 00659 /** 00660 * @} 00661 */ 00662 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ 00663 00664 #if defined(RNG) 00665 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source 00666 * @{ 00667 */ 00668 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) 00669 #define LL_RCC_RNG_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< RNG Clock source selection */ 00670 #else 00671 #define LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< RNG Clock source selection */ 00672 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ 00673 /** 00674 * @} 00675 */ 00676 #endif /* RNG */ 00677 00678 #if defined(USB_OTG_FS) || defined(USB_OTG_HS) 00679 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source 00680 * @{ 00681 */ 00682 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) 00683 #define LL_RCC_USB_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< USB Clock source selection */ 00684 #else 00685 #define LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< USB Clock source selection */ 00686 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ 00687 /** 00688 * @} 00689 */ 00690 #endif /* USB_OTG_FS || USB_OTG_HS */ 00691 00692 #if defined(CEC) 00693 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source 00694 * @{ 00695 */ 00696 #define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */ 00697 /** 00698 * @} 00699 */ 00700 #endif /* CEC */ 00701 00702 /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source 00703 * @{ 00704 */ 00705 #if defined(RCC_CFGR_I2SSRC) 00706 #define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S1 Clock source selection */ 00707 #endif /* RCC_CFGR_I2SSRC */ 00708 #if defined(RCC_DCKCFGR_I2SSRC) 00709 #define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2SSRC /*!< I2S1 Clock source selection */ 00710 #endif /* RCC_DCKCFGR_I2SSRC */ 00711 #if defined(RCC_DCKCFGR_I2S1SRC) 00712 #define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2S1SRC /*!< I2S1 Clock source selection */ 00713 #endif /* RCC_DCKCFGR_I2S1SRC */ 00714 #if defined(RCC_DCKCFGR_I2S2SRC) 00715 #define LL_RCC_I2S2_CLKSOURCE RCC_DCKCFGR_I2S2SRC /*!< I2S2 Clock source selection */ 00716 #endif /* RCC_DCKCFGR_I2S2SRC */ 00717 /** 00718 * @} 00719 */ 00720 00721 #if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0) 00722 /** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source 00723 * @{ 00724 */ 00725 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM1ASEL /*!< DFSDM1 Audio Clock source selection */ 00726 #if defined(DFSDM2_Channel0) 00727 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM2ASEL /*!< DFSDM2 Audio Clock source selection */ 00728 #endif /* DFSDM2_Channel0 */ 00729 /** 00730 * @} 00731 */ 00732 00733 /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source 00734 * @{ 00735 */ 00736 #define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM1 Clock source selection */ 00737 #if defined(DFSDM2_Channel0) 00738 #define LL_RCC_DFSDM2_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM2 Clock source selection */ 00739 #endif /* DFSDM2_Channel0 */ 00740 /** 00741 * @} 00742 */ 00743 #endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */ 00744 00745 #if defined(SPDIFRX) 00746 /** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source 00747 * @{ 00748 */ 00749 #define LL_RCC_SPDIFRX1_CLKSOURCE RCC_DCKCFGR2_SPDIFRXSEL /*!< SPDIFRX Clock source selection */ 00750 /** 00751 * @} 00752 */ 00753 #endif /* SPDIFRX */ 00754 00755 #if defined(DSI) 00756 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source 00757 * @{ 00758 */ 00759 #define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR_DSISEL /*!< DSI Clock source selection */ 00760 /** 00761 * @} 00762 */ 00763 #endif /* DSI */ 00764 00765 #if defined(LTDC) 00766 /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source 00767 * @{ 00768 */ 00769 #define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR /*!< LTDC Clock source selection */ 00770 /** 00771 * @} 00772 */ 00773 #endif /* LTDC */ 00774 00775 00776 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection 00777 * @{ 00778 */ 00779 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ 00780 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 00781 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 00782 #define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */ 00783 /** 00784 * @} 00785 */ 00786 00787 #if defined(RCC_DCKCFGR_TIMPRE) 00788 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection 00789 * @{ 00790 */ 00791 #define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */ 00792 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE /*!< Timers clock to four time PCLK */ 00793 /** 00794 * @} 00795 */ 00796 #endif /* RCC_DCKCFGR_TIMPRE */ 00797 00798 /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source 00799 * @{ 00800 */ 00801 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */ 00802 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ 00803 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC) 00804 #define LL_RCC_PLLI2SSOURCE_PIN (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U) /*!< I2S External pin input clock selected as PLLI2S entry clock source */ 00805 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */ 00806 /** 00807 * @} 00808 */ 00809 00810 /** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor 00811 * @{ 00812 */ 00813 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */ 00814 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */ 00815 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */ 00816 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */ 00817 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */ 00818 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */ 00819 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */ 00820 #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */ 00821 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */ 00822 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */ 00823 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */ 00824 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */ 00825 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */ 00826 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */ 00827 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */ 00828 #define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */ 00829 #define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */ 00830 #define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */ 00831 #define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */ 00832 #define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */ 00833 #define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */ 00834 #define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */ 00835 #define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */ 00836 #define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */ 00837 #define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */ 00838 #define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */ 00839 #define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */ 00840 #define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */ 00841 #define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */ 00842 #define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */ 00843 #define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */ 00844 #define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */ 00845 #define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */ 00846 #define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */ 00847 #define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */ 00848 #define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */ 00849 #define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */ 00850 #define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */ 00851 #define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */ 00852 #define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */ 00853 #define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */ 00854 #define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */ 00855 #define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */ 00856 #define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */ 00857 #define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */ 00858 #define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */ 00859 #define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */ 00860 #define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */ 00861 #define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */ 00862 #define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */ 00863 #define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */ 00864 #define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */ 00865 #define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */ 00866 #define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */ 00867 #define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */ 00868 #define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */ 00869 #define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */ 00870 #define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */ 00871 #define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */ 00872 #define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */ 00873 #define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */ 00874 #define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */ 00875 /** 00876 * @} 00877 */ 00878 00879 #if defined(RCC_PLLCFGR_PLLR) 00880 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) 00881 * @{ 00882 */ 00883 #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */ 00884 #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */ 00885 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */ 00886 #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */ 00887 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */ 00888 #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */ 00889 /** 00890 * @} 00891 */ 00892 #endif /* RCC_PLLCFGR_PLLR */ 00893 00894 #if defined(RCC_DCKCFGR_PLLDIVR) 00895 /** @defgroup RCC_LL_EC_PLLDIVR PLLDIVR division factor (PLLDIVR) 00896 * @{ 00897 */ 00898 #define LL_RCC_PLLDIVR_DIV_1 (RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 1 */ 00899 #define LL_RCC_PLLDIVR_DIV_2 (RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 2 */ 00900 #define LL_RCC_PLLDIVR_DIV_3 (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 3 */ 00901 #define LL_RCC_PLLDIVR_DIV_4 (RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 4 */ 00902 #define LL_RCC_PLLDIVR_DIV_5 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 5 */ 00903 #define LL_RCC_PLLDIVR_DIV_6 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 6 */ 00904 #define LL_RCC_PLLDIVR_DIV_7 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 7 */ 00905 #define LL_RCC_PLLDIVR_DIV_8 (RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 8 */ 00906 #define LL_RCC_PLLDIVR_DIV_9 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 9 */ 00907 #define LL_RCC_PLLDIVR_DIV_10 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 10 */ 00908 #define LL_RCC_PLLDIVR_DIV_11 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 11 */ 00909 #define LL_RCC_PLLDIVR_DIV_12 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 12 */ 00910 #define LL_RCC_PLLDIVR_DIV_13 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 13 */ 00911 #define LL_RCC_PLLDIVR_DIV_14 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 14 */ 00912 #define LL_RCC_PLLDIVR_DIV_15 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 15 */ 00913 #define LL_RCC_PLLDIVR_DIV_16 (RCC_DCKCFGR_PLLDIVR_4) /*!< PLL division factor for PLLDIVR output by 16 */ 00914 #define LL_RCC_PLLDIVR_DIV_17 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 17 */ 00915 #define LL_RCC_PLLDIVR_DIV_18 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 18 */ 00916 #define LL_RCC_PLLDIVR_DIV_19 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 19 */ 00917 #define LL_RCC_PLLDIVR_DIV_20 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 20 */ 00918 #define LL_RCC_PLLDIVR_DIV_21 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 21 */ 00919 #define LL_RCC_PLLDIVR_DIV_22 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 22 */ 00920 #define LL_RCC_PLLDIVR_DIV_23 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 23 */ 00921 #define LL_RCC_PLLDIVR_DIV_24 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 24 */ 00922 #define LL_RCC_PLLDIVR_DIV_25 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 25 */ 00923 #define LL_RCC_PLLDIVR_DIV_26 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 26 */ 00924 #define LL_RCC_PLLDIVR_DIV_27 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 27 */ 00925 #define LL_RCC_PLLDIVR_DIV_28 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 28 */ 00926 #define LL_RCC_PLLDIVR_DIV_29 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 29 */ 00927 #define LL_RCC_PLLDIVR_DIV_30 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 30 */ 00928 #define LL_RCC_PLLDIVR_DIV_31 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 31 */ 00929 /** 00930 * @} 00931 */ 00932 #endif /* RCC_DCKCFGR_PLLDIVR */ 00933 00934 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) 00935 * @{ 00936 */ 00937 #define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */ 00938 #define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */ 00939 #define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */ 00940 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */ 00941 /** 00942 * @} 00943 */ 00944 00945 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) 00946 * @{ 00947 */ 00948 #define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */ 00949 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */ 00950 #define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */ 00951 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */ 00952 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */ 00953 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */ 00954 #define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */ 00955 #define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */ 00956 #define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */ 00957 #define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */ 00958 #define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */ 00959 #define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */ 00960 #define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */ 00961 #define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */ 00962 /** 00963 * @} 00964 */ 00965 00966 /** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection 00967 * @{ 00968 */ 00969 #define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */ 00970 #define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */ 00971 /** 00972 * @} 00973 */ 00974 00975 #if defined(RCC_PLLI2S_SUPPORT) 00976 /** @defgroup RCC_LL_EC_PLLI2SM PLLI2SM division factor (PLLI2SM) 00977 * @{ 00978 */ 00979 #if defined(RCC_PLLI2SCFGR_PLLI2SM) 00980 #define LL_RCC_PLLI2SM_DIV_2 (RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 2 */ 00981 #define LL_RCC_PLLI2SM_DIV_3 (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 3 */ 00982 #define LL_RCC_PLLI2SM_DIV_4 (RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 4 */ 00983 #define LL_RCC_PLLI2SM_DIV_5 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 5 */ 00984 #define LL_RCC_PLLI2SM_DIV_6 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 6 */ 00985 #define LL_RCC_PLLI2SM_DIV_7 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 7 */ 00986 #define LL_RCC_PLLI2SM_DIV_8 (RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 8 */ 00987 #define LL_RCC_PLLI2SM_DIV_9 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 9 */ 00988 #define LL_RCC_PLLI2SM_DIV_10 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 10 */ 00989 #define LL_RCC_PLLI2SM_DIV_11 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 11 */ 00990 #define LL_RCC_PLLI2SM_DIV_12 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 12 */ 00991 #define LL_RCC_PLLI2SM_DIV_13 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 13 */ 00992 #define LL_RCC_PLLI2SM_DIV_14 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 14 */ 00993 #define LL_RCC_PLLI2SM_DIV_15 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 15 */ 00994 #define LL_RCC_PLLI2SM_DIV_16 (RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 16 */ 00995 #define LL_RCC_PLLI2SM_DIV_17 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 17 */ 00996 #define LL_RCC_PLLI2SM_DIV_18 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 18 */ 00997 #define LL_RCC_PLLI2SM_DIV_19 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 19 */ 00998 #define LL_RCC_PLLI2SM_DIV_20 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 20 */ 00999 #define LL_RCC_PLLI2SM_DIV_21 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 21 */ 01000 #define LL_RCC_PLLI2SM_DIV_22 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 22 */ 01001 #define LL_RCC_PLLI2SM_DIV_23 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 23 */ 01002 #define LL_RCC_PLLI2SM_DIV_24 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 24 */ 01003 #define LL_RCC_PLLI2SM_DIV_25 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 25 */ 01004 #define LL_RCC_PLLI2SM_DIV_26 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 26 */ 01005 #define LL_RCC_PLLI2SM_DIV_27 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 27 */ 01006 #define LL_RCC_PLLI2SM_DIV_28 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 28 */ 01007 #define LL_RCC_PLLI2SM_DIV_29 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 29 */ 01008 #define LL_RCC_PLLI2SM_DIV_30 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 30 */ 01009 #define LL_RCC_PLLI2SM_DIV_31 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 31 */ 01010 #define LL_RCC_PLLI2SM_DIV_32 (RCC_PLLI2SCFGR_PLLI2SM_5) /*!< PLLI2S division factor for PLLI2SM output by 32 */ 01011 #define LL_RCC_PLLI2SM_DIV_33 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 33 */ 01012 #define LL_RCC_PLLI2SM_DIV_34 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 34 */ 01013 #define LL_RCC_PLLI2SM_DIV_35 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 35 */ 01014 #define LL_RCC_PLLI2SM_DIV_36 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 36 */ 01015 #define LL_RCC_PLLI2SM_DIV_37 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 37 */ 01016 #define LL_RCC_PLLI2SM_DIV_38 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 38 */ 01017 #define LL_RCC_PLLI2SM_DIV_39 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 39 */ 01018 #define LL_RCC_PLLI2SM_DIV_40 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 40 */ 01019 #define LL_RCC_PLLI2SM_DIV_41 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 41 */ 01020 #define LL_RCC_PLLI2SM_DIV_42 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 42 */ 01021 #define LL_RCC_PLLI2SM_DIV_43 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 43 */ 01022 #define LL_RCC_PLLI2SM_DIV_44 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 44 */ 01023 #define LL_RCC_PLLI2SM_DIV_45 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 45 */ 01024 #define LL_RCC_PLLI2SM_DIV_46 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 46 */ 01025 #define LL_RCC_PLLI2SM_DIV_47 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 47 */ 01026 #define LL_RCC_PLLI2SM_DIV_48 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 48 */ 01027 #define LL_RCC_PLLI2SM_DIV_49 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 49 */ 01028 #define LL_RCC_PLLI2SM_DIV_50 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 50 */ 01029 #define LL_RCC_PLLI2SM_DIV_51 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 51 */ 01030 #define LL_RCC_PLLI2SM_DIV_52 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 52 */ 01031 #define LL_RCC_PLLI2SM_DIV_53 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 53 */ 01032 #define LL_RCC_PLLI2SM_DIV_54 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 54 */ 01033 #define LL_RCC_PLLI2SM_DIV_55 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 55 */ 01034 #define LL_RCC_PLLI2SM_DIV_56 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 56 */ 01035 #define LL_RCC_PLLI2SM_DIV_57 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 57 */ 01036 #define LL_RCC_PLLI2SM_DIV_58 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 58 */ 01037 #define LL_RCC_PLLI2SM_DIV_59 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 59 */ 01038 #define LL_RCC_PLLI2SM_DIV_60 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 60 */ 01039 #define LL_RCC_PLLI2SM_DIV_61 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 61 */ 01040 #define LL_RCC_PLLI2SM_DIV_62 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 62 */ 01041 #define LL_RCC_PLLI2SM_DIV_63 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 63 */ 01042 #else 01043 #define LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLI2S division factor for PLLI2SM output by 2 */ 01044 #define LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLI2S division factor for PLLI2SM output by 3 */ 01045 #define LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLI2S division factor for PLLI2SM output by 4 */ 01046 #define LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLI2S division factor for PLLI2SM output by 5 */ 01047 #define LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLI2S division factor for PLLI2SM output by 6 */ 01048 #define LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLI2S division factor for PLLI2SM output by 7 */ 01049 #define LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLI2S division factor for PLLI2SM output by 8 */ 01050 #define LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLI2S division factor for PLLI2SM output by 9 */ 01051 #define LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLI2S division factor for PLLI2SM output by 10 */ 01052 #define LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLI2S division factor for PLLI2SM output by 11 */ 01053 #define LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLI2S division factor for PLLI2SM output by 12 */ 01054 #define LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLI2S division factor for PLLI2SM output by 13 */ 01055 #define LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLI2S division factor for PLLI2SM output by 14 */ 01056 #define LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLI2S division factor for PLLI2SM output by 15 */ 01057 #define LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLI2S division factor for PLLI2SM output by 16 */ 01058 #define LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLI2S division factor for PLLI2SM output by 17 */ 01059 #define LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLI2S division factor for PLLI2SM output by 18 */ 01060 #define LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLI2S division factor for PLLI2SM output by 19 */ 01061 #define LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLI2S division factor for PLLI2SM output by 20 */ 01062 #define LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLI2S division factor for PLLI2SM output by 21 */ 01063 #define LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLI2S division factor for PLLI2SM output by 22 */ 01064 #define LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLI2S division factor for PLLI2SM output by 23 */ 01065 #define LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLI2S division factor for PLLI2SM output by 24 */ 01066 #define LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLI2S division factor for PLLI2SM output by 25 */ 01067 #define LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLI2S division factor for PLLI2SM output by 26 */ 01068 #define LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLI2S division factor for PLLI2SM output by 27 */ 01069 #define LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLI2S division factor for PLLI2SM output by 28 */ 01070 #define LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLI2S division factor for PLLI2SM output by 29 */ 01071 #define LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLI2S division factor for PLLI2SM output by 30 */ 01072 #define LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLI2S division factor for PLLI2SM output by 31 */ 01073 #define LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLI2S division factor for PLLI2SM output by 32 */ 01074 #define LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLI2S division factor for PLLI2SM output by 33 */ 01075 #define LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLI2S division factor for PLLI2SM output by 34 */ 01076 #define LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLI2S division factor for PLLI2SM output by 35 */ 01077 #define LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLI2S division factor for PLLI2SM output by 36 */ 01078 #define LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLI2S division factor for PLLI2SM output by 37 */ 01079 #define LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLI2S division factor for PLLI2SM output by 38 */ 01080 #define LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLI2S division factor for PLLI2SM output by 39 */ 01081 #define LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLI2S division factor for PLLI2SM output by 40 */ 01082 #define LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLI2S division factor for PLLI2SM output by 41 */ 01083 #define LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLI2S division factor for PLLI2SM output by 42 */ 01084 #define LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLI2S division factor for PLLI2SM output by 43 */ 01085 #define LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLI2S division factor for PLLI2SM output by 44 */ 01086 #define LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLI2S division factor for PLLI2SM output by 45 */ 01087 #define LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLI2S division factor for PLLI2SM output by 46 */ 01088 #define LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLI2S division factor for PLLI2SM output by 47 */ 01089 #define LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLI2S division factor for PLLI2SM output by 48 */ 01090 #define LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLI2S division factor for PLLI2SM output by 49 */ 01091 #define LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLI2S division factor for PLLI2SM output by 50 */ 01092 #define LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLI2S division factor for PLLI2SM output by 51 */ 01093 #define LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLI2S division factor for PLLI2SM output by 52 */ 01094 #define LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLI2S division factor for PLLI2SM output by 53 */ 01095 #define LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLI2S division factor for PLLI2SM output by 54 */ 01096 #define LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLI2S division factor for PLLI2SM output by 55 */ 01097 #define LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLI2S division factor for PLLI2SM output by 56 */ 01098 #define LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLI2S division factor for PLLI2SM output by 57 */ 01099 #define LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLI2S division factor for PLLI2SM output by 58 */ 01100 #define LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLI2S division factor for PLLI2SM output by 59 */ 01101 #define LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLI2S division factor for PLLI2SM output by 60 */ 01102 #define LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLI2S division factor for PLLI2SM output by 61 */ 01103 #define LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLI2S division factor for PLLI2SM output by 62 */ 01104 #define LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLI2S division factor for PLLI2SM output by 63 */ 01105 #endif /* RCC_PLLI2SCFGR_PLLI2SM */ 01106 /** 01107 * @} 01108 */ 01109 01110 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) 01111 /** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ) 01112 * @{ 01113 */ 01114 #define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */ 01115 #define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */ 01116 #define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */ 01117 #define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */ 01118 #define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */ 01119 #define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */ 01120 #define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */ 01121 #define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */ 01122 #define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */ 01123 #define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */ 01124 #define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */ 01125 #define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */ 01126 #define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */ 01127 #define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */ 01128 /** 01129 * @} 01130 */ 01131 #endif /* RCC_PLLI2SCFGR_PLLI2SQ */ 01132 01133 #if defined(RCC_DCKCFGR_PLLI2SDIVQ) 01134 /** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ) 01135 * @{ 01136 */ 01137 #define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */ 01138 #define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */ 01139 #define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */ 01140 #define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */ 01141 #define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */ 01142 #define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */ 01143 #define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */ 01144 #define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */ 01145 #define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */ 01146 #define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */ 01147 #define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */ 01148 #define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */ 01149 #define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */ 01150 #define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */ 01151 #define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */ 01152 #define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */ 01153 #define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */ 01154 #define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */ 01155 #define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */ 01156 #define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */ 01157 #define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */ 01158 #define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */ 01159 #define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */ 01160 #define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */ 01161 #define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */ 01162 #define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */ 01163 #define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */ 01164 #define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */ 01165 #define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */ 01166 #define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */ 01167 #define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */ 01168 #define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */ 01169 /** 01170 * @} 01171 */ 01172 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */ 01173 01174 #if defined(RCC_DCKCFGR_PLLI2SDIVR) 01175 /** @defgroup RCC_LL_EC_PLLI2SDIVR PLLI2SDIVR division factor (PLLI2SDIVR) 01176 * @{ 01177 */ 01178 #define LL_RCC_PLLI2SDIVR_DIV_1 (RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 1 */ 01179 #define LL_RCC_PLLI2SDIVR_DIV_2 (RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 2 */ 01180 #define LL_RCC_PLLI2SDIVR_DIV_3 (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 3 */ 01181 #define LL_RCC_PLLI2SDIVR_DIV_4 (RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 4 */ 01182 #define LL_RCC_PLLI2SDIVR_DIV_5 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 5 */ 01183 #define LL_RCC_PLLI2SDIVR_DIV_6 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 6 */ 01184 #define LL_RCC_PLLI2SDIVR_DIV_7 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 7 */ 01185 #define LL_RCC_PLLI2SDIVR_DIV_8 (RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 8 */ 01186 #define LL_RCC_PLLI2SDIVR_DIV_9 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 9 */ 01187 #define LL_RCC_PLLI2SDIVR_DIV_10 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 10 */ 01188 #define LL_RCC_PLLI2SDIVR_DIV_11 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 11 */ 01189 #define LL_RCC_PLLI2SDIVR_DIV_12 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 12 */ 01190 #define LL_RCC_PLLI2SDIVR_DIV_13 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 13 */ 01191 #define LL_RCC_PLLI2SDIVR_DIV_14 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 14 */ 01192 #define LL_RCC_PLLI2SDIVR_DIV_15 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 15 */ 01193 #define LL_RCC_PLLI2SDIVR_DIV_16 (RCC_DCKCFGR_PLLI2SDIVR_4) /*!< PLLI2S division factor for PLLI2SDIVR output by 16 */ 01194 #define LL_RCC_PLLI2SDIVR_DIV_17 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 17 */ 01195 #define LL_RCC_PLLI2SDIVR_DIV_18 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 18 */ 01196 #define LL_RCC_PLLI2SDIVR_DIV_19 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 19 */ 01197 #define LL_RCC_PLLI2SDIVR_DIV_20 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 20 */ 01198 #define LL_RCC_PLLI2SDIVR_DIV_21 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 21 */ 01199 #define LL_RCC_PLLI2SDIVR_DIV_22 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 22 */ 01200 #define LL_RCC_PLLI2SDIVR_DIV_23 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 23 */ 01201 #define LL_RCC_PLLI2SDIVR_DIV_24 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 24 */ 01202 #define LL_RCC_PLLI2SDIVR_DIV_25 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 25 */ 01203 #define LL_RCC_PLLI2SDIVR_DIV_26 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 26 */ 01204 #define LL_RCC_PLLI2SDIVR_DIV_27 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 27 */ 01205 #define LL_RCC_PLLI2SDIVR_DIV_28 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 28 */ 01206 #define LL_RCC_PLLI2SDIVR_DIV_29 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 29 */ 01207 #define LL_RCC_PLLI2SDIVR_DIV_30 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 30 */ 01208 #define LL_RCC_PLLI2SDIVR_DIV_31 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 31 */ 01209 /** 01210 * @} 01211 */ 01212 #endif /* RCC_DCKCFGR_PLLI2SDIVR */ 01213 01214 /** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR) 01215 * @{ 01216 */ 01217 #define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */ 01218 #define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */ 01219 #define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */ 01220 #define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */ 01221 #define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */ 01222 #define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */ 01223 /** 01224 * @} 01225 */ 01226 01227 #if defined(RCC_PLLI2SCFGR_PLLI2SP) 01228 /** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP) 01229 * @{ 01230 */ 01231 #define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */ 01232 #define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */ 01233 #define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */ 01234 #define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */ 01235 /** 01236 * @} 01237 */ 01238 #endif /* RCC_PLLI2SCFGR_PLLI2SP */ 01239 #endif /* RCC_PLLI2S_SUPPORT */ 01240 01241 #if defined(RCC_PLLSAI_SUPPORT) 01242 /** @defgroup RCC_LL_EC_PLLSAIM PLLSAIM division factor (PLLSAIM or PLLM) 01243 * @{ 01244 */ 01245 #if defined(RCC_PLLSAICFGR_PLLSAIM) 01246 #define LL_RCC_PLLSAIM_DIV_2 (RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 2 */ 01247 #define LL_RCC_PLLSAIM_DIV_3 (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 3 */ 01248 #define LL_RCC_PLLSAIM_DIV_4 (RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 4 */ 01249 #define LL_RCC_PLLSAIM_DIV_5 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 5 */ 01250 #define LL_RCC_PLLSAIM_DIV_6 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 6 */ 01251 #define LL_RCC_PLLSAIM_DIV_7 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 7 */ 01252 #define LL_RCC_PLLSAIM_DIV_8 (RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 8 */ 01253 #define LL_RCC_PLLSAIM_DIV_9 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 9 */ 01254 #define LL_RCC_PLLSAIM_DIV_10 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 10 */ 01255 #define LL_RCC_PLLSAIM_DIV_11 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 11 */ 01256 #define LL_RCC_PLLSAIM_DIV_12 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 12 */ 01257 #define LL_RCC_PLLSAIM_DIV_13 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 13 */ 01258 #define LL_RCC_PLLSAIM_DIV_14 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 14 */ 01259 #define LL_RCC_PLLSAIM_DIV_15 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 15 */ 01260 #define LL_RCC_PLLSAIM_DIV_16 (RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 16 */ 01261 #define LL_RCC_PLLSAIM_DIV_17 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 17 */ 01262 #define LL_RCC_PLLSAIM_DIV_18 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 18 */ 01263 #define LL_RCC_PLLSAIM_DIV_19 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 19 */ 01264 #define LL_RCC_PLLSAIM_DIV_20 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 20 */ 01265 #define LL_RCC_PLLSAIM_DIV_21 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 21 */ 01266 #define LL_RCC_PLLSAIM_DIV_22 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 22 */ 01267 #define LL_RCC_PLLSAIM_DIV_23 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 23 */ 01268 #define LL_RCC_PLLSAIM_DIV_24 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 24 */ 01269 #define LL_RCC_PLLSAIM_DIV_25 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 25 */ 01270 #define LL_RCC_PLLSAIM_DIV_26 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 26 */ 01271 #define LL_RCC_PLLSAIM_DIV_27 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 27 */ 01272 #define LL_RCC_PLLSAIM_DIV_28 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 28 */ 01273 #define LL_RCC_PLLSAIM_DIV_29 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 29 */ 01274 #define LL_RCC_PLLSAIM_DIV_30 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 30 */ 01275 #define LL_RCC_PLLSAIM_DIV_31 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 31 */ 01276 #define LL_RCC_PLLSAIM_DIV_32 (RCC_PLLSAICFGR_PLLSAIM_5) /*!< PLLSAI division factor for PLLSAIM output by 32 */ 01277 #define LL_RCC_PLLSAIM_DIV_33 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 33 */ 01278 #define LL_RCC_PLLSAIM_DIV_34 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 34 */ 01279 #define LL_RCC_PLLSAIM_DIV_35 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 35 */ 01280 #define LL_RCC_PLLSAIM_DIV_36 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 36 */ 01281 #define LL_RCC_PLLSAIM_DIV_37 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 37 */ 01282 #define LL_RCC_PLLSAIM_DIV_38 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 38 */ 01283 #define LL_RCC_PLLSAIM_DIV_39 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 39 */ 01284 #define LL_RCC_PLLSAIM_DIV_40 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 40 */ 01285 #define LL_RCC_PLLSAIM_DIV_41 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 41 */ 01286 #define LL_RCC_PLLSAIM_DIV_42 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 42 */ 01287 #define LL_RCC_PLLSAIM_DIV_43 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 43 */ 01288 #define LL_RCC_PLLSAIM_DIV_44 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 44 */ 01289 #define LL_RCC_PLLSAIM_DIV_45 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 45 */ 01290 #define LL_RCC_PLLSAIM_DIV_46 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 46 */ 01291 #define LL_RCC_PLLSAIM_DIV_47 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 47 */ 01292 #define LL_RCC_PLLSAIM_DIV_48 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 48 */ 01293 #define LL_RCC_PLLSAIM_DIV_49 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 49 */ 01294 #define LL_RCC_PLLSAIM_DIV_50 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 50 */ 01295 #define LL_RCC_PLLSAIM_DIV_51 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 51 */ 01296 #define LL_RCC_PLLSAIM_DIV_52 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 52 */ 01297 #define LL_RCC_PLLSAIM_DIV_53 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 53 */ 01298 #define LL_RCC_PLLSAIM_DIV_54 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 54 */ 01299 #define LL_RCC_PLLSAIM_DIV_55 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 55 */ 01300 #define LL_RCC_PLLSAIM_DIV_56 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 56 */ 01301 #define LL_RCC_PLLSAIM_DIV_57 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 57 */ 01302 #define LL_RCC_PLLSAIM_DIV_58 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 58 */ 01303 #define LL_RCC_PLLSAIM_DIV_59 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 59 */ 01304 #define LL_RCC_PLLSAIM_DIV_60 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 60 */ 01305 #define LL_RCC_PLLSAIM_DIV_61 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 61 */ 01306 #define LL_RCC_PLLSAIM_DIV_62 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 62 */ 01307 #define LL_RCC_PLLSAIM_DIV_63 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 63 */ 01308 #else 01309 #define LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLSAI division factor for PLLSAIM output by 2 */ 01310 #define LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLSAI division factor for PLLSAIM output by 3 */ 01311 #define LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLSAI division factor for PLLSAIM output by 4 */ 01312 #define LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLSAI division factor for PLLSAIM output by 5 */ 01313 #define LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLSAI division factor for PLLSAIM output by 6 */ 01314 #define LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLSAI division factor for PLLSAIM output by 7 */ 01315 #define LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLSAI division factor for PLLSAIM output by 8 */ 01316 #define LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLSAI division factor for PLLSAIM output by 9 */ 01317 #define LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLSAI division factor for PLLSAIM output by 10 */ 01318 #define LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLSAI division factor for PLLSAIM output by 11 */ 01319 #define LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLSAI division factor for PLLSAIM output by 12 */ 01320 #define LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLSAI division factor for PLLSAIM output by 13 */ 01321 #define LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLSAI division factor for PLLSAIM output by 14 */ 01322 #define LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLSAI division factor for PLLSAIM output by 15 */ 01323 #define LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLSAI division factor for PLLSAIM output by 16 */ 01324 #define LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLSAI division factor for PLLSAIM output by 17 */ 01325 #define LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLSAI division factor for PLLSAIM output by 18 */ 01326 #define LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLSAI division factor for PLLSAIM output by 19 */ 01327 #define LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLSAI division factor for PLLSAIM output by 20 */ 01328 #define LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLSAI division factor for PLLSAIM output by 21 */ 01329 #define LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLSAI division factor for PLLSAIM output by 22 */ 01330 #define LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLSAI division factor for PLLSAIM output by 23 */ 01331 #define LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLSAI division factor for PLLSAIM output by 24 */ 01332 #define LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLSAI division factor for PLLSAIM output by 25 */ 01333 #define LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLSAI division factor for PLLSAIM output by 26 */ 01334 #define LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLSAI division factor for PLLSAIM output by 27 */ 01335 #define LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLSAI division factor for PLLSAIM output by 28 */ 01336 #define LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLSAI division factor for PLLSAIM output by 29 */ 01337 #define LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLSAI division factor for PLLSAIM output by 30 */ 01338 #define LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLSAI division factor for PLLSAIM output by 31 */ 01339 #define LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLSAI division factor for PLLSAIM output by 32 */ 01340 #define LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLSAI division factor for PLLSAIM output by 33 */ 01341 #define LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLSAI division factor for PLLSAIM output by 34 */ 01342 #define LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLSAI division factor for PLLSAIM output by 35 */ 01343 #define LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLSAI division factor for PLLSAIM output by 36 */ 01344 #define LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLSAI division factor for PLLSAIM output by 37 */ 01345 #define LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLSAI division factor for PLLSAIM output by 38 */ 01346 #define LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLSAI division factor for PLLSAIM output by 39 */ 01347 #define LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLSAI division factor for PLLSAIM output by 40 */ 01348 #define LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLSAI division factor for PLLSAIM output by 41 */ 01349 #define LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLSAI division factor for PLLSAIM output by 42 */ 01350 #define LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLSAI division factor for PLLSAIM output by 43 */ 01351 #define LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLSAI division factor for PLLSAIM output by 44 */ 01352 #define LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLSAI division factor for PLLSAIM output by 45 */ 01353 #define LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLSAI division factor for PLLSAIM output by 46 */ 01354 #define LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLSAI division factor for PLLSAIM output by 47 */ 01355 #define LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLSAI division factor for PLLSAIM output by 48 */ 01356 #define LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLSAI division factor for PLLSAIM output by 49 */ 01357 #define LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLSAI division factor for PLLSAIM output by 50 */ 01358 #define LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLSAI division factor for PLLSAIM output by 51 */ 01359 #define LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLSAI division factor for PLLSAIM output by 52 */ 01360 #define LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLSAI division factor for PLLSAIM output by 53 */ 01361 #define LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLSAI division factor for PLLSAIM output by 54 */ 01362 #define LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLSAI division factor for PLLSAIM output by 55 */ 01363 #define LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLSAI division factor for PLLSAIM output by 56 */ 01364 #define LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLSAI division factor for PLLSAIM output by 57 */ 01365 #define LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLSAI division factor for PLLSAIM output by 58 */ 01366 #define LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLSAI division factor for PLLSAIM output by 59 */ 01367 #define LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLSAI division factor for PLLSAIM output by 60 */ 01368 #define LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLSAI division factor for PLLSAIM output by 61 */ 01369 #define LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLSAI division factor for PLLSAIM output by 62 */ 01370 #define LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLSAI division factor for PLLSAIM output by 63 */ 01371 #endif /* RCC_PLLSAICFGR_PLLSAIM */ 01372 /** 01373 * @} 01374 */ 01375 01376 /** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ) 01377 * @{ 01378 */ 01379 #define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */ 01380 #define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */ 01381 #define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */ 01382 #define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */ 01383 #define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */ 01384 #define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */ 01385 #define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */ 01386 #define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */ 01387 #define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */ 01388 #define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */ 01389 #define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */ 01390 #define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */ 01391 #define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */ 01392 #define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */ 01393 /** 01394 * @} 01395 */ 01396 01397 #if defined(RCC_DCKCFGR_PLLSAIDIVQ) 01398 /** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ) 01399 * @{ 01400 */ 01401 #define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */ 01402 #define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */ 01403 #define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */ 01404 #define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */ 01405 #define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */ 01406 #define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */ 01407 #define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */ 01408 #define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */ 01409 #define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */ 01410 #define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */ 01411 #define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */ 01412 #define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */ 01413 #define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */ 01414 #define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */ 01415 #define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */ 01416 #define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */ 01417 #define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */ 01418 #define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */ 01419 #define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */ 01420 #define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */ 01421 #define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */ 01422 #define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */ 01423 #define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */ 01424 #define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */ 01425 #define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */ 01426 #define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */ 01427 #define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */ 01428 #define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */ 01429 #define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */ 01430 #define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */ 01431 #define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */ 01432 #define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */ 01433 /** 01434 * @} 01435 */ 01436 #endif /* RCC_DCKCFGR_PLLSAIDIVQ */ 01437 01438 #if defined(RCC_PLLSAICFGR_PLLSAIR) 01439 /** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR) 01440 * @{ 01441 */ 01442 #define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */ 01443 #define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */ 01444 #define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */ 01445 #define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */ 01446 #define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */ 01447 #define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */ 01448 /** 01449 * @} 01450 */ 01451 #endif /* RCC_PLLSAICFGR_PLLSAIR */ 01452 01453 #if defined(RCC_DCKCFGR_PLLSAIDIVR) 01454 /** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR) 01455 * @{ 01456 */ 01457 #define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */ 01458 #define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */ 01459 #define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */ 01460 #define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */ 01461 /** 01462 * @} 01463 */ 01464 #endif /* RCC_DCKCFGR_PLLSAIDIVR */ 01465 01466 #if defined(RCC_PLLSAICFGR_PLLSAIP) 01467 /** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP) 01468 * @{ 01469 */ 01470 #define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */ 01471 #define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */ 01472 #define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */ 01473 #define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */ 01474 /** 01475 * @} 01476 */ 01477 #endif /* RCC_PLLSAICFGR_PLLSAIP */ 01478 #endif /* RCC_PLLSAI_SUPPORT */ 01479 /** 01480 * @} 01481 */ 01482 01483 /* Exported macro ------------------------------------------------------------*/ 01484 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros 01485 * @{ 01486 */ 01487 01488 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros 01489 * @{ 01490 */ 01491 01492 /** 01493 * @brief Write a value in RCC register 01494 * @param __REG__ Register to be written 01495 * @param __VALUE__ Value to be written in the register 01496 * @retval None 01497 */ 01498 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) 01499 01500 /** 01501 * @brief Read a value in RCC register 01502 * @param __REG__ Register to be read 01503 * @retval Register value 01504 */ 01505 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) 01506 /** 01507 * @} 01508 */ 01509 01510 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies 01511 * @{ 01512 */ 01513 01514 /** 01515 * @brief Helper macro to calculate the PLLCLK frequency on system domain 01516 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01517 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); 01518 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 01519 * @param __PLLM__ This parameter can be one of the following values: 01520 * @arg @ref LL_RCC_PLLM_DIV_2 01521 * @arg @ref LL_RCC_PLLM_DIV_3 01522 * @arg @ref LL_RCC_PLLM_DIV_4 01523 * @arg @ref LL_RCC_PLLM_DIV_5 01524 * @arg @ref LL_RCC_PLLM_DIV_6 01525 * @arg @ref LL_RCC_PLLM_DIV_7 01526 * @arg @ref LL_RCC_PLLM_DIV_8 01527 * @arg @ref LL_RCC_PLLM_DIV_9 01528 * @arg @ref LL_RCC_PLLM_DIV_10 01529 * @arg @ref LL_RCC_PLLM_DIV_11 01530 * @arg @ref LL_RCC_PLLM_DIV_12 01531 * @arg @ref LL_RCC_PLLM_DIV_13 01532 * @arg @ref LL_RCC_PLLM_DIV_14 01533 * @arg @ref LL_RCC_PLLM_DIV_15 01534 * @arg @ref LL_RCC_PLLM_DIV_16 01535 * @arg @ref LL_RCC_PLLM_DIV_17 01536 * @arg @ref LL_RCC_PLLM_DIV_18 01537 * @arg @ref LL_RCC_PLLM_DIV_19 01538 * @arg @ref LL_RCC_PLLM_DIV_20 01539 * @arg @ref LL_RCC_PLLM_DIV_21 01540 * @arg @ref LL_RCC_PLLM_DIV_22 01541 * @arg @ref LL_RCC_PLLM_DIV_23 01542 * @arg @ref LL_RCC_PLLM_DIV_24 01543 * @arg @ref LL_RCC_PLLM_DIV_25 01544 * @arg @ref LL_RCC_PLLM_DIV_26 01545 * @arg @ref LL_RCC_PLLM_DIV_27 01546 * @arg @ref LL_RCC_PLLM_DIV_28 01547 * @arg @ref LL_RCC_PLLM_DIV_29 01548 * @arg @ref LL_RCC_PLLM_DIV_30 01549 * @arg @ref LL_RCC_PLLM_DIV_31 01550 * @arg @ref LL_RCC_PLLM_DIV_32 01551 * @arg @ref LL_RCC_PLLM_DIV_33 01552 * @arg @ref LL_RCC_PLLM_DIV_34 01553 * @arg @ref LL_RCC_PLLM_DIV_35 01554 * @arg @ref LL_RCC_PLLM_DIV_36 01555 * @arg @ref LL_RCC_PLLM_DIV_37 01556 * @arg @ref LL_RCC_PLLM_DIV_38 01557 * @arg @ref LL_RCC_PLLM_DIV_39 01558 * @arg @ref LL_RCC_PLLM_DIV_40 01559 * @arg @ref LL_RCC_PLLM_DIV_41 01560 * @arg @ref LL_RCC_PLLM_DIV_42 01561 * @arg @ref LL_RCC_PLLM_DIV_43 01562 * @arg @ref LL_RCC_PLLM_DIV_44 01563 * @arg @ref LL_RCC_PLLM_DIV_45 01564 * @arg @ref LL_RCC_PLLM_DIV_46 01565 * @arg @ref LL_RCC_PLLM_DIV_47 01566 * @arg @ref LL_RCC_PLLM_DIV_48 01567 * @arg @ref LL_RCC_PLLM_DIV_49 01568 * @arg @ref LL_RCC_PLLM_DIV_50 01569 * @arg @ref LL_RCC_PLLM_DIV_51 01570 * @arg @ref LL_RCC_PLLM_DIV_52 01571 * @arg @ref LL_RCC_PLLM_DIV_53 01572 * @arg @ref LL_RCC_PLLM_DIV_54 01573 * @arg @ref LL_RCC_PLLM_DIV_55 01574 * @arg @ref LL_RCC_PLLM_DIV_56 01575 * @arg @ref LL_RCC_PLLM_DIV_57 01576 * @arg @ref LL_RCC_PLLM_DIV_58 01577 * @arg @ref LL_RCC_PLLM_DIV_59 01578 * @arg @ref LL_RCC_PLLM_DIV_60 01579 * @arg @ref LL_RCC_PLLM_DIV_61 01580 * @arg @ref LL_RCC_PLLM_DIV_62 01581 * @arg @ref LL_RCC_PLLM_DIV_63 01582 * @param __PLLN__ Between 50/192(*) and 432 01583 * 01584 * (*) value not defined in all devices. 01585 * @param __PLLP__ This parameter can be one of the following values: 01586 * @arg @ref LL_RCC_PLLP_DIV_2 01587 * @arg @ref LL_RCC_PLLP_DIV_4 01588 * @arg @ref LL_RCC_PLLP_DIV_6 01589 * @arg @ref LL_RCC_PLLP_DIV_8 01590 * @retval PLL clock frequency (in Hz) 01591 */ 01592 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ 01593 ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U)) 01594 01595 #if defined(RCC_PLLR_SYSCLK_SUPPORT) 01596 /** 01597 * @brief Helper macro to calculate the PLLRCLK frequency on system domain 01598 * @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01599 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); 01600 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 01601 * @param __PLLM__ This parameter can be one of the following values: 01602 * @arg @ref LL_RCC_PLLM_DIV_2 01603 * @arg @ref LL_RCC_PLLM_DIV_3 01604 * @arg @ref LL_RCC_PLLM_DIV_4 01605 * @arg @ref LL_RCC_PLLM_DIV_5 01606 * @arg @ref LL_RCC_PLLM_DIV_6 01607 * @arg @ref LL_RCC_PLLM_DIV_7 01608 * @arg @ref LL_RCC_PLLM_DIV_8 01609 * @arg @ref LL_RCC_PLLM_DIV_9 01610 * @arg @ref LL_RCC_PLLM_DIV_10 01611 * @arg @ref LL_RCC_PLLM_DIV_11 01612 * @arg @ref LL_RCC_PLLM_DIV_12 01613 * @arg @ref LL_RCC_PLLM_DIV_13 01614 * @arg @ref LL_RCC_PLLM_DIV_14 01615 * @arg @ref LL_RCC_PLLM_DIV_15 01616 * @arg @ref LL_RCC_PLLM_DIV_16 01617 * @arg @ref LL_RCC_PLLM_DIV_17 01618 * @arg @ref LL_RCC_PLLM_DIV_18 01619 * @arg @ref LL_RCC_PLLM_DIV_19 01620 * @arg @ref LL_RCC_PLLM_DIV_20 01621 * @arg @ref LL_RCC_PLLM_DIV_21 01622 * @arg @ref LL_RCC_PLLM_DIV_22 01623 * @arg @ref LL_RCC_PLLM_DIV_23 01624 * @arg @ref LL_RCC_PLLM_DIV_24 01625 * @arg @ref LL_RCC_PLLM_DIV_25 01626 * @arg @ref LL_RCC_PLLM_DIV_26 01627 * @arg @ref LL_RCC_PLLM_DIV_27 01628 * @arg @ref LL_RCC_PLLM_DIV_28 01629 * @arg @ref LL_RCC_PLLM_DIV_29 01630 * @arg @ref LL_RCC_PLLM_DIV_30 01631 * @arg @ref LL_RCC_PLLM_DIV_31 01632 * @arg @ref LL_RCC_PLLM_DIV_32 01633 * @arg @ref LL_RCC_PLLM_DIV_33 01634 * @arg @ref LL_RCC_PLLM_DIV_34 01635 * @arg @ref LL_RCC_PLLM_DIV_35 01636 * @arg @ref LL_RCC_PLLM_DIV_36 01637 * @arg @ref LL_RCC_PLLM_DIV_37 01638 * @arg @ref LL_RCC_PLLM_DIV_38 01639 * @arg @ref LL_RCC_PLLM_DIV_39 01640 * @arg @ref LL_RCC_PLLM_DIV_40 01641 * @arg @ref LL_RCC_PLLM_DIV_41 01642 * @arg @ref LL_RCC_PLLM_DIV_42 01643 * @arg @ref LL_RCC_PLLM_DIV_43 01644 * @arg @ref LL_RCC_PLLM_DIV_44 01645 * @arg @ref LL_RCC_PLLM_DIV_45 01646 * @arg @ref LL_RCC_PLLM_DIV_46 01647 * @arg @ref LL_RCC_PLLM_DIV_47 01648 * @arg @ref LL_RCC_PLLM_DIV_48 01649 * @arg @ref LL_RCC_PLLM_DIV_49 01650 * @arg @ref LL_RCC_PLLM_DIV_50 01651 * @arg @ref LL_RCC_PLLM_DIV_51 01652 * @arg @ref LL_RCC_PLLM_DIV_52 01653 * @arg @ref LL_RCC_PLLM_DIV_53 01654 * @arg @ref LL_RCC_PLLM_DIV_54 01655 * @arg @ref LL_RCC_PLLM_DIV_55 01656 * @arg @ref LL_RCC_PLLM_DIV_56 01657 * @arg @ref LL_RCC_PLLM_DIV_57 01658 * @arg @ref LL_RCC_PLLM_DIV_58 01659 * @arg @ref LL_RCC_PLLM_DIV_59 01660 * @arg @ref LL_RCC_PLLM_DIV_60 01661 * @arg @ref LL_RCC_PLLM_DIV_61 01662 * @arg @ref LL_RCC_PLLM_DIV_62 01663 * @arg @ref LL_RCC_PLLM_DIV_63 01664 * @param __PLLN__ Between 50 and 432 01665 * @param __PLLR__ This parameter can be one of the following values: 01666 * @arg @ref LL_RCC_PLLR_DIV_2 01667 * @arg @ref LL_RCC_PLLR_DIV_3 01668 * @arg @ref LL_RCC_PLLR_DIV_4 01669 * @arg @ref LL_RCC_PLLR_DIV_5 01670 * @arg @ref LL_RCC_PLLR_DIV_6 01671 * @arg @ref LL_RCC_PLLR_DIV_7 01672 * @retval PLL clock frequency (in Hz) 01673 */ 01674 #define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ 01675 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) 01676 01677 #endif /* RCC_PLLR_SYSCLK_SUPPORT */ 01678 01679 /** 01680 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain 01681 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01682 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); 01683 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 01684 * @param __PLLM__ This parameter can be one of the following values: 01685 * @arg @ref LL_RCC_PLLM_DIV_2 01686 * @arg @ref LL_RCC_PLLM_DIV_3 01687 * @arg @ref LL_RCC_PLLM_DIV_4 01688 * @arg @ref LL_RCC_PLLM_DIV_5 01689 * @arg @ref LL_RCC_PLLM_DIV_6 01690 * @arg @ref LL_RCC_PLLM_DIV_7 01691 * @arg @ref LL_RCC_PLLM_DIV_8 01692 * @arg @ref LL_RCC_PLLM_DIV_9 01693 * @arg @ref LL_RCC_PLLM_DIV_10 01694 * @arg @ref LL_RCC_PLLM_DIV_11 01695 * @arg @ref LL_RCC_PLLM_DIV_12 01696 * @arg @ref LL_RCC_PLLM_DIV_13 01697 * @arg @ref LL_RCC_PLLM_DIV_14 01698 * @arg @ref LL_RCC_PLLM_DIV_15 01699 * @arg @ref LL_RCC_PLLM_DIV_16 01700 * @arg @ref LL_RCC_PLLM_DIV_17 01701 * @arg @ref LL_RCC_PLLM_DIV_18 01702 * @arg @ref LL_RCC_PLLM_DIV_19 01703 * @arg @ref LL_RCC_PLLM_DIV_20 01704 * @arg @ref LL_RCC_PLLM_DIV_21 01705 * @arg @ref LL_RCC_PLLM_DIV_22 01706 * @arg @ref LL_RCC_PLLM_DIV_23 01707 * @arg @ref LL_RCC_PLLM_DIV_24 01708 * @arg @ref LL_RCC_PLLM_DIV_25 01709 * @arg @ref LL_RCC_PLLM_DIV_26 01710 * @arg @ref LL_RCC_PLLM_DIV_27 01711 * @arg @ref LL_RCC_PLLM_DIV_28 01712 * @arg @ref LL_RCC_PLLM_DIV_29 01713 * @arg @ref LL_RCC_PLLM_DIV_30 01714 * @arg @ref LL_RCC_PLLM_DIV_31 01715 * @arg @ref LL_RCC_PLLM_DIV_32 01716 * @arg @ref LL_RCC_PLLM_DIV_33 01717 * @arg @ref LL_RCC_PLLM_DIV_34 01718 * @arg @ref LL_RCC_PLLM_DIV_35 01719 * @arg @ref LL_RCC_PLLM_DIV_36 01720 * @arg @ref LL_RCC_PLLM_DIV_37 01721 * @arg @ref LL_RCC_PLLM_DIV_38 01722 * @arg @ref LL_RCC_PLLM_DIV_39 01723 * @arg @ref LL_RCC_PLLM_DIV_40 01724 * @arg @ref LL_RCC_PLLM_DIV_41 01725 * @arg @ref LL_RCC_PLLM_DIV_42 01726 * @arg @ref LL_RCC_PLLM_DIV_43 01727 * @arg @ref LL_RCC_PLLM_DIV_44 01728 * @arg @ref LL_RCC_PLLM_DIV_45 01729 * @arg @ref LL_RCC_PLLM_DIV_46 01730 * @arg @ref LL_RCC_PLLM_DIV_47 01731 * @arg @ref LL_RCC_PLLM_DIV_48 01732 * @arg @ref LL_RCC_PLLM_DIV_49 01733 * @arg @ref LL_RCC_PLLM_DIV_50 01734 * @arg @ref LL_RCC_PLLM_DIV_51 01735 * @arg @ref LL_RCC_PLLM_DIV_52 01736 * @arg @ref LL_RCC_PLLM_DIV_53 01737 * @arg @ref LL_RCC_PLLM_DIV_54 01738 * @arg @ref LL_RCC_PLLM_DIV_55 01739 * @arg @ref LL_RCC_PLLM_DIV_56 01740 * @arg @ref LL_RCC_PLLM_DIV_57 01741 * @arg @ref LL_RCC_PLLM_DIV_58 01742 * @arg @ref LL_RCC_PLLM_DIV_59 01743 * @arg @ref LL_RCC_PLLM_DIV_60 01744 * @arg @ref LL_RCC_PLLM_DIV_61 01745 * @arg @ref LL_RCC_PLLM_DIV_62 01746 * @arg @ref LL_RCC_PLLM_DIV_63 01747 * @param __PLLN__ Between 50/192(*) and 432 01748 * 01749 * (*) value not defined in all devices. 01750 * @param __PLLQ__ This parameter can be one of the following values: 01751 * @arg @ref LL_RCC_PLLQ_DIV_2 01752 * @arg @ref LL_RCC_PLLQ_DIV_3 01753 * @arg @ref LL_RCC_PLLQ_DIV_4 01754 * @arg @ref LL_RCC_PLLQ_DIV_5 01755 * @arg @ref LL_RCC_PLLQ_DIV_6 01756 * @arg @ref LL_RCC_PLLQ_DIV_7 01757 * @arg @ref LL_RCC_PLLQ_DIV_8 01758 * @arg @ref LL_RCC_PLLQ_DIV_9 01759 * @arg @ref LL_RCC_PLLQ_DIV_10 01760 * @arg @ref LL_RCC_PLLQ_DIV_11 01761 * @arg @ref LL_RCC_PLLQ_DIV_12 01762 * @arg @ref LL_RCC_PLLQ_DIV_13 01763 * @arg @ref LL_RCC_PLLQ_DIV_14 01764 * @arg @ref LL_RCC_PLLQ_DIV_15 01765 * @retval PLL clock frequency (in Hz) 01766 */ 01767 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ 01768 ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos )) 01769 01770 #if defined(DSI) 01771 /** 01772 * @brief Helper macro to calculate the PLLCLK frequency used on DSI 01773 * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), 01774 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); 01775 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 01776 * @param __PLLM__ This parameter can be one of the following values: 01777 * @arg @ref LL_RCC_PLLM_DIV_2 01778 * @arg @ref LL_RCC_PLLM_DIV_3 01779 * @arg @ref LL_RCC_PLLM_DIV_4 01780 * @arg @ref LL_RCC_PLLM_DIV_5 01781 * @arg @ref LL_RCC_PLLM_DIV_6 01782 * @arg @ref LL_RCC_PLLM_DIV_7 01783 * @arg @ref LL_RCC_PLLM_DIV_8 01784 * @arg @ref LL_RCC_PLLM_DIV_9 01785 * @arg @ref LL_RCC_PLLM_DIV_10 01786 * @arg @ref LL_RCC_PLLM_DIV_11 01787 * @arg @ref LL_RCC_PLLM_DIV_12 01788 * @arg @ref LL_RCC_PLLM_DIV_13 01789 * @arg @ref LL_RCC_PLLM_DIV_14 01790 * @arg @ref LL_RCC_PLLM_DIV_15 01791 * @arg @ref LL_RCC_PLLM_DIV_16 01792 * @arg @ref LL_RCC_PLLM_DIV_17 01793 * @arg @ref LL_RCC_PLLM_DIV_18 01794 * @arg @ref LL_RCC_PLLM_DIV_19 01795 * @arg @ref LL_RCC_PLLM_DIV_20 01796 * @arg @ref LL_RCC_PLLM_DIV_21 01797 * @arg @ref LL_RCC_PLLM_DIV_22 01798 * @arg @ref LL_RCC_PLLM_DIV_23 01799 * @arg @ref LL_RCC_PLLM_DIV_24 01800 * @arg @ref LL_RCC_PLLM_DIV_25 01801 * @arg @ref LL_RCC_PLLM_DIV_26 01802 * @arg @ref LL_RCC_PLLM_DIV_27 01803 * @arg @ref LL_RCC_PLLM_DIV_28 01804 * @arg @ref LL_RCC_PLLM_DIV_29 01805 * @arg @ref LL_RCC_PLLM_DIV_30 01806 * @arg @ref LL_RCC_PLLM_DIV_31 01807 * @arg @ref LL_RCC_PLLM_DIV_32 01808 * @arg @ref LL_RCC_PLLM_DIV_33 01809 * @arg @ref LL_RCC_PLLM_DIV_34 01810 * @arg @ref LL_RCC_PLLM_DIV_35 01811 * @arg @ref LL_RCC_PLLM_DIV_36 01812 * @arg @ref LL_RCC_PLLM_DIV_37 01813 * @arg @ref LL_RCC_PLLM_DIV_38 01814 * @arg @ref LL_RCC_PLLM_DIV_39 01815 * @arg @ref LL_RCC_PLLM_DIV_40 01816 * @arg @ref LL_RCC_PLLM_DIV_41 01817 * @arg @ref LL_RCC_PLLM_DIV_42 01818 * @arg @ref LL_RCC_PLLM_DIV_43 01819 * @arg @ref LL_RCC_PLLM_DIV_44 01820 * @arg @ref LL_RCC_PLLM_DIV_45 01821 * @arg @ref LL_RCC_PLLM_DIV_46 01822 * @arg @ref LL_RCC_PLLM_DIV_47 01823 * @arg @ref LL_RCC_PLLM_DIV_48 01824 * @arg @ref LL_RCC_PLLM_DIV_49 01825 * @arg @ref LL_RCC_PLLM_DIV_50 01826 * @arg @ref LL_RCC_PLLM_DIV_51 01827 * @arg @ref LL_RCC_PLLM_DIV_52 01828 * @arg @ref LL_RCC_PLLM_DIV_53 01829 * @arg @ref LL_RCC_PLLM_DIV_54 01830 * @arg @ref LL_RCC_PLLM_DIV_55 01831 * @arg @ref LL_RCC_PLLM_DIV_56 01832 * @arg @ref LL_RCC_PLLM_DIV_57 01833 * @arg @ref LL_RCC_PLLM_DIV_58 01834 * @arg @ref LL_RCC_PLLM_DIV_59 01835 * @arg @ref LL_RCC_PLLM_DIV_60 01836 * @arg @ref LL_RCC_PLLM_DIV_61 01837 * @arg @ref LL_RCC_PLLM_DIV_62 01838 * @arg @ref LL_RCC_PLLM_DIV_63 01839 * @param __PLLN__ Between 50 and 432 01840 * @param __PLLR__ This parameter can be one of the following values: 01841 * @arg @ref LL_RCC_PLLR_DIV_2 01842 * @arg @ref LL_RCC_PLLR_DIV_3 01843 * @arg @ref LL_RCC_PLLR_DIV_4 01844 * @arg @ref LL_RCC_PLLR_DIV_5 01845 * @arg @ref LL_RCC_PLLR_DIV_6 01846 * @arg @ref LL_RCC_PLLR_DIV_7 01847 * @retval PLL clock frequency (in Hz) 01848 */ 01849 #define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ 01850 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) 01851 #endif /* DSI */ 01852 01853 #if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT) 01854 /** 01855 * @brief Helper macro to calculate the PLLCLK frequency used on I2S 01856 * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), 01857 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); 01858 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 01859 * @param __PLLM__ This parameter can be one of the following values: 01860 * @arg @ref LL_RCC_PLLM_DIV_2 01861 * @arg @ref LL_RCC_PLLM_DIV_3 01862 * @arg @ref LL_RCC_PLLM_DIV_4 01863 * @arg @ref LL_RCC_PLLM_DIV_5 01864 * @arg @ref LL_RCC_PLLM_DIV_6 01865 * @arg @ref LL_RCC_PLLM_DIV_7 01866 * @arg @ref LL_RCC_PLLM_DIV_8 01867 * @arg @ref LL_RCC_PLLM_DIV_9 01868 * @arg @ref LL_RCC_PLLM_DIV_10 01869 * @arg @ref LL_RCC_PLLM_DIV_11 01870 * @arg @ref LL_RCC_PLLM_DIV_12 01871 * @arg @ref LL_RCC_PLLM_DIV_13 01872 * @arg @ref LL_RCC_PLLM_DIV_14 01873 * @arg @ref LL_RCC_PLLM_DIV_15 01874 * @arg @ref LL_RCC_PLLM_DIV_16 01875 * @arg @ref LL_RCC_PLLM_DIV_17 01876 * @arg @ref LL_RCC_PLLM_DIV_18 01877 * @arg @ref LL_RCC_PLLM_DIV_19 01878 * @arg @ref LL_RCC_PLLM_DIV_20 01879 * @arg @ref LL_RCC_PLLM_DIV_21 01880 * @arg @ref LL_RCC_PLLM_DIV_22 01881 * @arg @ref LL_RCC_PLLM_DIV_23 01882 * @arg @ref LL_RCC_PLLM_DIV_24 01883 * @arg @ref LL_RCC_PLLM_DIV_25 01884 * @arg @ref LL_RCC_PLLM_DIV_26 01885 * @arg @ref LL_RCC_PLLM_DIV_27 01886 * @arg @ref LL_RCC_PLLM_DIV_28 01887 * @arg @ref LL_RCC_PLLM_DIV_29 01888 * @arg @ref LL_RCC_PLLM_DIV_30 01889 * @arg @ref LL_RCC_PLLM_DIV_31 01890 * @arg @ref LL_RCC_PLLM_DIV_32 01891 * @arg @ref LL_RCC_PLLM_DIV_33 01892 * @arg @ref LL_RCC_PLLM_DIV_34 01893 * @arg @ref LL_RCC_PLLM_DIV_35 01894 * @arg @ref LL_RCC_PLLM_DIV_36 01895 * @arg @ref LL_RCC_PLLM_DIV_37 01896 * @arg @ref LL_RCC_PLLM_DIV_38 01897 * @arg @ref LL_RCC_PLLM_DIV_39 01898 * @arg @ref LL_RCC_PLLM_DIV_40 01899 * @arg @ref LL_RCC_PLLM_DIV_41 01900 * @arg @ref LL_RCC_PLLM_DIV_42 01901 * @arg @ref LL_RCC_PLLM_DIV_43 01902 * @arg @ref LL_RCC_PLLM_DIV_44 01903 * @arg @ref LL_RCC_PLLM_DIV_45 01904 * @arg @ref LL_RCC_PLLM_DIV_46 01905 * @arg @ref LL_RCC_PLLM_DIV_47 01906 * @arg @ref LL_RCC_PLLM_DIV_48 01907 * @arg @ref LL_RCC_PLLM_DIV_49 01908 * @arg @ref LL_RCC_PLLM_DIV_50 01909 * @arg @ref LL_RCC_PLLM_DIV_51 01910 * @arg @ref LL_RCC_PLLM_DIV_52 01911 * @arg @ref LL_RCC_PLLM_DIV_53 01912 * @arg @ref LL_RCC_PLLM_DIV_54 01913 * @arg @ref LL_RCC_PLLM_DIV_55 01914 * @arg @ref LL_RCC_PLLM_DIV_56 01915 * @arg @ref LL_RCC_PLLM_DIV_57 01916 * @arg @ref LL_RCC_PLLM_DIV_58 01917 * @arg @ref LL_RCC_PLLM_DIV_59 01918 * @arg @ref LL_RCC_PLLM_DIV_60 01919 * @arg @ref LL_RCC_PLLM_DIV_61 01920 * @arg @ref LL_RCC_PLLM_DIV_62 01921 * @arg @ref LL_RCC_PLLM_DIV_63 01922 * @param __PLLN__ Between 50 and 432 01923 * @param __PLLR__ This parameter can be one of the following values: 01924 * @arg @ref LL_RCC_PLLR_DIV_2 01925 * @arg @ref LL_RCC_PLLR_DIV_3 01926 * @arg @ref LL_RCC_PLLR_DIV_4 01927 * @arg @ref LL_RCC_PLLR_DIV_5 01928 * @arg @ref LL_RCC_PLLR_DIV_6 01929 * @arg @ref LL_RCC_PLLR_DIV_7 01930 * @retval PLL clock frequency (in Hz) 01931 */ 01932 #define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ 01933 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) 01934 #endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */ 01935 01936 #if defined(SPDIFRX) 01937 /** 01938 * @brief Helper macro to calculate the PLLCLK frequency used on SPDIFRX 01939 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), 01940 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); 01941 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 01942 * @param __PLLM__ This parameter can be one of the following values: 01943 * @arg @ref LL_RCC_PLLM_DIV_2 01944 * @arg @ref LL_RCC_PLLM_DIV_3 01945 * @arg @ref LL_RCC_PLLM_DIV_4 01946 * @arg @ref LL_RCC_PLLM_DIV_5 01947 * @arg @ref LL_RCC_PLLM_DIV_6 01948 * @arg @ref LL_RCC_PLLM_DIV_7 01949 * @arg @ref LL_RCC_PLLM_DIV_8 01950 * @arg @ref LL_RCC_PLLM_DIV_9 01951 * @arg @ref LL_RCC_PLLM_DIV_10 01952 * @arg @ref LL_RCC_PLLM_DIV_11 01953 * @arg @ref LL_RCC_PLLM_DIV_12 01954 * @arg @ref LL_RCC_PLLM_DIV_13 01955 * @arg @ref LL_RCC_PLLM_DIV_14 01956 * @arg @ref LL_RCC_PLLM_DIV_15 01957 * @arg @ref LL_RCC_PLLM_DIV_16 01958 * @arg @ref LL_RCC_PLLM_DIV_17 01959 * @arg @ref LL_RCC_PLLM_DIV_18 01960 * @arg @ref LL_RCC_PLLM_DIV_19 01961 * @arg @ref LL_RCC_PLLM_DIV_20 01962 * @arg @ref LL_RCC_PLLM_DIV_21 01963 * @arg @ref LL_RCC_PLLM_DIV_22 01964 * @arg @ref LL_RCC_PLLM_DIV_23 01965 * @arg @ref LL_RCC_PLLM_DIV_24 01966 * @arg @ref LL_RCC_PLLM_DIV_25 01967 * @arg @ref LL_RCC_PLLM_DIV_26 01968 * @arg @ref LL_RCC_PLLM_DIV_27 01969 * @arg @ref LL_RCC_PLLM_DIV_28 01970 * @arg @ref LL_RCC_PLLM_DIV_29 01971 * @arg @ref LL_RCC_PLLM_DIV_30 01972 * @arg @ref LL_RCC_PLLM_DIV_31 01973 * @arg @ref LL_RCC_PLLM_DIV_32 01974 * @arg @ref LL_RCC_PLLM_DIV_33 01975 * @arg @ref LL_RCC_PLLM_DIV_34 01976 * @arg @ref LL_RCC_PLLM_DIV_35 01977 * @arg @ref LL_RCC_PLLM_DIV_36 01978 * @arg @ref LL_RCC_PLLM_DIV_37 01979 * @arg @ref LL_RCC_PLLM_DIV_38 01980 * @arg @ref LL_RCC_PLLM_DIV_39 01981 * @arg @ref LL_RCC_PLLM_DIV_40 01982 * @arg @ref LL_RCC_PLLM_DIV_41 01983 * @arg @ref LL_RCC_PLLM_DIV_42 01984 * @arg @ref LL_RCC_PLLM_DIV_43 01985 * @arg @ref LL_RCC_PLLM_DIV_44 01986 * @arg @ref LL_RCC_PLLM_DIV_45 01987 * @arg @ref LL_RCC_PLLM_DIV_46 01988 * @arg @ref LL_RCC_PLLM_DIV_47 01989 * @arg @ref LL_RCC_PLLM_DIV_48 01990 * @arg @ref LL_RCC_PLLM_DIV_49 01991 * @arg @ref LL_RCC_PLLM_DIV_50 01992 * @arg @ref LL_RCC_PLLM_DIV_51 01993 * @arg @ref LL_RCC_PLLM_DIV_52 01994 * @arg @ref LL_RCC_PLLM_DIV_53 01995 * @arg @ref LL_RCC_PLLM_DIV_54 01996 * @arg @ref LL_RCC_PLLM_DIV_55 01997 * @arg @ref LL_RCC_PLLM_DIV_56 01998 * @arg @ref LL_RCC_PLLM_DIV_57 01999 * @arg @ref LL_RCC_PLLM_DIV_58 02000 * @arg @ref LL_RCC_PLLM_DIV_59 02001 * @arg @ref LL_RCC_PLLM_DIV_60 02002 * @arg @ref LL_RCC_PLLM_DIV_61 02003 * @arg @ref LL_RCC_PLLM_DIV_62 02004 * @arg @ref LL_RCC_PLLM_DIV_63 02005 * @param __PLLN__ Between 50 and 432 02006 * @param __PLLR__ This parameter can be one of the following values: 02007 * @arg @ref LL_RCC_PLLR_DIV_2 02008 * @arg @ref LL_RCC_PLLR_DIV_3 02009 * @arg @ref LL_RCC_PLLR_DIV_4 02010 * @arg @ref LL_RCC_PLLR_DIV_5 02011 * @arg @ref LL_RCC_PLLR_DIV_6 02012 * @arg @ref LL_RCC_PLLR_DIV_7 02013 * @retval PLL clock frequency (in Hz) 02014 */ 02015 #define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ 02016 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) 02017 #endif /* SPDIFRX */ 02018 02019 #if defined(RCC_PLLCFGR_PLLR) 02020 #if defined(SAI1) 02021 /** 02022 * @brief Helper macro to calculate the PLLCLK frequency used on SAI 02023 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), 02024 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ()); 02025 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 02026 * @param __PLLM__ This parameter can be one of the following values: 02027 * @arg @ref LL_RCC_PLLM_DIV_2 02028 * @arg @ref LL_RCC_PLLM_DIV_3 02029 * @arg @ref LL_RCC_PLLM_DIV_4 02030 * @arg @ref LL_RCC_PLLM_DIV_5 02031 * @arg @ref LL_RCC_PLLM_DIV_6 02032 * @arg @ref LL_RCC_PLLM_DIV_7 02033 * @arg @ref LL_RCC_PLLM_DIV_8 02034 * @arg @ref LL_RCC_PLLM_DIV_9 02035 * @arg @ref LL_RCC_PLLM_DIV_10 02036 * @arg @ref LL_RCC_PLLM_DIV_11 02037 * @arg @ref LL_RCC_PLLM_DIV_12 02038 * @arg @ref LL_RCC_PLLM_DIV_13 02039 * @arg @ref LL_RCC_PLLM_DIV_14 02040 * @arg @ref LL_RCC_PLLM_DIV_15 02041 * @arg @ref LL_RCC_PLLM_DIV_16 02042 * @arg @ref LL_RCC_PLLM_DIV_17 02043 * @arg @ref LL_RCC_PLLM_DIV_18 02044 * @arg @ref LL_RCC_PLLM_DIV_19 02045 * @arg @ref LL_RCC_PLLM_DIV_20 02046 * @arg @ref LL_RCC_PLLM_DIV_21 02047 * @arg @ref LL_RCC_PLLM_DIV_22 02048 * @arg @ref LL_RCC_PLLM_DIV_23 02049 * @arg @ref LL_RCC_PLLM_DIV_24 02050 * @arg @ref LL_RCC_PLLM_DIV_25 02051 * @arg @ref LL_RCC_PLLM_DIV_26 02052 * @arg @ref LL_RCC_PLLM_DIV_27 02053 * @arg @ref LL_RCC_PLLM_DIV_28 02054 * @arg @ref LL_RCC_PLLM_DIV_29 02055 * @arg @ref LL_RCC_PLLM_DIV_30 02056 * @arg @ref LL_RCC_PLLM_DIV_31 02057 * @arg @ref LL_RCC_PLLM_DIV_32 02058 * @arg @ref LL_RCC_PLLM_DIV_33 02059 * @arg @ref LL_RCC_PLLM_DIV_34 02060 * @arg @ref LL_RCC_PLLM_DIV_35 02061 * @arg @ref LL_RCC_PLLM_DIV_36 02062 * @arg @ref LL_RCC_PLLM_DIV_37 02063 * @arg @ref LL_RCC_PLLM_DIV_38 02064 * @arg @ref LL_RCC_PLLM_DIV_39 02065 * @arg @ref LL_RCC_PLLM_DIV_40 02066 * @arg @ref LL_RCC_PLLM_DIV_41 02067 * @arg @ref LL_RCC_PLLM_DIV_42 02068 * @arg @ref LL_RCC_PLLM_DIV_43 02069 * @arg @ref LL_RCC_PLLM_DIV_44 02070 * @arg @ref LL_RCC_PLLM_DIV_45 02071 * @arg @ref LL_RCC_PLLM_DIV_46 02072 * @arg @ref LL_RCC_PLLM_DIV_47 02073 * @arg @ref LL_RCC_PLLM_DIV_48 02074 * @arg @ref LL_RCC_PLLM_DIV_49 02075 * @arg @ref LL_RCC_PLLM_DIV_50 02076 * @arg @ref LL_RCC_PLLM_DIV_51 02077 * @arg @ref LL_RCC_PLLM_DIV_52 02078 * @arg @ref LL_RCC_PLLM_DIV_53 02079 * @arg @ref LL_RCC_PLLM_DIV_54 02080 * @arg @ref LL_RCC_PLLM_DIV_55 02081 * @arg @ref LL_RCC_PLLM_DIV_56 02082 * @arg @ref LL_RCC_PLLM_DIV_57 02083 * @arg @ref LL_RCC_PLLM_DIV_58 02084 * @arg @ref LL_RCC_PLLM_DIV_59 02085 * @arg @ref LL_RCC_PLLM_DIV_60 02086 * @arg @ref LL_RCC_PLLM_DIV_61 02087 * @arg @ref LL_RCC_PLLM_DIV_62 02088 * @arg @ref LL_RCC_PLLM_DIV_63 02089 * @param __PLLN__ Between 50 and 432 02090 * @param __PLLR__ This parameter can be one of the following values: 02091 * @arg @ref LL_RCC_PLLR_DIV_2 02092 * @arg @ref LL_RCC_PLLR_DIV_3 02093 * @arg @ref LL_RCC_PLLR_DIV_4 02094 * @arg @ref LL_RCC_PLLR_DIV_5 02095 * @arg @ref LL_RCC_PLLR_DIV_6 02096 * @arg @ref LL_RCC_PLLR_DIV_7 02097 * @param __PLLDIVR__ This parameter can be one of the following values: 02098 * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*) 02099 * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*) 02100 * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*) 02101 * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*) 02102 * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*) 02103 * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*) 02104 * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*) 02105 * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*) 02106 * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*) 02107 * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*) 02108 * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*) 02109 * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*) 02110 * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*) 02111 * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*) 02112 * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*) 02113 * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*) 02114 * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*) 02115 * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*) 02116 * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*) 02117 * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*) 02118 * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*) 02119 * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*) 02120 * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*) 02121 * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*) 02122 * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*) 02123 * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*) 02124 * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*) 02125 * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*) 02126 * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*) 02127 * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*) 02128 * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*) 02129 * 02130 * (*) value not defined in all devices. 02131 * @retval PLL clock frequency (in Hz) 02132 */ 02133 #if defined(RCC_DCKCFGR_PLLDIVR) 02134 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ 02135 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos )) 02136 #else 02137 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ 02138 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) 02139 #endif /* RCC_DCKCFGR_PLLDIVR */ 02140 #endif /* SAI1 */ 02141 #endif /* RCC_PLLCFGR_PLLR */ 02142 02143 #if defined(RCC_PLLSAI_SUPPORT) 02144 /** 02145 * @brief Helper macro to calculate the PLLSAI frequency used for SAI domain 02146 * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), 02147 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ()); 02148 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 02149 * @param __PLLM__ This parameter can be one of the following values: 02150 * @arg @ref LL_RCC_PLLSAIM_DIV_2 02151 * @arg @ref LL_RCC_PLLSAIM_DIV_3 02152 * @arg @ref LL_RCC_PLLSAIM_DIV_4 02153 * @arg @ref LL_RCC_PLLSAIM_DIV_5 02154 * @arg @ref LL_RCC_PLLSAIM_DIV_6 02155 * @arg @ref LL_RCC_PLLSAIM_DIV_7 02156 * @arg @ref LL_RCC_PLLSAIM_DIV_8 02157 * @arg @ref LL_RCC_PLLSAIM_DIV_9 02158 * @arg @ref LL_RCC_PLLSAIM_DIV_10 02159 * @arg @ref LL_RCC_PLLSAIM_DIV_11 02160 * @arg @ref LL_RCC_PLLSAIM_DIV_12 02161 * @arg @ref LL_RCC_PLLSAIM_DIV_13 02162 * @arg @ref LL_RCC_PLLSAIM_DIV_14 02163 * @arg @ref LL_RCC_PLLSAIM_DIV_15 02164 * @arg @ref LL_RCC_PLLSAIM_DIV_16 02165 * @arg @ref LL_RCC_PLLSAIM_DIV_17 02166 * @arg @ref LL_RCC_PLLSAIM_DIV_18 02167 * @arg @ref LL_RCC_PLLSAIM_DIV_19 02168 * @arg @ref LL_RCC_PLLSAIM_DIV_20 02169 * @arg @ref LL_RCC_PLLSAIM_DIV_21 02170 * @arg @ref LL_RCC_PLLSAIM_DIV_22 02171 * @arg @ref LL_RCC_PLLSAIM_DIV_23 02172 * @arg @ref LL_RCC_PLLSAIM_DIV_24 02173 * @arg @ref LL_RCC_PLLSAIM_DIV_25 02174 * @arg @ref LL_RCC_PLLSAIM_DIV_26 02175 * @arg @ref LL_RCC_PLLSAIM_DIV_27 02176 * @arg @ref LL_RCC_PLLSAIM_DIV_28 02177 * @arg @ref LL_RCC_PLLSAIM_DIV_29 02178 * @arg @ref LL_RCC_PLLSAIM_DIV_30 02179 * @arg @ref LL_RCC_PLLSAIM_DIV_31 02180 * @arg @ref LL_RCC_PLLSAIM_DIV_32 02181 * @arg @ref LL_RCC_PLLSAIM_DIV_33 02182 * @arg @ref LL_RCC_PLLSAIM_DIV_34 02183 * @arg @ref LL_RCC_PLLSAIM_DIV_35 02184 * @arg @ref LL_RCC_PLLSAIM_DIV_36 02185 * @arg @ref LL_RCC_PLLSAIM_DIV_37 02186 * @arg @ref LL_RCC_PLLSAIM_DIV_38 02187 * @arg @ref LL_RCC_PLLSAIM_DIV_39 02188 * @arg @ref LL_RCC_PLLSAIM_DIV_40 02189 * @arg @ref LL_RCC_PLLSAIM_DIV_41 02190 * @arg @ref LL_RCC_PLLSAIM_DIV_42 02191 * @arg @ref LL_RCC_PLLSAIM_DIV_43 02192 * @arg @ref LL_RCC_PLLSAIM_DIV_44 02193 * @arg @ref LL_RCC_PLLSAIM_DIV_45 02194 * @arg @ref LL_RCC_PLLSAIM_DIV_46 02195 * @arg @ref LL_RCC_PLLSAIM_DIV_47 02196 * @arg @ref LL_RCC_PLLSAIM_DIV_48 02197 * @arg @ref LL_RCC_PLLSAIM_DIV_49 02198 * @arg @ref LL_RCC_PLLSAIM_DIV_50 02199 * @arg @ref LL_RCC_PLLSAIM_DIV_51 02200 * @arg @ref LL_RCC_PLLSAIM_DIV_52 02201 * @arg @ref LL_RCC_PLLSAIM_DIV_53 02202 * @arg @ref LL_RCC_PLLSAIM_DIV_54 02203 * @arg @ref LL_RCC_PLLSAIM_DIV_55 02204 * @arg @ref LL_RCC_PLLSAIM_DIV_56 02205 * @arg @ref LL_RCC_PLLSAIM_DIV_57 02206 * @arg @ref LL_RCC_PLLSAIM_DIV_58 02207 * @arg @ref LL_RCC_PLLSAIM_DIV_59 02208 * @arg @ref LL_RCC_PLLSAIM_DIV_60 02209 * @arg @ref LL_RCC_PLLSAIM_DIV_61 02210 * @arg @ref LL_RCC_PLLSAIM_DIV_62 02211 * @arg @ref LL_RCC_PLLSAIM_DIV_63 02212 * @param __PLLSAIN__ Between 49/50(*) and 432 02213 * 02214 * (*) value not defined in all devices. 02215 * @param __PLLSAIQ__ This parameter can be one of the following values: 02216 * @arg @ref LL_RCC_PLLSAIQ_DIV_2 02217 * @arg @ref LL_RCC_PLLSAIQ_DIV_3 02218 * @arg @ref LL_RCC_PLLSAIQ_DIV_4 02219 * @arg @ref LL_RCC_PLLSAIQ_DIV_5 02220 * @arg @ref LL_RCC_PLLSAIQ_DIV_6 02221 * @arg @ref LL_RCC_PLLSAIQ_DIV_7 02222 * @arg @ref LL_RCC_PLLSAIQ_DIV_8 02223 * @arg @ref LL_RCC_PLLSAIQ_DIV_9 02224 * @arg @ref LL_RCC_PLLSAIQ_DIV_10 02225 * @arg @ref LL_RCC_PLLSAIQ_DIV_11 02226 * @arg @ref LL_RCC_PLLSAIQ_DIV_12 02227 * @arg @ref LL_RCC_PLLSAIQ_DIV_13 02228 * @arg @ref LL_RCC_PLLSAIQ_DIV_14 02229 * @arg @ref LL_RCC_PLLSAIQ_DIV_15 02230 * @param __PLLSAIDIVQ__ This parameter can be one of the following values: 02231 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 02232 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 02233 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 02234 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 02235 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 02236 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 02237 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 02238 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 02239 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 02240 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 02241 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 02242 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 02243 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 02244 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 02245 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 02246 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 02247 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 02248 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 02249 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 02250 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 02251 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 02252 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 02253 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 02254 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 02255 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 02256 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 02257 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 02258 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 02259 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 02260 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 02261 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 02262 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 02263 * @retval PLLSAI clock frequency (in Hz) 02264 */ 02265 #define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ 02266 (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U))) 02267 02268 #if defined(RCC_PLLSAICFGR_PLLSAIP) 02269 /** 02270 * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain 02271 * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), 02272 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ()); 02273 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 02274 * @param __PLLM__ This parameter can be one of the following values: 02275 * @arg @ref LL_RCC_PLLSAIM_DIV_2 02276 * @arg @ref LL_RCC_PLLSAIM_DIV_3 02277 * @arg @ref LL_RCC_PLLSAIM_DIV_4 02278 * @arg @ref LL_RCC_PLLSAIM_DIV_5 02279 * @arg @ref LL_RCC_PLLSAIM_DIV_6 02280 * @arg @ref LL_RCC_PLLSAIM_DIV_7 02281 * @arg @ref LL_RCC_PLLSAIM_DIV_8 02282 * @arg @ref LL_RCC_PLLSAIM_DIV_9 02283 * @arg @ref LL_RCC_PLLSAIM_DIV_10 02284 * @arg @ref LL_RCC_PLLSAIM_DIV_11 02285 * @arg @ref LL_RCC_PLLSAIM_DIV_12 02286 * @arg @ref LL_RCC_PLLSAIM_DIV_13 02287 * @arg @ref LL_RCC_PLLSAIM_DIV_14 02288 * @arg @ref LL_RCC_PLLSAIM_DIV_15 02289 * @arg @ref LL_RCC_PLLSAIM_DIV_16 02290 * @arg @ref LL_RCC_PLLSAIM_DIV_17 02291 * @arg @ref LL_RCC_PLLSAIM_DIV_18 02292 * @arg @ref LL_RCC_PLLSAIM_DIV_19 02293 * @arg @ref LL_RCC_PLLSAIM_DIV_20 02294 * @arg @ref LL_RCC_PLLSAIM_DIV_21 02295 * @arg @ref LL_RCC_PLLSAIM_DIV_22 02296 * @arg @ref LL_RCC_PLLSAIM_DIV_23 02297 * @arg @ref LL_RCC_PLLSAIM_DIV_24 02298 * @arg @ref LL_RCC_PLLSAIM_DIV_25 02299 * @arg @ref LL_RCC_PLLSAIM_DIV_26 02300 * @arg @ref LL_RCC_PLLSAIM_DIV_27 02301 * @arg @ref LL_RCC_PLLSAIM_DIV_28 02302 * @arg @ref LL_RCC_PLLSAIM_DIV_29 02303 * @arg @ref LL_RCC_PLLSAIM_DIV_30 02304 * @arg @ref LL_RCC_PLLSAIM_DIV_31 02305 * @arg @ref LL_RCC_PLLSAIM_DIV_32 02306 * @arg @ref LL_RCC_PLLSAIM_DIV_33 02307 * @arg @ref LL_RCC_PLLSAIM_DIV_34 02308 * @arg @ref LL_RCC_PLLSAIM_DIV_35 02309 * @arg @ref LL_RCC_PLLSAIM_DIV_36 02310 * @arg @ref LL_RCC_PLLSAIM_DIV_37 02311 * @arg @ref LL_RCC_PLLSAIM_DIV_38 02312 * @arg @ref LL_RCC_PLLSAIM_DIV_39 02313 * @arg @ref LL_RCC_PLLSAIM_DIV_40 02314 * @arg @ref LL_RCC_PLLSAIM_DIV_41 02315 * @arg @ref LL_RCC_PLLSAIM_DIV_42 02316 * @arg @ref LL_RCC_PLLSAIM_DIV_43 02317 * @arg @ref LL_RCC_PLLSAIM_DIV_44 02318 * @arg @ref LL_RCC_PLLSAIM_DIV_45 02319 * @arg @ref LL_RCC_PLLSAIM_DIV_46 02320 * @arg @ref LL_RCC_PLLSAIM_DIV_47 02321 * @arg @ref LL_RCC_PLLSAIM_DIV_48 02322 * @arg @ref LL_RCC_PLLSAIM_DIV_49 02323 * @arg @ref LL_RCC_PLLSAIM_DIV_50 02324 * @arg @ref LL_RCC_PLLSAIM_DIV_51 02325 * @arg @ref LL_RCC_PLLSAIM_DIV_52 02326 * @arg @ref LL_RCC_PLLSAIM_DIV_53 02327 * @arg @ref LL_RCC_PLLSAIM_DIV_54 02328 * @arg @ref LL_RCC_PLLSAIM_DIV_55 02329 * @arg @ref LL_RCC_PLLSAIM_DIV_56 02330 * @arg @ref LL_RCC_PLLSAIM_DIV_57 02331 * @arg @ref LL_RCC_PLLSAIM_DIV_58 02332 * @arg @ref LL_RCC_PLLSAIM_DIV_59 02333 * @arg @ref LL_RCC_PLLSAIM_DIV_60 02334 * @arg @ref LL_RCC_PLLSAIM_DIV_61 02335 * @arg @ref LL_RCC_PLLSAIM_DIV_62 02336 * @arg @ref LL_RCC_PLLSAIM_DIV_63 02337 * @param __PLLSAIN__ Between 50 and 432 02338 * @param __PLLSAIP__ This parameter can be one of the following values: 02339 * @arg @ref LL_RCC_PLLSAIP_DIV_2 02340 * @arg @ref LL_RCC_PLLSAIP_DIV_4 02341 * @arg @ref LL_RCC_PLLSAIP_DIV_6 02342 * @arg @ref LL_RCC_PLLSAIP_DIV_8 02343 * @retval PLLSAI clock frequency (in Hz) 02344 */ 02345 #define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ 02346 ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U)) 02347 #endif /* RCC_PLLSAICFGR_PLLSAIP */ 02348 02349 #if defined(LTDC) 02350 /** 02351 * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain 02352 * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), 02353 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ()); 02354 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 02355 * @param __PLLM__ This parameter can be one of the following values: 02356 * @arg @ref LL_RCC_PLLSAIM_DIV_2 02357 * @arg @ref LL_RCC_PLLSAIM_DIV_3 02358 * @arg @ref LL_RCC_PLLSAIM_DIV_4 02359 * @arg @ref LL_RCC_PLLSAIM_DIV_5 02360 * @arg @ref LL_RCC_PLLSAIM_DIV_6 02361 * @arg @ref LL_RCC_PLLSAIM_DIV_7 02362 * @arg @ref LL_RCC_PLLSAIM_DIV_8 02363 * @arg @ref LL_RCC_PLLSAIM_DIV_9 02364 * @arg @ref LL_RCC_PLLSAIM_DIV_10 02365 * @arg @ref LL_RCC_PLLSAIM_DIV_11 02366 * @arg @ref LL_RCC_PLLSAIM_DIV_12 02367 * @arg @ref LL_RCC_PLLSAIM_DIV_13 02368 * @arg @ref LL_RCC_PLLSAIM_DIV_14 02369 * @arg @ref LL_RCC_PLLSAIM_DIV_15 02370 * @arg @ref LL_RCC_PLLSAIM_DIV_16 02371 * @arg @ref LL_RCC_PLLSAIM_DIV_17 02372 * @arg @ref LL_RCC_PLLSAIM_DIV_18 02373 * @arg @ref LL_RCC_PLLSAIM_DIV_19 02374 * @arg @ref LL_RCC_PLLSAIM_DIV_20 02375 * @arg @ref LL_RCC_PLLSAIM_DIV_21 02376 * @arg @ref LL_RCC_PLLSAIM_DIV_22 02377 * @arg @ref LL_RCC_PLLSAIM_DIV_23 02378 * @arg @ref LL_RCC_PLLSAIM_DIV_24 02379 * @arg @ref LL_RCC_PLLSAIM_DIV_25 02380 * @arg @ref LL_RCC_PLLSAIM_DIV_26 02381 * @arg @ref LL_RCC_PLLSAIM_DIV_27 02382 * @arg @ref LL_RCC_PLLSAIM_DIV_28 02383 * @arg @ref LL_RCC_PLLSAIM_DIV_29 02384 * @arg @ref LL_RCC_PLLSAIM_DIV_30 02385 * @arg @ref LL_RCC_PLLSAIM_DIV_31 02386 * @arg @ref LL_RCC_PLLSAIM_DIV_32 02387 * @arg @ref LL_RCC_PLLSAIM_DIV_33 02388 * @arg @ref LL_RCC_PLLSAIM_DIV_34 02389 * @arg @ref LL_RCC_PLLSAIM_DIV_35 02390 * @arg @ref LL_RCC_PLLSAIM_DIV_36 02391 * @arg @ref LL_RCC_PLLSAIM_DIV_37 02392 * @arg @ref LL_RCC_PLLSAIM_DIV_38 02393 * @arg @ref LL_RCC_PLLSAIM_DIV_39 02394 * @arg @ref LL_RCC_PLLSAIM_DIV_40 02395 * @arg @ref LL_RCC_PLLSAIM_DIV_41 02396 * @arg @ref LL_RCC_PLLSAIM_DIV_42 02397 * @arg @ref LL_RCC_PLLSAIM_DIV_43 02398 * @arg @ref LL_RCC_PLLSAIM_DIV_44 02399 * @arg @ref LL_RCC_PLLSAIM_DIV_45 02400 * @arg @ref LL_RCC_PLLSAIM_DIV_46 02401 * @arg @ref LL_RCC_PLLSAIM_DIV_47 02402 * @arg @ref LL_RCC_PLLSAIM_DIV_48 02403 * @arg @ref LL_RCC_PLLSAIM_DIV_49 02404 * @arg @ref LL_RCC_PLLSAIM_DIV_50 02405 * @arg @ref LL_RCC_PLLSAIM_DIV_51 02406 * @arg @ref LL_RCC_PLLSAIM_DIV_52 02407 * @arg @ref LL_RCC_PLLSAIM_DIV_53 02408 * @arg @ref LL_RCC_PLLSAIM_DIV_54 02409 * @arg @ref LL_RCC_PLLSAIM_DIV_55 02410 * @arg @ref LL_RCC_PLLSAIM_DIV_56 02411 * @arg @ref LL_RCC_PLLSAIM_DIV_57 02412 * @arg @ref LL_RCC_PLLSAIM_DIV_58 02413 * @arg @ref LL_RCC_PLLSAIM_DIV_59 02414 * @arg @ref LL_RCC_PLLSAIM_DIV_60 02415 * @arg @ref LL_RCC_PLLSAIM_DIV_61 02416 * @arg @ref LL_RCC_PLLSAIM_DIV_62 02417 * @arg @ref LL_RCC_PLLSAIM_DIV_63 02418 * @param __PLLSAIN__ Between 49/50(*) and 432 02419 * 02420 * (*) value not defined in all devices. 02421 * @param __PLLSAIR__ This parameter can be one of the following values: 02422 * @arg @ref LL_RCC_PLLSAIR_DIV_2 02423 * @arg @ref LL_RCC_PLLSAIR_DIV_3 02424 * @arg @ref LL_RCC_PLLSAIR_DIV_4 02425 * @arg @ref LL_RCC_PLLSAIR_DIV_5 02426 * @arg @ref LL_RCC_PLLSAIR_DIV_6 02427 * @arg @ref LL_RCC_PLLSAIR_DIV_7 02428 * @param __PLLSAIDIVR__ This parameter can be one of the following values: 02429 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 02430 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 02431 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 02432 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 02433 * @retval PLLSAI clock frequency (in Hz) 02434 */ 02435 #define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ 02436 (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos]))) 02437 #endif /* LTDC */ 02438 #endif /* RCC_PLLSAI_SUPPORT */ 02439 02440 #if defined(RCC_PLLI2S_SUPPORT) 02441 #if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR) 02442 /** 02443 * @brief Helper macro to calculate the PLLI2S frequency used for SAI domain 02444 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), 02445 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ()); 02446 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 02447 * @param __PLLM__ This parameter can be one of the following values: 02448 * @arg @ref LL_RCC_PLLI2SM_DIV_2 02449 * @arg @ref LL_RCC_PLLI2SM_DIV_3 02450 * @arg @ref LL_RCC_PLLI2SM_DIV_4 02451 * @arg @ref LL_RCC_PLLI2SM_DIV_5 02452 * @arg @ref LL_RCC_PLLI2SM_DIV_6 02453 * @arg @ref LL_RCC_PLLI2SM_DIV_7 02454 * @arg @ref LL_RCC_PLLI2SM_DIV_8 02455 * @arg @ref LL_RCC_PLLI2SM_DIV_9 02456 * @arg @ref LL_RCC_PLLI2SM_DIV_10 02457 * @arg @ref LL_RCC_PLLI2SM_DIV_11 02458 * @arg @ref LL_RCC_PLLI2SM_DIV_12 02459 * @arg @ref LL_RCC_PLLI2SM_DIV_13 02460 * @arg @ref LL_RCC_PLLI2SM_DIV_14 02461 * @arg @ref LL_RCC_PLLI2SM_DIV_15 02462 * @arg @ref LL_RCC_PLLI2SM_DIV_16 02463 * @arg @ref LL_RCC_PLLI2SM_DIV_17 02464 * @arg @ref LL_RCC_PLLI2SM_DIV_18 02465 * @arg @ref LL_RCC_PLLI2SM_DIV_19 02466 * @arg @ref LL_RCC_PLLI2SM_DIV_20 02467 * @arg @ref LL_RCC_PLLI2SM_DIV_21 02468 * @arg @ref LL_RCC_PLLI2SM_DIV_22 02469 * @arg @ref LL_RCC_PLLI2SM_DIV_23 02470 * @arg @ref LL_RCC_PLLI2SM_DIV_24 02471 * @arg @ref LL_RCC_PLLI2SM_DIV_25 02472 * @arg @ref LL_RCC_PLLI2SM_DIV_26 02473 * @arg @ref LL_RCC_PLLI2SM_DIV_27 02474 * @arg @ref LL_RCC_PLLI2SM_DIV_28 02475 * @arg @ref LL_RCC_PLLI2SM_DIV_29 02476 * @arg @ref LL_RCC_PLLI2SM_DIV_30 02477 * @arg @ref LL_RCC_PLLI2SM_DIV_31 02478 * @arg @ref LL_RCC_PLLI2SM_DIV_32 02479 * @arg @ref LL_RCC_PLLI2SM_DIV_33 02480 * @arg @ref LL_RCC_PLLI2SM_DIV_34 02481 * @arg @ref LL_RCC_PLLI2SM_DIV_35 02482 * @arg @ref LL_RCC_PLLI2SM_DIV_36 02483 * @arg @ref LL_RCC_PLLI2SM_DIV_37 02484 * @arg @ref LL_RCC_PLLI2SM_DIV_38 02485 * @arg @ref LL_RCC_PLLI2SM_DIV_39 02486 * @arg @ref LL_RCC_PLLI2SM_DIV_40 02487 * @arg @ref LL_RCC_PLLI2SM_DIV_41 02488 * @arg @ref LL_RCC_PLLI2SM_DIV_42 02489 * @arg @ref LL_RCC_PLLI2SM_DIV_43 02490 * @arg @ref LL_RCC_PLLI2SM_DIV_44 02491 * @arg @ref LL_RCC_PLLI2SM_DIV_45 02492 * @arg @ref LL_RCC_PLLI2SM_DIV_46 02493 * @arg @ref LL_RCC_PLLI2SM_DIV_47 02494 * @arg @ref LL_RCC_PLLI2SM_DIV_48 02495 * @arg @ref LL_RCC_PLLI2SM_DIV_49 02496 * @arg @ref LL_RCC_PLLI2SM_DIV_50 02497 * @arg @ref LL_RCC_PLLI2SM_DIV_51 02498 * @arg @ref LL_RCC_PLLI2SM_DIV_52 02499 * @arg @ref LL_RCC_PLLI2SM_DIV_53 02500 * @arg @ref LL_RCC_PLLI2SM_DIV_54 02501 * @arg @ref LL_RCC_PLLI2SM_DIV_55 02502 * @arg @ref LL_RCC_PLLI2SM_DIV_56 02503 * @arg @ref LL_RCC_PLLI2SM_DIV_57 02504 * @arg @ref LL_RCC_PLLI2SM_DIV_58 02505 * @arg @ref LL_RCC_PLLI2SM_DIV_59 02506 * @arg @ref LL_RCC_PLLI2SM_DIV_60 02507 * @arg @ref LL_RCC_PLLI2SM_DIV_61 02508 * @arg @ref LL_RCC_PLLI2SM_DIV_62 02509 * @arg @ref LL_RCC_PLLI2SM_DIV_63 02510 * @param __PLLI2SN__ Between 50/192(*) and 432 02511 * 02512 * (*) value not defined in all devices. 02513 * @param __PLLI2SQ_R__ This parameter can be one of the following values: 02514 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*) 02515 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*) 02516 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*) 02517 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*) 02518 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*) 02519 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*) 02520 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*) 02521 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*) 02522 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*) 02523 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*) 02524 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*) 02525 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*) 02526 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*) 02527 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*) 02528 * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*) 02529 * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*) 02530 * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*) 02531 * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*) 02532 * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*) 02533 * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*) 02534 * 02535 * (*) value not defined in all devices. 02536 * @param __PLLI2SDIVQ_R__ This parameter can be one of the following values: 02537 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*) 02538 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*) 02539 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*) 02540 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*) 02541 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*) 02542 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*) 02543 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*) 02544 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*) 02545 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*) 02546 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*) 02547 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*) 02548 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*) 02549 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*) 02550 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*) 02551 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*) 02552 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*) 02553 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*) 02554 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*) 02555 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*) 02556 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*) 02557 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*) 02558 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*) 02559 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*) 02560 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*) 02561 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*) 02562 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*) 02563 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*) 02564 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*) 02565 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*) 02566 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*) 02567 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*) 02568 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*) 02569 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*) 02570 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*) 02571 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*) 02572 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*) 02573 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*) 02574 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*) 02575 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*) 02576 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*) 02577 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*) 02578 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*) 02579 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*) 02580 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*) 02581 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*) 02582 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*) 02583 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*) 02584 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*) 02585 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*) 02586 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*) 02587 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*) 02588 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*) 02589 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*) 02590 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*) 02591 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*) 02592 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*) 02593 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*) 02594 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*) 02595 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*) 02596 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*) 02597 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*) 02598 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*) 02599 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*) 02600 * 02601 * (*) value not defined in all devices. 02602 * @retval PLLI2S clock frequency (in Hz) 02603 */ 02604 #if defined(RCC_DCKCFGR_PLLI2SDIVQ) 02605 #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ 02606 (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U))) 02607 #else 02608 #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ 02609 (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos))) 02610 02611 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */ 02612 #endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */ 02613 02614 #if defined(SPDIFRX) 02615 /** 02616 * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain 02617 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), 02618 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ()); 02619 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 02620 * @param __PLLM__ This parameter can be one of the following values: 02621 * @arg @ref LL_RCC_PLLI2SM_DIV_2 02622 * @arg @ref LL_RCC_PLLI2SM_DIV_3 02623 * @arg @ref LL_RCC_PLLI2SM_DIV_4 02624 * @arg @ref LL_RCC_PLLI2SM_DIV_5 02625 * @arg @ref LL_RCC_PLLI2SM_DIV_6 02626 * @arg @ref LL_RCC_PLLI2SM_DIV_7 02627 * @arg @ref LL_RCC_PLLI2SM_DIV_8 02628 * @arg @ref LL_RCC_PLLI2SM_DIV_9 02629 * @arg @ref LL_RCC_PLLI2SM_DIV_10 02630 * @arg @ref LL_RCC_PLLI2SM_DIV_11 02631 * @arg @ref LL_RCC_PLLI2SM_DIV_12 02632 * @arg @ref LL_RCC_PLLI2SM_DIV_13 02633 * @arg @ref LL_RCC_PLLI2SM_DIV_14 02634 * @arg @ref LL_RCC_PLLI2SM_DIV_15 02635 * @arg @ref LL_RCC_PLLI2SM_DIV_16 02636 * @arg @ref LL_RCC_PLLI2SM_DIV_17 02637 * @arg @ref LL_RCC_PLLI2SM_DIV_18 02638 * @arg @ref LL_RCC_PLLI2SM_DIV_19 02639 * @arg @ref LL_RCC_PLLI2SM_DIV_20 02640 * @arg @ref LL_RCC_PLLI2SM_DIV_21 02641 * @arg @ref LL_RCC_PLLI2SM_DIV_22 02642 * @arg @ref LL_RCC_PLLI2SM_DIV_23 02643 * @arg @ref LL_RCC_PLLI2SM_DIV_24 02644 * @arg @ref LL_RCC_PLLI2SM_DIV_25 02645 * @arg @ref LL_RCC_PLLI2SM_DIV_26 02646 * @arg @ref LL_RCC_PLLI2SM_DIV_27 02647 * @arg @ref LL_RCC_PLLI2SM_DIV_28 02648 * @arg @ref LL_RCC_PLLI2SM_DIV_29 02649 * @arg @ref LL_RCC_PLLI2SM_DIV_30 02650 * @arg @ref LL_RCC_PLLI2SM_DIV_31 02651 * @arg @ref LL_RCC_PLLI2SM_DIV_32 02652 * @arg @ref LL_RCC_PLLI2SM_DIV_33 02653 * @arg @ref LL_RCC_PLLI2SM_DIV_34 02654 * @arg @ref LL_RCC_PLLI2SM_DIV_35 02655 * @arg @ref LL_RCC_PLLI2SM_DIV_36 02656 * @arg @ref LL_RCC_PLLI2SM_DIV_37 02657 * @arg @ref LL_RCC_PLLI2SM_DIV_38 02658 * @arg @ref LL_RCC_PLLI2SM_DIV_39 02659 * @arg @ref LL_RCC_PLLI2SM_DIV_40 02660 * @arg @ref LL_RCC_PLLI2SM_DIV_41 02661 * @arg @ref LL_RCC_PLLI2SM_DIV_42 02662 * @arg @ref LL_RCC_PLLI2SM_DIV_43 02663 * @arg @ref LL_RCC_PLLI2SM_DIV_44 02664 * @arg @ref LL_RCC_PLLI2SM_DIV_45 02665 * @arg @ref LL_RCC_PLLI2SM_DIV_46 02666 * @arg @ref LL_RCC_PLLI2SM_DIV_47 02667 * @arg @ref LL_RCC_PLLI2SM_DIV_48 02668 * @arg @ref LL_RCC_PLLI2SM_DIV_49 02669 * @arg @ref LL_RCC_PLLI2SM_DIV_50 02670 * @arg @ref LL_RCC_PLLI2SM_DIV_51 02671 * @arg @ref LL_RCC_PLLI2SM_DIV_52 02672 * @arg @ref LL_RCC_PLLI2SM_DIV_53 02673 * @arg @ref LL_RCC_PLLI2SM_DIV_54 02674 * @arg @ref LL_RCC_PLLI2SM_DIV_55 02675 * @arg @ref LL_RCC_PLLI2SM_DIV_56 02676 * @arg @ref LL_RCC_PLLI2SM_DIV_57 02677 * @arg @ref LL_RCC_PLLI2SM_DIV_58 02678 * @arg @ref LL_RCC_PLLI2SM_DIV_59 02679 * @arg @ref LL_RCC_PLLI2SM_DIV_60 02680 * @arg @ref LL_RCC_PLLI2SM_DIV_61 02681 * @arg @ref LL_RCC_PLLI2SM_DIV_62 02682 * @arg @ref LL_RCC_PLLI2SM_DIV_63 02683 * @param __PLLI2SN__ Between 50 and 432 02684 * @param __PLLI2SP__ This parameter can be one of the following values: 02685 * @arg @ref LL_RCC_PLLI2SP_DIV_2 02686 * @arg @ref LL_RCC_PLLI2SP_DIV_4 02687 * @arg @ref LL_RCC_PLLI2SP_DIV_6 02688 * @arg @ref LL_RCC_PLLI2SP_DIV_8 02689 * @retval PLLI2S clock frequency (in Hz) 02690 */ 02691 #define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ 02692 ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U)) 02693 02694 #endif /* SPDIFRX */ 02695 02696 /** 02697 * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain 02698 * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), 02699 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ()); 02700 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 02701 * @param __PLLM__ This parameter can be one of the following values: 02702 * @arg @ref LL_RCC_PLLI2SM_DIV_2 02703 * @arg @ref LL_RCC_PLLI2SM_DIV_3 02704 * @arg @ref LL_RCC_PLLI2SM_DIV_4 02705 * @arg @ref LL_RCC_PLLI2SM_DIV_5 02706 * @arg @ref LL_RCC_PLLI2SM_DIV_6 02707 * @arg @ref LL_RCC_PLLI2SM_DIV_7 02708 * @arg @ref LL_RCC_PLLI2SM_DIV_8 02709 * @arg @ref LL_RCC_PLLI2SM_DIV_9 02710 * @arg @ref LL_RCC_PLLI2SM_DIV_10 02711 * @arg @ref LL_RCC_PLLI2SM_DIV_11 02712 * @arg @ref LL_RCC_PLLI2SM_DIV_12 02713 * @arg @ref LL_RCC_PLLI2SM_DIV_13 02714 * @arg @ref LL_RCC_PLLI2SM_DIV_14 02715 * @arg @ref LL_RCC_PLLI2SM_DIV_15 02716 * @arg @ref LL_RCC_PLLI2SM_DIV_16 02717 * @arg @ref LL_RCC_PLLI2SM_DIV_17 02718 * @arg @ref LL_RCC_PLLI2SM_DIV_18 02719 * @arg @ref LL_RCC_PLLI2SM_DIV_19 02720 * @arg @ref LL_RCC_PLLI2SM_DIV_20 02721 * @arg @ref LL_RCC_PLLI2SM_DIV_21 02722 * @arg @ref LL_RCC_PLLI2SM_DIV_22 02723 * @arg @ref LL_RCC_PLLI2SM_DIV_23 02724 * @arg @ref LL_RCC_PLLI2SM_DIV_24 02725 * @arg @ref LL_RCC_PLLI2SM_DIV_25 02726 * @arg @ref LL_RCC_PLLI2SM_DIV_26 02727 * @arg @ref LL_RCC_PLLI2SM_DIV_27 02728 * @arg @ref LL_RCC_PLLI2SM_DIV_28 02729 * @arg @ref LL_RCC_PLLI2SM_DIV_29 02730 * @arg @ref LL_RCC_PLLI2SM_DIV_30 02731 * @arg @ref LL_RCC_PLLI2SM_DIV_31 02732 * @arg @ref LL_RCC_PLLI2SM_DIV_32 02733 * @arg @ref LL_RCC_PLLI2SM_DIV_33 02734 * @arg @ref LL_RCC_PLLI2SM_DIV_34 02735 * @arg @ref LL_RCC_PLLI2SM_DIV_35 02736 * @arg @ref LL_RCC_PLLI2SM_DIV_36 02737 * @arg @ref LL_RCC_PLLI2SM_DIV_37 02738 * @arg @ref LL_RCC_PLLI2SM_DIV_38 02739 * @arg @ref LL_RCC_PLLI2SM_DIV_39 02740 * @arg @ref LL_RCC_PLLI2SM_DIV_40 02741 * @arg @ref LL_RCC_PLLI2SM_DIV_41 02742 * @arg @ref LL_RCC_PLLI2SM_DIV_42 02743 * @arg @ref LL_RCC_PLLI2SM_DIV_43 02744 * @arg @ref LL_RCC_PLLI2SM_DIV_44 02745 * @arg @ref LL_RCC_PLLI2SM_DIV_45 02746 * @arg @ref LL_RCC_PLLI2SM_DIV_46 02747 * @arg @ref LL_RCC_PLLI2SM_DIV_47 02748 * @arg @ref LL_RCC_PLLI2SM_DIV_48 02749 * @arg @ref LL_RCC_PLLI2SM_DIV_49 02750 * @arg @ref LL_RCC_PLLI2SM_DIV_50 02751 * @arg @ref LL_RCC_PLLI2SM_DIV_51 02752 * @arg @ref LL_RCC_PLLI2SM_DIV_52 02753 * @arg @ref LL_RCC_PLLI2SM_DIV_53 02754 * @arg @ref LL_RCC_PLLI2SM_DIV_54 02755 * @arg @ref LL_RCC_PLLI2SM_DIV_55 02756 * @arg @ref LL_RCC_PLLI2SM_DIV_56 02757 * @arg @ref LL_RCC_PLLI2SM_DIV_57 02758 * @arg @ref LL_RCC_PLLI2SM_DIV_58 02759 * @arg @ref LL_RCC_PLLI2SM_DIV_59 02760 * @arg @ref LL_RCC_PLLI2SM_DIV_60 02761 * @arg @ref LL_RCC_PLLI2SM_DIV_61 02762 * @arg @ref LL_RCC_PLLI2SM_DIV_62 02763 * @arg @ref LL_RCC_PLLI2SM_DIV_63 02764 * @param __PLLI2SN__ Between 50/192(*) and 432 02765 * 02766 * (*) value not defined in all devices. 02767 * @param __PLLI2SR__ This parameter can be one of the following values: 02768 * @arg @ref LL_RCC_PLLI2SR_DIV_2 02769 * @arg @ref LL_RCC_PLLI2SR_DIV_3 02770 * @arg @ref LL_RCC_PLLI2SR_DIV_4 02771 * @arg @ref LL_RCC_PLLI2SR_DIV_5 02772 * @arg @ref LL_RCC_PLLI2SR_DIV_6 02773 * @arg @ref LL_RCC_PLLI2SR_DIV_7 02774 * @retval PLLI2S clock frequency (in Hz) 02775 */ 02776 #define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ 02777 ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos)) 02778 02779 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) 02780 /** 02781 * @brief Helper macro to calculate the PLLI2S frequency used for 48Mhz domain 02782 * @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), 02783 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ()); 02784 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 02785 * @param __PLLM__ This parameter can be one of the following values: 02786 * @arg @ref LL_RCC_PLLI2SM_DIV_2 02787 * @arg @ref LL_RCC_PLLI2SM_DIV_3 02788 * @arg @ref LL_RCC_PLLI2SM_DIV_4 02789 * @arg @ref LL_RCC_PLLI2SM_DIV_5 02790 * @arg @ref LL_RCC_PLLI2SM_DIV_6 02791 * @arg @ref LL_RCC_PLLI2SM_DIV_7 02792 * @arg @ref LL_RCC_PLLI2SM_DIV_8 02793 * @arg @ref LL_RCC_PLLI2SM_DIV_9 02794 * @arg @ref LL_RCC_PLLI2SM_DIV_10 02795 * @arg @ref LL_RCC_PLLI2SM_DIV_11 02796 * @arg @ref LL_RCC_PLLI2SM_DIV_12 02797 * @arg @ref LL_RCC_PLLI2SM_DIV_13 02798 * @arg @ref LL_RCC_PLLI2SM_DIV_14 02799 * @arg @ref LL_RCC_PLLI2SM_DIV_15 02800 * @arg @ref LL_RCC_PLLI2SM_DIV_16 02801 * @arg @ref LL_RCC_PLLI2SM_DIV_17 02802 * @arg @ref LL_RCC_PLLI2SM_DIV_18 02803 * @arg @ref LL_RCC_PLLI2SM_DIV_19 02804 * @arg @ref LL_RCC_PLLI2SM_DIV_20 02805 * @arg @ref LL_RCC_PLLI2SM_DIV_21 02806 * @arg @ref LL_RCC_PLLI2SM_DIV_22 02807 * @arg @ref LL_RCC_PLLI2SM_DIV_23 02808 * @arg @ref LL_RCC_PLLI2SM_DIV_24 02809 * @arg @ref LL_RCC_PLLI2SM_DIV_25 02810 * @arg @ref LL_RCC_PLLI2SM_DIV_26 02811 * @arg @ref LL_RCC_PLLI2SM_DIV_27 02812 * @arg @ref LL_RCC_PLLI2SM_DIV_28 02813 * @arg @ref LL_RCC_PLLI2SM_DIV_29 02814 * @arg @ref LL_RCC_PLLI2SM_DIV_30 02815 * @arg @ref LL_RCC_PLLI2SM_DIV_31 02816 * @arg @ref LL_RCC_PLLI2SM_DIV_32 02817 * @arg @ref LL_RCC_PLLI2SM_DIV_33 02818 * @arg @ref LL_RCC_PLLI2SM_DIV_34 02819 * @arg @ref LL_RCC_PLLI2SM_DIV_35 02820 * @arg @ref LL_RCC_PLLI2SM_DIV_36 02821 * @arg @ref LL_RCC_PLLI2SM_DIV_37 02822 * @arg @ref LL_RCC_PLLI2SM_DIV_38 02823 * @arg @ref LL_RCC_PLLI2SM_DIV_39 02824 * @arg @ref LL_RCC_PLLI2SM_DIV_40 02825 * @arg @ref LL_RCC_PLLI2SM_DIV_41 02826 * @arg @ref LL_RCC_PLLI2SM_DIV_42 02827 * @arg @ref LL_RCC_PLLI2SM_DIV_43 02828 * @arg @ref LL_RCC_PLLI2SM_DIV_44 02829 * @arg @ref LL_RCC_PLLI2SM_DIV_45 02830 * @arg @ref LL_RCC_PLLI2SM_DIV_46 02831 * @arg @ref LL_RCC_PLLI2SM_DIV_47 02832 * @arg @ref LL_RCC_PLLI2SM_DIV_48 02833 * @arg @ref LL_RCC_PLLI2SM_DIV_49 02834 * @arg @ref LL_RCC_PLLI2SM_DIV_50 02835 * @arg @ref LL_RCC_PLLI2SM_DIV_51 02836 * @arg @ref LL_RCC_PLLI2SM_DIV_52 02837 * @arg @ref LL_RCC_PLLI2SM_DIV_53 02838 * @arg @ref LL_RCC_PLLI2SM_DIV_54 02839 * @arg @ref LL_RCC_PLLI2SM_DIV_55 02840 * @arg @ref LL_RCC_PLLI2SM_DIV_56 02841 * @arg @ref LL_RCC_PLLI2SM_DIV_57 02842 * @arg @ref LL_RCC_PLLI2SM_DIV_58 02843 * @arg @ref LL_RCC_PLLI2SM_DIV_59 02844 * @arg @ref LL_RCC_PLLI2SM_DIV_60 02845 * @arg @ref LL_RCC_PLLI2SM_DIV_61 02846 * @arg @ref LL_RCC_PLLI2SM_DIV_62 02847 * @arg @ref LL_RCC_PLLI2SM_DIV_63 02848 * @param __PLLI2SN__ Between 50 and 432 02849 * @param __PLLI2SQ__ This parameter can be one of the following values: 02850 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 02851 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 02852 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 02853 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 02854 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 02855 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 02856 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 02857 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 02858 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 02859 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 02860 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 02861 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 02862 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 02863 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 02864 * @retval PLLI2S clock frequency (in Hz) 02865 */ 02866 #define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ 02867 ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos)) 02868 02869 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ 02870 #endif /* RCC_PLLI2S_SUPPORT */ 02871 02872 /** 02873 * @brief Helper macro to calculate the HCLK frequency 02874 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) 02875 * @param __AHBPRESCALER__ This parameter can be one of the following values: 02876 * @arg @ref LL_RCC_SYSCLK_DIV_1 02877 * @arg @ref LL_RCC_SYSCLK_DIV_2 02878 * @arg @ref LL_RCC_SYSCLK_DIV_4 02879 * @arg @ref LL_RCC_SYSCLK_DIV_8 02880 * @arg @ref LL_RCC_SYSCLK_DIV_16 02881 * @arg @ref LL_RCC_SYSCLK_DIV_64 02882 * @arg @ref LL_RCC_SYSCLK_DIV_128 02883 * @arg @ref LL_RCC_SYSCLK_DIV_256 02884 * @arg @ref LL_RCC_SYSCLK_DIV_512 02885 * @retval HCLK clock frequency (in Hz) 02886 */ 02887 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) 02888 02889 /** 02890 * @brief Helper macro to calculate the PCLK1 frequency (ABP1) 02891 * @param __HCLKFREQ__ HCLK frequency 02892 * @param __APB1PRESCALER__ This parameter can be one of the following values: 02893 * @arg @ref LL_RCC_APB1_DIV_1 02894 * @arg @ref LL_RCC_APB1_DIV_2 02895 * @arg @ref LL_RCC_APB1_DIV_4 02896 * @arg @ref LL_RCC_APB1_DIV_8 02897 * @arg @ref LL_RCC_APB1_DIV_16 02898 * @retval PCLK1 clock frequency (in Hz) 02899 */ 02900 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) 02901 02902 /** 02903 * @brief Helper macro to calculate the PCLK2 frequency (ABP2) 02904 * @param __HCLKFREQ__ HCLK frequency 02905 * @param __APB2PRESCALER__ This parameter can be one of the following values: 02906 * @arg @ref LL_RCC_APB2_DIV_1 02907 * @arg @ref LL_RCC_APB2_DIV_2 02908 * @arg @ref LL_RCC_APB2_DIV_4 02909 * @arg @ref LL_RCC_APB2_DIV_8 02910 * @arg @ref LL_RCC_APB2_DIV_16 02911 * @retval PCLK2 clock frequency (in Hz) 02912 */ 02913 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) 02914 02915 /** 02916 * @} 02917 */ 02918 02919 /** 02920 * @} 02921 */ 02922 02923 /* Exported functions --------------------------------------------------------*/ 02924 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions 02925 * @{ 02926 */ 02927 02928 /** @defgroup RCC_LL_EF_HSE HSE 02929 * @{ 02930 */ 02931 02932 /** 02933 * @brief Enable the Clock Security System. 02934 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS 02935 * @retval None 02936 */ 02937 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) 02938 { 02939 SET_BIT(RCC->CR, RCC_CR_CSSON); 02940 } 02941 02942 /** 02943 * @brief Enable HSE external oscillator (HSE Bypass) 02944 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass 02945 * @retval None 02946 */ 02947 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) 02948 { 02949 SET_BIT(RCC->CR, RCC_CR_HSEBYP); 02950 } 02951 02952 /** 02953 * @brief Disable HSE external oscillator (HSE Bypass) 02954 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass 02955 * @retval None 02956 */ 02957 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) 02958 { 02959 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 02960 } 02961 02962 /** 02963 * @brief Enable HSE crystal oscillator (HSE ON) 02964 * @rmtoll CR HSEON LL_RCC_HSE_Enable 02965 * @retval None 02966 */ 02967 __STATIC_INLINE void LL_RCC_HSE_Enable(void) 02968 { 02969 SET_BIT(RCC->CR, RCC_CR_HSEON); 02970 } 02971 02972 /** 02973 * @brief Disable HSE crystal oscillator (HSE ON) 02974 * @rmtoll CR HSEON LL_RCC_HSE_Disable 02975 * @retval None 02976 */ 02977 __STATIC_INLINE void LL_RCC_HSE_Disable(void) 02978 { 02979 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); 02980 } 02981 02982 /** 02983 * @brief Check if HSE oscillator Ready 02984 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady 02985 * @retval State of bit (1 or 0). 02986 */ 02987 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) 02988 { 02989 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); 02990 } 02991 02992 /** 02993 * @} 02994 */ 02995 02996 /** @defgroup RCC_LL_EF_HSI HSI 02997 * @{ 02998 */ 02999 03000 /** 03001 * @brief Enable HSI oscillator 03002 * @rmtoll CR HSION LL_RCC_HSI_Enable 03003 * @retval None 03004 */ 03005 __STATIC_INLINE void LL_RCC_HSI_Enable(void) 03006 { 03007 SET_BIT(RCC->CR, RCC_CR_HSION); 03008 } 03009 03010 /** 03011 * @brief Disable HSI oscillator 03012 * @rmtoll CR HSION LL_RCC_HSI_Disable 03013 * @retval None 03014 */ 03015 __STATIC_INLINE void LL_RCC_HSI_Disable(void) 03016 { 03017 CLEAR_BIT(RCC->CR, RCC_CR_HSION); 03018 } 03019 03020 /** 03021 * @brief Check if HSI clock is ready 03022 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady 03023 * @retval State of bit (1 or 0). 03024 */ 03025 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) 03026 { 03027 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); 03028 } 03029 03030 /** 03031 * @brief Get HSI Calibration value 03032 * @note When HSITRIM is written, HSICAL is updated with the sum of 03033 * HSITRIM and the factory trim value 03034 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration 03035 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF 03036 */ 03037 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) 03038 { 03039 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); 03040 } 03041 03042 /** 03043 * @brief Set HSI Calibration trimming 03044 * @note user-programmable trimming value that is added to the HSICAL 03045 * @note Default value is 16, which, when added to the HSICAL value, 03046 * should trim the HSI to 16 MHz +/- 1 % 03047 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming 03048 * @param Value Between Min_Data = 0 and Max_Data = 31 03049 * @retval None 03050 */ 03051 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) 03052 { 03053 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); 03054 } 03055 03056 /** 03057 * @brief Get HSI Calibration trimming 03058 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming 03059 * @retval Between Min_Data = 0 and Max_Data = 31 03060 */ 03061 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) 03062 { 03063 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); 03064 } 03065 03066 /** 03067 * @} 03068 */ 03069 03070 /** @defgroup RCC_LL_EF_LSE LSE 03071 * @{ 03072 */ 03073 03074 /** 03075 * @brief Enable Low Speed External (LSE) crystal. 03076 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable 03077 * @retval None 03078 */ 03079 __STATIC_INLINE void LL_RCC_LSE_Enable(void) 03080 { 03081 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); 03082 } 03083 03084 /** 03085 * @brief Disable Low Speed External (LSE) crystal. 03086 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable 03087 * @retval None 03088 */ 03089 __STATIC_INLINE void LL_RCC_LSE_Disable(void) 03090 { 03091 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); 03092 } 03093 03094 /** 03095 * @brief Enable external clock source (LSE bypass). 03096 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass 03097 * @retval None 03098 */ 03099 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) 03100 { 03101 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 03102 } 03103 03104 /** 03105 * @brief Disable external clock source (LSE bypass). 03106 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass 03107 * @retval None 03108 */ 03109 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) 03110 { 03111 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 03112 } 03113 03114 /** 03115 * @brief Check if LSE oscillator Ready 03116 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady 03117 * @retval State of bit (1 or 0). 03118 */ 03119 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) 03120 { 03121 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); 03122 } 03123 03124 #if defined(RCC_BDCR_LSEMOD) 03125 /** 03126 * @brief Enable LSE high drive mode. 03127 * @note LSE high drive mode can be enabled only when the LSE clock is disabled 03128 * @rmtoll BDCR LSEMOD LL_RCC_LSE_EnableHighDriveMode 03129 * @retval None 03130 */ 03131 __STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void) 03132 { 03133 SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); 03134 } 03135 03136 /** 03137 * @brief Disable LSE high drive mode. 03138 * @note LSE high drive mode can be disabled only when the LSE clock is disabled 03139 * @rmtoll BDCR LSEMOD LL_RCC_LSE_DisableHighDriveMode 03140 * @retval None 03141 */ 03142 __STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void) 03143 { 03144 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); 03145 } 03146 #endif /* RCC_BDCR_LSEMOD */ 03147 03148 /** 03149 * @} 03150 */ 03151 03152 /** @defgroup RCC_LL_EF_LSI LSI 03153 * @{ 03154 */ 03155 03156 /** 03157 * @brief Enable LSI Oscillator 03158 * @rmtoll CSR LSION LL_RCC_LSI_Enable 03159 * @retval None 03160 */ 03161 __STATIC_INLINE void LL_RCC_LSI_Enable(void) 03162 { 03163 SET_BIT(RCC->CSR, RCC_CSR_LSION); 03164 } 03165 03166 /** 03167 * @brief Disable LSI Oscillator 03168 * @rmtoll CSR LSION LL_RCC_LSI_Disable 03169 * @retval None 03170 */ 03171 __STATIC_INLINE void LL_RCC_LSI_Disable(void) 03172 { 03173 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); 03174 } 03175 03176 /** 03177 * @brief Check if LSI is Ready 03178 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady 03179 * @retval State of bit (1 or 0). 03180 */ 03181 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) 03182 { 03183 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); 03184 } 03185 03186 /** 03187 * @} 03188 */ 03189 03190 /** @defgroup RCC_LL_EF_System System 03191 * @{ 03192 */ 03193 03194 /** 03195 * @brief Configure the system clock source 03196 * @rmtoll CFGR SW LL_RCC_SetSysClkSource 03197 * @param Source This parameter can be one of the following values: 03198 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI 03199 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE 03200 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL 03201 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*) 03202 * 03203 * (*) value not defined in all devices. 03204 * @retval None 03205 */ 03206 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) 03207 { 03208 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); 03209 } 03210 03211 /** 03212 * @brief Get the system clock source 03213 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource 03214 * @retval Returned value can be one of the following values: 03215 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI 03216 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE 03217 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL 03218 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*) 03219 * 03220 * (*) value not defined in all devices. 03221 */ 03222 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) 03223 { 03224 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); 03225 } 03226 03227 /** 03228 * @brief Set AHB prescaler 03229 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler 03230 * @param Prescaler This parameter can be one of the following values: 03231 * @arg @ref LL_RCC_SYSCLK_DIV_1 03232 * @arg @ref LL_RCC_SYSCLK_DIV_2 03233 * @arg @ref LL_RCC_SYSCLK_DIV_4 03234 * @arg @ref LL_RCC_SYSCLK_DIV_8 03235 * @arg @ref LL_RCC_SYSCLK_DIV_16 03236 * @arg @ref LL_RCC_SYSCLK_DIV_64 03237 * @arg @ref LL_RCC_SYSCLK_DIV_128 03238 * @arg @ref LL_RCC_SYSCLK_DIV_256 03239 * @arg @ref LL_RCC_SYSCLK_DIV_512 03240 * @retval None 03241 */ 03242 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) 03243 { 03244 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); 03245 } 03246 03247 /** 03248 * @brief Set APB1 prescaler 03249 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler 03250 * @param Prescaler This parameter can be one of the following values: 03251 * @arg @ref LL_RCC_APB1_DIV_1 03252 * @arg @ref LL_RCC_APB1_DIV_2 03253 * @arg @ref LL_RCC_APB1_DIV_4 03254 * @arg @ref LL_RCC_APB1_DIV_8 03255 * @arg @ref LL_RCC_APB1_DIV_16 03256 * @retval None 03257 */ 03258 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) 03259 { 03260 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); 03261 } 03262 03263 /** 03264 * @brief Set APB2 prescaler 03265 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler 03266 * @param Prescaler This parameter can be one of the following values: 03267 * @arg @ref LL_RCC_APB2_DIV_1 03268 * @arg @ref LL_RCC_APB2_DIV_2 03269 * @arg @ref LL_RCC_APB2_DIV_4 03270 * @arg @ref LL_RCC_APB2_DIV_8 03271 * @arg @ref LL_RCC_APB2_DIV_16 03272 * @retval None 03273 */ 03274 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) 03275 { 03276 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); 03277 } 03278 03279 /** 03280 * @brief Get AHB prescaler 03281 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler 03282 * @retval Returned value can be one of the following values: 03283 * @arg @ref LL_RCC_SYSCLK_DIV_1 03284 * @arg @ref LL_RCC_SYSCLK_DIV_2 03285 * @arg @ref LL_RCC_SYSCLK_DIV_4 03286 * @arg @ref LL_RCC_SYSCLK_DIV_8 03287 * @arg @ref LL_RCC_SYSCLK_DIV_16 03288 * @arg @ref LL_RCC_SYSCLK_DIV_64 03289 * @arg @ref LL_RCC_SYSCLK_DIV_128 03290 * @arg @ref LL_RCC_SYSCLK_DIV_256 03291 * @arg @ref LL_RCC_SYSCLK_DIV_512 03292 */ 03293 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) 03294 { 03295 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); 03296 } 03297 03298 /** 03299 * @brief Get APB1 prescaler 03300 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler 03301 * @retval Returned value can be one of the following values: 03302 * @arg @ref LL_RCC_APB1_DIV_1 03303 * @arg @ref LL_RCC_APB1_DIV_2 03304 * @arg @ref LL_RCC_APB1_DIV_4 03305 * @arg @ref LL_RCC_APB1_DIV_8 03306 * @arg @ref LL_RCC_APB1_DIV_16 03307 */ 03308 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) 03309 { 03310 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); 03311 } 03312 03313 /** 03314 * @brief Get APB2 prescaler 03315 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler 03316 * @retval Returned value can be one of the following values: 03317 * @arg @ref LL_RCC_APB2_DIV_1 03318 * @arg @ref LL_RCC_APB2_DIV_2 03319 * @arg @ref LL_RCC_APB2_DIV_4 03320 * @arg @ref LL_RCC_APB2_DIV_8 03321 * @arg @ref LL_RCC_APB2_DIV_16 03322 */ 03323 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) 03324 { 03325 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); 03326 } 03327 03328 /** 03329 * @} 03330 */ 03331 03332 /** @defgroup RCC_LL_EF_MCO MCO 03333 * @{ 03334 */ 03335 03336 #if defined(RCC_CFGR_MCO1EN) 03337 /** 03338 * @brief Enable MCO1 output 03339 * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Enable 03340 * @retval None 03341 */ 03342 __STATIC_INLINE void LL_RCC_MCO1_Enable(void) 03343 { 03344 SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN); 03345 } 03346 03347 /** 03348 * @brief Disable MCO1 output 03349 * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Disable 03350 * @retval None 03351 */ 03352 __STATIC_INLINE void LL_RCC_MCO1_Disable(void) 03353 { 03354 CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN); 03355 } 03356 #endif /* RCC_CFGR_MCO1EN */ 03357 03358 #if defined(RCC_CFGR_MCO2EN) 03359 /** 03360 * @brief Enable MCO2 output 03361 * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Enable 03362 * @retval None 03363 */ 03364 __STATIC_INLINE void LL_RCC_MCO2_Enable(void) 03365 { 03366 SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN); 03367 } 03368 03369 /** 03370 * @brief Disable MCO2 output 03371 * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Disable 03372 * @retval None 03373 */ 03374 __STATIC_INLINE void LL_RCC_MCO2_Disable(void) 03375 { 03376 CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN); 03377 } 03378 #endif /* RCC_CFGR_MCO2EN */ 03379 03380 /** 03381 * @brief Configure MCOx 03382 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n 03383 * CFGR MCO1PRE LL_RCC_ConfigMCO\n 03384 * CFGR MCO2 LL_RCC_ConfigMCO\n 03385 * CFGR MCO2PRE LL_RCC_ConfigMCO 03386 * @param MCOxSource This parameter can be one of the following values: 03387 * @arg @ref LL_RCC_MCO1SOURCE_HSI 03388 * @arg @ref LL_RCC_MCO1SOURCE_LSE 03389 * @arg @ref LL_RCC_MCO1SOURCE_HSE 03390 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK 03391 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK 03392 * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S 03393 * @arg @ref LL_RCC_MCO2SOURCE_HSE 03394 * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK 03395 * @param MCOxPrescaler This parameter can be one of the following values: 03396 * @arg @ref LL_RCC_MCO1_DIV_1 03397 * @arg @ref LL_RCC_MCO1_DIV_2 03398 * @arg @ref LL_RCC_MCO1_DIV_3 03399 * @arg @ref LL_RCC_MCO1_DIV_4 03400 * @arg @ref LL_RCC_MCO1_DIV_5 03401 * @arg @ref LL_RCC_MCO2_DIV_1 03402 * @arg @ref LL_RCC_MCO2_DIV_2 03403 * @arg @ref LL_RCC_MCO2_DIV_3 03404 * @arg @ref LL_RCC_MCO2_DIV_4 03405 * @arg @ref LL_RCC_MCO2_DIV_5 03406 * @retval None 03407 */ 03408 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) 03409 { 03410 MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U)); 03411 } 03412 03413 /** 03414 * @} 03415 */ 03416 03417 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source 03418 * @{ 03419 */ 03420 #if defined(FMPI2C1) 03421 /** 03422 * @brief Configure FMPI2C clock source 03423 * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_SetFMPI2CClockSource 03424 * @param FMPI2CxSource This parameter can be one of the following values: 03425 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 03426 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK 03427 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI 03428 * @retval None 03429 */ 03430 __STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource) 03431 { 03432 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource); 03433 } 03434 #endif /* FMPI2C1 */ 03435 03436 #if defined(LPTIM1) 03437 /** 03438 * @brief Configure LPTIMx clock source 03439 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource 03440 * @param LPTIMxSource This parameter can be one of the following values: 03441 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 03442 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI 03443 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI 03444 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE 03445 * @retval None 03446 */ 03447 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) 03448 { 03449 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource); 03450 } 03451 #endif /* LPTIM1 */ 03452 03453 #if defined(SAI1) 03454 /** 03455 * @brief Configure SAIx clock source 03456 * @rmtoll DCKCFGR SAI1SRC LL_RCC_SetSAIClockSource\n 03457 * DCKCFGR SAI2SRC LL_RCC_SetSAIClockSource\n 03458 * DCKCFGR SAI1ASRC LL_RCC_SetSAIClockSource\n 03459 * DCKCFGR SAI1BSRC LL_RCC_SetSAIClockSource 03460 * @param SAIxSource This parameter can be one of the following values: 03461 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*) 03462 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*) 03463 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*) 03464 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*) 03465 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*) 03466 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*) 03467 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) 03468 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) 03469 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*) 03470 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*) 03471 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*) 03472 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*) 03473 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*) 03474 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*) 03475 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*) 03476 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*) 03477 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*) 03478 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*) 03479 * 03480 * (*) value not defined in all devices. 03481 * @retval None 03482 */ 03483 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) 03484 { 03485 MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); 03486 } 03487 #endif /* SAI1 */ 03488 03489 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) 03490 /** 03491 * @brief Configure SDIO clock source 03492 * @rmtoll DCKCFGR SDIOSEL LL_RCC_SetSDIOClockSource\n 03493 * DCKCFGR2 SDIOSEL LL_RCC_SetSDIOClockSource 03494 * @param SDIOxSource This parameter can be one of the following values: 03495 * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK 03496 * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK 03497 * @retval None 03498 */ 03499 __STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource) 03500 { 03501 #if defined(RCC_DCKCFGR_SDIOSEL) 03502 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource); 03503 #else 03504 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource); 03505 #endif /* RCC_DCKCFGR_SDIOSEL */ 03506 } 03507 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ 03508 03509 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) 03510 /** 03511 * @brief Configure 48Mhz domain clock source 03512 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetCK48MClockSource\n 03513 * DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource 03514 * @param CK48MxSource This parameter can be one of the following values: 03515 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL 03516 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*) 03517 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*) 03518 * 03519 * (*) value not defined in all devices. 03520 * @retval None 03521 */ 03522 __STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource) 03523 { 03524 #if defined(RCC_DCKCFGR_CK48MSEL) 03525 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource); 03526 #else 03527 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource); 03528 #endif /* RCC_DCKCFGR_CK48MSEL */ 03529 } 03530 03531 #if defined(RNG) 03532 /** 03533 * @brief Configure RNG clock source 03534 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetRNGClockSource\n 03535 * DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource 03536 * @param RNGxSource This parameter can be one of the following values: 03537 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL 03538 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*) 03539 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*) 03540 * 03541 * (*) value not defined in all devices. 03542 * @retval None 03543 */ 03544 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) 03545 { 03546 #if defined(RCC_DCKCFGR_CK48MSEL) 03547 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource); 03548 #else 03549 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource); 03550 #endif /* RCC_DCKCFGR_CK48MSEL */ 03551 } 03552 #endif /* RNG */ 03553 03554 #if defined(USB_OTG_FS) || defined(USB_OTG_HS) 03555 /** 03556 * @brief Configure USB clock source 03557 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetUSBClockSource\n 03558 * DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource 03559 * @param USBxSource This parameter can be one of the following values: 03560 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL 03561 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*) 03562 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*) 03563 * 03564 * (*) value not defined in all devices. 03565 * @retval None 03566 */ 03567 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) 03568 { 03569 #if defined(RCC_DCKCFGR_CK48MSEL) 03570 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource); 03571 #else 03572 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource); 03573 #endif /* RCC_DCKCFGR_CK48MSEL */ 03574 } 03575 #endif /* USB_OTG_FS || USB_OTG_HS */ 03576 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ 03577 03578 #if defined(CEC) 03579 /** 03580 * @brief Configure CEC clock source 03581 * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource 03582 * @param Source This parameter can be one of the following values: 03583 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 03584 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE 03585 * @retval None 03586 */ 03587 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source) 03588 { 03589 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source); 03590 } 03591 #endif /* CEC */ 03592 03593 /** 03594 * @brief Configure I2S clock source 03595 * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource\n 03596 * DCKCFGR I2SSRC LL_RCC_SetI2SClockSource\n 03597 * DCKCFGR I2S1SRC LL_RCC_SetI2SClockSource\n 03598 * DCKCFGR I2S2SRC LL_RCC_SetI2SClockSource 03599 * @param Source This parameter can be one of the following values: 03600 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*) 03601 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN 03602 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*) 03603 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*) 03604 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*) 03605 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*) 03606 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*) 03607 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*) 03608 * 03609 * (*) value not defined in all devices. 03610 * @retval None 03611 */ 03612 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source) 03613 { 03614 #if defined(RCC_CFGR_I2SSRC) 03615 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source); 03616 #else 03617 MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U)); 03618 #endif /* RCC_CFGR_I2SSRC */ 03619 } 03620 03621 #if defined(DSI) 03622 /** 03623 * @brief Configure DSI clock source 03624 * @rmtoll DCKCFGR DSISEL LL_RCC_SetDSIClockSource 03625 * @param Source This parameter can be one of the following values: 03626 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY 03627 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL 03628 * @retval None 03629 */ 03630 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) 03631 { 03632 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source); 03633 } 03634 #endif /* DSI */ 03635 03636 #if defined(DFSDM1_Channel0) 03637 /** 03638 * @brief Configure DFSDM Audio clock source 03639 * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_SetDFSDMAudioClockSource\n 03640 * DCKCFGR CKDFSDM2ASEL LL_RCC_SetDFSDMAudioClockSource 03641 * @param Source This parameter can be one of the following values: 03642 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 03643 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 03644 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*) 03645 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*) 03646 * 03647 * (*) value not defined in all devices. 03648 * @retval None 03649 */ 03650 __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source) 03651 { 03652 MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U)); 03653 } 03654 03655 /** 03656 * @brief Configure DFSDM Kernel clock source 03657 * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_SetDFSDMClockSource 03658 * @param Source This parameter can be one of the following values: 03659 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 03660 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK 03661 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*) 03662 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*) 03663 * 03664 * (*) value not defined in all devices. 03665 * @retval None 03666 */ 03667 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source) 03668 { 03669 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source); 03670 } 03671 #endif /* DFSDM1_Channel0 */ 03672 03673 #if defined(SPDIFRX) 03674 /** 03675 * @brief Configure SPDIFRX clock source 03676 * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource 03677 * @param SPDIFRXxSource This parameter can be one of the following values: 03678 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL 03679 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S 03680 * 03681 * (*) value not defined in all devices. 03682 * @retval None 03683 */ 03684 __STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource) 03685 { 03686 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource); 03687 } 03688 #endif /* SPDIFRX */ 03689 03690 #if defined(FMPI2C1) 03691 /** 03692 * @brief Get FMPI2C clock source 03693 * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_GetFMPI2CClockSource 03694 * @param FMPI2Cx This parameter can be one of the following values: 03695 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE 03696 * @retval Returned value can be one of the following values: 03697 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 03698 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK 03699 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI 03700 */ 03701 __STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx) 03702 { 03703 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx)); 03704 } 03705 #endif /* FMPI2C1 */ 03706 03707 #if defined(LPTIM1) 03708 /** 03709 * @brief Get LPTIMx clock source 03710 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource 03711 * @param LPTIMx This parameter can be one of the following values: 03712 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE 03713 * @retval Returned value can be one of the following values: 03714 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 03715 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI 03716 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI 03717 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE 03718 */ 03719 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) 03720 { 03721 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)); 03722 } 03723 #endif /* LPTIM1 */ 03724 03725 #if defined(SAI1) 03726 /** 03727 * @brief Get SAIx clock source 03728 * @rmtoll DCKCFGR SAI1SEL LL_RCC_GetSAIClockSource\n 03729 * DCKCFGR SAI2SEL LL_RCC_GetSAIClockSource\n 03730 * DCKCFGR SAI1ASRC LL_RCC_GetSAIClockSource\n 03731 * DCKCFGR SAI1BSRC LL_RCC_GetSAIClockSource 03732 * @param SAIx This parameter can be one of the following values: 03733 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*) 03734 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) 03735 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*) 03736 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*) 03737 * 03738 * (*) value not defined in all devices. 03739 * @retval Returned value can be one of the following values: 03740 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*) 03741 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*) 03742 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*) 03743 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*) 03744 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*) 03745 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*) 03746 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) 03747 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) 03748 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*) 03749 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*) 03750 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*) 03751 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*) 03752 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*) 03753 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*) 03754 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*) 03755 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*) 03756 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*) 03757 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*) 03758 * 03759 * (*) value not defined in all devices. 03760 */ 03761 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) 03762 { 03763 return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx); 03764 } 03765 #endif /* SAI1 */ 03766 03767 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) 03768 /** 03769 * @brief Get SDIOx clock source 03770 * @rmtoll DCKCFGR SDIOSEL LL_RCC_GetSDIOClockSource\n 03771 * DCKCFGR2 SDIOSEL LL_RCC_GetSDIOClockSource 03772 * @param SDIOx This parameter can be one of the following values: 03773 * @arg @ref LL_RCC_SDIO_CLKSOURCE 03774 * @retval Returned value can be one of the following values: 03775 * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK 03776 * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK 03777 */ 03778 __STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx) 03779 { 03780 #if defined(RCC_DCKCFGR_SDIOSEL) 03781 return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx)); 03782 #else 03783 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx)); 03784 #endif /* RCC_DCKCFGR_SDIOSEL */ 03785 } 03786 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ 03787 03788 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) 03789 /** 03790 * @brief Get 48Mhz domain clock source 03791 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetCK48MClockSource\n 03792 * DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource 03793 * @param CK48Mx This parameter can be one of the following values: 03794 * @arg @ref LL_RCC_CK48M_CLKSOURCE 03795 * @retval Returned value can be one of the following values: 03796 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL 03797 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*) 03798 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*) 03799 * 03800 * (*) value not defined in all devices. 03801 */ 03802 __STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx) 03803 { 03804 #if defined(RCC_DCKCFGR_CK48MSEL) 03805 return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx)); 03806 #else 03807 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx)); 03808 #endif /* RCC_DCKCFGR_CK48MSEL */ 03809 } 03810 03811 #if defined(RNG) 03812 /** 03813 * @brief Get RNGx clock source 03814 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetRNGClockSource\n 03815 * DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource 03816 * @param RNGx This parameter can be one of the following values: 03817 * @arg @ref LL_RCC_RNG_CLKSOURCE 03818 * @retval Returned value can be one of the following values: 03819 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL 03820 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*) 03821 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*) 03822 * 03823 * (*) value not defined in all devices. 03824 */ 03825 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) 03826 { 03827 #if defined(RCC_DCKCFGR_CK48MSEL) 03828 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx)); 03829 #else 03830 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx)); 03831 #endif /* RCC_DCKCFGR_CK48MSEL */ 03832 } 03833 #endif /* RNG */ 03834 03835 #if defined(USB_OTG_FS) || defined(USB_OTG_HS) 03836 /** 03837 * @brief Get USBx clock source 03838 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetUSBClockSource\n 03839 * DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource 03840 * @param USBx This parameter can be one of the following values: 03841 * @arg @ref LL_RCC_USB_CLKSOURCE 03842 * @retval Returned value can be one of the following values: 03843 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL 03844 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*) 03845 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*) 03846 * 03847 * (*) value not defined in all devices. 03848 */ 03849 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) 03850 { 03851 #if defined(RCC_DCKCFGR_CK48MSEL) 03852 return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx)); 03853 #else 03854 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx)); 03855 #endif /* RCC_DCKCFGR_CK48MSEL */ 03856 } 03857 #endif /* USB_OTG_FS || USB_OTG_HS */ 03858 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ 03859 03860 #if defined(CEC) 03861 /** 03862 * @brief Get CEC Clock Source 03863 * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource 03864 * @param CECx This parameter can be one of the following values: 03865 * @arg @ref LL_RCC_CEC_CLKSOURCE 03866 * @retval Returned value can be one of the following values: 03867 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 03868 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE 03869 */ 03870 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) 03871 { 03872 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx)); 03873 } 03874 #endif /* CEC */ 03875 03876 /** 03877 * @brief Get I2S Clock Source 03878 * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource\n 03879 * DCKCFGR I2SSRC LL_RCC_GetI2SClockSource\n 03880 * DCKCFGR I2S1SRC LL_RCC_GetI2SClockSource\n 03881 * DCKCFGR I2S2SRC LL_RCC_GetI2SClockSource 03882 * @param I2Sx This parameter can be one of the following values: 03883 * @arg @ref LL_RCC_I2S1_CLKSOURCE 03884 * @arg @ref LL_RCC_I2S2_CLKSOURCE (*) 03885 * @retval Returned value can be one of the following values: 03886 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*) 03887 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN 03888 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*) 03889 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*) 03890 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*) 03891 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*) 03892 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*) 03893 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*) 03894 * 03895 * (*) value not defined in all devices. 03896 */ 03897 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) 03898 { 03899 #if defined(RCC_CFGR_I2SSRC) 03900 return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx)); 03901 #else 03902 return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx); 03903 #endif /* RCC_CFGR_I2SSRC */ 03904 } 03905 03906 #if defined(DFSDM1_Channel0) 03907 /** 03908 * @brief Get DFSDM Audio Clock Source 03909 * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_GetDFSDMAudioClockSource\n 03910 * DCKCFGR CKDFSDM2ASEL LL_RCC_GetDFSDMAudioClockSource 03911 * @param DFSDMx This parameter can be one of the following values: 03912 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE 03913 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*) 03914 * @retval Returned value can be one of the following values: 03915 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 03916 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 03917 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*) 03918 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*) 03919 * 03920 * (*) value not defined in all devices. 03921 */ 03922 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx) 03923 { 03924 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx); 03925 } 03926 03927 /** 03928 * @brief Get DFSDM Audio Clock Source 03929 * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_GetDFSDMClockSource 03930 * @param DFSDMx This parameter can be one of the following values: 03931 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE 03932 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*) 03933 * @retval Returned value can be one of the following values: 03934 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 03935 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK 03936 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*) 03937 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*) 03938 * 03939 * (*) value not defined in all devices. 03940 */ 03941 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx) 03942 { 03943 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx)); 03944 } 03945 #endif /* DFSDM1_Channel0 */ 03946 03947 #if defined(SPDIFRX) 03948 /** 03949 * @brief Get SPDIFRX clock source 03950 * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource 03951 * @param SPDIFRXx This parameter can be one of the following values: 03952 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE 03953 * @retval Returned value can be one of the following values: 03954 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL 03955 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S 03956 * 03957 * (*) value not defined in all devices. 03958 */ 03959 __STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx) 03960 { 03961 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx)); 03962 } 03963 #endif /* SPDIFRX */ 03964 03965 #if defined(DSI) 03966 /** 03967 * @brief Get DSI Clock Source 03968 * @rmtoll DCKCFGR DSISEL LL_RCC_GetDSIClockSource 03969 * @param DSIx This parameter can be one of the following values: 03970 * @arg @ref LL_RCC_DSI_CLKSOURCE 03971 * @retval Returned value can be one of the following values: 03972 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY 03973 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL 03974 */ 03975 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) 03976 { 03977 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx)); 03978 } 03979 #endif /* DSI */ 03980 03981 /** 03982 * @} 03983 */ 03984 03985 /** @defgroup RCC_LL_EF_RTC RTC 03986 * @{ 03987 */ 03988 03989 /** 03990 * @brief Set RTC Clock Source 03991 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless 03992 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is 03993 * set). The BDRST bit can be used to reset them. 03994 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource 03995 * @param Source This parameter can be one of the following values: 03996 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 03997 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 03998 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 03999 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE 04000 * @retval None 04001 */ 04002 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) 04003 { 04004 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); 04005 } 04006 04007 /** 04008 * @brief Get RTC Clock Source 04009 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource 04010 * @retval Returned value can be one of the following values: 04011 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 04012 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 04013 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 04014 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE 04015 */ 04016 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) 04017 { 04018 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); 04019 } 04020 04021 /** 04022 * @brief Enable RTC 04023 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC 04024 * @retval None 04025 */ 04026 __STATIC_INLINE void LL_RCC_EnableRTC(void) 04027 { 04028 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 04029 } 04030 04031 /** 04032 * @brief Disable RTC 04033 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC 04034 * @retval None 04035 */ 04036 __STATIC_INLINE void LL_RCC_DisableRTC(void) 04037 { 04038 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 04039 } 04040 04041 /** 04042 * @brief Check if RTC has been enabled or not 04043 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC 04044 * @retval State of bit (1 or 0). 04045 */ 04046 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) 04047 { 04048 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); 04049 } 04050 04051 /** 04052 * @brief Force the Backup domain reset 04053 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset 04054 * @retval None 04055 */ 04056 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) 04057 { 04058 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); 04059 } 04060 04061 /** 04062 * @brief Release the Backup domain reset 04063 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset 04064 * @retval None 04065 */ 04066 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) 04067 { 04068 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); 04069 } 04070 04071 /** 04072 * @brief Set HSE Prescalers for RTC Clock 04073 * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler 04074 * @param Prescaler This parameter can be one of the following values: 04075 * @arg @ref LL_RCC_RTC_NOCLOCK 04076 * @arg @ref LL_RCC_RTC_HSE_DIV_2 04077 * @arg @ref LL_RCC_RTC_HSE_DIV_3 04078 * @arg @ref LL_RCC_RTC_HSE_DIV_4 04079 * @arg @ref LL_RCC_RTC_HSE_DIV_5 04080 * @arg @ref LL_RCC_RTC_HSE_DIV_6 04081 * @arg @ref LL_RCC_RTC_HSE_DIV_7 04082 * @arg @ref LL_RCC_RTC_HSE_DIV_8 04083 * @arg @ref LL_RCC_RTC_HSE_DIV_9 04084 * @arg @ref LL_RCC_RTC_HSE_DIV_10 04085 * @arg @ref LL_RCC_RTC_HSE_DIV_11 04086 * @arg @ref LL_RCC_RTC_HSE_DIV_12 04087 * @arg @ref LL_RCC_RTC_HSE_DIV_13 04088 * @arg @ref LL_RCC_RTC_HSE_DIV_14 04089 * @arg @ref LL_RCC_RTC_HSE_DIV_15 04090 * @arg @ref LL_RCC_RTC_HSE_DIV_16 04091 * @arg @ref LL_RCC_RTC_HSE_DIV_17 04092 * @arg @ref LL_RCC_RTC_HSE_DIV_18 04093 * @arg @ref LL_RCC_RTC_HSE_DIV_19 04094 * @arg @ref LL_RCC_RTC_HSE_DIV_20 04095 * @arg @ref LL_RCC_RTC_HSE_DIV_21 04096 * @arg @ref LL_RCC_RTC_HSE_DIV_22 04097 * @arg @ref LL_RCC_RTC_HSE_DIV_23 04098 * @arg @ref LL_RCC_RTC_HSE_DIV_24 04099 * @arg @ref LL_RCC_RTC_HSE_DIV_25 04100 * @arg @ref LL_RCC_RTC_HSE_DIV_26 04101 * @arg @ref LL_RCC_RTC_HSE_DIV_27 04102 * @arg @ref LL_RCC_RTC_HSE_DIV_28 04103 * @arg @ref LL_RCC_RTC_HSE_DIV_29 04104 * @arg @ref LL_RCC_RTC_HSE_DIV_30 04105 * @arg @ref LL_RCC_RTC_HSE_DIV_31 04106 * @retval None 04107 */ 04108 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) 04109 { 04110 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); 04111 } 04112 04113 /** 04114 * @brief Get HSE Prescalers for RTC Clock 04115 * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler 04116 * @retval Returned value can be one of the following values: 04117 * @arg @ref LL_RCC_RTC_NOCLOCK 04118 * @arg @ref LL_RCC_RTC_HSE_DIV_2 04119 * @arg @ref LL_RCC_RTC_HSE_DIV_3 04120 * @arg @ref LL_RCC_RTC_HSE_DIV_4 04121 * @arg @ref LL_RCC_RTC_HSE_DIV_5 04122 * @arg @ref LL_RCC_RTC_HSE_DIV_6 04123 * @arg @ref LL_RCC_RTC_HSE_DIV_7 04124 * @arg @ref LL_RCC_RTC_HSE_DIV_8 04125 * @arg @ref LL_RCC_RTC_HSE_DIV_9 04126 * @arg @ref LL_RCC_RTC_HSE_DIV_10 04127 * @arg @ref LL_RCC_RTC_HSE_DIV_11 04128 * @arg @ref LL_RCC_RTC_HSE_DIV_12 04129 * @arg @ref LL_RCC_RTC_HSE_DIV_13 04130 * @arg @ref LL_RCC_RTC_HSE_DIV_14 04131 * @arg @ref LL_RCC_RTC_HSE_DIV_15 04132 * @arg @ref LL_RCC_RTC_HSE_DIV_16 04133 * @arg @ref LL_RCC_RTC_HSE_DIV_17 04134 * @arg @ref LL_RCC_RTC_HSE_DIV_18 04135 * @arg @ref LL_RCC_RTC_HSE_DIV_19 04136 * @arg @ref LL_RCC_RTC_HSE_DIV_20 04137 * @arg @ref LL_RCC_RTC_HSE_DIV_21 04138 * @arg @ref LL_RCC_RTC_HSE_DIV_22 04139 * @arg @ref LL_RCC_RTC_HSE_DIV_23 04140 * @arg @ref LL_RCC_RTC_HSE_DIV_24 04141 * @arg @ref LL_RCC_RTC_HSE_DIV_25 04142 * @arg @ref LL_RCC_RTC_HSE_DIV_26 04143 * @arg @ref LL_RCC_RTC_HSE_DIV_27 04144 * @arg @ref LL_RCC_RTC_HSE_DIV_28 04145 * @arg @ref LL_RCC_RTC_HSE_DIV_29 04146 * @arg @ref LL_RCC_RTC_HSE_DIV_30 04147 * @arg @ref LL_RCC_RTC_HSE_DIV_31 04148 */ 04149 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) 04150 { 04151 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)); 04152 } 04153 04154 /** 04155 * @} 04156 */ 04157 04158 #if defined(RCC_DCKCFGR_TIMPRE) 04159 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM 04160 * @{ 04161 */ 04162 04163 /** 04164 * @brief Set Timers Clock Prescalers 04165 * @rmtoll DCKCFGR TIMPRE LL_RCC_SetTIMPrescaler 04166 * @param Prescaler This parameter can be one of the following values: 04167 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE 04168 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES 04169 * @retval None 04170 */ 04171 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) 04172 { 04173 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler); 04174 } 04175 04176 /** 04177 * @brief Get Timers Clock Prescalers 04178 * @rmtoll DCKCFGR TIMPRE LL_RCC_GetTIMPrescaler 04179 * @retval Returned value can be one of the following values: 04180 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE 04181 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES 04182 */ 04183 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) 04184 { 04185 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE)); 04186 } 04187 04188 /** 04189 * @} 04190 */ 04191 #endif /* RCC_DCKCFGR_TIMPRE */ 04192 04193 /** @defgroup RCC_LL_EF_PLL PLL 04194 * @{ 04195 */ 04196 04197 /** 04198 * @brief Enable PLL 04199 * @rmtoll CR PLLON LL_RCC_PLL_Enable 04200 * @retval None 04201 */ 04202 __STATIC_INLINE void LL_RCC_PLL_Enable(void) 04203 { 04204 SET_BIT(RCC->CR, RCC_CR_PLLON); 04205 } 04206 04207 /** 04208 * @brief Disable PLL 04209 * @note Cannot be disabled if the PLL clock is used as the system clock 04210 * @rmtoll CR PLLON LL_RCC_PLL_Disable 04211 * @retval None 04212 */ 04213 __STATIC_INLINE void LL_RCC_PLL_Disable(void) 04214 { 04215 CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 04216 } 04217 04218 /** 04219 * @brief Check if PLL Ready 04220 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady 04221 * @retval State of bit (1 or 0). 04222 */ 04223 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) 04224 { 04225 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); 04226 } 04227 04228 /** 04229 * @brief Configure PLL used for SYSCLK Domain 04230 * @note PLL Source and PLLM Divider can be written only when PLL, 04231 * PLLI2S and PLLSAI(*) are disabled 04232 * @note PLLN/PLLP can be written only when PLL is disabled 04233 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n 04234 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n 04235 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n 04236 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS\n 04237 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS 04238 * @param Source This parameter can be one of the following values: 04239 * @arg @ref LL_RCC_PLLSOURCE_HSI 04240 * @arg @ref LL_RCC_PLLSOURCE_HSE 04241 * @param PLLM This parameter can be one of the following values: 04242 * @arg @ref LL_RCC_PLLM_DIV_2 04243 * @arg @ref LL_RCC_PLLM_DIV_3 04244 * @arg @ref LL_RCC_PLLM_DIV_4 04245 * @arg @ref LL_RCC_PLLM_DIV_5 04246 * @arg @ref LL_RCC_PLLM_DIV_6 04247 * @arg @ref LL_RCC_PLLM_DIV_7 04248 * @arg @ref LL_RCC_PLLM_DIV_8 04249 * @arg @ref LL_RCC_PLLM_DIV_9 04250 * @arg @ref LL_RCC_PLLM_DIV_10 04251 * @arg @ref LL_RCC_PLLM_DIV_11 04252 * @arg @ref LL_RCC_PLLM_DIV_12 04253 * @arg @ref LL_RCC_PLLM_DIV_13 04254 * @arg @ref LL_RCC_PLLM_DIV_14 04255 * @arg @ref LL_RCC_PLLM_DIV_15 04256 * @arg @ref LL_RCC_PLLM_DIV_16 04257 * @arg @ref LL_RCC_PLLM_DIV_17 04258 * @arg @ref LL_RCC_PLLM_DIV_18 04259 * @arg @ref LL_RCC_PLLM_DIV_19 04260 * @arg @ref LL_RCC_PLLM_DIV_20 04261 * @arg @ref LL_RCC_PLLM_DIV_21 04262 * @arg @ref LL_RCC_PLLM_DIV_22 04263 * @arg @ref LL_RCC_PLLM_DIV_23 04264 * @arg @ref LL_RCC_PLLM_DIV_24 04265 * @arg @ref LL_RCC_PLLM_DIV_25 04266 * @arg @ref LL_RCC_PLLM_DIV_26 04267 * @arg @ref LL_RCC_PLLM_DIV_27 04268 * @arg @ref LL_RCC_PLLM_DIV_28 04269 * @arg @ref LL_RCC_PLLM_DIV_29 04270 * @arg @ref LL_RCC_PLLM_DIV_30 04271 * @arg @ref LL_RCC_PLLM_DIV_31 04272 * @arg @ref LL_RCC_PLLM_DIV_32 04273 * @arg @ref LL_RCC_PLLM_DIV_33 04274 * @arg @ref LL_RCC_PLLM_DIV_34 04275 * @arg @ref LL_RCC_PLLM_DIV_35 04276 * @arg @ref LL_RCC_PLLM_DIV_36 04277 * @arg @ref LL_RCC_PLLM_DIV_37 04278 * @arg @ref LL_RCC_PLLM_DIV_38 04279 * @arg @ref LL_RCC_PLLM_DIV_39 04280 * @arg @ref LL_RCC_PLLM_DIV_40 04281 * @arg @ref LL_RCC_PLLM_DIV_41 04282 * @arg @ref LL_RCC_PLLM_DIV_42 04283 * @arg @ref LL_RCC_PLLM_DIV_43 04284 * @arg @ref LL_RCC_PLLM_DIV_44 04285 * @arg @ref LL_RCC_PLLM_DIV_45 04286 * @arg @ref LL_RCC_PLLM_DIV_46 04287 * @arg @ref LL_RCC_PLLM_DIV_47 04288 * @arg @ref LL_RCC_PLLM_DIV_48 04289 * @arg @ref LL_RCC_PLLM_DIV_49 04290 * @arg @ref LL_RCC_PLLM_DIV_50 04291 * @arg @ref LL_RCC_PLLM_DIV_51 04292 * @arg @ref LL_RCC_PLLM_DIV_52 04293 * @arg @ref LL_RCC_PLLM_DIV_53 04294 * @arg @ref LL_RCC_PLLM_DIV_54 04295 * @arg @ref LL_RCC_PLLM_DIV_55 04296 * @arg @ref LL_RCC_PLLM_DIV_56 04297 * @arg @ref LL_RCC_PLLM_DIV_57 04298 * @arg @ref LL_RCC_PLLM_DIV_58 04299 * @arg @ref LL_RCC_PLLM_DIV_59 04300 * @arg @ref LL_RCC_PLLM_DIV_60 04301 * @arg @ref LL_RCC_PLLM_DIV_61 04302 * @arg @ref LL_RCC_PLLM_DIV_62 04303 * @arg @ref LL_RCC_PLLM_DIV_63 04304 * @param PLLN Between 50/192(*) and 432 04305 * 04306 * (*) value not defined in all devices. 04307 * @param PLLP_R This parameter can be one of the following values: 04308 * @arg @ref LL_RCC_PLLP_DIV_2 04309 * @arg @ref LL_RCC_PLLP_DIV_4 04310 * @arg @ref LL_RCC_PLLP_DIV_6 04311 * @arg @ref LL_RCC_PLLP_DIV_8 04312 * @arg @ref LL_RCC_PLLR_DIV_2 (*) 04313 * @arg @ref LL_RCC_PLLR_DIV_3 (*) 04314 * @arg @ref LL_RCC_PLLR_DIV_4 (*) 04315 * @arg @ref LL_RCC_PLLR_DIV_5 (*) 04316 * @arg @ref LL_RCC_PLLR_DIV_6 (*) 04317 * @arg @ref LL_RCC_PLLR_DIV_7 (*) 04318 * 04319 * (*) value not defined in all devices. 04320 * @retval None 04321 */ 04322 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R) 04323 { 04324 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN, 04325 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos); 04326 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R); 04327 #if defined(RCC_PLLR_SYSCLK_SUPPORT) 04328 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R); 04329 #endif /* RCC_PLLR_SYSCLK_SUPPORT */ 04330 } 04331 04332 /** 04333 * @brief Configure PLL used for 48Mhz domain clock 04334 * @note PLL Source and PLLM Divider can be written only when PLL, 04335 * PLLI2S and PLLSAI(*) are disabled 04336 * @note PLLN/PLLQ can be written only when PLL is disabled 04337 * @note This can be selected for USB, RNG, SDIO 04338 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n 04339 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n 04340 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n 04341 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M 04342 * @param Source This parameter can be one of the following values: 04343 * @arg @ref LL_RCC_PLLSOURCE_HSI 04344 * @arg @ref LL_RCC_PLLSOURCE_HSE 04345 * @param PLLM This parameter can be one of the following values: 04346 * @arg @ref LL_RCC_PLLM_DIV_2 04347 * @arg @ref LL_RCC_PLLM_DIV_3 04348 * @arg @ref LL_RCC_PLLM_DIV_4 04349 * @arg @ref LL_RCC_PLLM_DIV_5 04350 * @arg @ref LL_RCC_PLLM_DIV_6 04351 * @arg @ref LL_RCC_PLLM_DIV_7 04352 * @arg @ref LL_RCC_PLLM_DIV_8 04353 * @arg @ref LL_RCC_PLLM_DIV_9 04354 * @arg @ref LL_RCC_PLLM_DIV_10 04355 * @arg @ref LL_RCC_PLLM_DIV_11 04356 * @arg @ref LL_RCC_PLLM_DIV_12 04357 * @arg @ref LL_RCC_PLLM_DIV_13 04358 * @arg @ref LL_RCC_PLLM_DIV_14 04359 * @arg @ref LL_RCC_PLLM_DIV_15 04360 * @arg @ref LL_RCC_PLLM_DIV_16 04361 * @arg @ref LL_RCC_PLLM_DIV_17 04362 * @arg @ref LL_RCC_PLLM_DIV_18 04363 * @arg @ref LL_RCC_PLLM_DIV_19 04364 * @arg @ref LL_RCC_PLLM_DIV_20 04365 * @arg @ref LL_RCC_PLLM_DIV_21 04366 * @arg @ref LL_RCC_PLLM_DIV_22 04367 * @arg @ref LL_RCC_PLLM_DIV_23 04368 * @arg @ref LL_RCC_PLLM_DIV_24 04369 * @arg @ref LL_RCC_PLLM_DIV_25 04370 * @arg @ref LL_RCC_PLLM_DIV_26 04371 * @arg @ref LL_RCC_PLLM_DIV_27 04372 * @arg @ref LL_RCC_PLLM_DIV_28 04373 * @arg @ref LL_RCC_PLLM_DIV_29 04374 * @arg @ref LL_RCC_PLLM_DIV_30 04375 * @arg @ref LL_RCC_PLLM_DIV_31 04376 * @arg @ref LL_RCC_PLLM_DIV_32 04377 * @arg @ref LL_RCC_PLLM_DIV_33 04378 * @arg @ref LL_RCC_PLLM_DIV_34 04379 * @arg @ref LL_RCC_PLLM_DIV_35 04380 * @arg @ref LL_RCC_PLLM_DIV_36 04381 * @arg @ref LL_RCC_PLLM_DIV_37 04382 * @arg @ref LL_RCC_PLLM_DIV_38 04383 * @arg @ref LL_RCC_PLLM_DIV_39 04384 * @arg @ref LL_RCC_PLLM_DIV_40 04385 * @arg @ref LL_RCC_PLLM_DIV_41 04386 * @arg @ref LL_RCC_PLLM_DIV_42 04387 * @arg @ref LL_RCC_PLLM_DIV_43 04388 * @arg @ref LL_RCC_PLLM_DIV_44 04389 * @arg @ref LL_RCC_PLLM_DIV_45 04390 * @arg @ref LL_RCC_PLLM_DIV_46 04391 * @arg @ref LL_RCC_PLLM_DIV_47 04392 * @arg @ref LL_RCC_PLLM_DIV_48 04393 * @arg @ref LL_RCC_PLLM_DIV_49 04394 * @arg @ref LL_RCC_PLLM_DIV_50 04395 * @arg @ref LL_RCC_PLLM_DIV_51 04396 * @arg @ref LL_RCC_PLLM_DIV_52 04397 * @arg @ref LL_RCC_PLLM_DIV_53 04398 * @arg @ref LL_RCC_PLLM_DIV_54 04399 * @arg @ref LL_RCC_PLLM_DIV_55 04400 * @arg @ref LL_RCC_PLLM_DIV_56 04401 * @arg @ref LL_RCC_PLLM_DIV_57 04402 * @arg @ref LL_RCC_PLLM_DIV_58 04403 * @arg @ref LL_RCC_PLLM_DIV_59 04404 * @arg @ref LL_RCC_PLLM_DIV_60 04405 * @arg @ref LL_RCC_PLLM_DIV_61 04406 * @arg @ref LL_RCC_PLLM_DIV_62 04407 * @arg @ref LL_RCC_PLLM_DIV_63 04408 * @param PLLN Between 50/192(*) and 432 04409 * 04410 * (*) value not defined in all devices. 04411 * @param PLLQ This parameter can be one of the following values: 04412 * @arg @ref LL_RCC_PLLQ_DIV_2 04413 * @arg @ref LL_RCC_PLLQ_DIV_3 04414 * @arg @ref LL_RCC_PLLQ_DIV_4 04415 * @arg @ref LL_RCC_PLLQ_DIV_5 04416 * @arg @ref LL_RCC_PLLQ_DIV_6 04417 * @arg @ref LL_RCC_PLLQ_DIV_7 04418 * @arg @ref LL_RCC_PLLQ_DIV_8 04419 * @arg @ref LL_RCC_PLLQ_DIV_9 04420 * @arg @ref LL_RCC_PLLQ_DIV_10 04421 * @arg @ref LL_RCC_PLLQ_DIV_11 04422 * @arg @ref LL_RCC_PLLQ_DIV_12 04423 * @arg @ref LL_RCC_PLLQ_DIV_13 04424 * @arg @ref LL_RCC_PLLQ_DIV_14 04425 * @arg @ref LL_RCC_PLLQ_DIV_15 04426 * @retval None 04427 */ 04428 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) 04429 { 04430 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, 04431 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); 04432 } 04433 04434 #if defined(DSI) 04435 /** 04436 * @brief Configure PLL used for DSI clock 04437 * @note PLL Source and PLLM Divider can be written only when PLL, 04438 * PLLI2S and PLLSAI are disabled 04439 * @note PLLN/PLLR can be written only when PLL is disabled 04440 * @note This can be selected for DSI 04441 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n 04442 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n 04443 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n 04444 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI 04445 * @param Source This parameter can be one of the following values: 04446 * @arg @ref LL_RCC_PLLSOURCE_HSI 04447 * @arg @ref LL_RCC_PLLSOURCE_HSE 04448 * @param PLLM This parameter can be one of the following values: 04449 * @arg @ref LL_RCC_PLLM_DIV_2 04450 * @arg @ref LL_RCC_PLLM_DIV_3 04451 * @arg @ref LL_RCC_PLLM_DIV_4 04452 * @arg @ref LL_RCC_PLLM_DIV_5 04453 * @arg @ref LL_RCC_PLLM_DIV_6 04454 * @arg @ref LL_RCC_PLLM_DIV_7 04455 * @arg @ref LL_RCC_PLLM_DIV_8 04456 * @arg @ref LL_RCC_PLLM_DIV_9 04457 * @arg @ref LL_RCC_PLLM_DIV_10 04458 * @arg @ref LL_RCC_PLLM_DIV_11 04459 * @arg @ref LL_RCC_PLLM_DIV_12 04460 * @arg @ref LL_RCC_PLLM_DIV_13 04461 * @arg @ref LL_RCC_PLLM_DIV_14 04462 * @arg @ref LL_RCC_PLLM_DIV_15 04463 * @arg @ref LL_RCC_PLLM_DIV_16 04464 * @arg @ref LL_RCC_PLLM_DIV_17 04465 * @arg @ref LL_RCC_PLLM_DIV_18 04466 * @arg @ref LL_RCC_PLLM_DIV_19 04467 * @arg @ref LL_RCC_PLLM_DIV_20 04468 * @arg @ref LL_RCC_PLLM_DIV_21 04469 * @arg @ref LL_RCC_PLLM_DIV_22 04470 * @arg @ref LL_RCC_PLLM_DIV_23 04471 * @arg @ref LL_RCC_PLLM_DIV_24 04472 * @arg @ref LL_RCC_PLLM_DIV_25 04473 * @arg @ref LL_RCC_PLLM_DIV_26 04474 * @arg @ref LL_RCC_PLLM_DIV_27 04475 * @arg @ref LL_RCC_PLLM_DIV_28 04476 * @arg @ref LL_RCC_PLLM_DIV_29 04477 * @arg @ref LL_RCC_PLLM_DIV_30 04478 * @arg @ref LL_RCC_PLLM_DIV_31 04479 * @arg @ref LL_RCC_PLLM_DIV_32 04480 * @arg @ref LL_RCC_PLLM_DIV_33 04481 * @arg @ref LL_RCC_PLLM_DIV_34 04482 * @arg @ref LL_RCC_PLLM_DIV_35 04483 * @arg @ref LL_RCC_PLLM_DIV_36 04484 * @arg @ref LL_RCC_PLLM_DIV_37 04485 * @arg @ref LL_RCC_PLLM_DIV_38 04486 * @arg @ref LL_RCC_PLLM_DIV_39 04487 * @arg @ref LL_RCC_PLLM_DIV_40 04488 * @arg @ref LL_RCC_PLLM_DIV_41 04489 * @arg @ref LL_RCC_PLLM_DIV_42 04490 * @arg @ref LL_RCC_PLLM_DIV_43 04491 * @arg @ref LL_RCC_PLLM_DIV_44 04492 * @arg @ref LL_RCC_PLLM_DIV_45 04493 * @arg @ref LL_RCC_PLLM_DIV_46 04494 * @arg @ref LL_RCC_PLLM_DIV_47 04495 * @arg @ref LL_RCC_PLLM_DIV_48 04496 * @arg @ref LL_RCC_PLLM_DIV_49 04497 * @arg @ref LL_RCC_PLLM_DIV_50 04498 * @arg @ref LL_RCC_PLLM_DIV_51 04499 * @arg @ref LL_RCC_PLLM_DIV_52 04500 * @arg @ref LL_RCC_PLLM_DIV_53 04501 * @arg @ref LL_RCC_PLLM_DIV_54 04502 * @arg @ref LL_RCC_PLLM_DIV_55 04503 * @arg @ref LL_RCC_PLLM_DIV_56 04504 * @arg @ref LL_RCC_PLLM_DIV_57 04505 * @arg @ref LL_RCC_PLLM_DIV_58 04506 * @arg @ref LL_RCC_PLLM_DIV_59 04507 * @arg @ref LL_RCC_PLLM_DIV_60 04508 * @arg @ref LL_RCC_PLLM_DIV_61 04509 * @arg @ref LL_RCC_PLLM_DIV_62 04510 * @arg @ref LL_RCC_PLLM_DIV_63 04511 * @param PLLN Between 50 and 432 04512 * @param PLLR This parameter can be one of the following values: 04513 * @arg @ref LL_RCC_PLLR_DIV_2 04514 * @arg @ref LL_RCC_PLLR_DIV_3 04515 * @arg @ref LL_RCC_PLLR_DIV_4 04516 * @arg @ref LL_RCC_PLLR_DIV_5 04517 * @arg @ref LL_RCC_PLLR_DIV_6 04518 * @arg @ref LL_RCC_PLLR_DIV_7 04519 * @retval None 04520 */ 04521 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 04522 { 04523 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, 04524 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); 04525 } 04526 #endif /* DSI */ 04527 04528 #if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT) 04529 /** 04530 * @brief Configure PLL used for I2S clock 04531 * @note PLL Source and PLLM Divider can be written only when PLL, 04532 * PLLI2S and PLLSAI are disabled 04533 * @note PLLN/PLLR can be written only when PLL is disabled 04534 * @note This can be selected for I2S 04535 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n 04536 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n 04537 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n 04538 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_I2S 04539 * @param Source This parameter can be one of the following values: 04540 * @arg @ref LL_RCC_PLLSOURCE_HSI 04541 * @arg @ref LL_RCC_PLLSOURCE_HSE 04542 * @param PLLM This parameter can be one of the following values: 04543 * @arg @ref LL_RCC_PLLM_DIV_2 04544 * @arg @ref LL_RCC_PLLM_DIV_3 04545 * @arg @ref LL_RCC_PLLM_DIV_4 04546 * @arg @ref LL_RCC_PLLM_DIV_5 04547 * @arg @ref LL_RCC_PLLM_DIV_6 04548 * @arg @ref LL_RCC_PLLM_DIV_7 04549 * @arg @ref LL_RCC_PLLM_DIV_8 04550 * @arg @ref LL_RCC_PLLM_DIV_9 04551 * @arg @ref LL_RCC_PLLM_DIV_10 04552 * @arg @ref LL_RCC_PLLM_DIV_11 04553 * @arg @ref LL_RCC_PLLM_DIV_12 04554 * @arg @ref LL_RCC_PLLM_DIV_13 04555 * @arg @ref LL_RCC_PLLM_DIV_14 04556 * @arg @ref LL_RCC_PLLM_DIV_15 04557 * @arg @ref LL_RCC_PLLM_DIV_16 04558 * @arg @ref LL_RCC_PLLM_DIV_17 04559 * @arg @ref LL_RCC_PLLM_DIV_18 04560 * @arg @ref LL_RCC_PLLM_DIV_19 04561 * @arg @ref LL_RCC_PLLM_DIV_20 04562 * @arg @ref LL_RCC_PLLM_DIV_21 04563 * @arg @ref LL_RCC_PLLM_DIV_22 04564 * @arg @ref LL_RCC_PLLM_DIV_23 04565 * @arg @ref LL_RCC_PLLM_DIV_24 04566 * @arg @ref LL_RCC_PLLM_DIV_25 04567 * @arg @ref LL_RCC_PLLM_DIV_26 04568 * @arg @ref LL_RCC_PLLM_DIV_27 04569 * @arg @ref LL_RCC_PLLM_DIV_28 04570 * @arg @ref LL_RCC_PLLM_DIV_29 04571 * @arg @ref LL_RCC_PLLM_DIV_30 04572 * @arg @ref LL_RCC_PLLM_DIV_31 04573 * @arg @ref LL_RCC_PLLM_DIV_32 04574 * @arg @ref LL_RCC_PLLM_DIV_33 04575 * @arg @ref LL_RCC_PLLM_DIV_34 04576 * @arg @ref LL_RCC_PLLM_DIV_35 04577 * @arg @ref LL_RCC_PLLM_DIV_36 04578 * @arg @ref LL_RCC_PLLM_DIV_37 04579 * @arg @ref LL_RCC_PLLM_DIV_38 04580 * @arg @ref LL_RCC_PLLM_DIV_39 04581 * @arg @ref LL_RCC_PLLM_DIV_40 04582 * @arg @ref LL_RCC_PLLM_DIV_41 04583 * @arg @ref LL_RCC_PLLM_DIV_42 04584 * @arg @ref LL_RCC_PLLM_DIV_43 04585 * @arg @ref LL_RCC_PLLM_DIV_44 04586 * @arg @ref LL_RCC_PLLM_DIV_45 04587 * @arg @ref LL_RCC_PLLM_DIV_46 04588 * @arg @ref LL_RCC_PLLM_DIV_47 04589 * @arg @ref LL_RCC_PLLM_DIV_48 04590 * @arg @ref LL_RCC_PLLM_DIV_49 04591 * @arg @ref LL_RCC_PLLM_DIV_50 04592 * @arg @ref LL_RCC_PLLM_DIV_51 04593 * @arg @ref LL_RCC_PLLM_DIV_52 04594 * @arg @ref LL_RCC_PLLM_DIV_53 04595 * @arg @ref LL_RCC_PLLM_DIV_54 04596 * @arg @ref LL_RCC_PLLM_DIV_55 04597 * @arg @ref LL_RCC_PLLM_DIV_56 04598 * @arg @ref LL_RCC_PLLM_DIV_57 04599 * @arg @ref LL_RCC_PLLM_DIV_58 04600 * @arg @ref LL_RCC_PLLM_DIV_59 04601 * @arg @ref LL_RCC_PLLM_DIV_60 04602 * @arg @ref LL_RCC_PLLM_DIV_61 04603 * @arg @ref LL_RCC_PLLM_DIV_62 04604 * @arg @ref LL_RCC_PLLM_DIV_63 04605 * @param PLLN Between 50 and 432 04606 * @param PLLR This parameter can be one of the following values: 04607 * @arg @ref LL_RCC_PLLR_DIV_2 04608 * @arg @ref LL_RCC_PLLR_DIV_3 04609 * @arg @ref LL_RCC_PLLR_DIV_4 04610 * @arg @ref LL_RCC_PLLR_DIV_5 04611 * @arg @ref LL_RCC_PLLR_DIV_6 04612 * @arg @ref LL_RCC_PLLR_DIV_7 04613 * @retval None 04614 */ 04615 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 04616 { 04617 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, 04618 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); 04619 } 04620 #endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */ 04621 04622 #if defined(SPDIFRX) 04623 /** 04624 * @brief Configure PLL used for SPDIFRX clock 04625 * @note PLL Source and PLLM Divider can be written only when PLL, 04626 * PLLI2S and PLLSAI are disabled 04627 * @note PLLN/PLLR can be written only when PLL is disabled 04628 * @note This can be selected for SPDIFRX 04629 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SPDIFRX\n 04630 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SPDIFRX\n 04631 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SPDIFRX\n 04632 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SPDIFRX 04633 * @param Source This parameter can be one of the following values: 04634 * @arg @ref LL_RCC_PLLSOURCE_HSI 04635 * @arg @ref LL_RCC_PLLSOURCE_HSE 04636 * @param PLLM This parameter can be one of the following values: 04637 * @arg @ref LL_RCC_PLLM_DIV_2 04638 * @arg @ref LL_RCC_PLLM_DIV_3 04639 * @arg @ref LL_RCC_PLLM_DIV_4 04640 * @arg @ref LL_RCC_PLLM_DIV_5 04641 * @arg @ref LL_RCC_PLLM_DIV_6 04642 * @arg @ref LL_RCC_PLLM_DIV_7 04643 * @arg @ref LL_RCC_PLLM_DIV_8 04644 * @arg @ref LL_RCC_PLLM_DIV_9 04645 * @arg @ref LL_RCC_PLLM_DIV_10 04646 * @arg @ref LL_RCC_PLLM_DIV_11 04647 * @arg @ref LL_RCC_PLLM_DIV_12 04648 * @arg @ref LL_RCC_PLLM_DIV_13 04649 * @arg @ref LL_RCC_PLLM_DIV_14 04650 * @arg @ref LL_RCC_PLLM_DIV_15 04651 * @arg @ref LL_RCC_PLLM_DIV_16 04652 * @arg @ref LL_RCC_PLLM_DIV_17 04653 * @arg @ref LL_RCC_PLLM_DIV_18 04654 * @arg @ref LL_RCC_PLLM_DIV_19 04655 * @arg @ref LL_RCC_PLLM_DIV_20 04656 * @arg @ref LL_RCC_PLLM_DIV_21 04657 * @arg @ref LL_RCC_PLLM_DIV_22 04658 * @arg @ref LL_RCC_PLLM_DIV_23 04659 * @arg @ref LL_RCC_PLLM_DIV_24 04660 * @arg @ref LL_RCC_PLLM_DIV_25 04661 * @arg @ref LL_RCC_PLLM_DIV_26 04662 * @arg @ref LL_RCC_PLLM_DIV_27 04663 * @arg @ref LL_RCC_PLLM_DIV_28 04664 * @arg @ref LL_RCC_PLLM_DIV_29 04665 * @arg @ref LL_RCC_PLLM_DIV_30 04666 * @arg @ref LL_RCC_PLLM_DIV_31 04667 * @arg @ref LL_RCC_PLLM_DIV_32 04668 * @arg @ref LL_RCC_PLLM_DIV_33 04669 * @arg @ref LL_RCC_PLLM_DIV_34 04670 * @arg @ref LL_RCC_PLLM_DIV_35 04671 * @arg @ref LL_RCC_PLLM_DIV_36 04672 * @arg @ref LL_RCC_PLLM_DIV_37 04673 * @arg @ref LL_RCC_PLLM_DIV_38 04674 * @arg @ref LL_RCC_PLLM_DIV_39 04675 * @arg @ref LL_RCC_PLLM_DIV_40 04676 * @arg @ref LL_RCC_PLLM_DIV_41 04677 * @arg @ref LL_RCC_PLLM_DIV_42 04678 * @arg @ref LL_RCC_PLLM_DIV_43 04679 * @arg @ref LL_RCC_PLLM_DIV_44 04680 * @arg @ref LL_RCC_PLLM_DIV_45 04681 * @arg @ref LL_RCC_PLLM_DIV_46 04682 * @arg @ref LL_RCC_PLLM_DIV_47 04683 * @arg @ref LL_RCC_PLLM_DIV_48 04684 * @arg @ref LL_RCC_PLLM_DIV_49 04685 * @arg @ref LL_RCC_PLLM_DIV_50 04686 * @arg @ref LL_RCC_PLLM_DIV_51 04687 * @arg @ref LL_RCC_PLLM_DIV_52 04688 * @arg @ref LL_RCC_PLLM_DIV_53 04689 * @arg @ref LL_RCC_PLLM_DIV_54 04690 * @arg @ref LL_RCC_PLLM_DIV_55 04691 * @arg @ref LL_RCC_PLLM_DIV_56 04692 * @arg @ref LL_RCC_PLLM_DIV_57 04693 * @arg @ref LL_RCC_PLLM_DIV_58 04694 * @arg @ref LL_RCC_PLLM_DIV_59 04695 * @arg @ref LL_RCC_PLLM_DIV_60 04696 * @arg @ref LL_RCC_PLLM_DIV_61 04697 * @arg @ref LL_RCC_PLLM_DIV_62 04698 * @arg @ref LL_RCC_PLLM_DIV_63 04699 * @param PLLN Between 50 and 432 04700 * @param PLLR This parameter can be one of the following values: 04701 * @arg @ref LL_RCC_PLLR_DIV_2 04702 * @arg @ref LL_RCC_PLLR_DIV_3 04703 * @arg @ref LL_RCC_PLLR_DIV_4 04704 * @arg @ref LL_RCC_PLLR_DIV_5 04705 * @arg @ref LL_RCC_PLLR_DIV_6 04706 * @arg @ref LL_RCC_PLLR_DIV_7 04707 * @retval None 04708 */ 04709 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 04710 { 04711 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, 04712 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); 04713 } 04714 #endif /* SPDIFRX */ 04715 04716 #if defined(RCC_PLLCFGR_PLLR) 04717 #if defined(SAI1) 04718 /** 04719 * @brief Configure PLL used for SAI clock 04720 * @note PLL Source and PLLM Divider can be written only when PLL, 04721 * PLLI2S and PLLSAI are disabled 04722 * @note PLLN/PLLR can be written only when PLL is disabled 04723 * @note This can be selected for SAI 04724 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n 04725 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n 04726 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n 04727 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SAI\n 04728 * DCKCFGR PLLDIVR LL_RCC_PLL_ConfigDomain_SAI 04729 * @param Source This parameter can be one of the following values: 04730 * @arg @ref LL_RCC_PLLSOURCE_HSI 04731 * @arg @ref LL_RCC_PLLSOURCE_HSE 04732 * @param PLLM This parameter can be one of the following values: 04733 * @arg @ref LL_RCC_PLLM_DIV_2 04734 * @arg @ref LL_RCC_PLLM_DIV_3 04735 * @arg @ref LL_RCC_PLLM_DIV_4 04736 * @arg @ref LL_RCC_PLLM_DIV_5 04737 * @arg @ref LL_RCC_PLLM_DIV_6 04738 * @arg @ref LL_RCC_PLLM_DIV_7 04739 * @arg @ref LL_RCC_PLLM_DIV_8 04740 * @arg @ref LL_RCC_PLLM_DIV_9 04741 * @arg @ref LL_RCC_PLLM_DIV_10 04742 * @arg @ref LL_RCC_PLLM_DIV_11 04743 * @arg @ref LL_RCC_PLLM_DIV_12 04744 * @arg @ref LL_RCC_PLLM_DIV_13 04745 * @arg @ref LL_RCC_PLLM_DIV_14 04746 * @arg @ref LL_RCC_PLLM_DIV_15 04747 * @arg @ref LL_RCC_PLLM_DIV_16 04748 * @arg @ref LL_RCC_PLLM_DIV_17 04749 * @arg @ref LL_RCC_PLLM_DIV_18 04750 * @arg @ref LL_RCC_PLLM_DIV_19 04751 * @arg @ref LL_RCC_PLLM_DIV_20 04752 * @arg @ref LL_RCC_PLLM_DIV_21 04753 * @arg @ref LL_RCC_PLLM_DIV_22 04754 * @arg @ref LL_RCC_PLLM_DIV_23 04755 * @arg @ref LL_RCC_PLLM_DIV_24 04756 * @arg @ref LL_RCC_PLLM_DIV_25 04757 * @arg @ref LL_RCC_PLLM_DIV_26 04758 * @arg @ref LL_RCC_PLLM_DIV_27 04759 * @arg @ref LL_RCC_PLLM_DIV_28 04760 * @arg @ref LL_RCC_PLLM_DIV_29 04761 * @arg @ref LL_RCC_PLLM_DIV_30 04762 * @arg @ref LL_RCC_PLLM_DIV_31 04763 * @arg @ref LL_RCC_PLLM_DIV_32 04764 * @arg @ref LL_RCC_PLLM_DIV_33 04765 * @arg @ref LL_RCC_PLLM_DIV_34 04766 * @arg @ref LL_RCC_PLLM_DIV_35 04767 * @arg @ref LL_RCC_PLLM_DIV_36 04768 * @arg @ref LL_RCC_PLLM_DIV_37 04769 * @arg @ref LL_RCC_PLLM_DIV_38 04770 * @arg @ref LL_RCC_PLLM_DIV_39 04771 * @arg @ref LL_RCC_PLLM_DIV_40 04772 * @arg @ref LL_RCC_PLLM_DIV_41 04773 * @arg @ref LL_RCC_PLLM_DIV_42 04774 * @arg @ref LL_RCC_PLLM_DIV_43 04775 * @arg @ref LL_RCC_PLLM_DIV_44 04776 * @arg @ref LL_RCC_PLLM_DIV_45 04777 * @arg @ref LL_RCC_PLLM_DIV_46 04778 * @arg @ref LL_RCC_PLLM_DIV_47 04779 * @arg @ref LL_RCC_PLLM_DIV_48 04780 * @arg @ref LL_RCC_PLLM_DIV_49 04781 * @arg @ref LL_RCC_PLLM_DIV_50 04782 * @arg @ref LL_RCC_PLLM_DIV_51 04783 * @arg @ref LL_RCC_PLLM_DIV_52 04784 * @arg @ref LL_RCC_PLLM_DIV_53 04785 * @arg @ref LL_RCC_PLLM_DIV_54 04786 * @arg @ref LL_RCC_PLLM_DIV_55 04787 * @arg @ref LL_RCC_PLLM_DIV_56 04788 * @arg @ref LL_RCC_PLLM_DIV_57 04789 * @arg @ref LL_RCC_PLLM_DIV_58 04790 * @arg @ref LL_RCC_PLLM_DIV_59 04791 * @arg @ref LL_RCC_PLLM_DIV_60 04792 * @arg @ref LL_RCC_PLLM_DIV_61 04793 * @arg @ref LL_RCC_PLLM_DIV_62 04794 * @arg @ref LL_RCC_PLLM_DIV_63 04795 * @param PLLN Between 50 and 432 04796 * @param PLLR This parameter can be one of the following values: 04797 * @arg @ref LL_RCC_PLLR_DIV_2 04798 * @arg @ref LL_RCC_PLLR_DIV_3 04799 * @arg @ref LL_RCC_PLLR_DIV_4 04800 * @arg @ref LL_RCC_PLLR_DIV_5 04801 * @arg @ref LL_RCC_PLLR_DIV_6 04802 * @arg @ref LL_RCC_PLLR_DIV_7 04803 * @param PLLDIVR This parameter can be one of the following values: 04804 * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*) 04805 * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*) 04806 * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*) 04807 * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*) 04808 * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*) 04809 * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*) 04810 * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*) 04811 * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*) 04812 * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*) 04813 * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*) 04814 * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*) 04815 * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*) 04816 * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*) 04817 * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*) 04818 * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*) 04819 * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*) 04820 * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*) 04821 * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*) 04822 * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*) 04823 * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*) 04824 * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*) 04825 * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*) 04826 * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*) 04827 * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*) 04828 * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*) 04829 * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*) 04830 * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*) 04831 * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*) 04832 * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*) 04833 * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*) 04834 * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*) 04835 * 04836 * (*) value not defined in all devices. 04837 * @retval None 04838 */ 04839 #if defined(RCC_DCKCFGR_PLLDIVR) 04840 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) 04841 #else 04842 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 04843 #endif /* RCC_DCKCFGR_PLLDIVR */ 04844 { 04845 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, 04846 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); 04847 #if defined(RCC_DCKCFGR_PLLDIVR) 04848 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR); 04849 #endif /* RCC_DCKCFGR_PLLDIVR */ 04850 } 04851 #endif /* SAI1 */ 04852 #endif /* RCC_PLLCFGR_PLLR */ 04853 04854 /** 04855 * @brief Configure PLL clock source 04856 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource 04857 * @param PLLSource This parameter can be one of the following values: 04858 * @arg @ref LL_RCC_PLLSOURCE_HSI 04859 * @arg @ref LL_RCC_PLLSOURCE_HSE 04860 * @retval None 04861 */ 04862 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) 04863 { 04864 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); 04865 } 04866 04867 /** 04868 * @brief Get the oscillator used as PLL clock source. 04869 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource 04870 * @retval Returned value can be one of the following values: 04871 * @arg @ref LL_RCC_PLLSOURCE_HSI 04872 * @arg @ref LL_RCC_PLLSOURCE_HSE 04873 */ 04874 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) 04875 { 04876 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); 04877 } 04878 04879 /** 04880 * @brief Get Main PLL multiplication factor for VCO 04881 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN 04882 * @retval Between 50/192(*) and 432 04883 * 04884 * (*) value not defined in all devices. 04885 */ 04886 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) 04887 { 04888 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 04889 } 04890 04891 /** 04892 * @brief Get Main PLL division factor for PLLP 04893 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP 04894 * @retval Returned value can be one of the following values: 04895 * @arg @ref LL_RCC_PLLP_DIV_2 04896 * @arg @ref LL_RCC_PLLP_DIV_4 04897 * @arg @ref LL_RCC_PLLP_DIV_6 04898 * @arg @ref LL_RCC_PLLP_DIV_8 04899 */ 04900 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) 04901 { 04902 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); 04903 } 04904 04905 /** 04906 * @brief Get Main PLL division factor for PLLQ 04907 * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock) 04908 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ 04909 * @retval Returned value can be one of the following values: 04910 * @arg @ref LL_RCC_PLLQ_DIV_2 04911 * @arg @ref LL_RCC_PLLQ_DIV_3 04912 * @arg @ref LL_RCC_PLLQ_DIV_4 04913 * @arg @ref LL_RCC_PLLQ_DIV_5 04914 * @arg @ref LL_RCC_PLLQ_DIV_6 04915 * @arg @ref LL_RCC_PLLQ_DIV_7 04916 * @arg @ref LL_RCC_PLLQ_DIV_8 04917 * @arg @ref LL_RCC_PLLQ_DIV_9 04918 * @arg @ref LL_RCC_PLLQ_DIV_10 04919 * @arg @ref LL_RCC_PLLQ_DIV_11 04920 * @arg @ref LL_RCC_PLLQ_DIV_12 04921 * @arg @ref LL_RCC_PLLQ_DIV_13 04922 * @arg @ref LL_RCC_PLLQ_DIV_14 04923 * @arg @ref LL_RCC_PLLQ_DIV_15 04924 */ 04925 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) 04926 { 04927 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); 04928 } 04929 04930 #if defined(RCC_PLLCFGR_PLLR) 04931 /** 04932 * @brief Get Main PLL division factor for PLLR 04933 * @note used for PLLCLK (system clock) 04934 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR 04935 * @retval Returned value can be one of the following values: 04936 * @arg @ref LL_RCC_PLLR_DIV_2 04937 * @arg @ref LL_RCC_PLLR_DIV_3 04938 * @arg @ref LL_RCC_PLLR_DIV_4 04939 * @arg @ref LL_RCC_PLLR_DIV_5 04940 * @arg @ref LL_RCC_PLLR_DIV_6 04941 * @arg @ref LL_RCC_PLLR_DIV_7 04942 */ 04943 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) 04944 { 04945 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); 04946 } 04947 #endif /* RCC_PLLCFGR_PLLR */ 04948 04949 #if defined(RCC_DCKCFGR_PLLDIVR) 04950 /** 04951 * @brief Get Main PLL division factor for PLLDIVR 04952 * @note used for PLLSAICLK (SAI1 and SAI2 clock) 04953 * @rmtoll DCKCFGR PLLDIVR LL_RCC_PLL_GetDIVR 04954 * @retval Returned value can be one of the following values: 04955 * @arg @ref LL_RCC_PLLDIVR_DIV_1 04956 * @arg @ref LL_RCC_PLLDIVR_DIV_2 04957 * @arg @ref LL_RCC_PLLDIVR_DIV_3 04958 * @arg @ref LL_RCC_PLLDIVR_DIV_4 04959 * @arg @ref LL_RCC_PLLDIVR_DIV_5 04960 * @arg @ref LL_RCC_PLLDIVR_DIV_6 04961 * @arg @ref LL_RCC_PLLDIVR_DIV_7 04962 * @arg @ref LL_RCC_PLLDIVR_DIV_8 04963 * @arg @ref LL_RCC_PLLDIVR_DIV_9 04964 * @arg @ref LL_RCC_PLLDIVR_DIV_10 04965 * @arg @ref LL_RCC_PLLDIVR_DIV_11 04966 * @arg @ref LL_RCC_PLLDIVR_DIV_12 04967 * @arg @ref LL_RCC_PLLDIVR_DIV_13 04968 * @arg @ref LL_RCC_PLLDIVR_DIV_14 04969 * @arg @ref LL_RCC_PLLDIVR_DIV_15 04970 * @arg @ref LL_RCC_PLLDIVR_DIV_16 04971 * @arg @ref LL_RCC_PLLDIVR_DIV_17 04972 * @arg @ref LL_RCC_PLLDIVR_DIV_18 04973 * @arg @ref LL_RCC_PLLDIVR_DIV_19 04974 * @arg @ref LL_RCC_PLLDIVR_DIV_20 04975 * @arg @ref LL_RCC_PLLDIVR_DIV_21 04976 * @arg @ref LL_RCC_PLLDIVR_DIV_22 04977 * @arg @ref LL_RCC_PLLDIVR_DIV_23 04978 * @arg @ref LL_RCC_PLLDIVR_DIV_24 04979 * @arg @ref LL_RCC_PLLDIVR_DIV_25 04980 * @arg @ref LL_RCC_PLLDIVR_DIV_26 04981 * @arg @ref LL_RCC_PLLDIVR_DIV_27 04982 * @arg @ref LL_RCC_PLLDIVR_DIV_28 04983 * @arg @ref LL_RCC_PLLDIVR_DIV_29 04984 * @arg @ref LL_RCC_PLLDIVR_DIV_30 04985 * @arg @ref LL_RCC_PLLDIVR_DIV_31 04986 */ 04987 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void) 04988 { 04989 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR)); 04990 } 04991 #endif /* RCC_DCKCFGR_PLLDIVR */ 04992 04993 /** 04994 * @brief Get Division factor for the main PLL and other PLL 04995 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider 04996 * @retval Returned value can be one of the following values: 04997 * @arg @ref LL_RCC_PLLM_DIV_2 04998 * @arg @ref LL_RCC_PLLM_DIV_3 04999 * @arg @ref LL_RCC_PLLM_DIV_4 05000 * @arg @ref LL_RCC_PLLM_DIV_5 05001 * @arg @ref LL_RCC_PLLM_DIV_6 05002 * @arg @ref LL_RCC_PLLM_DIV_7 05003 * @arg @ref LL_RCC_PLLM_DIV_8 05004 * @arg @ref LL_RCC_PLLM_DIV_9 05005 * @arg @ref LL_RCC_PLLM_DIV_10 05006 * @arg @ref LL_RCC_PLLM_DIV_11 05007 * @arg @ref LL_RCC_PLLM_DIV_12 05008 * @arg @ref LL_RCC_PLLM_DIV_13 05009 * @arg @ref LL_RCC_PLLM_DIV_14 05010 * @arg @ref LL_RCC_PLLM_DIV_15 05011 * @arg @ref LL_RCC_PLLM_DIV_16 05012 * @arg @ref LL_RCC_PLLM_DIV_17 05013 * @arg @ref LL_RCC_PLLM_DIV_18 05014 * @arg @ref LL_RCC_PLLM_DIV_19 05015 * @arg @ref LL_RCC_PLLM_DIV_20 05016 * @arg @ref LL_RCC_PLLM_DIV_21 05017 * @arg @ref LL_RCC_PLLM_DIV_22 05018 * @arg @ref LL_RCC_PLLM_DIV_23 05019 * @arg @ref LL_RCC_PLLM_DIV_24 05020 * @arg @ref LL_RCC_PLLM_DIV_25 05021 * @arg @ref LL_RCC_PLLM_DIV_26 05022 * @arg @ref LL_RCC_PLLM_DIV_27 05023 * @arg @ref LL_RCC_PLLM_DIV_28 05024 * @arg @ref LL_RCC_PLLM_DIV_29 05025 * @arg @ref LL_RCC_PLLM_DIV_30 05026 * @arg @ref LL_RCC_PLLM_DIV_31 05027 * @arg @ref LL_RCC_PLLM_DIV_32 05028 * @arg @ref LL_RCC_PLLM_DIV_33 05029 * @arg @ref LL_RCC_PLLM_DIV_34 05030 * @arg @ref LL_RCC_PLLM_DIV_35 05031 * @arg @ref LL_RCC_PLLM_DIV_36 05032 * @arg @ref LL_RCC_PLLM_DIV_37 05033 * @arg @ref LL_RCC_PLLM_DIV_38 05034 * @arg @ref LL_RCC_PLLM_DIV_39 05035 * @arg @ref LL_RCC_PLLM_DIV_40 05036 * @arg @ref LL_RCC_PLLM_DIV_41 05037 * @arg @ref LL_RCC_PLLM_DIV_42 05038 * @arg @ref LL_RCC_PLLM_DIV_43 05039 * @arg @ref LL_RCC_PLLM_DIV_44 05040 * @arg @ref LL_RCC_PLLM_DIV_45 05041 * @arg @ref LL_RCC_PLLM_DIV_46 05042 * @arg @ref LL_RCC_PLLM_DIV_47 05043 * @arg @ref LL_RCC_PLLM_DIV_48 05044 * @arg @ref LL_RCC_PLLM_DIV_49 05045 * @arg @ref LL_RCC_PLLM_DIV_50 05046 * @arg @ref LL_RCC_PLLM_DIV_51 05047 * @arg @ref LL_RCC_PLLM_DIV_52 05048 * @arg @ref LL_RCC_PLLM_DIV_53 05049 * @arg @ref LL_RCC_PLLM_DIV_54 05050 * @arg @ref LL_RCC_PLLM_DIV_55 05051 * @arg @ref LL_RCC_PLLM_DIV_56 05052 * @arg @ref LL_RCC_PLLM_DIV_57 05053 * @arg @ref LL_RCC_PLLM_DIV_58 05054 * @arg @ref LL_RCC_PLLM_DIV_59 05055 * @arg @ref LL_RCC_PLLM_DIV_60 05056 * @arg @ref LL_RCC_PLLM_DIV_61 05057 * @arg @ref LL_RCC_PLLM_DIV_62 05058 * @arg @ref LL_RCC_PLLM_DIV_63 05059 */ 05060 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) 05061 { 05062 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); 05063 } 05064 05065 /** 05066 * @brief Configure Spread Spectrum used for PLL 05067 * @note These bits must be written before enabling PLL 05068 * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n 05069 * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n 05070 * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum 05071 * @param Mod Between Min_Data=0 and Max_Data=8191 05072 * @param Inc Between Min_Data=0 and Max_Data=32767 05073 * @param Sel This parameter can be one of the following values: 05074 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER 05075 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN 05076 * @retval None 05077 */ 05078 __STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel) 05079 { 05080 MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel); 05081 } 05082 05083 /** 05084 * @brief Get Spread Spectrum Modulation Period for PLL 05085 * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation 05086 * @retval Between Min_Data=0 and Max_Data=8191 05087 */ 05088 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void) 05089 { 05090 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER)); 05091 } 05092 05093 /** 05094 * @brief Get Spread Spectrum Incrementation Step for PLL 05095 * @note Must be written before enabling PLL 05096 * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation 05097 * @retval Between Min_Data=0 and Max_Data=32767 05098 */ 05099 __STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void) 05100 { 05101 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos); 05102 } 05103 05104 /** 05105 * @brief Get Spread Spectrum Selection for PLL 05106 * @note Must be written before enabling PLL 05107 * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection 05108 * @retval Returned value can be one of the following values: 05109 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER 05110 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN 05111 */ 05112 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void) 05113 { 05114 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL)); 05115 } 05116 05117 /** 05118 * @brief Enable Spread Spectrum for PLL. 05119 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable 05120 * @retval None 05121 */ 05122 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void) 05123 { 05124 SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); 05125 } 05126 05127 /** 05128 * @brief Disable Spread Spectrum for PLL. 05129 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable 05130 * @retval None 05131 */ 05132 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void) 05133 { 05134 CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); 05135 } 05136 05137 /** 05138 * @} 05139 */ 05140 05141 #if defined(RCC_PLLI2S_SUPPORT) 05142 /** @defgroup RCC_LL_EF_PLLI2S PLLI2S 05143 * @{ 05144 */ 05145 05146 /** 05147 * @brief Enable PLLI2S 05148 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable 05149 * @retval None 05150 */ 05151 __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) 05152 { 05153 SET_BIT(RCC->CR, RCC_CR_PLLI2SON); 05154 } 05155 05156 /** 05157 * @brief Disable PLLI2S 05158 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable 05159 * @retval None 05160 */ 05161 __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) 05162 { 05163 CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); 05164 } 05165 05166 /** 05167 * @brief Check if PLLI2S Ready 05168 * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady 05169 * @retval State of bit (1 or 0). 05170 */ 05171 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) 05172 { 05173 return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY)); 05174 } 05175 05176 #if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)) 05177 /** 05178 * @brief Configure PLLI2S used for SAI domain clock 05179 * @note PLL Source and PLLM Divider can be written only when PLL, 05180 * PLLI2S and PLLSAI(*) are disabled 05181 * @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled 05182 * @note This can be selected for SAI 05183 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n 05184 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n 05185 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n 05186 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SAI\n 05187 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n 05188 * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n 05189 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_SAI\n 05190 * DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI\n 05191 * DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_ConfigDomain_SAI 05192 * @param Source This parameter can be one of the following values: 05193 * @arg @ref LL_RCC_PLLSOURCE_HSI 05194 * @arg @ref LL_RCC_PLLSOURCE_HSE 05195 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) 05196 * 05197 * (*) value not defined in all devices. 05198 * @param PLLM This parameter can be one of the following values: 05199 * @arg @ref LL_RCC_PLLI2SM_DIV_2 05200 * @arg @ref LL_RCC_PLLI2SM_DIV_3 05201 * @arg @ref LL_RCC_PLLI2SM_DIV_4 05202 * @arg @ref LL_RCC_PLLI2SM_DIV_5 05203 * @arg @ref LL_RCC_PLLI2SM_DIV_6 05204 * @arg @ref LL_RCC_PLLI2SM_DIV_7 05205 * @arg @ref LL_RCC_PLLI2SM_DIV_8 05206 * @arg @ref LL_RCC_PLLI2SM_DIV_9 05207 * @arg @ref LL_RCC_PLLI2SM_DIV_10 05208 * @arg @ref LL_RCC_PLLI2SM_DIV_11 05209 * @arg @ref LL_RCC_PLLI2SM_DIV_12 05210 * @arg @ref LL_RCC_PLLI2SM_DIV_13 05211 * @arg @ref LL_RCC_PLLI2SM_DIV_14 05212 * @arg @ref LL_RCC_PLLI2SM_DIV_15 05213 * @arg @ref LL_RCC_PLLI2SM_DIV_16 05214 * @arg @ref LL_RCC_PLLI2SM_DIV_17 05215 * @arg @ref LL_RCC_PLLI2SM_DIV_18 05216 * @arg @ref LL_RCC_PLLI2SM_DIV_19 05217 * @arg @ref LL_RCC_PLLI2SM_DIV_20 05218 * @arg @ref LL_RCC_PLLI2SM_DIV_21 05219 * @arg @ref LL_RCC_PLLI2SM_DIV_22 05220 * @arg @ref LL_RCC_PLLI2SM_DIV_23 05221 * @arg @ref LL_RCC_PLLI2SM_DIV_24 05222 * @arg @ref LL_RCC_PLLI2SM_DIV_25 05223 * @arg @ref LL_RCC_PLLI2SM_DIV_26 05224 * @arg @ref LL_RCC_PLLI2SM_DIV_27 05225 * @arg @ref LL_RCC_PLLI2SM_DIV_28 05226 * @arg @ref LL_RCC_PLLI2SM_DIV_29 05227 * @arg @ref LL_RCC_PLLI2SM_DIV_30 05228 * @arg @ref LL_RCC_PLLI2SM_DIV_31 05229 * @arg @ref LL_RCC_PLLI2SM_DIV_32 05230 * @arg @ref LL_RCC_PLLI2SM_DIV_33 05231 * @arg @ref LL_RCC_PLLI2SM_DIV_34 05232 * @arg @ref LL_RCC_PLLI2SM_DIV_35 05233 * @arg @ref LL_RCC_PLLI2SM_DIV_36 05234 * @arg @ref LL_RCC_PLLI2SM_DIV_37 05235 * @arg @ref LL_RCC_PLLI2SM_DIV_38 05236 * @arg @ref LL_RCC_PLLI2SM_DIV_39 05237 * @arg @ref LL_RCC_PLLI2SM_DIV_40 05238 * @arg @ref LL_RCC_PLLI2SM_DIV_41 05239 * @arg @ref LL_RCC_PLLI2SM_DIV_42 05240 * @arg @ref LL_RCC_PLLI2SM_DIV_43 05241 * @arg @ref LL_RCC_PLLI2SM_DIV_44 05242 * @arg @ref LL_RCC_PLLI2SM_DIV_45 05243 * @arg @ref LL_RCC_PLLI2SM_DIV_46 05244 * @arg @ref LL_RCC_PLLI2SM_DIV_47 05245 * @arg @ref LL_RCC_PLLI2SM_DIV_48 05246 * @arg @ref LL_RCC_PLLI2SM_DIV_49 05247 * @arg @ref LL_RCC_PLLI2SM_DIV_50 05248 * @arg @ref LL_RCC_PLLI2SM_DIV_51 05249 * @arg @ref LL_RCC_PLLI2SM_DIV_52 05250 * @arg @ref LL_RCC_PLLI2SM_DIV_53 05251 * @arg @ref LL_RCC_PLLI2SM_DIV_54 05252 * @arg @ref LL_RCC_PLLI2SM_DIV_55 05253 * @arg @ref LL_RCC_PLLI2SM_DIV_56 05254 * @arg @ref LL_RCC_PLLI2SM_DIV_57 05255 * @arg @ref LL_RCC_PLLI2SM_DIV_58 05256 * @arg @ref LL_RCC_PLLI2SM_DIV_59 05257 * @arg @ref LL_RCC_PLLI2SM_DIV_60 05258 * @arg @ref LL_RCC_PLLI2SM_DIV_61 05259 * @arg @ref LL_RCC_PLLI2SM_DIV_62 05260 * @arg @ref LL_RCC_PLLI2SM_DIV_63 05261 * @param PLLN Between 50/192(*) and 432 05262 * 05263 * (*) value not defined in all devices. 05264 * @param PLLQ_R This parameter can be one of the following values: 05265 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*) 05266 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*) 05267 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*) 05268 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*) 05269 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*) 05270 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*) 05271 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*) 05272 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*) 05273 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*) 05274 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*) 05275 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*) 05276 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*) 05277 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*) 05278 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*) 05279 * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*) 05280 * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*) 05281 * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*) 05282 * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*) 05283 * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*) 05284 * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*) 05285 * 05286 * (*) value not defined in all devices. 05287 * @param PLLDIVQ_R This parameter can be one of the following values: 05288 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*) 05289 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*) 05290 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*) 05291 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*) 05292 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*) 05293 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*) 05294 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*) 05295 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*) 05296 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*) 05297 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*) 05298 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*) 05299 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*) 05300 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*) 05301 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*) 05302 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*) 05303 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*) 05304 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*) 05305 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*) 05306 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*) 05307 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*) 05308 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*) 05309 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*) 05310 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*) 05311 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*) 05312 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*) 05313 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*) 05314 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*) 05315 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*) 05316 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*) 05317 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*) 05318 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*) 05319 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*) 05320 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*) 05321 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*) 05322 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*) 05323 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*) 05324 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*) 05325 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*) 05326 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*) 05327 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*) 05328 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*) 05329 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*) 05330 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*) 05331 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*) 05332 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*) 05333 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*) 05334 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*) 05335 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*) 05336 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*) 05337 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*) 05338 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*) 05339 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*) 05340 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*) 05341 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*) 05342 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*) 05343 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*) 05344 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*) 05345 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*) 05346 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*) 05347 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*) 05348 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*) 05349 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*) 05350 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*) 05351 * 05352 * (*) value not defined in all devices. 05353 * @retval None 05354 */ 05355 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R) 05356 { 05357 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); 05358 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); 05359 #if defined(RCC_PLLI2SCFGR_PLLI2SM) 05360 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); 05361 #else 05362 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); 05363 #endif /* RCC_PLLI2SCFGR_PLLI2SM */ 05364 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos); 05365 #if defined(RCC_DCKCFGR_PLLI2SDIVQ) 05366 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R); 05367 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R); 05368 #else 05369 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R); 05370 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R); 05371 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */ 05372 } 05373 #endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */ 05374 05375 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) 05376 /** 05377 * @brief Configure PLLI2S used for 48Mhz domain clock 05378 * @note PLL Source and PLLM Divider can be written only when PLL, 05379 * PLLI2S and PLLSAI(*) are disabled 05380 * @note PLLN/PLLQ can be written only when PLLI2S is disabled 05381 * @note This can be selected for RNG, USB, SDIO 05382 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_48M\n 05383 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_48M\n 05384 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_48M\n 05385 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_48M\n 05386 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_48M\n 05387 * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_48M 05388 * @param Source This parameter can be one of the following values: 05389 * @arg @ref LL_RCC_PLLSOURCE_HSI 05390 * @arg @ref LL_RCC_PLLSOURCE_HSE 05391 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) 05392 * 05393 * (*) value not defined in all devices. 05394 * @param PLLM This parameter can be one of the following values: 05395 * @arg @ref LL_RCC_PLLI2SM_DIV_2 05396 * @arg @ref LL_RCC_PLLI2SM_DIV_3 05397 * @arg @ref LL_RCC_PLLI2SM_DIV_4 05398 * @arg @ref LL_RCC_PLLI2SM_DIV_5 05399 * @arg @ref LL_RCC_PLLI2SM_DIV_6 05400 * @arg @ref LL_RCC_PLLI2SM_DIV_7 05401 * @arg @ref LL_RCC_PLLI2SM_DIV_8 05402 * @arg @ref LL_RCC_PLLI2SM_DIV_9 05403 * @arg @ref LL_RCC_PLLI2SM_DIV_10 05404 * @arg @ref LL_RCC_PLLI2SM_DIV_11 05405 * @arg @ref LL_RCC_PLLI2SM_DIV_12 05406 * @arg @ref LL_RCC_PLLI2SM_DIV_13 05407 * @arg @ref LL_RCC_PLLI2SM_DIV_14 05408 * @arg @ref LL_RCC_PLLI2SM_DIV_15 05409 * @arg @ref LL_RCC_PLLI2SM_DIV_16 05410 * @arg @ref LL_RCC_PLLI2SM_DIV_17 05411 * @arg @ref LL_RCC_PLLI2SM_DIV_18 05412 * @arg @ref LL_RCC_PLLI2SM_DIV_19 05413 * @arg @ref LL_RCC_PLLI2SM_DIV_20 05414 * @arg @ref LL_RCC_PLLI2SM_DIV_21 05415 * @arg @ref LL_RCC_PLLI2SM_DIV_22 05416 * @arg @ref LL_RCC_PLLI2SM_DIV_23 05417 * @arg @ref LL_RCC_PLLI2SM_DIV_24 05418 * @arg @ref LL_RCC_PLLI2SM_DIV_25 05419 * @arg @ref LL_RCC_PLLI2SM_DIV_26 05420 * @arg @ref LL_RCC_PLLI2SM_DIV_27 05421 * @arg @ref LL_RCC_PLLI2SM_DIV_28 05422 * @arg @ref LL_RCC_PLLI2SM_DIV_29 05423 * @arg @ref LL_RCC_PLLI2SM_DIV_30 05424 * @arg @ref LL_RCC_PLLI2SM_DIV_31 05425 * @arg @ref LL_RCC_PLLI2SM_DIV_32 05426 * @arg @ref LL_RCC_PLLI2SM_DIV_33 05427 * @arg @ref LL_RCC_PLLI2SM_DIV_34 05428 * @arg @ref LL_RCC_PLLI2SM_DIV_35 05429 * @arg @ref LL_RCC_PLLI2SM_DIV_36 05430 * @arg @ref LL_RCC_PLLI2SM_DIV_37 05431 * @arg @ref LL_RCC_PLLI2SM_DIV_38 05432 * @arg @ref LL_RCC_PLLI2SM_DIV_39 05433 * @arg @ref LL_RCC_PLLI2SM_DIV_40 05434 * @arg @ref LL_RCC_PLLI2SM_DIV_41 05435 * @arg @ref LL_RCC_PLLI2SM_DIV_42 05436 * @arg @ref LL_RCC_PLLI2SM_DIV_43 05437 * @arg @ref LL_RCC_PLLI2SM_DIV_44 05438 * @arg @ref LL_RCC_PLLI2SM_DIV_45 05439 * @arg @ref LL_RCC_PLLI2SM_DIV_46 05440 * @arg @ref LL_RCC_PLLI2SM_DIV_47 05441 * @arg @ref LL_RCC_PLLI2SM_DIV_48 05442 * @arg @ref LL_RCC_PLLI2SM_DIV_49 05443 * @arg @ref LL_RCC_PLLI2SM_DIV_50 05444 * @arg @ref LL_RCC_PLLI2SM_DIV_51 05445 * @arg @ref LL_RCC_PLLI2SM_DIV_52 05446 * @arg @ref LL_RCC_PLLI2SM_DIV_53 05447 * @arg @ref LL_RCC_PLLI2SM_DIV_54 05448 * @arg @ref LL_RCC_PLLI2SM_DIV_55 05449 * @arg @ref LL_RCC_PLLI2SM_DIV_56 05450 * @arg @ref LL_RCC_PLLI2SM_DIV_57 05451 * @arg @ref LL_RCC_PLLI2SM_DIV_58 05452 * @arg @ref LL_RCC_PLLI2SM_DIV_59 05453 * @arg @ref LL_RCC_PLLI2SM_DIV_60 05454 * @arg @ref LL_RCC_PLLI2SM_DIV_61 05455 * @arg @ref LL_RCC_PLLI2SM_DIV_62 05456 * @arg @ref LL_RCC_PLLI2SM_DIV_63 05457 * @param PLLN Between 50 and 432 05458 * @param PLLQ This parameter can be one of the following values: 05459 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 05460 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 05461 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 05462 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 05463 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 05464 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 05465 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 05466 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 05467 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 05468 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 05469 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 05470 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 05471 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 05472 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 05473 * @retval None 05474 */ 05475 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) 05476 { 05477 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); 05478 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); 05479 #if defined(RCC_PLLI2SCFGR_PLLI2SM) 05480 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); 05481 #else 05482 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); 05483 #endif /* RCC_PLLI2SCFGR_PLLI2SM */ 05484 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ); 05485 } 05486 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ 05487 05488 #if defined(SPDIFRX) 05489 /** 05490 * @brief Configure PLLI2S used for SPDIFRX domain clock 05491 * @note PLL Source and PLLM Divider can be written only when PLL, 05492 * PLLI2S and PLLSAI(*) are disabled 05493 * @note PLLN/PLLP can be written only when PLLI2S is disabled 05494 * @note This can be selected for SPDIFRX 05495 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n 05496 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n 05497 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n 05498 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n 05499 * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX 05500 * @param Source This parameter can be one of the following values: 05501 * @arg @ref LL_RCC_PLLSOURCE_HSI 05502 * @arg @ref LL_RCC_PLLSOURCE_HSE 05503 * @param PLLM This parameter can be one of the following values: 05504 * @arg @ref LL_RCC_PLLI2SM_DIV_2 05505 * @arg @ref LL_RCC_PLLI2SM_DIV_3 05506 * @arg @ref LL_RCC_PLLI2SM_DIV_4 05507 * @arg @ref LL_RCC_PLLI2SM_DIV_5 05508 * @arg @ref LL_RCC_PLLI2SM_DIV_6 05509 * @arg @ref LL_RCC_PLLI2SM_DIV_7 05510 * @arg @ref LL_RCC_PLLI2SM_DIV_8 05511 * @arg @ref LL_RCC_PLLI2SM_DIV_9 05512 * @arg @ref LL_RCC_PLLI2SM_DIV_10 05513 * @arg @ref LL_RCC_PLLI2SM_DIV_11 05514 * @arg @ref LL_RCC_PLLI2SM_DIV_12 05515 * @arg @ref LL_RCC_PLLI2SM_DIV_13 05516 * @arg @ref LL_RCC_PLLI2SM_DIV_14 05517 * @arg @ref LL_RCC_PLLI2SM_DIV_15 05518 * @arg @ref LL_RCC_PLLI2SM_DIV_16 05519 * @arg @ref LL_RCC_PLLI2SM_DIV_17 05520 * @arg @ref LL_RCC_PLLI2SM_DIV_18 05521 * @arg @ref LL_RCC_PLLI2SM_DIV_19 05522 * @arg @ref LL_RCC_PLLI2SM_DIV_20 05523 * @arg @ref LL_RCC_PLLI2SM_DIV_21 05524 * @arg @ref LL_RCC_PLLI2SM_DIV_22 05525 * @arg @ref LL_RCC_PLLI2SM_DIV_23 05526 * @arg @ref LL_RCC_PLLI2SM_DIV_24 05527 * @arg @ref LL_RCC_PLLI2SM_DIV_25 05528 * @arg @ref LL_RCC_PLLI2SM_DIV_26 05529 * @arg @ref LL_RCC_PLLI2SM_DIV_27 05530 * @arg @ref LL_RCC_PLLI2SM_DIV_28 05531 * @arg @ref LL_RCC_PLLI2SM_DIV_29 05532 * @arg @ref LL_RCC_PLLI2SM_DIV_30 05533 * @arg @ref LL_RCC_PLLI2SM_DIV_31 05534 * @arg @ref LL_RCC_PLLI2SM_DIV_32 05535 * @arg @ref LL_RCC_PLLI2SM_DIV_33 05536 * @arg @ref LL_RCC_PLLI2SM_DIV_34 05537 * @arg @ref LL_RCC_PLLI2SM_DIV_35 05538 * @arg @ref LL_RCC_PLLI2SM_DIV_36 05539 * @arg @ref LL_RCC_PLLI2SM_DIV_37 05540 * @arg @ref LL_RCC_PLLI2SM_DIV_38 05541 * @arg @ref LL_RCC_PLLI2SM_DIV_39 05542 * @arg @ref LL_RCC_PLLI2SM_DIV_40 05543 * @arg @ref LL_RCC_PLLI2SM_DIV_41 05544 * @arg @ref LL_RCC_PLLI2SM_DIV_42 05545 * @arg @ref LL_RCC_PLLI2SM_DIV_43 05546 * @arg @ref LL_RCC_PLLI2SM_DIV_44 05547 * @arg @ref LL_RCC_PLLI2SM_DIV_45 05548 * @arg @ref LL_RCC_PLLI2SM_DIV_46 05549 * @arg @ref LL_RCC_PLLI2SM_DIV_47 05550 * @arg @ref LL_RCC_PLLI2SM_DIV_48 05551 * @arg @ref LL_RCC_PLLI2SM_DIV_49 05552 * @arg @ref LL_RCC_PLLI2SM_DIV_50 05553 * @arg @ref LL_RCC_PLLI2SM_DIV_51 05554 * @arg @ref LL_RCC_PLLI2SM_DIV_52 05555 * @arg @ref LL_RCC_PLLI2SM_DIV_53 05556 * @arg @ref LL_RCC_PLLI2SM_DIV_54 05557 * @arg @ref LL_RCC_PLLI2SM_DIV_55 05558 * @arg @ref LL_RCC_PLLI2SM_DIV_56 05559 * @arg @ref LL_RCC_PLLI2SM_DIV_57 05560 * @arg @ref LL_RCC_PLLI2SM_DIV_58 05561 * @arg @ref LL_RCC_PLLI2SM_DIV_59 05562 * @arg @ref LL_RCC_PLLI2SM_DIV_60 05563 * @arg @ref LL_RCC_PLLI2SM_DIV_61 05564 * @arg @ref LL_RCC_PLLI2SM_DIV_62 05565 * @arg @ref LL_RCC_PLLI2SM_DIV_63 05566 * @param PLLN Between 50 and 432 05567 * @param PLLP This parameter can be one of the following values: 05568 * @arg @ref LL_RCC_PLLI2SP_DIV_2 05569 * @arg @ref LL_RCC_PLLI2SP_DIV_4 05570 * @arg @ref LL_RCC_PLLI2SP_DIV_6 05571 * @arg @ref LL_RCC_PLLI2SP_DIV_8 05572 * @retval None 05573 */ 05574 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 05575 { 05576 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 05577 #if defined(RCC_PLLI2SCFGR_PLLI2SM) 05578 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); 05579 #else 05580 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); 05581 #endif /* RCC_PLLI2SCFGR_PLLI2SM */ 05582 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP); 05583 } 05584 #endif /* SPDIFRX */ 05585 05586 /** 05587 * @brief Configure PLLI2S used for I2S1 domain clock 05588 * @note PLL Source and PLLM Divider can be written only when PLL, 05589 * PLLI2S and PLLSAI(*) are disabled 05590 * @note PLLN/PLLR can be written only when PLLI2S is disabled 05591 * @note This can be selected for I2S 05592 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n 05593 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n 05594 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n 05595 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_I2S\n 05596 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n 05597 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S 05598 * @param Source This parameter can be one of the following values: 05599 * @arg @ref LL_RCC_PLLSOURCE_HSI 05600 * @arg @ref LL_RCC_PLLSOURCE_HSE 05601 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) 05602 * 05603 * (*) value not defined in all devices. 05604 * @param PLLM This parameter can be one of the following values: 05605 * @arg @ref LL_RCC_PLLI2SM_DIV_2 05606 * @arg @ref LL_RCC_PLLI2SM_DIV_3 05607 * @arg @ref LL_RCC_PLLI2SM_DIV_4 05608 * @arg @ref LL_RCC_PLLI2SM_DIV_5 05609 * @arg @ref LL_RCC_PLLI2SM_DIV_6 05610 * @arg @ref LL_RCC_PLLI2SM_DIV_7 05611 * @arg @ref LL_RCC_PLLI2SM_DIV_8 05612 * @arg @ref LL_RCC_PLLI2SM_DIV_9 05613 * @arg @ref LL_RCC_PLLI2SM_DIV_10 05614 * @arg @ref LL_RCC_PLLI2SM_DIV_11 05615 * @arg @ref LL_RCC_PLLI2SM_DIV_12 05616 * @arg @ref LL_RCC_PLLI2SM_DIV_13 05617 * @arg @ref LL_RCC_PLLI2SM_DIV_14 05618 * @arg @ref LL_RCC_PLLI2SM_DIV_15 05619 * @arg @ref LL_RCC_PLLI2SM_DIV_16 05620 * @arg @ref LL_RCC_PLLI2SM_DIV_17 05621 * @arg @ref LL_RCC_PLLI2SM_DIV_18 05622 * @arg @ref LL_RCC_PLLI2SM_DIV_19 05623 * @arg @ref LL_RCC_PLLI2SM_DIV_20 05624 * @arg @ref LL_RCC_PLLI2SM_DIV_21 05625 * @arg @ref LL_RCC_PLLI2SM_DIV_22 05626 * @arg @ref LL_RCC_PLLI2SM_DIV_23 05627 * @arg @ref LL_RCC_PLLI2SM_DIV_24 05628 * @arg @ref LL_RCC_PLLI2SM_DIV_25 05629 * @arg @ref LL_RCC_PLLI2SM_DIV_26 05630 * @arg @ref LL_RCC_PLLI2SM_DIV_27 05631 * @arg @ref LL_RCC_PLLI2SM_DIV_28 05632 * @arg @ref LL_RCC_PLLI2SM_DIV_29 05633 * @arg @ref LL_RCC_PLLI2SM_DIV_30 05634 * @arg @ref LL_RCC_PLLI2SM_DIV_31 05635 * @arg @ref LL_RCC_PLLI2SM_DIV_32 05636 * @arg @ref LL_RCC_PLLI2SM_DIV_33 05637 * @arg @ref LL_RCC_PLLI2SM_DIV_34 05638 * @arg @ref LL_RCC_PLLI2SM_DIV_35 05639 * @arg @ref LL_RCC_PLLI2SM_DIV_36 05640 * @arg @ref LL_RCC_PLLI2SM_DIV_37 05641 * @arg @ref LL_RCC_PLLI2SM_DIV_38 05642 * @arg @ref LL_RCC_PLLI2SM_DIV_39 05643 * @arg @ref LL_RCC_PLLI2SM_DIV_40 05644 * @arg @ref LL_RCC_PLLI2SM_DIV_41 05645 * @arg @ref LL_RCC_PLLI2SM_DIV_42 05646 * @arg @ref LL_RCC_PLLI2SM_DIV_43 05647 * @arg @ref LL_RCC_PLLI2SM_DIV_44 05648 * @arg @ref LL_RCC_PLLI2SM_DIV_45 05649 * @arg @ref LL_RCC_PLLI2SM_DIV_46 05650 * @arg @ref LL_RCC_PLLI2SM_DIV_47 05651 * @arg @ref LL_RCC_PLLI2SM_DIV_48 05652 * @arg @ref LL_RCC_PLLI2SM_DIV_49 05653 * @arg @ref LL_RCC_PLLI2SM_DIV_50 05654 * @arg @ref LL_RCC_PLLI2SM_DIV_51 05655 * @arg @ref LL_RCC_PLLI2SM_DIV_52 05656 * @arg @ref LL_RCC_PLLI2SM_DIV_53 05657 * @arg @ref LL_RCC_PLLI2SM_DIV_54 05658 * @arg @ref LL_RCC_PLLI2SM_DIV_55 05659 * @arg @ref LL_RCC_PLLI2SM_DIV_56 05660 * @arg @ref LL_RCC_PLLI2SM_DIV_57 05661 * @arg @ref LL_RCC_PLLI2SM_DIV_58 05662 * @arg @ref LL_RCC_PLLI2SM_DIV_59 05663 * @arg @ref LL_RCC_PLLI2SM_DIV_60 05664 * @arg @ref LL_RCC_PLLI2SM_DIV_61 05665 * @arg @ref LL_RCC_PLLI2SM_DIV_62 05666 * @arg @ref LL_RCC_PLLI2SM_DIV_63 05667 * @param PLLN Between 50/192(*) and 432 05668 * 05669 * (*) value not defined in all devices. 05670 * @param PLLR This parameter can be one of the following values: 05671 * @arg @ref LL_RCC_PLLI2SR_DIV_2 05672 * @arg @ref LL_RCC_PLLI2SR_DIV_3 05673 * @arg @ref LL_RCC_PLLI2SR_DIV_4 05674 * @arg @ref LL_RCC_PLLI2SR_DIV_5 05675 * @arg @ref LL_RCC_PLLI2SR_DIV_6 05676 * @arg @ref LL_RCC_PLLI2SR_DIV_7 05677 * @retval None 05678 */ 05679 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 05680 { 05681 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); 05682 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); 05683 #if defined(RCC_PLLI2SCFGR_PLLI2SM) 05684 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); 05685 #else 05686 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); 05687 #endif /* RCC_PLLI2SCFGR_PLLI2SM */ 05688 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR); 05689 } 05690 05691 /** 05692 * @brief Get I2SPLL multiplication factor for VCO 05693 * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN 05694 * @retval Between 50/192(*) and 432 05695 * 05696 * (*) value not defined in all devices. 05697 */ 05698 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void) 05699 { 05700 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); 05701 } 05702 05703 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) 05704 /** 05705 * @brief Get I2SPLL division factor for PLLI2SQ 05706 * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ 05707 * @retval Returned value can be one of the following values: 05708 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 05709 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 05710 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 05711 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 05712 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 05713 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 05714 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 05715 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 05716 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 05717 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 05718 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 05719 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 05720 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 05721 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 05722 */ 05723 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void) 05724 { 05725 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ)); 05726 } 05727 #endif /* RCC_PLLI2SCFGR_PLLI2SQ */ 05728 05729 /** 05730 * @brief Get I2SPLL division factor for PLLI2SR 05731 * @note used for PLLI2SCLK (I2S clock) 05732 * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR 05733 * @retval Returned value can be one of the following values: 05734 * @arg @ref LL_RCC_PLLI2SR_DIV_2 05735 * @arg @ref LL_RCC_PLLI2SR_DIV_3 05736 * @arg @ref LL_RCC_PLLI2SR_DIV_4 05737 * @arg @ref LL_RCC_PLLI2SR_DIV_5 05738 * @arg @ref LL_RCC_PLLI2SR_DIV_6 05739 * @arg @ref LL_RCC_PLLI2SR_DIV_7 05740 */ 05741 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void) 05742 { 05743 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR)); 05744 } 05745 05746 #if defined(RCC_PLLI2SCFGR_PLLI2SP) 05747 /** 05748 * @brief Get I2SPLL division factor for PLLI2SP 05749 * @note used for PLLSPDIFRXCLK (SPDIFRX clock) 05750 * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP 05751 * @retval Returned value can be one of the following values: 05752 * @arg @ref LL_RCC_PLLI2SP_DIV_2 05753 * @arg @ref LL_RCC_PLLI2SP_DIV_4 05754 * @arg @ref LL_RCC_PLLI2SP_DIV_6 05755 * @arg @ref LL_RCC_PLLI2SP_DIV_8 05756 */ 05757 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void) 05758 { 05759 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP)); 05760 } 05761 #endif /* RCC_PLLI2SCFGR_PLLI2SP */ 05762 05763 #if defined(RCC_DCKCFGR_PLLI2SDIVQ) 05764 /** 05765 * @brief Get I2SPLL division factor for PLLI2SDIVQ 05766 * @note used PLLSAICLK selected (SAI clock) 05767 * @rmtoll DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ 05768 * @retval Returned value can be one of the following values: 05769 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 05770 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 05771 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 05772 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 05773 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 05774 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 05775 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 05776 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 05777 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 05778 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 05779 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 05780 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 05781 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 05782 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 05783 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 05784 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 05785 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 05786 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 05787 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 05788 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 05789 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 05790 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 05791 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 05792 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 05793 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 05794 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 05795 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 05796 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 05797 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 05798 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 05799 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 05800 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 05801 */ 05802 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void) 05803 { 05804 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ)); 05805 } 05806 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */ 05807 05808 #if defined(RCC_DCKCFGR_PLLI2SDIVR) 05809 /** 05810 * @brief Get I2SPLL division factor for PLLI2SDIVR 05811 * @note used PLLSAICLK selected (SAI clock) 05812 * @rmtoll DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_GetDIVR 05813 * @retval Returned value can be one of the following values: 05814 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 05815 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 05816 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 05817 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 05818 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 05819 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 05820 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 05821 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 05822 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 05823 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 05824 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 05825 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 05826 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 05827 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 05828 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 05829 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 05830 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 05831 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 05832 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 05833 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 05834 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 05835 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 05836 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 05837 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 05838 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 05839 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 05840 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 05841 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 05842 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 05843 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 05844 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 05845 */ 05846 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void) 05847 { 05848 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR)); 05849 } 05850 #endif /* RCC_DCKCFGR_PLLI2SDIVR */ 05851 05852 /** 05853 * @brief Get division factor for PLLI2S input clock 05854 * @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider\n 05855 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider 05856 * @retval Returned value can be one of the following values: 05857 * @arg @ref LL_RCC_PLLI2SM_DIV_2 05858 * @arg @ref LL_RCC_PLLI2SM_DIV_3 05859 * @arg @ref LL_RCC_PLLI2SM_DIV_4 05860 * @arg @ref LL_RCC_PLLI2SM_DIV_5 05861 * @arg @ref LL_RCC_PLLI2SM_DIV_6 05862 * @arg @ref LL_RCC_PLLI2SM_DIV_7 05863 * @arg @ref LL_RCC_PLLI2SM_DIV_8 05864 * @arg @ref LL_RCC_PLLI2SM_DIV_9 05865 * @arg @ref LL_RCC_PLLI2SM_DIV_10 05866 * @arg @ref LL_RCC_PLLI2SM_DIV_11 05867 * @arg @ref LL_RCC_PLLI2SM_DIV_12 05868 * @arg @ref LL_RCC_PLLI2SM_DIV_13 05869 * @arg @ref LL_RCC_PLLI2SM_DIV_14 05870 * @arg @ref LL_RCC_PLLI2SM_DIV_15 05871 * @arg @ref LL_RCC_PLLI2SM_DIV_16 05872 * @arg @ref LL_RCC_PLLI2SM_DIV_17 05873 * @arg @ref LL_RCC_PLLI2SM_DIV_18 05874 * @arg @ref LL_RCC_PLLI2SM_DIV_19 05875 * @arg @ref LL_RCC_PLLI2SM_DIV_20 05876 * @arg @ref LL_RCC_PLLI2SM_DIV_21 05877 * @arg @ref LL_RCC_PLLI2SM_DIV_22 05878 * @arg @ref LL_RCC_PLLI2SM_DIV_23 05879 * @arg @ref LL_RCC_PLLI2SM_DIV_24 05880 * @arg @ref LL_RCC_PLLI2SM_DIV_25 05881 * @arg @ref LL_RCC_PLLI2SM_DIV_26 05882 * @arg @ref LL_RCC_PLLI2SM_DIV_27 05883 * @arg @ref LL_RCC_PLLI2SM_DIV_28 05884 * @arg @ref LL_RCC_PLLI2SM_DIV_29 05885 * @arg @ref LL_RCC_PLLI2SM_DIV_30 05886 * @arg @ref LL_RCC_PLLI2SM_DIV_31 05887 * @arg @ref LL_RCC_PLLI2SM_DIV_32 05888 * @arg @ref LL_RCC_PLLI2SM_DIV_33 05889 * @arg @ref LL_RCC_PLLI2SM_DIV_34 05890 * @arg @ref LL_RCC_PLLI2SM_DIV_35 05891 * @arg @ref LL_RCC_PLLI2SM_DIV_36 05892 * @arg @ref LL_RCC_PLLI2SM_DIV_37 05893 * @arg @ref LL_RCC_PLLI2SM_DIV_38 05894 * @arg @ref LL_RCC_PLLI2SM_DIV_39 05895 * @arg @ref LL_RCC_PLLI2SM_DIV_40 05896 * @arg @ref LL_RCC_PLLI2SM_DIV_41 05897 * @arg @ref LL_RCC_PLLI2SM_DIV_42 05898 * @arg @ref LL_RCC_PLLI2SM_DIV_43 05899 * @arg @ref LL_RCC_PLLI2SM_DIV_44 05900 * @arg @ref LL_RCC_PLLI2SM_DIV_45 05901 * @arg @ref LL_RCC_PLLI2SM_DIV_46 05902 * @arg @ref LL_RCC_PLLI2SM_DIV_47 05903 * @arg @ref LL_RCC_PLLI2SM_DIV_48 05904 * @arg @ref LL_RCC_PLLI2SM_DIV_49 05905 * @arg @ref LL_RCC_PLLI2SM_DIV_50 05906 * @arg @ref LL_RCC_PLLI2SM_DIV_51 05907 * @arg @ref LL_RCC_PLLI2SM_DIV_52 05908 * @arg @ref LL_RCC_PLLI2SM_DIV_53 05909 * @arg @ref LL_RCC_PLLI2SM_DIV_54 05910 * @arg @ref LL_RCC_PLLI2SM_DIV_55 05911 * @arg @ref LL_RCC_PLLI2SM_DIV_56 05912 * @arg @ref LL_RCC_PLLI2SM_DIV_57 05913 * @arg @ref LL_RCC_PLLI2SM_DIV_58 05914 * @arg @ref LL_RCC_PLLI2SM_DIV_59 05915 * @arg @ref LL_RCC_PLLI2SM_DIV_60 05916 * @arg @ref LL_RCC_PLLI2SM_DIV_61 05917 * @arg @ref LL_RCC_PLLI2SM_DIV_62 05918 * @arg @ref LL_RCC_PLLI2SM_DIV_63 05919 */ 05920 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void) 05921 { 05922 #if defined(RCC_PLLI2SCFGR_PLLI2SM) 05923 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM)); 05924 #else 05925 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); 05926 #endif /* RCC_PLLI2SCFGR_PLLI2SM */ 05927 } 05928 05929 /** 05930 * @brief Get the oscillator used as PLL clock source. 05931 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource\n 05932 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource 05933 * @retval Returned value can be one of the following values: 05934 * @arg @ref LL_RCC_PLLSOURCE_HSI 05935 * @arg @ref LL_RCC_PLLSOURCE_HSE 05936 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) 05937 * 05938 * (*) value not defined in all devices. 05939 */ 05940 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void) 05941 { 05942 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC) 05943 register uint32_t pllsrc = read_bit(rcc->pllcfgr, RCC_PLLCFGR_PLLSRC); 05944 register uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC); 05945 register uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U; 05946 return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1); 05947 #else 05948 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); 05949 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */ 05950 } 05951 05952 /** 05953 * @} 05954 */ 05955 #endif /* RCC_PLLI2S_SUPPORT */ 05956 05957 #if defined(RCC_PLLSAI_SUPPORT) 05958 /** @defgroup RCC_LL_EF_PLLSAI PLLSAI 05959 * @{ 05960 */ 05961 05962 /** 05963 * @brief Enable PLLSAI 05964 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable 05965 * @retval None 05966 */ 05967 __STATIC_INLINE void LL_RCC_PLLSAI_Enable(void) 05968 { 05969 SET_BIT(RCC->CR, RCC_CR_PLLSAION); 05970 } 05971 05972 /** 05973 * @brief Disable PLLSAI 05974 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable 05975 * @retval None 05976 */ 05977 __STATIC_INLINE void LL_RCC_PLLSAI_Disable(void) 05978 { 05979 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); 05980 } 05981 05982 /** 05983 * @brief Check if PLLSAI Ready 05984 * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady 05985 * @retval State of bit (1 or 0). 05986 */ 05987 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void) 05988 { 05989 return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY)); 05990 } 05991 05992 /** 05993 * @brief Configure PLLSAI used for SAI domain clock 05994 * @note PLL Source and PLLM Divider can be written only when PLL, 05995 * PLLI2S and PLLSAI(*) are disabled 05996 * @note PLLN/PLLQ can be written only when PLLSAI is disabled 05997 * @note This can be selected for SAI 05998 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n 05999 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n 06000 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_SAI\n 06001 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n 06002 * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n 06003 * DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI 06004 * @param Source This parameter can be one of the following values: 06005 * @arg @ref LL_RCC_PLLSOURCE_HSI 06006 * @arg @ref LL_RCC_PLLSOURCE_HSE 06007 * @param PLLM This parameter can be one of the following values: 06008 * @arg @ref LL_RCC_PLLSAIM_DIV_2 06009 * @arg @ref LL_RCC_PLLSAIM_DIV_3 06010 * @arg @ref LL_RCC_PLLSAIM_DIV_4 06011 * @arg @ref LL_RCC_PLLSAIM_DIV_5 06012 * @arg @ref LL_RCC_PLLSAIM_DIV_6 06013 * @arg @ref LL_RCC_PLLSAIM_DIV_7 06014 * @arg @ref LL_RCC_PLLSAIM_DIV_8 06015 * @arg @ref LL_RCC_PLLSAIM_DIV_9 06016 * @arg @ref LL_RCC_PLLSAIM_DIV_10 06017 * @arg @ref LL_RCC_PLLSAIM_DIV_11 06018 * @arg @ref LL_RCC_PLLSAIM_DIV_12 06019 * @arg @ref LL_RCC_PLLSAIM_DIV_13 06020 * @arg @ref LL_RCC_PLLSAIM_DIV_14 06021 * @arg @ref LL_RCC_PLLSAIM_DIV_15 06022 * @arg @ref LL_RCC_PLLSAIM_DIV_16 06023 * @arg @ref LL_RCC_PLLSAIM_DIV_17 06024 * @arg @ref LL_RCC_PLLSAIM_DIV_18 06025 * @arg @ref LL_RCC_PLLSAIM_DIV_19 06026 * @arg @ref LL_RCC_PLLSAIM_DIV_20 06027 * @arg @ref LL_RCC_PLLSAIM_DIV_21 06028 * @arg @ref LL_RCC_PLLSAIM_DIV_22 06029 * @arg @ref LL_RCC_PLLSAIM_DIV_23 06030 * @arg @ref LL_RCC_PLLSAIM_DIV_24 06031 * @arg @ref LL_RCC_PLLSAIM_DIV_25 06032 * @arg @ref LL_RCC_PLLSAIM_DIV_26 06033 * @arg @ref LL_RCC_PLLSAIM_DIV_27 06034 * @arg @ref LL_RCC_PLLSAIM_DIV_28 06035 * @arg @ref LL_RCC_PLLSAIM_DIV_29 06036 * @arg @ref LL_RCC_PLLSAIM_DIV_30 06037 * @arg @ref LL_RCC_PLLSAIM_DIV_31 06038 * @arg @ref LL_RCC_PLLSAIM_DIV_32 06039 * @arg @ref LL_RCC_PLLSAIM_DIV_33 06040 * @arg @ref LL_RCC_PLLSAIM_DIV_34 06041 * @arg @ref LL_RCC_PLLSAIM_DIV_35 06042 * @arg @ref LL_RCC_PLLSAIM_DIV_36 06043 * @arg @ref LL_RCC_PLLSAIM_DIV_37 06044 * @arg @ref LL_RCC_PLLSAIM_DIV_38 06045 * @arg @ref LL_RCC_PLLSAIM_DIV_39 06046 * @arg @ref LL_RCC_PLLSAIM_DIV_40 06047 * @arg @ref LL_RCC_PLLSAIM_DIV_41 06048 * @arg @ref LL_RCC_PLLSAIM_DIV_42 06049 * @arg @ref LL_RCC_PLLSAIM_DIV_43 06050 * @arg @ref LL_RCC_PLLSAIM_DIV_44 06051 * @arg @ref LL_RCC_PLLSAIM_DIV_45 06052 * @arg @ref LL_RCC_PLLSAIM_DIV_46 06053 * @arg @ref LL_RCC_PLLSAIM_DIV_47 06054 * @arg @ref LL_RCC_PLLSAIM_DIV_48 06055 * @arg @ref LL_RCC_PLLSAIM_DIV_49 06056 * @arg @ref LL_RCC_PLLSAIM_DIV_50 06057 * @arg @ref LL_RCC_PLLSAIM_DIV_51 06058 * @arg @ref LL_RCC_PLLSAIM_DIV_52 06059 * @arg @ref LL_RCC_PLLSAIM_DIV_53 06060 * @arg @ref LL_RCC_PLLSAIM_DIV_54 06061 * @arg @ref LL_RCC_PLLSAIM_DIV_55 06062 * @arg @ref LL_RCC_PLLSAIM_DIV_56 06063 * @arg @ref LL_RCC_PLLSAIM_DIV_57 06064 * @arg @ref LL_RCC_PLLSAIM_DIV_58 06065 * @arg @ref LL_RCC_PLLSAIM_DIV_59 06066 * @arg @ref LL_RCC_PLLSAIM_DIV_60 06067 * @arg @ref LL_RCC_PLLSAIM_DIV_61 06068 * @arg @ref LL_RCC_PLLSAIM_DIV_62 06069 * @arg @ref LL_RCC_PLLSAIM_DIV_63 06070 * @param PLLN Between 49/50(*) and 432 06071 * 06072 * (*) value not defined in all devices. 06073 * @param PLLQ This parameter can be one of the following values: 06074 * @arg @ref LL_RCC_PLLSAIQ_DIV_2 06075 * @arg @ref LL_RCC_PLLSAIQ_DIV_3 06076 * @arg @ref LL_RCC_PLLSAIQ_DIV_4 06077 * @arg @ref LL_RCC_PLLSAIQ_DIV_5 06078 * @arg @ref LL_RCC_PLLSAIQ_DIV_6 06079 * @arg @ref LL_RCC_PLLSAIQ_DIV_7 06080 * @arg @ref LL_RCC_PLLSAIQ_DIV_8 06081 * @arg @ref LL_RCC_PLLSAIQ_DIV_9 06082 * @arg @ref LL_RCC_PLLSAIQ_DIV_10 06083 * @arg @ref LL_RCC_PLLSAIQ_DIV_11 06084 * @arg @ref LL_RCC_PLLSAIQ_DIV_12 06085 * @arg @ref LL_RCC_PLLSAIQ_DIV_13 06086 * @arg @ref LL_RCC_PLLSAIQ_DIV_14 06087 * @arg @ref LL_RCC_PLLSAIQ_DIV_15 06088 * @param PLLDIVQ This parameter can be one of the following values: 06089 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 06090 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 06091 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 06092 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 06093 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 06094 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 06095 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 06096 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 06097 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 06098 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 06099 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 06100 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 06101 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 06102 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 06103 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 06104 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 06105 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 06106 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 06107 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 06108 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 06109 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 06110 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 06111 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 06112 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 06113 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 06114 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 06115 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 06116 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 06117 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 06118 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 06119 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 06120 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 06121 * @retval None 06122 */ 06123 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ) 06124 { 06125 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 06126 #if defined(RCC_PLLSAICFGR_PLLSAIM) 06127 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM); 06128 #else 06129 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); 06130 #endif /* RCC_PLLSAICFGR_PLLSAIM */ 06131 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ); 06132 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ); 06133 } 06134 06135 #if defined(RCC_PLLSAICFGR_PLLSAIP) 06136 /** 06137 * @brief Configure PLLSAI used for 48Mhz domain clock 06138 * @note PLL Source and PLLM Divider can be written only when PLL, 06139 * PLLI2S and PLLSAI(*) are disabled 06140 * @note PLLN/PLLP can be written only when PLLSAI is disabled 06141 * @note This can be selected for USB, RNG, SDIO 06142 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n 06143 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n 06144 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_48M\n 06145 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n 06146 * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M 06147 * @param Source This parameter can be one of the following values: 06148 * @arg @ref LL_RCC_PLLSOURCE_HSI 06149 * @arg @ref LL_RCC_PLLSOURCE_HSE 06150 * @param PLLM This parameter can be one of the following values: 06151 * @arg @ref LL_RCC_PLLSAIM_DIV_2 06152 * @arg @ref LL_RCC_PLLSAIM_DIV_3 06153 * @arg @ref LL_RCC_PLLSAIM_DIV_4 06154 * @arg @ref LL_RCC_PLLSAIM_DIV_5 06155 * @arg @ref LL_RCC_PLLSAIM_DIV_6 06156 * @arg @ref LL_RCC_PLLSAIM_DIV_7 06157 * @arg @ref LL_RCC_PLLSAIM_DIV_8 06158 * @arg @ref LL_RCC_PLLSAIM_DIV_9 06159 * @arg @ref LL_RCC_PLLSAIM_DIV_10 06160 * @arg @ref LL_RCC_PLLSAIM_DIV_11 06161 * @arg @ref LL_RCC_PLLSAIM_DIV_12 06162 * @arg @ref LL_RCC_PLLSAIM_DIV_13 06163 * @arg @ref LL_RCC_PLLSAIM_DIV_14 06164 * @arg @ref LL_RCC_PLLSAIM_DIV_15 06165 * @arg @ref LL_RCC_PLLSAIM_DIV_16 06166 * @arg @ref LL_RCC_PLLSAIM_DIV_17 06167 * @arg @ref LL_RCC_PLLSAIM_DIV_18 06168 * @arg @ref LL_RCC_PLLSAIM_DIV_19 06169 * @arg @ref LL_RCC_PLLSAIM_DIV_20 06170 * @arg @ref LL_RCC_PLLSAIM_DIV_21 06171 * @arg @ref LL_RCC_PLLSAIM_DIV_22 06172 * @arg @ref LL_RCC_PLLSAIM_DIV_23 06173 * @arg @ref LL_RCC_PLLSAIM_DIV_24 06174 * @arg @ref LL_RCC_PLLSAIM_DIV_25 06175 * @arg @ref LL_RCC_PLLSAIM_DIV_26 06176 * @arg @ref LL_RCC_PLLSAIM_DIV_27 06177 * @arg @ref LL_RCC_PLLSAIM_DIV_28 06178 * @arg @ref LL_RCC_PLLSAIM_DIV_29 06179 * @arg @ref LL_RCC_PLLSAIM_DIV_30 06180 * @arg @ref LL_RCC_PLLSAIM_DIV_31 06181 * @arg @ref LL_RCC_PLLSAIM_DIV_32 06182 * @arg @ref LL_RCC_PLLSAIM_DIV_33 06183 * @arg @ref LL_RCC_PLLSAIM_DIV_34 06184 * @arg @ref LL_RCC_PLLSAIM_DIV_35 06185 * @arg @ref LL_RCC_PLLSAIM_DIV_36 06186 * @arg @ref LL_RCC_PLLSAIM_DIV_37 06187 * @arg @ref LL_RCC_PLLSAIM_DIV_38 06188 * @arg @ref LL_RCC_PLLSAIM_DIV_39 06189 * @arg @ref LL_RCC_PLLSAIM_DIV_40 06190 * @arg @ref LL_RCC_PLLSAIM_DIV_41 06191 * @arg @ref LL_RCC_PLLSAIM_DIV_42 06192 * @arg @ref LL_RCC_PLLSAIM_DIV_43 06193 * @arg @ref LL_RCC_PLLSAIM_DIV_44 06194 * @arg @ref LL_RCC_PLLSAIM_DIV_45 06195 * @arg @ref LL_RCC_PLLSAIM_DIV_46 06196 * @arg @ref LL_RCC_PLLSAIM_DIV_47 06197 * @arg @ref LL_RCC_PLLSAIM_DIV_48 06198 * @arg @ref LL_RCC_PLLSAIM_DIV_49 06199 * @arg @ref LL_RCC_PLLSAIM_DIV_50 06200 * @arg @ref LL_RCC_PLLSAIM_DIV_51 06201 * @arg @ref LL_RCC_PLLSAIM_DIV_52 06202 * @arg @ref LL_RCC_PLLSAIM_DIV_53 06203 * @arg @ref LL_RCC_PLLSAIM_DIV_54 06204 * @arg @ref LL_RCC_PLLSAIM_DIV_55 06205 * @arg @ref LL_RCC_PLLSAIM_DIV_56 06206 * @arg @ref LL_RCC_PLLSAIM_DIV_57 06207 * @arg @ref LL_RCC_PLLSAIM_DIV_58 06208 * @arg @ref LL_RCC_PLLSAIM_DIV_59 06209 * @arg @ref LL_RCC_PLLSAIM_DIV_60 06210 * @arg @ref LL_RCC_PLLSAIM_DIV_61 06211 * @arg @ref LL_RCC_PLLSAIM_DIV_62 06212 * @arg @ref LL_RCC_PLLSAIM_DIV_63 06213 * @param PLLN Between 50 and 432 06214 * @param PLLP This parameter can be one of the following values: 06215 * @arg @ref LL_RCC_PLLSAIP_DIV_2 06216 * @arg @ref LL_RCC_PLLSAIP_DIV_4 06217 * @arg @ref LL_RCC_PLLSAIP_DIV_6 06218 * @arg @ref LL_RCC_PLLSAIP_DIV_8 06219 * @retval None 06220 */ 06221 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 06222 { 06223 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 06224 #if defined(RCC_PLLSAICFGR_PLLSAIM) 06225 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM); 06226 #else 06227 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); 06228 #endif /* RCC_PLLSAICFGR_PLLSAIM */ 06229 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP); 06230 } 06231 #endif /* RCC_PLLSAICFGR_PLLSAIP */ 06232 06233 #if defined(LTDC) 06234 /** 06235 * @brief Configure PLLSAI used for LTDC domain clock 06236 * @note PLL Source and PLLM Divider can be written only when PLL, 06237 * PLLI2S and PLLSAI(*) are disabled 06238 * @note PLLN/PLLR can be written only when PLLSAI is disabled 06239 * @note This can be selected for LTDC 06240 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n 06241 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n 06242 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n 06243 * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n 06244 * DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC 06245 * @param Source This parameter can be one of the following values: 06246 * @arg @ref LL_RCC_PLLSOURCE_HSI 06247 * @arg @ref LL_RCC_PLLSOURCE_HSE 06248 * @param PLLM This parameter can be one of the following values: 06249 * @arg @ref LL_RCC_PLLSAIM_DIV_2 06250 * @arg @ref LL_RCC_PLLSAIM_DIV_3 06251 * @arg @ref LL_RCC_PLLSAIM_DIV_4 06252 * @arg @ref LL_RCC_PLLSAIM_DIV_5 06253 * @arg @ref LL_RCC_PLLSAIM_DIV_6 06254 * @arg @ref LL_RCC_PLLSAIM_DIV_7 06255 * @arg @ref LL_RCC_PLLSAIM_DIV_8 06256 * @arg @ref LL_RCC_PLLSAIM_DIV_9 06257 * @arg @ref LL_RCC_PLLSAIM_DIV_10 06258 * @arg @ref LL_RCC_PLLSAIM_DIV_11 06259 * @arg @ref LL_RCC_PLLSAIM_DIV_12 06260 * @arg @ref LL_RCC_PLLSAIM_DIV_13 06261 * @arg @ref LL_RCC_PLLSAIM_DIV_14 06262 * @arg @ref LL_RCC_PLLSAIM_DIV_15 06263 * @arg @ref LL_RCC_PLLSAIM_DIV_16 06264 * @arg @ref LL_RCC_PLLSAIM_DIV_17 06265 * @arg @ref LL_RCC_PLLSAIM_DIV_18 06266 * @arg @ref LL_RCC_PLLSAIM_DIV_19 06267 * @arg @ref LL_RCC_PLLSAIM_DIV_20 06268 * @arg @ref LL_RCC_PLLSAIM_DIV_21 06269 * @arg @ref LL_RCC_PLLSAIM_DIV_22 06270 * @arg @ref LL_RCC_PLLSAIM_DIV_23 06271 * @arg @ref LL_RCC_PLLSAIM_DIV_24 06272 * @arg @ref LL_RCC_PLLSAIM_DIV_25 06273 * @arg @ref LL_RCC_PLLSAIM_DIV_26 06274 * @arg @ref LL_RCC_PLLSAIM_DIV_27 06275 * @arg @ref LL_RCC_PLLSAIM_DIV_28 06276 * @arg @ref LL_RCC_PLLSAIM_DIV_29 06277 * @arg @ref LL_RCC_PLLSAIM_DIV_30 06278 * @arg @ref LL_RCC_PLLSAIM_DIV_31 06279 * @arg @ref LL_RCC_PLLSAIM_DIV_32 06280 * @arg @ref LL_RCC_PLLSAIM_DIV_33 06281 * @arg @ref LL_RCC_PLLSAIM_DIV_34 06282 * @arg @ref LL_RCC_PLLSAIM_DIV_35 06283 * @arg @ref LL_RCC_PLLSAIM_DIV_36 06284 * @arg @ref LL_RCC_PLLSAIM_DIV_37 06285 * @arg @ref LL_RCC_PLLSAIM_DIV_38 06286 * @arg @ref LL_RCC_PLLSAIM_DIV_39 06287 * @arg @ref LL_RCC_PLLSAIM_DIV_40 06288 * @arg @ref LL_RCC_PLLSAIM_DIV_41 06289 * @arg @ref LL_RCC_PLLSAIM_DIV_42 06290 * @arg @ref LL_RCC_PLLSAIM_DIV_43 06291 * @arg @ref LL_RCC_PLLSAIM_DIV_44 06292 * @arg @ref LL_RCC_PLLSAIM_DIV_45 06293 * @arg @ref LL_RCC_PLLSAIM_DIV_46 06294 * @arg @ref LL_RCC_PLLSAIM_DIV_47 06295 * @arg @ref LL_RCC_PLLSAIM_DIV_48 06296 * @arg @ref LL_RCC_PLLSAIM_DIV_49 06297 * @arg @ref LL_RCC_PLLSAIM_DIV_50 06298 * @arg @ref LL_RCC_PLLSAIM_DIV_51 06299 * @arg @ref LL_RCC_PLLSAIM_DIV_52 06300 * @arg @ref LL_RCC_PLLSAIM_DIV_53 06301 * @arg @ref LL_RCC_PLLSAIM_DIV_54 06302 * @arg @ref LL_RCC_PLLSAIM_DIV_55 06303 * @arg @ref LL_RCC_PLLSAIM_DIV_56 06304 * @arg @ref LL_RCC_PLLSAIM_DIV_57 06305 * @arg @ref LL_RCC_PLLSAIM_DIV_58 06306 * @arg @ref LL_RCC_PLLSAIM_DIV_59 06307 * @arg @ref LL_RCC_PLLSAIM_DIV_60 06308 * @arg @ref LL_RCC_PLLSAIM_DIV_61 06309 * @arg @ref LL_RCC_PLLSAIM_DIV_62 06310 * @arg @ref LL_RCC_PLLSAIM_DIV_63 06311 * @param PLLN Between 49/50(*) and 432 06312 * 06313 * (*) value not defined in all devices. 06314 * @param PLLR This parameter can be one of the following values: 06315 * @arg @ref LL_RCC_PLLSAIR_DIV_2 06316 * @arg @ref LL_RCC_PLLSAIR_DIV_3 06317 * @arg @ref LL_RCC_PLLSAIR_DIV_4 06318 * @arg @ref LL_RCC_PLLSAIR_DIV_5 06319 * @arg @ref LL_RCC_PLLSAIR_DIV_6 06320 * @arg @ref LL_RCC_PLLSAIR_DIV_7 06321 * @param PLLDIVR This parameter can be one of the following values: 06322 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 06323 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 06324 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 06325 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 06326 * @retval None 06327 */ 06328 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) 06329 { 06330 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 06331 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR); 06332 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR); 06333 } 06334 #endif /* LTDC */ 06335 06336 /** 06337 * @brief Get division factor for PLLSAI input clock 06338 * @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider\n 06339 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider 06340 * @retval Returned value can be one of the following values: 06341 * @arg @ref LL_RCC_PLLSAIM_DIV_2 06342 * @arg @ref LL_RCC_PLLSAIM_DIV_3 06343 * @arg @ref LL_RCC_PLLSAIM_DIV_4 06344 * @arg @ref LL_RCC_PLLSAIM_DIV_5 06345 * @arg @ref LL_RCC_PLLSAIM_DIV_6 06346 * @arg @ref LL_RCC_PLLSAIM_DIV_7 06347 * @arg @ref LL_RCC_PLLSAIM_DIV_8 06348 * @arg @ref LL_RCC_PLLSAIM_DIV_9 06349 * @arg @ref LL_RCC_PLLSAIM_DIV_10 06350 * @arg @ref LL_RCC_PLLSAIM_DIV_11 06351 * @arg @ref LL_RCC_PLLSAIM_DIV_12 06352 * @arg @ref LL_RCC_PLLSAIM_DIV_13 06353 * @arg @ref LL_RCC_PLLSAIM_DIV_14 06354 * @arg @ref LL_RCC_PLLSAIM_DIV_15 06355 * @arg @ref LL_RCC_PLLSAIM_DIV_16 06356 * @arg @ref LL_RCC_PLLSAIM_DIV_17 06357 * @arg @ref LL_RCC_PLLSAIM_DIV_18 06358 * @arg @ref LL_RCC_PLLSAIM_DIV_19 06359 * @arg @ref LL_RCC_PLLSAIM_DIV_20 06360 * @arg @ref LL_RCC_PLLSAIM_DIV_21 06361 * @arg @ref LL_RCC_PLLSAIM_DIV_22 06362 * @arg @ref LL_RCC_PLLSAIM_DIV_23 06363 * @arg @ref LL_RCC_PLLSAIM_DIV_24 06364 * @arg @ref LL_RCC_PLLSAIM_DIV_25 06365 * @arg @ref LL_RCC_PLLSAIM_DIV_26 06366 * @arg @ref LL_RCC_PLLSAIM_DIV_27 06367 * @arg @ref LL_RCC_PLLSAIM_DIV_28 06368 * @arg @ref LL_RCC_PLLSAIM_DIV_29 06369 * @arg @ref LL_RCC_PLLSAIM_DIV_30 06370 * @arg @ref LL_RCC_PLLSAIM_DIV_31 06371 * @arg @ref LL_RCC_PLLSAIM_DIV_32 06372 * @arg @ref LL_RCC_PLLSAIM_DIV_33 06373 * @arg @ref LL_RCC_PLLSAIM_DIV_34 06374 * @arg @ref LL_RCC_PLLSAIM_DIV_35 06375 * @arg @ref LL_RCC_PLLSAIM_DIV_36 06376 * @arg @ref LL_RCC_PLLSAIM_DIV_37 06377 * @arg @ref LL_RCC_PLLSAIM_DIV_38 06378 * @arg @ref LL_RCC_PLLSAIM_DIV_39 06379 * @arg @ref LL_RCC_PLLSAIM_DIV_40 06380 * @arg @ref LL_RCC_PLLSAIM_DIV_41 06381 * @arg @ref LL_RCC_PLLSAIM_DIV_42 06382 * @arg @ref LL_RCC_PLLSAIM_DIV_43 06383 * @arg @ref LL_RCC_PLLSAIM_DIV_44 06384 * @arg @ref LL_RCC_PLLSAIM_DIV_45 06385 * @arg @ref LL_RCC_PLLSAIM_DIV_46 06386 * @arg @ref LL_RCC_PLLSAIM_DIV_47 06387 * @arg @ref LL_RCC_PLLSAIM_DIV_48 06388 * @arg @ref LL_RCC_PLLSAIM_DIV_49 06389 * @arg @ref LL_RCC_PLLSAIM_DIV_50 06390 * @arg @ref LL_RCC_PLLSAIM_DIV_51 06391 * @arg @ref LL_RCC_PLLSAIM_DIV_52 06392 * @arg @ref LL_RCC_PLLSAIM_DIV_53 06393 * @arg @ref LL_RCC_PLLSAIM_DIV_54 06394 * @arg @ref LL_RCC_PLLSAIM_DIV_55 06395 * @arg @ref LL_RCC_PLLSAIM_DIV_56 06396 * @arg @ref LL_RCC_PLLSAIM_DIV_57 06397 * @arg @ref LL_RCC_PLLSAIM_DIV_58 06398 * @arg @ref LL_RCC_PLLSAIM_DIV_59 06399 * @arg @ref LL_RCC_PLLSAIM_DIV_60 06400 * @arg @ref LL_RCC_PLLSAIM_DIV_61 06401 * @arg @ref LL_RCC_PLLSAIM_DIV_62 06402 * @arg @ref LL_RCC_PLLSAIM_DIV_63 06403 */ 06404 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void) 06405 { 06406 #if defined(RCC_PLLSAICFGR_PLLSAIM) 06407 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM)); 06408 #else 06409 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); 06410 #endif /* RCC_PLLSAICFGR_PLLSAIM */ 06411 } 06412 06413 /** 06414 * @brief Get SAIPLL multiplication factor for VCO 06415 * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN 06416 * @retval Between 49/50(*) and 432 06417 * 06418 * (*) value not defined in all devices. 06419 */ 06420 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void) 06421 { 06422 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); 06423 } 06424 06425 /** 06426 * @brief Get SAIPLL division factor for PLLSAIQ 06427 * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ 06428 * @retval Returned value can be one of the following values: 06429 * @arg @ref LL_RCC_PLLSAIQ_DIV_2 06430 * @arg @ref LL_RCC_PLLSAIQ_DIV_3 06431 * @arg @ref LL_RCC_PLLSAIQ_DIV_4 06432 * @arg @ref LL_RCC_PLLSAIQ_DIV_5 06433 * @arg @ref LL_RCC_PLLSAIQ_DIV_6 06434 * @arg @ref LL_RCC_PLLSAIQ_DIV_7 06435 * @arg @ref LL_RCC_PLLSAIQ_DIV_8 06436 * @arg @ref LL_RCC_PLLSAIQ_DIV_9 06437 * @arg @ref LL_RCC_PLLSAIQ_DIV_10 06438 * @arg @ref LL_RCC_PLLSAIQ_DIV_11 06439 * @arg @ref LL_RCC_PLLSAIQ_DIV_12 06440 * @arg @ref LL_RCC_PLLSAIQ_DIV_13 06441 * @arg @ref LL_RCC_PLLSAIQ_DIV_14 06442 * @arg @ref LL_RCC_PLLSAIQ_DIV_15 06443 */ 06444 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void) 06445 { 06446 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ)); 06447 } 06448 06449 #if defined(RCC_PLLSAICFGR_PLLSAIR) 06450 /** 06451 * @brief Get SAIPLL division factor for PLLSAIR 06452 * @note used for PLLSAICLK (SAI clock) 06453 * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR 06454 * @retval Returned value can be one of the following values: 06455 * @arg @ref LL_RCC_PLLSAIR_DIV_2 06456 * @arg @ref LL_RCC_PLLSAIR_DIV_3 06457 * @arg @ref LL_RCC_PLLSAIR_DIV_4 06458 * @arg @ref LL_RCC_PLLSAIR_DIV_5 06459 * @arg @ref LL_RCC_PLLSAIR_DIV_6 06460 * @arg @ref LL_RCC_PLLSAIR_DIV_7 06461 */ 06462 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void) 06463 { 06464 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR)); 06465 } 06466 #endif /* RCC_PLLSAICFGR_PLLSAIR */ 06467 06468 #if defined(RCC_PLLSAICFGR_PLLSAIP) 06469 /** 06470 * @brief Get SAIPLL division factor for PLLSAIP 06471 * @note used for PLL48MCLK (48M domain clock) 06472 * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP 06473 * @retval Returned value can be one of the following values: 06474 * @arg @ref LL_RCC_PLLSAIP_DIV_2 06475 * @arg @ref LL_RCC_PLLSAIP_DIV_4 06476 * @arg @ref LL_RCC_PLLSAIP_DIV_6 06477 * @arg @ref LL_RCC_PLLSAIP_DIV_8 06478 */ 06479 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void) 06480 { 06481 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP)); 06482 } 06483 #endif /* RCC_PLLSAICFGR_PLLSAIP */ 06484 06485 /** 06486 * @brief Get SAIPLL division factor for PLLSAIDIVQ 06487 * @note used PLLSAICLK selected (SAI clock) 06488 * @rmtoll DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ 06489 * @retval Returned value can be one of the following values: 06490 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 06491 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 06492 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 06493 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 06494 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 06495 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 06496 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 06497 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 06498 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 06499 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 06500 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 06501 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 06502 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 06503 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 06504 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 06505 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 06506 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 06507 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 06508 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 06509 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 06510 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 06511 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 06512 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 06513 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 06514 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 06515 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 06516 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 06517 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 06518 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 06519 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 06520 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 06521 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 06522 */ 06523 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void) 06524 { 06525 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ)); 06526 } 06527 06528 #if defined(RCC_DCKCFGR_PLLSAIDIVR) 06529 /** 06530 * @brief Get SAIPLL division factor for PLLSAIDIVR 06531 * @note used for LTDC domain clock 06532 * @rmtoll DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR 06533 * @retval Returned value can be one of the following values: 06534 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 06535 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 06536 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 06537 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 06538 */ 06539 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void) 06540 { 06541 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR)); 06542 } 06543 #endif /* RCC_DCKCFGR_PLLSAIDIVR */ 06544 06545 /** 06546 * @} 06547 */ 06548 #endif /* RCC_PLLSAI_SUPPORT */ 06549 06550 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management 06551 * @{ 06552 */ 06553 06554 /** 06555 * @brief Clear LSI ready interrupt flag 06556 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY 06557 * @retval None 06558 */ 06559 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) 06560 { 06561 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); 06562 } 06563 06564 /** 06565 * @brief Clear LSE ready interrupt flag 06566 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY 06567 * @retval None 06568 */ 06569 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) 06570 { 06571 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); 06572 } 06573 06574 /** 06575 * @brief Clear HSI ready interrupt flag 06576 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY 06577 * @retval None 06578 */ 06579 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) 06580 { 06581 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); 06582 } 06583 06584 /** 06585 * @brief Clear HSE ready interrupt flag 06586 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY 06587 * @retval None 06588 */ 06589 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) 06590 { 06591 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); 06592 } 06593 06594 /** 06595 * @brief Clear PLL ready interrupt flag 06596 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY 06597 * @retval None 06598 */ 06599 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) 06600 { 06601 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); 06602 } 06603 06604 #if defined(RCC_PLLI2S_SUPPORT) 06605 /** 06606 * @brief Clear PLLI2S ready interrupt flag 06607 * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY 06608 * @retval None 06609 */ 06610 __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void) 06611 { 06612 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); 06613 } 06614 06615 #endif /* RCC_PLLI2S_SUPPORT */ 06616 06617 #if defined(RCC_PLLSAI_SUPPORT) 06618 /** 06619 * @brief Clear PLLSAI ready interrupt flag 06620 * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY 06621 * @retval None 06622 */ 06623 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void) 06624 { 06625 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); 06626 } 06627 06628 #endif /* RCC_PLLSAI_SUPPORT */ 06629 06630 /** 06631 * @brief Clear Clock security system interrupt flag 06632 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS 06633 * @retval None 06634 */ 06635 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) 06636 { 06637 SET_BIT(RCC->CIR, RCC_CIR_CSSC); 06638 } 06639 06640 /** 06641 * @brief Check if LSI ready interrupt occurred or not 06642 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY 06643 * @retval State of bit (1 or 0). 06644 */ 06645 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) 06646 { 06647 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); 06648 } 06649 06650 /** 06651 * @brief Check if LSE ready interrupt occurred or not 06652 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY 06653 * @retval State of bit (1 or 0). 06654 */ 06655 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) 06656 { 06657 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); 06658 } 06659 06660 /** 06661 * @brief Check if HSI ready interrupt occurred or not 06662 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY 06663 * @retval State of bit (1 or 0). 06664 */ 06665 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) 06666 { 06667 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); 06668 } 06669 06670 /** 06671 * @brief Check if HSE ready interrupt occurred or not 06672 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY 06673 * @retval State of bit (1 or 0). 06674 */ 06675 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) 06676 { 06677 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); 06678 } 06679 06680 /** 06681 * @brief Check if PLL ready interrupt occurred or not 06682 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY 06683 * @retval State of bit (1 or 0). 06684 */ 06685 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) 06686 { 06687 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); 06688 } 06689 06690 #if defined(RCC_PLLI2S_SUPPORT) 06691 /** 06692 * @brief Check if PLLI2S ready interrupt occurred or not 06693 * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY 06694 * @retval State of bit (1 or 0). 06695 */ 06696 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void) 06697 { 06698 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF)); 06699 } 06700 #endif /* RCC_PLLI2S_SUPPORT */ 06701 06702 #if defined(RCC_PLLSAI_SUPPORT) 06703 /** 06704 * @brief Check if PLLSAI ready interrupt occurred or not 06705 * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY 06706 * @retval State of bit (1 or 0). 06707 */ 06708 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void) 06709 { 06710 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF)); 06711 } 06712 #endif /* RCC_PLLSAI_SUPPORT */ 06713 06714 /** 06715 * @brief Check if Clock security system interrupt occurred or not 06716 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS 06717 * @retval State of bit (1 or 0). 06718 */ 06719 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) 06720 { 06721 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); 06722 } 06723 06724 /** 06725 * @brief Check if RCC flag Independent Watchdog reset is set or not. 06726 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST 06727 * @retval State of bit (1 or 0). 06728 */ 06729 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) 06730 { 06731 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); 06732 } 06733 06734 /** 06735 * @brief Check if RCC flag Low Power reset is set or not. 06736 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST 06737 * @retval State of bit (1 or 0). 06738 */ 06739 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) 06740 { 06741 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); 06742 } 06743 06744 /** 06745 * @brief Check if RCC flag Pin reset is set or not. 06746 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST 06747 * @retval State of bit (1 or 0). 06748 */ 06749 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) 06750 { 06751 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); 06752 } 06753 06754 /** 06755 * @brief Check if RCC flag POR/PDR reset is set or not. 06756 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST 06757 * @retval State of bit (1 or 0). 06758 */ 06759 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) 06760 { 06761 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); 06762 } 06763 06764 /** 06765 * @brief Check if RCC flag Software reset is set or not. 06766 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST 06767 * @retval State of bit (1 or 0). 06768 */ 06769 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) 06770 { 06771 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); 06772 } 06773 06774 /** 06775 * @brief Check if RCC flag Window Watchdog reset is set or not. 06776 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST 06777 * @retval State of bit (1 or 0). 06778 */ 06779 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) 06780 { 06781 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); 06782 } 06783 06784 #if defined(RCC_CSR_BORRSTF) 06785 /** 06786 * @brief Check if RCC flag BOR reset is set or not. 06787 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST 06788 * @retval State of bit (1 or 0). 06789 */ 06790 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) 06791 { 06792 return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)); 06793 } 06794 #endif /* RCC_CSR_BORRSTF */ 06795 06796 /** 06797 * @brief Set RMVF bit to clear the reset flags. 06798 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags 06799 * @retval None 06800 */ 06801 __STATIC_INLINE void LL_RCC_ClearResetFlags(void) 06802 { 06803 SET_BIT(RCC->CSR, RCC_CSR_RMVF); 06804 } 06805 06806 /** 06807 * @} 06808 */ 06809 06810 /** @defgroup RCC_LL_EF_IT_Management IT Management 06811 * @{ 06812 */ 06813 06814 /** 06815 * @brief Enable LSI ready interrupt 06816 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY 06817 * @retval None 06818 */ 06819 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) 06820 { 06821 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); 06822 } 06823 06824 /** 06825 * @brief Enable LSE ready interrupt 06826 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY 06827 * @retval None 06828 */ 06829 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) 06830 { 06831 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); 06832 } 06833 06834 /** 06835 * @brief Enable HSI ready interrupt 06836 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY 06837 * @retval None 06838 */ 06839 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) 06840 { 06841 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); 06842 } 06843 06844 /** 06845 * @brief Enable HSE ready interrupt 06846 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY 06847 * @retval None 06848 */ 06849 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) 06850 { 06851 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); 06852 } 06853 06854 /** 06855 * @brief Enable PLL ready interrupt 06856 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY 06857 * @retval None 06858 */ 06859 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) 06860 { 06861 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); 06862 } 06863 06864 #if defined(RCC_PLLI2S_SUPPORT) 06865 /** 06866 * @brief Enable PLLI2S ready interrupt 06867 * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY 06868 * @retval None 06869 */ 06870 __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void) 06871 { 06872 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); 06873 } 06874 #endif /* RCC_PLLI2S_SUPPORT */ 06875 06876 #if defined(RCC_PLLSAI_SUPPORT) 06877 /** 06878 * @brief Enable PLLSAI ready interrupt 06879 * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY 06880 * @retval None 06881 */ 06882 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void) 06883 { 06884 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); 06885 } 06886 #endif /* RCC_PLLSAI_SUPPORT */ 06887 06888 /** 06889 * @brief Disable LSI ready interrupt 06890 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY 06891 * @retval None 06892 */ 06893 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) 06894 { 06895 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); 06896 } 06897 06898 /** 06899 * @brief Disable LSE ready interrupt 06900 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY 06901 * @retval None 06902 */ 06903 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) 06904 { 06905 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); 06906 } 06907 06908 /** 06909 * @brief Disable HSI ready interrupt 06910 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY 06911 * @retval None 06912 */ 06913 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) 06914 { 06915 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); 06916 } 06917 06918 /** 06919 * @brief Disable HSE ready interrupt 06920 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY 06921 * @retval None 06922 */ 06923 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) 06924 { 06925 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); 06926 } 06927 06928 /** 06929 * @brief Disable PLL ready interrupt 06930 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY 06931 * @retval None 06932 */ 06933 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) 06934 { 06935 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); 06936 } 06937 06938 #if defined(RCC_PLLI2S_SUPPORT) 06939 /** 06940 * @brief Disable PLLI2S ready interrupt 06941 * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY 06942 * @retval None 06943 */ 06944 __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void) 06945 { 06946 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); 06947 } 06948 06949 #endif /* RCC_PLLI2S_SUPPORT */ 06950 06951 #if defined(RCC_PLLSAI_SUPPORT) 06952 /** 06953 * @brief Disable PLLSAI ready interrupt 06954 * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY 06955 * @retval None 06956 */ 06957 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void) 06958 { 06959 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); 06960 } 06961 #endif /* RCC_PLLSAI_SUPPORT */ 06962 06963 /** 06964 * @brief Checks if LSI ready interrupt source is enabled or disabled. 06965 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY 06966 * @retval State of bit (1 or 0). 06967 */ 06968 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) 06969 { 06970 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); 06971 } 06972 06973 /** 06974 * @brief Checks if LSE ready interrupt source is enabled or disabled. 06975 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY 06976 * @retval State of bit (1 or 0). 06977 */ 06978 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) 06979 { 06980 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); 06981 } 06982 06983 /** 06984 * @brief Checks if HSI ready interrupt source is enabled or disabled. 06985 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY 06986 * @retval State of bit (1 or 0). 06987 */ 06988 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) 06989 { 06990 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); 06991 } 06992 06993 /** 06994 * @brief Checks if HSE ready interrupt source is enabled or disabled. 06995 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY 06996 * @retval State of bit (1 or 0). 06997 */ 06998 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) 06999 { 07000 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); 07001 } 07002 07003 /** 07004 * @brief Checks if PLL ready interrupt source is enabled or disabled. 07005 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY 07006 * @retval State of bit (1 or 0). 07007 */ 07008 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) 07009 { 07010 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); 07011 } 07012 07013 #if defined(RCC_PLLI2S_SUPPORT) 07014 /** 07015 * @brief Checks if PLLI2S ready interrupt source is enabled or disabled. 07016 * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY 07017 * @retval State of bit (1 or 0). 07018 */ 07019 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void) 07020 { 07021 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE)); 07022 } 07023 07024 #endif /* RCC_PLLI2S_SUPPORT */ 07025 07026 #if defined(RCC_PLLSAI_SUPPORT) 07027 /** 07028 * @brief Checks if PLLSAI ready interrupt source is enabled or disabled. 07029 * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY 07030 * @retval State of bit (1 or 0). 07031 */ 07032 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void) 07033 { 07034 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE)); 07035 } 07036 #endif /* RCC_PLLSAI_SUPPORT */ 07037 07038 /** 07039 * @} 07040 */ 07041 07042 #if defined(USE_FULL_LL_DRIVER) 07043 /** @defgroup RCC_LL_EF_Init De-initialization function 07044 * @{ 07045 */ 07046 ErrorStatus LL_RCC_DeInit(void); 07047 /** 07048 * @} 07049 */ 07050 07051 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions 07052 * @{ 07053 */ 07054 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); 07055 #if defined(FMPI2C1) 07056 uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource); 07057 #endif /* FMPI2C1 */ 07058 #if defined(LPTIM1) 07059 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); 07060 #endif /* LPTIM1 */ 07061 #if defined(SAI1) 07062 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); 07063 #endif /* SAI1 */ 07064 #if defined(SDIO) 07065 uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource); 07066 #endif /* SDIO */ 07067 #if defined(RNG) 07068 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); 07069 #endif /* RNG */ 07070 #if defined(USB_OTG_FS) || defined(USB_OTG_HS) 07071 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); 07072 #endif /* USB_OTG_FS || USB_OTG_HS */ 07073 #if defined(DFSDM1_Channel0) 07074 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); 07075 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource); 07076 #endif /* DFSDM1_Channel0 */ 07077 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); 07078 #if defined(CEC) 07079 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); 07080 #endif /* CEC */ 07081 #if defined(LTDC) 07082 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); 07083 #endif /* LTDC */ 07084 #if defined(SPDIFRX) 07085 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource); 07086 #endif /* SPDIFRX */ 07087 #if defined(DSI) 07088 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); 07089 #endif /* DSI */ 07090 /** 07091 * @} 07092 */ 07093 #endif /* USE_FULL_LL_DRIVER */ 07094 07095 /** 07096 * @} 07097 */ 07098 07099 /** 07100 * @} 07101 */ 07102 07103 #endif /* defined(RCC) */ 07104 07105 /** 07106 * @} 07107 */ 07108 07109 #ifdef __cplusplus 07110 } 07111 #endif 07112 07113 #endif /* __STM32F4xx_LL_RCC_H */ 07114 07115 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1