STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_system.h 00004 * @author MCD Application Team 00005 * @brief Header file of SYSTEM LL module. 00006 @verbatim 00007 ============================================================================== 00008 ##### How to use this driver ##### 00009 ============================================================================== 00010 [..] 00011 The LL SYSTEM driver contains a set of generic APIs that can be 00012 used by user: 00013 (+) Some of the FLASH features need to be handled in the SYSTEM file. 00014 (+) Access to DBGCMU registers 00015 (+) Access to SYSCFG registers 00016 (+) Access to VREFBUF registers 00017 00018 @endverbatim 00019 ****************************************************************************** 00020 * @attention 00021 * 00022 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00023 * 00024 * Redistribution and use in source and binary forms, with or without modification, 00025 * are permitted provided that the following conditions are met: 00026 * 1. Redistributions of source code must retain the above copyright notice, 00027 * this list of conditions and the following disclaimer. 00028 * 2. Redistributions in binary form must reproduce the above copyright notice, 00029 * this list of conditions and the following disclaimer in the documentation 00030 * and/or other materials provided with the distribution. 00031 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00032 * may be used to endorse or promote products derived from this software 00033 * without specific prior written permission. 00034 * 00035 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00036 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00037 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00038 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00039 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00040 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00041 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00042 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00043 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00044 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00045 * 00046 ****************************************************************************** 00047 */ 00048 00049 /* Define to prevent recursive inclusion -------------------------------------*/ 00050 #ifndef __STM32L4xx_LL_SYSTEM_H 00051 #define __STM32L4xx_LL_SYSTEM_H 00052 00053 #ifdef __cplusplus 00054 extern "C" { 00055 #endif 00056 00057 /* Includes ------------------------------------------------------------------*/ 00058 #include "stm32l4xx.h" 00059 00060 /** @addtogroup STM32L4xx_LL_Driver 00061 * @{ 00062 */ 00063 00064 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) 00065 00066 /** @defgroup SYSTEM_LL SYSTEM 00067 * @{ 00068 */ 00069 00070 /* Private types -------------------------------------------------------------*/ 00071 /* Private variables ---------------------------------------------------------*/ 00072 00073 /* Private constants ---------------------------------------------------------*/ 00074 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants 00075 * @{ 00076 */ 00077 00078 /** 00079 * @brief Power-down in Run mode Flash key 00080 */ 00081 #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ 00082 #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 00083 to unlock the RUN_PD bit in FLASH_ACR */ 00084 00085 /** 00086 * @} 00087 */ 00088 00089 /* Private macros ------------------------------------------------------------*/ 00090 00091 /* Exported types ------------------------------------------------------------*/ 00092 /* Exported constants --------------------------------------------------------*/ 00093 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants 00094 * @{ 00095 */ 00096 00097 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP 00098 * @{ 00099 */ 00100 #define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */ 00101 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ 00102 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */ 00103 #if defined(FMC_Bank1_R) 00104 #define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */ 00105 #endif /* FMC_Bank1_R */ 00106 #define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000 */ 00107 /** 00108 * @} 00109 */ 00110 00111 #if defined(SYSCFG_MEMRMP_FB_MODE) 00112 /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE 00113 * @{ 00114 */ 00115 #define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) 00116 and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000) */ 00117 #define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) 00118 and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000) */ 00119 /** 00120 * @} 00121 */ 00122 00123 #endif /* SYSCFG_MEMRMP_FB_MODE */ 00124 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS 00125 * @{ 00126 */ 00127 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ 00128 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ 00129 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) 00130 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ 00131 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ 00132 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP) 00133 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ 00134 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ 00135 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ 00136 #if defined(I2C2) 00137 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ 00138 #endif /* I2C2 */ 00139 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ 00140 #if defined(I2C4) 00141 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ 00142 #endif /* I2C4 */ 00143 /** 00144 * @} 00145 */ 00146 00147 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT 00148 * @{ 00149 */ 00150 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */ 00151 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */ 00152 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */ 00153 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */ 00154 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */ 00155 #if defined(GPIOF) 00156 #define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */ 00157 #endif /* GPIOF */ 00158 #if defined(GPIOG) 00159 #define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */ 00160 #endif /* GPIOG */ 00161 #define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */ 00162 #if defined(GPIOI) 00163 #define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */ 00164 #endif /* GPIOI */ 00165 /** 00166 * @} 00167 */ 00168 00169 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE 00170 * @{ 00171 */ 00172 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */ 00173 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */ 00174 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */ 00175 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */ 00176 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */ 00177 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */ 00178 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */ 00179 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */ 00180 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */ 00181 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */ 00182 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */ 00183 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */ 00184 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */ 00185 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */ 00186 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */ 00187 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */ 00188 /** 00189 * @} 00190 */ 00191 00192 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK 00193 * @{ 00194 */ 00195 #define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal 00196 with Break Input of TIM1/8/15/16/17 */ 00197 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection 00198 with TIM1/8/15/16/17 Break Input 00199 and also the PVDE and PLS bits of the Power Control Interface */ 00200 #define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal 00201 with Break Input of TIM1/8/15/16/17 */ 00202 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 00203 with Break Input of TIM1/15/16/17 */ 00204 /** 00205 * @} 00206 */ 00207 00208 /** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP 00209 * @{ 00210 */ 00211 #define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */ 00212 #define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */ 00213 #define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */ 00214 #define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */ 00215 #define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */ 00216 #define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */ 00217 #define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */ 00218 #define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */ 00219 #define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */ 00220 #define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */ 00221 #define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */ 00222 #define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */ 00223 #define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */ 00224 #define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */ 00225 #define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */ 00226 #define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */ 00227 #if defined(SYSCFG_SWPR_PAGE31) 00228 #define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */ 00229 #define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */ 00230 #define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */ 00231 #define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */ 00232 #define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */ 00233 #define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */ 00234 #define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */ 00235 #define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */ 00236 #define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */ 00237 #define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */ 00238 #define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */ 00239 #define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */ 00240 #define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */ 00241 #define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */ 00242 #define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */ 00243 #define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */ 00244 #endif /* SYSCFG_SWPR_PAGE31 */ 00245 #if defined(SYSCFG_SWPR2_PAGE63) 00246 #define LL_SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */ 00247 #define LL_SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */ 00248 #define LL_SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */ 00249 #define LL_SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */ 00250 #define LL_SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */ 00251 #define LL_SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */ 00252 #define LL_SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */ 00253 #define LL_SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */ 00254 #define LL_SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */ 00255 #define LL_SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */ 00256 #define LL_SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */ 00257 #define LL_SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */ 00258 #define LL_SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */ 00259 #define LL_SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */ 00260 #define LL_SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */ 00261 #define LL_SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */ 00262 #define LL_SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */ 00263 #define LL_SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */ 00264 #define LL_SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */ 00265 #define LL_SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */ 00266 #define LL_SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */ 00267 #define LL_SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */ 00268 #define LL_SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */ 00269 #define LL_SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */ 00270 #define LL_SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */ 00271 #define LL_SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */ 00272 #define LL_SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */ 00273 #define LL_SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */ 00274 #define LL_SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */ 00275 #define LL_SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */ 00276 #define LL_SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */ 00277 #define LL_SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */ 00278 #endif /* SYSCFG_SWPR2_PAGE63 */ 00279 /** 00280 * @} 00281 */ 00282 00283 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment 00284 * @{ 00285 */ 00286 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ 00287 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ 00288 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ 00289 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ 00290 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ 00291 /** 00292 * @} 00293 */ 00294 00295 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP 00296 * @{ 00297 */ 00298 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/ 00299 #if defined(TIM3) 00300 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/ 00301 #endif /* TIM3 */ 00302 #if defined(TIM4) 00303 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/ 00304 #endif /* TIM4 */ 00305 #if defined(TIM5) 00306 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/ 00307 #endif /* TIM5 */ 00308 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/ 00309 #if defined(TIM7) 00310 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/ 00311 #endif /* TIM7 */ 00312 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted*/ 00313 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/ 00314 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/ 00315 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/ 00316 #if defined(I2C2) 00317 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/ 00318 #endif /* I2C2 */ 00319 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen*/ 00320 #define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP /*!< The bxCAN receive registers are frozen*/ 00321 #if defined(CAN2) 00322 #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1FZR1_DBG_CAN2_STOP /*!< The bxCAN2 receive registers are frozen*/ 00323 #endif /* CAN2 */ 00324 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/ 00325 /** 00326 * @} 00327 */ 00328 00329 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP 00330 * @{ 00331 */ 00332 #if defined(I2C4) 00333 #define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/ 00334 #endif /* I2C4 */ 00335 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/ 00336 /** 00337 * @} 00338 */ 00339 00340 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP 00341 * @{ 00342 */ 00343 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/ 00344 #if defined(TIM8) 00345 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/ 00346 #endif /* TIM8 */ 00347 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/ 00348 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/ 00349 #if defined(TIM17) 00350 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/ 00351 #endif /* TIM17 */ 00352 /** 00353 * @} 00354 */ 00355 00356 #if defined(VREFBUF) 00357 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE 00358 * @{ 00359 */ 00360 #define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ 00361 #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ 00362 /** 00363 * @} 00364 */ 00365 #endif /* VREFBUF */ 00366 00367 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY 00368 * @{ 00369 */ 00370 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ 00371 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ 00372 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ 00373 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ 00374 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ 00375 #if defined(FLASH_ACR_LATENCY_5WS) 00376 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ 00377 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ 00378 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ 00379 #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */ 00380 #define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */ 00381 #define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */ 00382 #define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */ 00383 #define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */ 00384 #define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */ 00385 #define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */ 00386 #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */ 00387 #endif 00388 /** 00389 * @} 00390 */ 00391 00392 /** 00393 * @} 00394 */ 00395 00396 /* Exported macro ------------------------------------------------------------*/ 00397 00398 /* Exported functions --------------------------------------------------------*/ 00399 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions 00400 * @{ 00401 */ 00402 00403 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG 00404 * @{ 00405 */ 00406 00407 /** 00408 * @brief Set memory mapping at address 0x00000000 00409 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory 00410 * @param Memory This parameter can be one of the following values: 00411 * @arg @ref LL_SYSCFG_REMAP_FLASH 00412 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH 00413 * @arg @ref LL_SYSCFG_REMAP_SRAM 00414 * @arg @ref LL_SYSCFG_REMAP_FMC (*) 00415 * @arg @ref LL_SYSCFG_REMAP_QUADSPI 00416 * 00417 * (*) value not defined in all devices 00418 * @retval None 00419 */ 00420 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) 00421 { 00422 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory); 00423 } 00424 00425 /** 00426 * @brief Get memory mapping at address 0x00000000 00427 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory 00428 * @retval Returned value can be one of the following values: 00429 * @arg @ref LL_SYSCFG_REMAP_FLASH 00430 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH 00431 * @arg @ref LL_SYSCFG_REMAP_SRAM 00432 * @arg @ref LL_SYSCFG_REMAP_FMC (*) 00433 * @arg @ref LL_SYSCFG_REMAP_QUADSPI 00434 * 00435 * (*) value not defined in all devices 00436 */ 00437 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) 00438 { 00439 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)); 00440 } 00441 00442 #if defined(SYSCFG_MEMRMP_FB_MODE) 00443 /** 00444 * @brief Select Flash bank mode (Bank flashed at 0x08000000) 00445 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode 00446 * @param Bank This parameter can be one of the following values: 00447 * @arg @ref LL_SYSCFG_BANKMODE_BANK1 00448 * @arg @ref LL_SYSCFG_BANKMODE_BANK2 00449 * @retval None 00450 */ 00451 __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank) 00452 { 00453 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank); 00454 } 00455 00456 /** 00457 * @brief Get Flash bank mode (Bank flashed at 0x08000000) 00458 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode 00459 * @retval Returned value can be one of the following values: 00460 * @arg @ref LL_SYSCFG_BANKMODE_BANK1 00461 * @arg @ref LL_SYSCFG_BANKMODE_BANK2 00462 */ 00463 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void) 00464 { 00465 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE)); 00466 } 00467 #endif /* SYSCFG_MEMRMP_FB_MODE */ 00468 00469 /** 00470 * @brief Firewall protection enabled 00471 * @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_EnableFirewall 00472 * @retval None 00473 */ 00474 __STATIC_INLINE void LL_SYSCFG_EnableFirewall(void) 00475 { 00476 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS); 00477 } 00478 00479 /** 00480 * @brief Check if Firewall protection is enabled or not 00481 * @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_IsEnabledFirewall 00482 * @retval State of bit (1 or 0). 00483 */ 00484 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void) 00485 { 00486 return !(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) == SYSCFG_CFGR1_FWDIS); 00487 } 00488 00489 /** 00490 * @brief Enable I/O analog switch voltage booster. 00491 * @note When voltage booster is enabled, I/O analog switches are supplied 00492 * by a dedicated voltage booster, from VDD power domain. This is 00493 * the recommended configuration with low VDDA voltage operation. 00494 * @note The I/O analog switch voltage booster is relevant for peripherals 00495 * using I/O in analog input: ADC, COMP, OPAMP. 00496 * However, COMP and OPAMP inputs have a high impedance and 00497 * voltage booster do not impact performance significantly. 00498 * Therefore, the voltage booster is mainly intended for 00499 * usage with ADC. 00500 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster 00501 * @retval None 00502 */ 00503 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void) 00504 { 00505 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); 00506 } 00507 00508 /** 00509 * @brief Disable I/O analog switch voltage booster. 00510 * @note When voltage booster is enabled, I/O analog switches are supplied 00511 * by a dedicated voltage booster, from VDD power domain. This is 00512 * the recommended configuration with low VDDA voltage operation. 00513 * @note The I/O analog switch voltage booster is relevant for peripherals 00514 * using I/O in analog input: ADC, COMP, OPAMP. 00515 * However, COMP and OPAMP inputs have a high impedance and 00516 * voltage booster do not impact performance significantly. 00517 * Therefore, the voltage booster is mainly intended for 00518 * usage with ADC. 00519 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster 00520 * @retval None 00521 */ 00522 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) 00523 { 00524 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); 00525 } 00526 00527 /** 00528 * @brief Enable the I2C fast mode plus driving capability. 00529 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n 00530 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus 00531 * @param ConfigFastModePlus This parameter can be a combination of the following values: 00532 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 00533 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 00534 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) 00535 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) 00536 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 00537 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) 00538 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 00539 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*) 00540 * 00541 * (*) value not defined in all devices 00542 * @retval None 00543 */ 00544 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) 00545 { 00546 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); 00547 } 00548 00549 /** 00550 * @brief Disable the I2C fast mode plus driving capability. 00551 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n 00552 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus 00553 * @param ConfigFastModePlus This parameter can be a combination of the following values: 00554 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 00555 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 00556 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) 00557 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) 00558 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 00559 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) 00560 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 00561 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*) 00562 * 00563 * (*) value not defined in all devices 00564 * @retval None 00565 */ 00566 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) 00567 { 00568 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); 00569 } 00570 00571 /** 00572 * @brief Enable Floating Point Unit Invalid operation Interrupt 00573 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC 00574 * @retval None 00575 */ 00576 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void) 00577 { 00578 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0); 00579 } 00580 00581 /** 00582 * @brief Enable Floating Point Unit Divide-by-zero Interrupt 00583 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC 00584 * @retval None 00585 */ 00586 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void) 00587 { 00588 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1); 00589 } 00590 00591 /** 00592 * @brief Enable Floating Point Unit Underflow Interrupt 00593 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC 00594 * @retval None 00595 */ 00596 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void) 00597 { 00598 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2); 00599 } 00600 00601 /** 00602 * @brief Enable Floating Point Unit Overflow Interrupt 00603 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC 00604 * @retval None 00605 */ 00606 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void) 00607 { 00608 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3); 00609 } 00610 00611 /** 00612 * @brief Enable Floating Point Unit Input denormal Interrupt 00613 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC 00614 * @retval None 00615 */ 00616 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void) 00617 { 00618 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4); 00619 } 00620 00621 /** 00622 * @brief Enable Floating Point Unit Inexact Interrupt 00623 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC 00624 * @retval None 00625 */ 00626 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void) 00627 { 00628 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5); 00629 } 00630 00631 /** 00632 * @brief Disable Floating Point Unit Invalid operation Interrupt 00633 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC 00634 * @retval None 00635 */ 00636 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void) 00637 { 00638 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0); 00639 } 00640 00641 /** 00642 * @brief Disable Floating Point Unit Divide-by-zero Interrupt 00643 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC 00644 * @retval None 00645 */ 00646 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void) 00647 { 00648 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1); 00649 } 00650 00651 /** 00652 * @brief Disable Floating Point Unit Underflow Interrupt 00653 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC 00654 * @retval None 00655 */ 00656 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void) 00657 { 00658 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2); 00659 } 00660 00661 /** 00662 * @brief Disable Floating Point Unit Overflow Interrupt 00663 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC 00664 * @retval None 00665 */ 00666 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void) 00667 { 00668 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3); 00669 } 00670 00671 /** 00672 * @brief Disable Floating Point Unit Input denormal Interrupt 00673 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC 00674 * @retval None 00675 */ 00676 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void) 00677 { 00678 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4); 00679 } 00680 00681 /** 00682 * @brief Disable Floating Point Unit Inexact Interrupt 00683 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC 00684 * @retval None 00685 */ 00686 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void) 00687 { 00688 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5); 00689 } 00690 00691 /** 00692 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled. 00693 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC 00694 * @retval State of bit (1 or 0). 00695 */ 00696 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void) 00697 { 00698 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0)); 00699 } 00700 00701 /** 00702 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled. 00703 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC 00704 * @retval State of bit (1 or 0). 00705 */ 00706 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void) 00707 { 00708 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1)); 00709 } 00710 00711 /** 00712 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled. 00713 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC 00714 * @retval State of bit (1 or 0). 00715 */ 00716 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void) 00717 { 00718 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2)); 00719 } 00720 00721 /** 00722 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled. 00723 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC 00724 * @retval State of bit (1 or 0). 00725 */ 00726 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void) 00727 { 00728 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3)); 00729 } 00730 00731 /** 00732 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled. 00733 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC 00734 * @retval State of bit (1 or 0). 00735 */ 00736 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void) 00737 { 00738 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4)); 00739 } 00740 00741 /** 00742 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled. 00743 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC 00744 * @retval State of bit (1 or 0). 00745 */ 00746 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void) 00747 { 00748 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5)); 00749 } 00750 00751 /** 00752 * @brief Configure source input for the EXTI external interrupt. 00753 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n 00754 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n 00755 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n 00756 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource 00757 * @param Port This parameter can be one of the following values: 00758 * @arg @ref LL_SYSCFG_EXTI_PORTA 00759 * @arg @ref LL_SYSCFG_EXTI_PORTB 00760 * @arg @ref LL_SYSCFG_EXTI_PORTC 00761 * @arg @ref LL_SYSCFG_EXTI_PORTD 00762 * @arg @ref LL_SYSCFG_EXTI_PORTE 00763 * @arg @ref LL_SYSCFG_EXTI_PORTF (*) 00764 * @arg @ref LL_SYSCFG_EXTI_PORTG (*) 00765 * @arg @ref LL_SYSCFG_EXTI_PORTH 00766 * @arg @ref LL_SYSCFG_EXTI_PORTI (*) 00767 * 00768 * (*) value not defined in all devices 00769 * @param Line This parameter can be one of the following values: 00770 * @arg @ref LL_SYSCFG_EXTI_LINE0 00771 * @arg @ref LL_SYSCFG_EXTI_LINE1 00772 * @arg @ref LL_SYSCFG_EXTI_LINE2 00773 * @arg @ref LL_SYSCFG_EXTI_LINE3 00774 * @arg @ref LL_SYSCFG_EXTI_LINE4 00775 * @arg @ref LL_SYSCFG_EXTI_LINE5 00776 * @arg @ref LL_SYSCFG_EXTI_LINE6 00777 * @arg @ref LL_SYSCFG_EXTI_LINE7 00778 * @arg @ref LL_SYSCFG_EXTI_LINE8 00779 * @arg @ref LL_SYSCFG_EXTI_LINE9 00780 * @arg @ref LL_SYSCFG_EXTI_LINE10 00781 * @arg @ref LL_SYSCFG_EXTI_LINE11 00782 * @arg @ref LL_SYSCFG_EXTI_LINE12 00783 * @arg @ref LL_SYSCFG_EXTI_LINE13 00784 * @arg @ref LL_SYSCFG_EXTI_LINE14 00785 * @arg @ref LL_SYSCFG_EXTI_LINE15 00786 * @retval None 00787 */ 00788 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) 00789 { 00790 MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U))); 00791 } 00792 00793 /** 00794 * @brief Get the configured defined for specific EXTI Line 00795 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n 00796 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n 00797 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n 00798 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource 00799 * @param Line This parameter can be one of the following values: 00800 * @arg @ref LL_SYSCFG_EXTI_LINE0 00801 * @arg @ref LL_SYSCFG_EXTI_LINE1 00802 * @arg @ref LL_SYSCFG_EXTI_LINE2 00803 * @arg @ref LL_SYSCFG_EXTI_LINE3 00804 * @arg @ref LL_SYSCFG_EXTI_LINE4 00805 * @arg @ref LL_SYSCFG_EXTI_LINE5 00806 * @arg @ref LL_SYSCFG_EXTI_LINE6 00807 * @arg @ref LL_SYSCFG_EXTI_LINE7 00808 * @arg @ref LL_SYSCFG_EXTI_LINE8 00809 * @arg @ref LL_SYSCFG_EXTI_LINE9 00810 * @arg @ref LL_SYSCFG_EXTI_LINE10 00811 * @arg @ref LL_SYSCFG_EXTI_LINE11 00812 * @arg @ref LL_SYSCFG_EXTI_LINE12 00813 * @arg @ref LL_SYSCFG_EXTI_LINE13 00814 * @arg @ref LL_SYSCFG_EXTI_LINE14 00815 * @arg @ref LL_SYSCFG_EXTI_LINE15 00816 * @retval Returned value can be one of the following values: 00817 * @arg @ref LL_SYSCFG_EXTI_PORTA 00818 * @arg @ref LL_SYSCFG_EXTI_PORTB 00819 * @arg @ref LL_SYSCFG_EXTI_PORTC 00820 * @arg @ref LL_SYSCFG_EXTI_PORTD 00821 * @arg @ref LL_SYSCFG_EXTI_PORTE 00822 * @arg @ref LL_SYSCFG_EXTI_PORTF (*) 00823 * @arg @ref LL_SYSCFG_EXTI_PORTG (*) 00824 * @arg @ref LL_SYSCFG_EXTI_PORTH 00825 * @arg @ref LL_SYSCFG_EXTI_PORTI (*) 00826 * 00827 * (*) value not defined in all devices 00828 */ 00829 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) 00830 { 00831 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U)); 00832 } 00833 00834 /** 00835 * @brief Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is 00836 * automatically cleared at the end of the SRAM2 erase operation.) 00837 * @note This bit is write-protected: setting this bit is possible only after the 00838 * correct key sequence is written in the SYSCFG_SKR register as described in 00839 * the Reference Manual. 00840 * @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase 00841 * @retval None 00842 */ 00843 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void) 00844 { 00845 /* Starts a hardware SRAM2 erase operation*/ 00846 SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER); 00847 } 00848 00849 /** 00850 * @brief Check if SRAM2 erase operation is on going 00851 * @rmtoll SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing 00852 * @retval State of bit (1 or 0). 00853 */ 00854 __STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void) 00855 { 00856 return (READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY)); 00857 } 00858 00859 /** 00860 * @brief Set connections to TIM1/8/15/16/17 Break inputs 00861 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n 00862 * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n 00863 * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n 00864 * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs 00865 * @param Break This parameter can be a combination of the following values: 00866 * @arg @ref LL_SYSCFG_TIMBREAK_ECC 00867 * @arg @ref LL_SYSCFG_TIMBREAK_PVD 00868 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY 00869 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP 00870 * @retval None 00871 */ 00872 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) 00873 { 00874 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break); 00875 } 00876 00877 /** 00878 * @brief Get connections to TIM1/8/15/16/17 Break inputs 00879 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n 00880 * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n 00881 * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n 00882 * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs 00883 * @retval Returned value can be can be a combination of the following values: 00884 * @arg @ref LL_SYSCFG_TIMBREAK_ECC 00885 * @arg @ref LL_SYSCFG_TIMBREAK_PVD 00886 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY 00887 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP 00888 */ 00889 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) 00890 { 00891 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL)); 00892 } 00893 00894 /** 00895 * @brief Check if SRAM2 parity error detected 00896 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP 00897 * @retval State of bit (1 or 0). 00898 */ 00899 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void) 00900 { 00901 return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)); 00902 } 00903 00904 /** 00905 * @brief Clear SRAM2 parity error flag 00906 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP 00907 * @retval None 00908 */ 00909 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) 00910 { 00911 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF); 00912 } 00913 00914 /** 00915 * @brief Enable SRAM2 page write protection for Pages in range 0 to 31 00916 * @note Write protection is cleared only by a system reset 00917 * @rmtoll SYSCFG_SWPR PxWP LL_SYSCFG_EnableSRAM2PageWRP_0_31 00918 * @param SRAM2WRP This parameter can be a combination of the following values: 00919 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0 00920 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1 00921 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2 00922 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3 00923 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4 00924 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5 00925 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6 00926 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7 00927 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8 00928 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9 00929 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10 00930 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11 00931 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12 00932 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13 00933 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14 00934 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15 00935 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16 (*) 00936 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17 (*) 00937 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18 (*) 00938 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19 (*) 00939 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20 (*) 00940 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21 (*) 00941 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22 (*) 00942 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23 (*) 00943 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24 (*) 00944 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25 (*) 00945 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26 (*) 00946 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27 (*) 00947 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28 (*) 00948 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29 (*) 00949 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30 (*) 00950 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31 (*) 00951 * 00952 * (*) value not defined in all devices 00953 * @retval None 00954 */ 00955 /* Legacy define */ 00956 #define LL_SYSCFG_EnableSRAM2PageWRP LL_SYSCFG_EnableSRAM2PageWRP_0_31 00957 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP) 00958 { 00959 SET_BIT(SYSCFG->SWPR, SRAM2WRP); 00960 } 00961 00962 #if defined(SYSCFG_SWPR2_PAGE63) 00963 /** 00964 * @brief Enable SRAM2 page write protection for Pages in range 32 to 63 00965 * @note Write protection is cleared only by a system reset 00966 * @rmtoll SYSCFG_SWPR2 PxWP LL_SYSCFG_EnableSRAM2PageWRP_32_63 00967 * @param SRAM2WRP This parameter can be a combination of the following values: 00968 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE32 (*) 00969 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE33 (*) 00970 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE34 (*) 00971 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE35 (*) 00972 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE36 (*) 00973 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE37 (*) 00974 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE38 (*) 00975 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE39 (*) 00976 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE40 (*) 00977 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE41 (*) 00978 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE42 (*) 00979 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE43 (*) 00980 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE44 (*) 00981 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE45 (*) 00982 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE46 (*) 00983 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE47 (*) 00984 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE48 (*) 00985 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE49 (*) 00986 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE50 (*) 00987 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE51 (*) 00988 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE52 (*) 00989 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE53 (*) 00990 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE54 (*) 00991 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE55 (*) 00992 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE56 (*) 00993 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE57 (*) 00994 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE58 (*) 00995 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE59 (*) 00996 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE60 (*) 00997 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE61 (*) 00998 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE62 (*) 00999 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE63 (*) 01000 * 01001 * (*) value not defined in all devices 01002 * @retval None 01003 */ 01004 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP) 01005 { 01006 SET_BIT(SYSCFG->SWPR2, SRAM2WRP); 01007 } 01008 #endif /* SYSCFG_SWPR2_PAGE63 */ 01009 01010 /** 01011 * @brief SRAM2 page write protection lock prior to erase 01012 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP 01013 * @retval None 01014 */ 01015 __STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void) 01016 { 01017 /* Writing a wrong key reactivates the write protection */ 01018 WRITE_REG(SYSCFG->SKR, 0x00); 01019 } 01020 01021 /** 01022 * @brief SRAM2 page write protection unlock prior to erase 01023 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP 01024 * @retval None 01025 */ 01026 __STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void) 01027 { 01028 /* unlock the write protection of the SRAM2ER bit */ 01029 WRITE_REG(SYSCFG->SKR, 0xCA); 01030 WRITE_REG(SYSCFG->SKR, 0x53); 01031 } 01032 01033 /** 01034 * @} 01035 */ 01036 01037 01038 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU 01039 * @{ 01040 */ 01041 01042 /** 01043 * @brief Return the device identifier 01044 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID 01045 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415) 01046 */ 01047 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) 01048 { 01049 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); 01050 } 01051 01052 /** 01053 * @brief Return the device revision identifier 01054 * @note This field indicates the revision of the device. 01055 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID 01056 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF 01057 */ 01058 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) 01059 { 01060 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); 01061 } 01062 01063 /** 01064 * @brief Enable the Debug Module during SLEEP mode 01065 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode 01066 * @retval None 01067 */ 01068 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) 01069 { 01070 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); 01071 } 01072 01073 /** 01074 * @brief Disable the Debug Module during SLEEP mode 01075 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode 01076 * @retval None 01077 */ 01078 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) 01079 { 01080 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); 01081 } 01082 01083 /** 01084 * @brief Enable the Debug Module during STOP mode 01085 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode 01086 * @retval None 01087 */ 01088 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) 01089 { 01090 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); 01091 } 01092 01093 /** 01094 * @brief Disable the Debug Module during STOP mode 01095 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode 01096 * @retval None 01097 */ 01098 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) 01099 { 01100 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); 01101 } 01102 01103 /** 01104 * @brief Enable the Debug Module during STANDBY mode 01105 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode 01106 * @retval None 01107 */ 01108 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) 01109 { 01110 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); 01111 } 01112 01113 /** 01114 * @brief Disable the Debug Module during STANDBY mode 01115 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode 01116 * @retval None 01117 */ 01118 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) 01119 { 01120 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); 01121 } 01122 01123 /** 01124 * @brief Set Trace pin assignment control 01125 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n 01126 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment 01127 * @param PinAssignment This parameter can be one of the following values: 01128 * @arg @ref LL_DBGMCU_TRACE_NONE 01129 * @arg @ref LL_DBGMCU_TRACE_ASYNCH 01130 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 01131 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 01132 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 01133 * @retval None 01134 */ 01135 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) 01136 { 01137 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); 01138 } 01139 01140 /** 01141 * @brief Get Trace pin assignment control 01142 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n 01143 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment 01144 * @retval Returned value can be one of the following values: 01145 * @arg @ref LL_DBGMCU_TRACE_NONE 01146 * @arg @ref LL_DBGMCU_TRACE_ASYNCH 01147 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 01148 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 01149 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 01150 */ 01151 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) 01152 { 01153 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); 01154 } 01155 01156 /** 01157 * @brief Freeze APB1 peripherals (group1 peripherals) 01158 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph 01159 * @param Periphs This parameter can be a combination of the following values: 01160 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP 01161 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) 01162 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) 01163 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) 01164 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP 01165 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) 01166 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP 01167 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP 01168 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP 01169 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP 01170 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) 01171 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP 01172 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP 01173 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) 01174 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP 01175 * 01176 * (*) value not defined in all devices. 01177 * @retval None 01178 */ 01179 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) 01180 { 01181 SET_BIT(DBGMCU->APB1FZR1, Periphs); 01182 } 01183 01184 /** 01185 * @brief Freeze APB1 peripherals (group2 peripherals) 01186 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph 01187 * @param Periphs This parameter can be a combination of the following values: 01188 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*) 01189 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP 01190 * 01191 * (*) value not defined in all devices. 01192 * @retval None 01193 */ 01194 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) 01195 { 01196 SET_BIT(DBGMCU->APB1FZR2, Periphs); 01197 } 01198 01199 /** 01200 * @brief Unfreeze APB1 peripherals (group1 peripherals) 01201 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph 01202 * @param Periphs This parameter can be a combination of the following values: 01203 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP 01204 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) 01205 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) 01206 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) 01207 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP 01208 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) 01209 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP 01210 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP 01211 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP 01212 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP 01213 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) 01214 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP 01215 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP 01216 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) 01217 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP 01218 * 01219 * (*) value not defined in all devices. 01220 * @retval None 01221 */ 01222 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) 01223 { 01224 CLEAR_BIT(DBGMCU->APB1FZR1, Periphs); 01225 } 01226 01227 /** 01228 * @brief Unfreeze APB1 peripherals (group2 peripherals) 01229 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph 01230 * @param Periphs This parameter can be a combination of the following values: 01231 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*) 01232 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP 01233 * 01234 * (*) value not defined in all devices. 01235 * @retval None 01236 */ 01237 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) 01238 { 01239 CLEAR_BIT(DBGMCU->APB1FZR2, Periphs); 01240 } 01241 01242 /** 01243 * @brief Freeze APB2 peripherals 01244 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph 01245 * @param Periphs This parameter can be a combination of the following values: 01246 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP 01247 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) 01248 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP 01249 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP 01250 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) 01251 * 01252 * (*) value not defined in all devices. 01253 * @retval None 01254 */ 01255 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) 01256 { 01257 SET_BIT(DBGMCU->APB2FZ, Periphs); 01258 } 01259 01260 /** 01261 * @brief Unfreeze APB2 peripherals 01262 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph 01263 * @param Periphs This parameter can be a combination of the following values: 01264 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP 01265 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) 01266 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP 01267 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP 01268 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) 01269 * 01270 * (*) value not defined in all devices. 01271 * @retval None 01272 */ 01273 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) 01274 { 01275 CLEAR_BIT(DBGMCU->APB2FZ, Periphs); 01276 } 01277 01278 /** 01279 * @} 01280 */ 01281 01282 #if defined(VREFBUF) 01283 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF 01284 * @{ 01285 */ 01286 01287 /** 01288 * @brief Enable Internal voltage reference 01289 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable 01290 * @retval None 01291 */ 01292 __STATIC_INLINE void LL_VREFBUF_Enable(void) 01293 { 01294 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); 01295 } 01296 01297 /** 01298 * @brief Disable Internal voltage reference 01299 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable 01300 * @retval None 01301 */ 01302 __STATIC_INLINE void LL_VREFBUF_Disable(void) 01303 { 01304 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); 01305 } 01306 01307 /** 01308 * @brief Enable high impedance (VREF+pin is high impedance) 01309 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ 01310 * @retval None 01311 */ 01312 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void) 01313 { 01314 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); 01315 } 01316 01317 /** 01318 * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output) 01319 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ 01320 * @retval None 01321 */ 01322 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void) 01323 { 01324 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); 01325 } 01326 01327 /** 01328 * @brief Set the Voltage reference scale 01329 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling 01330 * @param Scale This parameter can be one of the following values: 01331 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 01332 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 01333 * @retval None 01334 */ 01335 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale) 01336 { 01337 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale); 01338 } 01339 01340 /** 01341 * @brief Get the Voltage reference scale 01342 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling 01343 * @retval Returned value can be one of the following values: 01344 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 01345 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 01346 */ 01347 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void) 01348 { 01349 return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS)); 01350 } 01351 01352 /** 01353 * @brief Check if Voltage reference buffer is ready 01354 * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady 01355 * @retval State of bit (1 or 0). 01356 */ 01357 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void) 01358 { 01359 return (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)); 01360 } 01361 01362 /** 01363 * @brief Get the trimming code for VREFBUF calibration 01364 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming 01365 * @retval Between 0 and 0x3F 01366 */ 01367 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void) 01368 { 01369 return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM)); 01370 } 01371 01372 /** 01373 * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage) 01374 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming 01375 * @param Value Between 0 and 0x3F 01376 * @retval None 01377 */ 01378 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value) 01379 { 01380 WRITE_REG(VREFBUF->CCR, Value); 01381 } 01382 01383 /** 01384 * @} 01385 */ 01386 #endif /* VREFBUF */ 01387 01388 /** @defgroup SYSTEM_LL_EF_FLASH FLASH 01389 * @{ 01390 */ 01391 01392 /** 01393 * @brief Set FLASH Latency 01394 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency 01395 * @param Latency This parameter can be one of the following values: 01396 * @arg @ref LL_FLASH_LATENCY_0 01397 * @arg @ref LL_FLASH_LATENCY_1 01398 * @arg @ref LL_FLASH_LATENCY_2 01399 * @arg @ref LL_FLASH_LATENCY_3 01400 * @arg @ref LL_FLASH_LATENCY_4 01401 * @arg @ref LL_FLASH_LATENCY_5 (*) 01402 * @arg @ref LL_FLASH_LATENCY_6 (*) 01403 * @arg @ref LL_FLASH_LATENCY_7 (*) 01404 * @arg @ref LL_FLASH_LATENCY_8 (*) 01405 * @arg @ref LL_FLASH_LATENCY_9 (*) 01406 * @arg @ref LL_FLASH_LATENCY_10 (*) 01407 * @arg @ref LL_FLASH_LATENCY_11 (*) 01408 * @arg @ref LL_FLASH_LATENCY_12 (*) 01409 * @arg @ref LL_FLASH_LATENCY_13 (*) 01410 * @arg @ref LL_FLASH_LATENCY_14 (*) 01411 * @arg @ref LL_FLASH_LATENCY_15 (*) 01412 * 01413 * (*) value not defined in all devices. 01414 * @retval None 01415 */ 01416 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) 01417 { 01418 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); 01419 } 01420 01421 /** 01422 * @brief Get FLASH Latency 01423 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency 01424 * @retval Returned value can be one of the following values: 01425 * @arg @ref LL_FLASH_LATENCY_0 01426 * @arg @ref LL_FLASH_LATENCY_1 01427 * @arg @ref LL_FLASH_LATENCY_2 01428 * @arg @ref LL_FLASH_LATENCY_3 01429 * @arg @ref LL_FLASH_LATENCY_4 01430 * @arg @ref LL_FLASH_LATENCY_5 (*) 01431 * @arg @ref LL_FLASH_LATENCY_6 (*) 01432 * @arg @ref LL_FLASH_LATENCY_7 (*) 01433 * @arg @ref LL_FLASH_LATENCY_8 (*) 01434 * @arg @ref LL_FLASH_LATENCY_9 (*) 01435 * @arg @ref LL_FLASH_LATENCY_10 (*) 01436 * @arg @ref LL_FLASH_LATENCY_11 (*) 01437 * @arg @ref LL_FLASH_LATENCY_12 (*) 01438 * @arg @ref LL_FLASH_LATENCY_13 (*) 01439 * @arg @ref LL_FLASH_LATENCY_14 (*) 01440 * @arg @ref LL_FLASH_LATENCY_15 (*) 01441 * 01442 * (*) value not defined in all devices. 01443 */ 01444 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) 01445 { 01446 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); 01447 } 01448 01449 /** 01450 * @brief Enable Prefetch 01451 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch 01452 * @retval None 01453 */ 01454 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void) 01455 { 01456 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); 01457 } 01458 01459 /** 01460 * @brief Disable Prefetch 01461 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch 01462 * @retval None 01463 */ 01464 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void) 01465 { 01466 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); 01467 } 01468 01469 /** 01470 * @brief Check if Prefetch buffer is enabled 01471 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled 01472 * @retval State of bit (1 or 0). 01473 */ 01474 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) 01475 { 01476 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)); 01477 } 01478 01479 /** 01480 * @brief Enable Instruction cache 01481 * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache 01482 * @retval None 01483 */ 01484 __STATIC_INLINE void LL_FLASH_EnableInstCache(void) 01485 { 01486 SET_BIT(FLASH->ACR, FLASH_ACR_ICEN); 01487 } 01488 01489 /** 01490 * @brief Disable Instruction cache 01491 * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache 01492 * @retval None 01493 */ 01494 __STATIC_INLINE void LL_FLASH_DisableInstCache(void) 01495 { 01496 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN); 01497 } 01498 01499 /** 01500 * @brief Enable Data cache 01501 * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache 01502 * @retval None 01503 */ 01504 __STATIC_INLINE void LL_FLASH_EnableDataCache(void) 01505 { 01506 SET_BIT(FLASH->ACR, FLASH_ACR_DCEN); 01507 } 01508 01509 /** 01510 * @brief Disable Data cache 01511 * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache 01512 * @retval None 01513 */ 01514 __STATIC_INLINE void LL_FLASH_DisableDataCache(void) 01515 { 01516 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN); 01517 } 01518 01519 /** 01520 * @brief Enable Instruction cache reset 01521 * @note bit can be written only when the instruction cache is disabled 01522 * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset 01523 * @retval None 01524 */ 01525 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void) 01526 { 01527 SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); 01528 } 01529 01530 /** 01531 * @brief Disable Instruction cache reset 01532 * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset 01533 * @retval None 01534 */ 01535 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void) 01536 { 01537 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); 01538 } 01539 01540 /** 01541 * @brief Enable Data cache reset 01542 * @note bit can be written only when the data cache is disabled 01543 * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset 01544 * @retval None 01545 */ 01546 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void) 01547 { 01548 SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); 01549 } 01550 01551 /** 01552 * @brief Disable Data cache reset 01553 * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset 01554 * @retval None 01555 */ 01556 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void) 01557 { 01558 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); 01559 } 01560 01561 /** 01562 * @brief Enable Flash Power-down mode during run mode or Low-power run mode 01563 * @note Flash memory can be put in power-down mode only when the code is executed 01564 * from RAM 01565 * @note Flash must not be accessed when power down is enabled 01566 * @note Flash must not be put in power-down while a program or an erase operation 01567 * is on-going 01568 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n 01569 * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n 01570 * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown 01571 * @retval None 01572 */ 01573 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void) 01574 { 01575 /* Following values must be written consecutively to unlock the RUN_PD bit in 01576 FLASH_ACR */ 01577 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); 01578 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); 01579 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); 01580 } 01581 01582 /** 01583 * @brief Disable Flash Power-down mode during run mode or Low-power run mode 01584 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n 01585 * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n 01586 * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown 01587 * @retval None 01588 */ 01589 __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void) 01590 { 01591 /* Following values must be written consecutively to unlock the RUN_PD bit in 01592 FLASH_ACR */ 01593 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); 01594 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); 01595 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); 01596 } 01597 01598 /** 01599 * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode 01600 * @note Flash must not be put in power-down while a program or an erase operation 01601 * is on-going 01602 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown 01603 * @retval None 01604 */ 01605 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void) 01606 { 01607 SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); 01608 } 01609 01610 /** 01611 * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode 01612 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown 01613 * @retval None 01614 */ 01615 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) 01616 { 01617 CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); 01618 } 01619 01620 /** 01621 * @} 01622 */ 01623 01624 /** 01625 * @} 01626 */ 01627 01628 /** 01629 * @} 01630 */ 01631 01632 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */ 01633 01634 /** 01635 * @} 01636 */ 01637 01638 #ifdef __cplusplus 01639 } 01640 #endif 01641 01642 #endif /* __STM32L4xx_LL_SYSTEM_H */ 01643 01644 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/