STM32L486xx HAL User Manual: stm32l4xx_ll

Header file of ADC LL module. More...

#include "stm32l4xx.h"

Data Structures
struct	LL_ADC_CommonInitTypeDef
	Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...
struct	LL_ADC_InitTypeDef
	Structure definition of some features of ADC instance. More...
struct	LL_ADC_REG_InitTypeDef
	Structure definition of some features of ADC group regular. More...
struct	LL_ADC_INJ_InitTypeDef
	Structure definition of some features of ADC group injected. More...
Defines
#define	ADC_SQR1_REGOFFSET (0x00000000U)
#define	ADC_SQR2_REGOFFSET (0x00000100U)
#define	ADC_SQR3_REGOFFSET (0x00000200U)
#define	ADC_SQR4_REGOFFSET (0x00000300U)
#define	ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET \| ADC_SQR2_REGOFFSET \| ADC_SQR3_REGOFFSET \| ADC_SQR4_REGOFFSET)
#define	ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define	ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */
#define	ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */
#define	ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */
#define	ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */
#define	ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */
#define	ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */
#define	ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
#define	ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
#define	ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
#define	ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */
#define	ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */
#define	ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */
#define	ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
#define	ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
#define	ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */
#define	ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */
#define	ADC_JDR1_REGOFFSET (0x00000000U)
#define	ADC_JDR2_REGOFFSET (0x00000100U)
#define	ADC_JDR3_REGOFFSET (0x00000200U)
#define	ADC_JDR4_REGOFFSET (0x00000300U)
#define	ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET \| ADC_JDR2_REGOFFSET \| ADC_JDR3_REGOFFSET \| ADC_JDR4_REGOFFSET)
#define	ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define	ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
#define	ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
#define	ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
#define	ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
#define	ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define	ADC_REG_TRIG_SOURCE_MASK
#define	ADC_REG_TRIG_EDGE_MASK
#define	ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */
#define	ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */
#define	ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
#define	ADC_INJ_TRIG_SOURCE_MASK
#define	ADC_INJ_TRIG_EDGE_MASK
#define	ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */
#define	ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */
#define	ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
#define	ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
#define	ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
#define	ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK \| ADC_CHANNEL_ID_BITFIELD_MASK \| ADC_CHANNEL_ID_INTERNAL_CH_MASK)
#define	ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
#define	ADC_CHANNEL_ID_INTERNAL_CH (0x80000000U) /* Marker of internal channel */
#define	ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define	ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_ID_INTERNAL_CH_2)
#define	ADC_SMPR1_REGOFFSET (0x00000000U)
#define	ADC_SMPR2_REGOFFSET (0x02000000U)
#define	ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET \| ADC_SMPR2_REGOFFSET)
#define	ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000U)
#define	ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
#define	ADC_CHANNEL_0_NUMBER (0x00000000U)
#define	ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
#define	ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
#define	ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_1 )
#define	ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_1 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
#define	ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_1 )
#define	ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_1 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_2 )
#define	ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_1 )
#define	ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 \| ADC_CFGR_AWD1CH_2 \| ADC_CFGR_AWD1CH_1 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
#define	ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 \| ADC_CFGR_AWD1CH_0)
#define	ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 \| ADC_CFGR_AWD1CH_1 )
#define	ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
#define	ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
#define	ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
#define	ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
#define	ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
#define	ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
#define	ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
#define	ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
#define	ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
#define	ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
#define	ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
#define	ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
#define	ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
#define	ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
#define	ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
#define	ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
#define	ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
#define	ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
#define	ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
#define	ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET \| (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */
#define	ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET \| (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */
#define	ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET \| (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */
#define	ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET \| (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */
#define	ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET \| ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */
#define	ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET \| ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */
#define	ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET \| ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */
#define	ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET \| ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */
#define	ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET \| ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */
#define	ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET \| ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */
#define	ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET \| (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
#define	ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET \| (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
#define	ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET \| (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
#define	ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET \| (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
#define	ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET \| ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
#define	ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET \| ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
#define	ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET \| ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
#define	ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET \| ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
#define	ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET \| ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
#define	ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
#define	ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D \| ADC_CALFACT_CALFACT_S)
#define	ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
#define	ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
#define	ADC_AWD_CR1_REGOFFSET (0x00000000U)
#define	ADC_AWD_CR2_REGOFFSET (0x00100000U)
#define	ADC_AWD_CR3_REGOFFSET (0x00200000U)
#define	ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define	ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024U)
#define	ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET \| ADC_AWD_CR2_REGOFFSET \| ADC_AWD_CR3_REGOFFSET)
#define	ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define	ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR23_CHANNEL_MASK)
#define	ADC_AWD_CRX_REGOFFSET_POS (20U) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
#define	ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define	ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define	ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
#define	ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET \| ADC_AWD_TR2_REGOFFSET \| ADC_AWD_TR3_REGOFFSET)
#define	ADC_OFR1_REGOFFSET (0x00000000U)
#define	ADC_OFR2_REGOFFSET (0x00000001U)
#define	ADC_OFR3_REGOFFSET (0x00000002U)
#define	ADC_OFR4_REGOFFSET (0x00000003U)
#define	ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET \| ADC_OFR2_REGOFFSET \| ADC_OFR3_REGOFFSET \| ADC_OFR4_REGOFFSET)
#define	ADC_CFGR_RES_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */
#define	ADC_CFGR_AWD1SGL_BITOFFSET_POS (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */
#define	ADC_CFGR_AWD1EN_BITOFFSET_POS (23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */
#define	ADC_CFGR_JAWD1EN_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */
#define	ADC_TR1_HT1_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */
#define	ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL \| ADC_CR_JADSTP \| ADC_CR_ADSTP \| ADC_CR_JADSTART \| ADC_CR_ADSTART \| ADC_CR_ADDIS \| ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
#define	VREFINT_CAL_ADDR ((uint16_t) (0x1FFF75AAU)) / Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define	VREFINT_CAL_VREF ( 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
#define	TEMPSENSOR_CAL1_ADDR ((uint16_t) (0x1FFF75A8U)) / Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define	TEMPSENSOR_CAL2_ADDR ((uint16_t) (0x1FFF75CAU)) / Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature defined by TEMPSENSOR_CAL2_TEMP (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define	TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define	TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define	TEMPSENSOR_CAL_VREFANALOG ( 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
#define	__ADC_MASK_SHIFT(__BITS__, __MASK__) (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
	Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).
#define	__ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
	Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define	LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY
#define	LL_ADC_FLAG_EOC ADC_ISR_EOC
#define	LL_ADC_FLAG_EOS ADC_ISR_EOS
#define	LL_ADC_FLAG_OVR ADC_ISR_OVR
#define	LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP
#define	LL_ADC_FLAG_JEOC ADC_ISR_JEOC
#define	LL_ADC_FLAG_JEOS ADC_ISR_JEOS
#define	LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF
#define	LL_ADC_FLAG_AWD1 ADC_ISR_AWD1
#define	LL_ADC_FLAG_AWD2 ADC_ISR_AWD2
#define	LL_ADC_FLAG_AWD3 ADC_ISR_AWD3
#define	LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST
#define	LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV
#define	LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST
#define	LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV
#define	LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST
#define	LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV
#define	LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST
#define	LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV
#define	LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST
#define	LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV
#define	LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST
#define	LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV
#define	LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST
#define	LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV
#define	LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST
#define	LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV
#define	LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST
#define	LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV
#define	LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST
#define	LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV
#define	LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST
#define	LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV
#define	LL_ADC_IT_ADRDY ADC_IER_ADRDYIE
#define	LL_ADC_IT_EOC ADC_IER_EOCIE
#define	LL_ADC_IT_EOS ADC_IER_EOSIE
#define	LL_ADC_IT_OVR ADC_IER_OVRIE
#define	LL_ADC_IT_EOSMP ADC_IER_EOSMPIE
#define	LL_ADC_IT_JEOC ADC_IER_JEOCIE
#define	LL_ADC_IT_JEOS ADC_IER_JEOSIE
#define	LL_ADC_IT_JQOVF ADC_IER_JQOVFIE
#define	LL_ADC_IT_AWD1 ADC_IER_AWD1IE
#define	LL_ADC_IT_AWD2 ADC_IER_AWD2IE
#define	LL_ADC_IT_AWD3 ADC_IER_AWD3IE
#define	LL_ADC_DMA_REG_REGULAR_DATA (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
#define	LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
#define	LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0)
#define	LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 )
#define	LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 \| ADC_CCR_CKMODE_0)
#define	LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000U)
#define	LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0)
#define	LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 )
#define	LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0)
#define	LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 )
#define	LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_0)
#define	LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_1 )
#define	LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0)
#define	LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3)
#define	LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_0)
#define	LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_1)
#define	LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0)
#define	LL_ADC_PATH_INTERNAL_NONE (0x00000000U)
#define	LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN)
#define	LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN)
#define	LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN)
#define	LL_ADC_RESOLUTION_12B (0x00000000U)
#define	LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0)
#define	LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 )
#define	LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 \| ADC_CFGR_RES_0)
#define	LL_ADC_DATA_ALIGN_RIGHT (0x00000000U)
#define	LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN)
#define	LL_ADC_LP_MODE_NONE (0x00000000U)
#define	LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY)
#define	LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET
#define	LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET
#define	LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET
#define	LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET
#define	LL_ADC_OFFSET_DISABLE (0x00000000U)
#define	LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN)
#define	LL_ADC_GROUP_REGULAR (0x00000001U)
#define	LL_ADC_GROUP_INJECTED (0x00000002U)
#define	LL_ADC_GROUP_REGULAR_INJECTED (0x00000003U)
#define	LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \| ADC_CHANNEL_0_SMP \| ADC_CHANNEL_0_BITFIELD )
#define	LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \| ADC_CHANNEL_1_SMP \| ADC_CHANNEL_1_BITFIELD )
#define	LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \| ADC_CHANNEL_2_SMP \| ADC_CHANNEL_2_BITFIELD )
#define	LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \| ADC_CHANNEL_3_SMP \| ADC_CHANNEL_3_BITFIELD )
#define	LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \| ADC_CHANNEL_4_SMP \| ADC_CHANNEL_4_BITFIELD )
#define	LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \| ADC_CHANNEL_5_SMP \| ADC_CHANNEL_5_BITFIELD )
#define	LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \| ADC_CHANNEL_6_SMP \| ADC_CHANNEL_6_BITFIELD )
#define	LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \| ADC_CHANNEL_7_SMP \| ADC_CHANNEL_7_BITFIELD )
#define	LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \| ADC_CHANNEL_8_SMP \| ADC_CHANNEL_8_BITFIELD )
#define	LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \| ADC_CHANNEL_9_SMP \| ADC_CHANNEL_9_BITFIELD )
#define	LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \| ADC_CHANNEL_10_SMP \| ADC_CHANNEL_10_BITFIELD)
#define	LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \| ADC_CHANNEL_11_SMP \| ADC_CHANNEL_11_BITFIELD)
#define	LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \| ADC_CHANNEL_12_SMP \| ADC_CHANNEL_12_BITFIELD)
#define	LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \| ADC_CHANNEL_13_SMP \| ADC_CHANNEL_13_BITFIELD)
#define	LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \| ADC_CHANNEL_14_SMP \| ADC_CHANNEL_14_BITFIELD)
#define	LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \| ADC_CHANNEL_15_SMP \| ADC_CHANNEL_15_BITFIELD)
#define	LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \| ADC_CHANNEL_16_SMP \| ADC_CHANNEL_16_BITFIELD)
#define	LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \| ADC_CHANNEL_17_SMP \| ADC_CHANNEL_17_BITFIELD)
#define	LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER \| ADC_CHANNEL_18_SMP \| ADC_CHANNEL_18_BITFIELD)
#define	LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 \| ADC_CHANNEL_ID_INTERNAL_CH)
#define	LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 \| ADC_CHANNEL_ID_INTERNAL_CH)
#define	LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 \| ADC_CHANNEL_ID_INTERNAL_CH)
#define	LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_17 \| ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_ID_INTERNAL_CH_2)
#define	LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_18 \| ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_ID_INTERNAL_CH_2)
#define	LL_ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_14 \| ADC_CHANNEL_ID_INTERNAL_CH)
#define	LL_ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_15 \| ADC_CHANNEL_ID_INTERNAL_CH)
#define	LL_ADC_REG_TRIG_SOFTWARE (0x00000000U)
#define	LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0)
#define	LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 )
#define	LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 \| ADC_CFGR_EXTEN_0)
#define	LL_ADC_REG_CONV_SINGLE (0x00000000U)
#define	LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT)
#define	LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U)
#define	LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN)
#define	LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG \| ADC_CFGR_DMAEN)
#define	LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000U)
#define	LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD)
#define	LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000U)
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 \| ADC_SQR1_L_0)
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_0)
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_1 )
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0)
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_0)
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_1 )
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0)
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 )
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_0)
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_1 )
#define	LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0)
#define	LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U)
#define	LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN)
#define	LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 \| ADC_CFGR_DISCEN)
#define	LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 \| ADC_CFGR_DISCEN)
#define	LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 \| ADC_CFGR_DISCNUM_0 \| ADC_CFGR_DISCEN)
#define	LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 \| ADC_CFGR_DISCEN)
#define	LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 \| ADC_CFGR_DISCNUM_0 \| ADC_CFGR_DISCEN)
#define	LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 \| ADC_CFGR_DISCNUM_1 \| ADC_CFGR_DISCEN)
#define	LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 \| ADC_CFGR_DISCNUM_1 \| ADC_CFGR_DISCNUM_0 \| ADC_CFGR_DISCEN)
#define	LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET \| ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
#define	LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET \| ADC_REG_RANK_16_SQRX_BITOFFSET_POS)
#define	LL_ADC_INJ_TRIG_SOFTWARE (0x00000000U)
#define	LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
#define	LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0)
#define	LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 )
#define	LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 \| ADC_JSQR_JEXTEN_0)
#define	LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000U)
#define	LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO)
#define	LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000U) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
#define	LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
#define	LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
#define	LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000U)
#define	LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
#define	LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
#define	LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 \| ADC_JSQR_JL_0)
#define	LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000U)
#define	LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN)
#define	LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET \| ADC_INJ_RANK_1_JSQR_BITOFFSET_POS)
#define	LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET \| ADC_INJ_RANK_2_JSQR_BITOFFSET_POS)
#define	LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET \| ADC_INJ_RANK_3_JSQR_BITOFFSET_POS)
#define	LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET \| ADC_INJ_RANK_4_JSQR_BITOFFSET_POS)
#define	LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000U)
#define	LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0)
#define	LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 )
#define	LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 \| ADC_SMPR2_SMP10_0)
#define	LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 )
#define	LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 \| ADC_SMPR2_SMP10_0)
#define	LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 \| ADC_SMPR2_SMP10_1 )
#define	LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 \| ADC_SMPR2_SMP10_1 \| ADC_SMPR2_SMP10_0)
#define	LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S)
#define	LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF \| ADC_CALFACT_CALFACT_D)
#define	LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED \| LL_ADC_DIFFERENTIAL_ENDED)
#define	LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR1_REGOFFSET)
#define	LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \| ADC_AWD_CR2_REGOFFSET)
#define	LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \| ADC_AWD_CR3_REGOFFSET)
#define	LL_ADC_AWD_DISABLE (0x00000000U)
#define	LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \| ADC_CFGR_AWD1EN )
#define	LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK \| ADC_CFGR_JAWD1EN )
#define	LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN )
#define	LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_DAC1CH1_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_DAC1CH2_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR_JAWD1EN \| ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL)
#define	LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 )
#define	LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1)
#define	LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 \| ADC_TR1_LT1)
#define	LL_ADC_OVS_DISABLE (0x00000000U)
#define	LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE)
#define	LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM \| ADC_CFGR2_ROVSE)
#define	LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE )
#define	LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE \| ADC_CFGR2_ROVSE)
#define	LL_ADC_OVS_REG_CONT (0x00000000U)
#define	LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS)
#define	LL_ADC_OVS_RATIO_2 (0x00000000U)
#define	LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0)
#define	LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 )
#define	LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 \| ADC_CFGR2_OVSR_0)
#define	LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 )
#define	LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 \| ADC_CFGR2_OVSR_0)
#define	LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 \| ADC_CFGR2_OVSR_1 )
#define	LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 \| ADC_CFGR2_OVSR_1 \| ADC_CFGR2_OVSR_0)
#define	LL_ADC_OVS_SHIFT_NONE (0x00000000U)
#define	LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0)
#define	LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 )
#define	LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 \| ADC_CFGR2_OVSS_0)
#define	LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 )
#define	LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 \| ADC_CFGR2_OVSS_0)
#define	LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 \| ADC_CFGR2_OVSS_1 )
#define	LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 \| ADC_CFGR2_OVSS_1 \| ADC_CFGR2_OVSS_0)
#define	LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 )
#define	LL_ADC_MULTI_INDEPENDENT (0x00000000U)
#define	LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 \| ADC_CCR_DUAL_1 )
#define	LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 \| ADC_CCR_DUAL_1 \| ADC_CCR_DUAL_0)
#define	LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 \| ADC_CCR_DUAL_0)
#define	LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 \| ADC_CCR_DUAL_0)
#define	LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0)
#define	LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 )
#define	LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 \| ADC_CCR_DUAL_0)
#define	LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000U)
#define	LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 )
#define	LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 \| ADC_CCR_MDMA_0)
#define	LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG \| ADC_CCR_MDMA_1 )
#define	LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG \| ADC_CCR_MDMA_1 \| ADC_CCR_MDMA_0)
#define	LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000U)
#define	LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0)
#define	LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 )
#define	LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0)
#define	LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 )
#define	LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0)
#define	LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 )
#define	LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0)
#define	LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 )
#define	LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_0)
#define	LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 )
#define	LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0)
#define	LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST)
#define	LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV )
#define	LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV \| ADC_CDR_RDATA_MST)
#define	LL_ADC_REG_TRIG_SW_START (LL_ADC_REG_TRIG_SOFTWARE)
#define	LL_ADC_REG_TRIG_EXT_TIM1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
#define	LL_ADC_REG_TRIG_EXT_TIM1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
#define	LL_ADC_REG_TRIG_EXT_TIM1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
#define	LL_ADC_REG_TRIG_EXT_TIM2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
#define	LL_ADC_REG_TRIG_EXT_TIM3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
#define	LL_ADC_REG_TRIG_EXT_TIM4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
#define	LL_ADC_INJ_TRIG_SW_START (LL_ADC_INJ_TRIG_SOFTWARE)
#define	LL_ADC_INJ_TRIG_EXT_TIM1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
#define	LL_ADC_INJ_TRIG_EXT_TIM2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
#define	LL_ADC_INJ_TRIG_EXT_TIM3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)
#define	LL_ADC_INJ_TRIG_EXT_TIM3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)
#define	LL_ADC_INJ_TRIG_EXT_TIM3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
#define	LL_ADC_INJ_TRIG_EXT_TIM8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)
#define	LL_ADC_OVS_DATA_SHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
#define	LL_ADC_OVS_DATA_SHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
#define	LL_ADC_OVS_DATA_SHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
#define	LL_ADC_OVS_DATA_SHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
#define	LL_ADC_OVS_DATA_SHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
#define	LL_ADC_OVS_DATA_SHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
#define	LL_ADC_OVS_DATA_SHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
#define	LL_ADC_OVS_DATA_SHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
#define	LL_ADC_OVS_DATA_SHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)
#define	LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10U)
#define	LL_ADC_DELAY_VREFINT_STAB_US ( 12U)
#define	LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 120U)
#define	LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4U)
#define	LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
	Write a value in ADC register.
#define	LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
	Read a value in ADC register.
#define	__LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)
	Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.
#define	__LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
	Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.
#define	__LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
	Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define	__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
	Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
#define	__LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
	Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define	__LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)
	Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.
#define	__LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
	Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define	__LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
	Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define	__LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW)
	Helper macro to get the ADC analog watchdog threshold high or low from raw value containing both thresholds concatenated.
#define	__LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) \| (__CALIB_FACTOR_SINGLE_ENDED__))
	Helper macro to set the ADC calibration value with both single ended and differential modes calibration factors concatenated.
#define	__LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
	Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.
#define	__LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC123_COMMON)
	Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define	__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)
	Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define	__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))
	Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define	__LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__)
	Helper macro to convert the ADC conversion data from a resolution to another resolution.
#define	__LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
	Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define	__LL_ADC_CALC_DATA_VOLTAGE() __LL_ADC_CALC_DATA_TO_VOLTAGE()
#define	__LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__, __ADC_RESOLUTION__)
	Helper macro to calculate analog reference voltage (Vref+) (unit: mVolt) from ADC conversion data of internal voltage reference VrefInt.
#define	__LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
	Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
#define	__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
	Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.
Functions
__STATIC_INLINE uint32_t	LL_ADC_DMA_GetRegAddr (ADC_TypeDef *ADCx, uint32_t Register)
	Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.
__STATIC_INLINE void	LL_ADC_SetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
	Set parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE uint32_t	LL_ADC_GetCommonClock (ADC_Common_TypeDef *ADCxy_COMMON)
	Get parameter common to several ADC: Clock source and prescaler.
__STATIC_INLINE void	LL_ADC_SetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
	Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE uint32_t	LL_ADC_GetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON)
	Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE void	LL_ADC_SetCalibrationFactor (ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
	Set ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t	LL_ADC_GetCalibrationFactor (ADC_TypeDef *ADCx, uint32_t SingleDiff)
	Get ADC calibration factor in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE void	LL_ADC_SetResolution (ADC_TypeDef *ADCx, uint32_t Resolution)
	Set ADC resolution.
__STATIC_INLINE uint32_t	LL_ADC_GetResolution (ADC_TypeDef *ADCx)
	Get ADC resolution.
__STATIC_INLINE void	LL_ADC_SetDataAlignment (ADC_TypeDef *ADCx, uint32_t DataAlignment)
	Set ADC conversion data alignment.
__STATIC_INLINE uint32_t	LL_ADC_GetDataAlignment (ADC_TypeDef *ADCx)
	Get ADC conversion data alignment.
__STATIC_INLINE void	LL_ADC_SetLowPowerMode (ADC_TypeDef *ADCx, uint32_t LowPowerMode)
	Set ADC low power mode.
__STATIC_INLINE uint32_t	LL_ADC_GetLowPowerMode (ADC_TypeDef *ADCx)
	Get ADC low power mode:
__STATIC_INLINE void	LL_ADC_SetOffset (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
	Set ADC selected offset number 1, 2, 3 or 4.
__STATIC_INLINE uint32_t	LL_ADC_GetOffsetChannel (ADC_TypeDef *ADCx, uint32_t Offsety)
	Get for the ADC selected offset number 1, 2, 3 or 4: Channel to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected)
__STATIC_INLINE uint32_t	LL_ADC_GetOffsetLevel (ADC_TypeDef *ADCx, uint32_t Offsety)
	Get for the ADC selected offset number 1, 2, 3 or 4: Offset level (offset to be subtracted from the raw converted data).
__STATIC_INLINE void	LL_ADC_SetOffsetState (ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
	Set for the ADC selected offset number 1, 2, 3 or 4: force offset state disable or enable without modifying offset channel or offset value.
__STATIC_INLINE uint32_t	LL_ADC_GetOffsetState (ADC_TypeDef *ADCx, uint32_t Offsety)
	Get for the ADC selected offset number 1, 2, 3 or 4: offset state disabled or enabled.
__STATIC_INLINE void	LL_ADC_REG_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
	Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t	LL_ADC_REG_GetTriggerSource (ADC_TypeDef *ADCx)
	Get ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t	LL_ADC_REG_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
	Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void	LL_ADC_REG_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
	Set ADC group regular conversion trigger polarity.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetTriggerEdge (ADC_TypeDef *ADCx)
	Get ADC group regular conversion trigger polarity.
__STATIC_INLINE void	LL_ADC_REG_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
	Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetSequencerLength (ADC_TypeDef *ADCx)
	Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void	LL_ADC_REG_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
	Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetSequencerDiscont (ADC_TypeDef *ADCx)
	Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void	LL_ADC_REG_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
	Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
	Get ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE void	LL_ADC_REG_SetContinuousMode (ADC_TypeDef *ADCx, uint32_t Continuous)
	Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetContinuousMode (ADC_TypeDef *ADCx)
	Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void	LL_ADC_REG_SetDMATransfer (ADC_TypeDef *ADCx, uint32_t DMATransfer)
	Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetDMATransfer (ADC_TypeDef *ADCx)
	Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE void	LL_ADC_REG_SetOverrun (ADC_TypeDef *ADCx, uint32_t Overrun)
	Set ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE uint32_t	LL_ADC_REG_GetOverrun (ADC_TypeDef *ADCx)
	Get ADC group regular behavior in case of overrun: data preserved or overwritten.
__STATIC_INLINE void	LL_ADC_INJ_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
	Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetTriggerSource (ADC_TypeDef *ADCx)
	Get ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t	LL_ADC_INJ_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
	Get ADC group injected conversion trigger source internal (SW start) or external.
__STATIC_INLINE void	LL_ADC_INJ_SetTriggerEdge (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
	Set ADC group injected conversion trigger polarity.
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetTriggerEdge (ADC_TypeDef *ADCx)
	Get ADC group injected conversion trigger polarity.
__STATIC_INLINE void	LL_ADC_INJ_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
	Set ADC group injected sequencer length and scan direction.
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetSequencerLength (ADC_TypeDef *ADCx)
	Get ADC group injected sequencer length and scan direction.
__STATIC_INLINE void	LL_ADC_INJ_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
	Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetSequencerDiscont (ADC_TypeDef *ADCx)
	Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void	LL_ADC_INJ_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
	Set ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
	Get ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE void	LL_ADC_INJ_SetTrigAuto (ADC_TypeDef *ADCx, uint32_t TrigAuto)
	Set ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetTrigAuto (ADC_TypeDef *ADCx)
	Get ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE void	LL_ADC_INJ_SetQueueMode (ADC_TypeDef *ADCx, uint32_t QueueMode)
	Set ADC group injected contexts queue mode.
__STATIC_INLINE uint32_t	LL_ADC_INJ_GetQueueMode (ADC_TypeDef *ADCx)
	Get ADC group injected context queue mode.
__STATIC_INLINE void	LL_ADC_INJ_ConfigQueueContext (ADC_TypeDef *ADCx, uint32_t TriggerSource, uint32_t ExternalTriggerEdge, uint32_t SequencerNbRanks, uint32_t Rank1_Channel, uint32_t Rank2_Channel, uint32_t Rank3_Channel, uint32_t Rank4_Channel)
	Set one context on ADC group injected that will be checked in contexts queue.
__STATIC_INLINE void	LL_ADC_SetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
	Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t	LL_ADC_GetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel)
	Get sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE void	LL_ADC_SetChannelSingleDiff (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
	Set mode single-ended or differential input of the selected ADC channel.
__STATIC_INLINE uint32_t	LL_ADC_GetChannelSingleDiff (ADC_TypeDef *ADCx, uint32_t Channel)
	Get mode single-ended or differential input of the selected ADC channel.
__STATIC_INLINE void	LL_ADC_SetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
	Set ADC analog watchdog monitored channels: a single channel, multiple channels or all channels, on ADC groups regular and-or injected.
__STATIC_INLINE uint32_t	LL_ADC_GetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDy)
	Get ADC analog watchdog monitored channel.
__STATIC_INLINE void	LL_ADC_ConfigAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
	Set ADC analog watchdog thresholds value of both thresholds high and low.
__STATIC_INLINE void	LL_ADC_SetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
	Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t	LL_ADC_GetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
	Get ADC analog watchdog threshold value of threshold high, threshold low or raw data with ADC thresholds high and low concatenated.
__STATIC_INLINE void	LL_ADC_SetOverSamplingScope (ADC_TypeDef *ADCx, uint32_t OvsScope)
	Set ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).
__STATIC_INLINE uint32_t	LL_ADC_GetOverSamplingScope (ADC_TypeDef *ADCx)
	Get ADC oversampling scope: ADC groups regular and-or injected (availability of ADC group injected depends on STM32 families).
__STATIC_INLINE void	LL_ADC_SetOverSamplingDiscont (ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
	Set ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE uint32_t	LL_ADC_GetOverSamplingDiscont (ADC_TypeDef *ADCx)
	Get ADC oversampling discontinuous mode (triggered mode) on the selected ADC group.
__STATIC_INLINE void	LL_ADC_ConfigOverSamplingRatioShift (ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
	Set ADC oversampling (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t	LL_ADC_GetOverSamplingRatio (ADC_TypeDef *ADCx)
	Get ADC oversampling ratio (impacting both ADC groups regular and injected)
__STATIC_INLINE uint32_t	LL_ADC_GetOverSamplingShift (ADC_TypeDef *ADCx)
	Get ADC oversampling shift (impacting both ADC groups regular and injected)
__STATIC_INLINE void	LL_ADC_SetMultimode (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
	Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE uint32_t	LL_ADC_GetMultimode (ADC_Common_TypeDef *ADCxy_COMMON)
	Get ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE void	LL_ADC_SetMultiDMATransfer (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
	Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
__STATIC_INLINE uint32_t	LL_ADC_GetMultiDMATransfer (ADC_Common_TypeDef *ADCxy_COMMON)
	Get ADC multimode conversion data transfer: no transfer or transfer by DMA.
__STATIC_INLINE void	LL_ADC_SetMultiTwoSamplingDelay (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
	Set ADC multimode delay between 2 sampling phases.
__STATIC_INLINE uint32_t	LL_ADC_GetMultiTwoSamplingDelay (ADC_Common_TypeDef *ADCxy_COMMON)
	Get ADC multimode delay between 2 sampling phases.
__STATIC_INLINE void	LL_ADC_REG_SetTrigSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
__STATIC_INLINE void	LL_ADC_INJ_SetTrigSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
__STATIC_INLINE void	LL_ADC_EnableDeepPowerDown (ADC_TypeDef *ADCx)
	Put ADC instance in deep power down state.
__STATIC_INLINE void	LL_ADC_DisableDeepPowerDown (ADC_TypeDef *ADCx)
	Disable ADC deep power down mode.
__STATIC_INLINE uint32_t	LL_ADC_IsDeepPowerDownEnabled (ADC_TypeDef *ADCx)
	Get the selected ADC instance deep power down state.
__STATIC_INLINE void	LL_ADC_EnableInternalRegulator (ADC_TypeDef *ADCx)
	Enable ADC instance internal voltage regulator.
__STATIC_INLINE void	LL_ADC_DisableInternalRegulator (ADC_TypeDef *ADCx)
	Disable ADC internal voltage regulator.
__STATIC_INLINE uint32_t	LL_ADC_IsInternalRegulatorEnabled (ADC_TypeDef *ADCx)
	Get the selected ADC instance internal voltage regulator state.
__STATIC_INLINE void	LL_ADC_Enable (ADC_TypeDef *ADCx)
	Enable the selected ADC instance.
__STATIC_INLINE void	LL_ADC_Disable (ADC_TypeDef *ADCx)
	Disable the selected ADC instance.
__STATIC_INLINE uint32_t	LL_ADC_IsEnabled (ADC_TypeDef *ADCx)
	Get the selected ADC instance enable state.
__STATIC_INLINE uint32_t	LL_ADC_IsDisableOngoing (ADC_TypeDef *ADCx)
	Get the selected ADC instance disable state.
__STATIC_INLINE void	LL_ADC_StartCalibration (ADC_TypeDef *ADCx, uint32_t SingleDiff)
	Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t	LL_ADC_IsCalibrationOnGoing (ADC_TypeDef *ADCx)
	Get ADC calibration state.
__STATIC_INLINE void	LL_ADC_REG_StartConversion (ADC_TypeDef *ADCx)
	Start ADC group regular conversion.
__STATIC_INLINE void	LL_ADC_REG_StopConversion (ADC_TypeDef *ADCx)
	Stop ADC group regular conversion.
__STATIC_INLINE uint32_t	LL_ADC_REG_IsConversionOngoing (ADC_TypeDef *ADCx)
	Get ADC group regular conversion state.
__STATIC_INLINE uint32_t	LL_ADC_REG_IsStopConversionOngoing (ADC_TypeDef *ADCx)
	Get ADC group regular command of conversion stop state.
__STATIC_INLINE uint32_t	LL_ADC_REG_ReadConversionData32 (ADC_TypeDef *ADCx)
	Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t	LL_ADC_REG_ReadConversionData12 (ADC_TypeDef *ADCx)
	Get ADC group regular conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t	LL_ADC_REG_ReadConversionData10 (ADC_TypeDef *ADCx)
	Get ADC group regular conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t	LL_ADC_REG_ReadConversionData8 (ADC_TypeDef *ADCx)
	Get ADC group regular conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t	LL_ADC_REG_ReadConversionData6 (ADC_TypeDef *ADCx)
	Get ADC group regular conversion data, range fit for ADC resolution 6 bits.
__STATIC_INLINE uint32_t	LL_ADC_REG_ReadMultiConversionData32 (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
	Get ADC multimode conversion data of ADC master, ADC slave or raw data with ADC master and slave concatenated.
__STATIC_INLINE void	LL_ADC_INJ_StartConversion (ADC_TypeDef *ADCx)
	Start ADC group injected conversion.
__STATIC_INLINE void	LL_ADC_INJ_StopConversion (ADC_TypeDef *ADCx)
	Stop ADC group injected conversion.
__STATIC_INLINE uint32_t	LL_ADC_INJ_IsConversionOngoing (ADC_TypeDef *ADCx)
	Get ADC group injected conversion state.
__STATIC_INLINE uint32_t	LL_ADC_INJ_IsStopConversionOngoing (ADC_TypeDef *ADCx)
	Get ADC group injected command of conversion stop state.
__STATIC_INLINE uint32_t	LL_ADC_INJ_ReadConversionData32 (ADC_TypeDef *ADCx, uint32_t Rank)
	Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t	LL_ADC_INJ_ReadConversionData12 (ADC_TypeDef *ADCx, uint32_t Rank)
	Get ADC group injected conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint16_t	LL_ADC_INJ_ReadConversionData10 (ADC_TypeDef *ADCx, uint32_t Rank)
	Get ADC group injected conversion data, range fit for ADC resolution 10 bits.
__STATIC_INLINE uint8_t	LL_ADC_INJ_ReadConversionData8 (ADC_TypeDef *ADCx, uint32_t Rank)
	Get ADC group injected conversion data, range fit for ADC resolution 8 bits.
__STATIC_INLINE uint8_t	LL_ADC_INJ_ReadConversionData6 (ADC_TypeDef *ADCx, uint32_t Rank)
	Get ADC group injected conversion data, range fit for ADC resolution 6 bits.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_ADRDY (ADC_TypeDef *ADCx)
	Get flag ADC ready.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_EOC (ADC_TypeDef *ADCx)
	Get flag ADC group regular end of unitary conversion.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_EOS (ADC_TypeDef *ADCx)
	Get flag ADC group regular end of sequence conversions.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_OVR (ADC_TypeDef *ADCx)
	Get flag ADC group regular overrun.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_EOSMP (ADC_TypeDef *ADCx)
	Get flag ADC group regular end of sampling phase.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_JEOC (ADC_TypeDef *ADCx)
	Get flag ADC group injected end of unitary conversion.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_JEOS (ADC_TypeDef *ADCx)
	Get flag ADC group injected end of sequence conversions.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_JQOVF (ADC_TypeDef *ADCx)
	Get flag ADC group injected contexts queue overflow.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_AWD1 (ADC_TypeDef *ADCx)
	Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_AWD2 (ADC_TypeDef *ADCx)
	Get flag ADC analog watchdog 2.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_AWD3 (ADC_TypeDef *ADCx)
	Get flag ADC analog watchdog 3.
__STATIC_INLINE void	LL_ADC_ClearFlag_ADRDY (ADC_TypeDef *ADCx)
	Clear flag ADC ready.
__STATIC_INLINE void	LL_ADC_ClearFlag_EOC (ADC_TypeDef *ADCx)
	Clear flag ADC group regular end of unitary conversion.
__STATIC_INLINE void	LL_ADC_ClearFlag_EOS (ADC_TypeDef *ADCx)
	Clear flag ADC group regular end of sequence conversions.
__STATIC_INLINE void	LL_ADC_ClearFlag_OVR (ADC_TypeDef *ADCx)
	Clear flag ADC group regular overrun.
__STATIC_INLINE void	LL_ADC_ClearFlag_EOSMP (ADC_TypeDef *ADCx)
	Clear flag ADC group regular end of sampling phase.
__STATIC_INLINE void	LL_ADC_ClearFlag_JEOC (ADC_TypeDef *ADCx)
	Clear flag ADC group injected end of unitary conversion.
__STATIC_INLINE void	LL_ADC_ClearFlag_JEOS (ADC_TypeDef *ADCx)
	Clear flag ADC group injected end of sequence conversions.
__STATIC_INLINE void	LL_ADC_ClearFlag_JQOVF (ADC_TypeDef *ADCx)
	Clear flag ADC group injected contexts queue overflow.
__STATIC_INLINE void	LL_ADC_ClearFlag_AWD1 (ADC_TypeDef *ADCx)
	Clear flag ADC analog watchdog 1.
__STATIC_INLINE void	LL_ADC_ClearFlag_AWD2 (ADC_TypeDef *ADCx)
	Clear flag ADC analog watchdog 2.
__STATIC_INLINE void	LL_ADC_ClearFlag_AWD3 (ADC_TypeDef *ADCx)
	Clear flag ADC analog watchdog 3.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_MST_ADRDY (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC ready of the ADC master.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV_ADRDY (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC ready of the ADC slave.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_MST_EOC (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group regular end of unitary conversion of the ADC master.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV_EOC (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_MST_EOS (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group regular end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV_EOS (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_MST_OVR (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group regular overrun of the ADC master.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV_OVR (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group regular overrun of the ADC slave.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_MST_EOSMP (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group regular end of sampling of the ADC master.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV_EOSMP (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group regular end of sampling of the ADC slave.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_MST_JEOC (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group injected end of unitary conversion of the ADC master.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV_JEOC (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_MST_JEOS (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group injected end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV_JEOS (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_MST_JQOVF (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group injected context queue overflow of the ADC master.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV_JQOVF (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC group injected context queue overflow of the ADC slave.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_MST_AWD1 (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC analog watchdog 1 of the ADC master.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV_AWD1 (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode analog watchdog 1 of the ADC slave.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_MST_AWD2 (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC analog watchdog 2 of the ADC master.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV_AWD2 (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC analog watchdog 2 of the ADC slave.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_MST_AWD3 (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC analog watchdog 3 of the ADC master.
__STATIC_INLINE uint32_t	LL_ADC_IsActiveFlag_SLV_AWD3 (ADC_Common_TypeDef *ADCxy_COMMON)
	Get flag multimode ADC analog watchdog 3 of the ADC slave.
__STATIC_INLINE void	LL_ADC_EnableIT_ADRDY (ADC_TypeDef *ADCx)
	Enable ADC ready.
__STATIC_INLINE void	LL_ADC_EnableIT_EOC (ADC_TypeDef *ADCx)
	Enable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void	LL_ADC_EnableIT_EOS (ADC_TypeDef *ADCx)
	Enable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void	LL_ADC_EnableIT_OVR (ADC_TypeDef *ADCx)
	Enable ADC group regular interruption overrun.
__STATIC_INLINE void	LL_ADC_EnableIT_EOSMP (ADC_TypeDef *ADCx)
	Enable interruption ADC group regular end of sampling.
__STATIC_INLINE void	LL_ADC_EnableIT_JEOC (ADC_TypeDef *ADCx)
	Enable interruption ADC group injected end of unitary conversion.
__STATIC_INLINE void	LL_ADC_EnableIT_JEOS (ADC_TypeDef *ADCx)
	Enable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void	LL_ADC_EnableIT_JQOVF (ADC_TypeDef *ADCx)
	Enable interruption ADC group injected context queue overflow.
__STATIC_INLINE void	LL_ADC_EnableIT_AWD1 (ADC_TypeDef *ADCx)
	Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void	LL_ADC_EnableIT_AWD2 (ADC_TypeDef *ADCx)
	Enable interruption ADC analog watchdog 2.
__STATIC_INLINE void	LL_ADC_EnableIT_AWD3 (ADC_TypeDef *ADCx)
	Enable interruption ADC analog watchdog 3.
__STATIC_INLINE void	LL_ADC_DisableIT_ADRDY (ADC_TypeDef *ADCx)
	Disable interruption ADC ready.
__STATIC_INLINE void	LL_ADC_DisableIT_EOC (ADC_TypeDef *ADCx)
	Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void	LL_ADC_DisableIT_EOS (ADC_TypeDef *ADCx)
	Disable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void	LL_ADC_DisableIT_OVR (ADC_TypeDef *ADCx)
	Disable interruption ADC group regular overrun.
__STATIC_INLINE void	LL_ADC_DisableIT_EOSMP (ADC_TypeDef *ADCx)
	Disable interruption ADC group regular end of sampling.
__STATIC_INLINE void	LL_ADC_DisableIT_JEOC (ADC_TypeDef *ADCx)
	Disable interruption ADC group regular end of unitary conversion.
__STATIC_INLINE void	LL_ADC_DisableIT_JEOS (ADC_TypeDef *ADCx)
	Disable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void	LL_ADC_DisableIT_JQOVF (ADC_TypeDef *ADCx)
	Disable interruption ADC group injected context queue overflow.
__STATIC_INLINE void	LL_ADC_DisableIT_AWD1 (ADC_TypeDef *ADCx)
	Disable interruption ADC analog watchdog 1.
__STATIC_INLINE void	LL_ADC_DisableIT_AWD2 (ADC_TypeDef *ADCx)
	Disable interruption ADC analog watchdog 2.
__STATIC_INLINE void	LL_ADC_DisableIT_AWD3 (ADC_TypeDef *ADCx)
	Disable interruption ADC analog watchdog 3.
__STATIC_INLINE uint32_t	LL_ADC_IsEnabledIT_ADRDY (ADC_TypeDef *ADCx)
	Get state of interruption ADC ready (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t	LL_ADC_IsEnabledIT_EOC (ADC_TypeDef *ADCx)
	Get state of interruption ADC group regular end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t	LL_ADC_IsEnabledIT_EOS (ADC_TypeDef *ADCx)
	Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t	LL_ADC_IsEnabledIT_OVR (ADC_TypeDef *ADCx)
	Get state of interruption ADC group regular overrun (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t	LL_ADC_IsEnabledIT_EOSMP (ADC_TypeDef *ADCx)
	Get state of interruption ADC group regular end of sampling (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t	LL_ADC_IsEnabledIT_JEOC (ADC_TypeDef *ADCx)
	Get state of interruption ADC group injected end of unitary conversion (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t	LL_ADC_IsEnabledIT_JEOS (ADC_TypeDef *ADCx)
	Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t	LL_ADC_IsEnabledIT_JQOVF (ADC_TypeDef *ADCx)
	Get state of interruption ADC group injected context queue overflow interrupt state (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t	LL_ADC_IsEnabledIT_AWD1 (ADC_TypeDef *ADCx)
	Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t	LL_ADC_IsEnabledIT_AWD2 (ADC_TypeDef *ADCx)
	Get state of interruption Get ADC analog watchdog 2 (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t	LL_ADC_IsEnabledIT_AWD3 (ADC_TypeDef *ADCx)
	Get state of interruption Get ADC analog watchdog 3 (0: interrupt disabled, 1: interrupt enabled).
ErrorStatus	LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
	De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus	LL_ADC_CommonInit (ADC_Common_TypeDef ADCxy_COMMON, LL_ADC_CommonInitTypeDef ADC_CommonInitStruct)
	Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void	LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
	Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus	LL_ADC_DeInit (ADC_TypeDef *ADCx)
	De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus	LL_ADC_Init (ADC_TypeDef ADCx, LL_ADC_InitTypeDef ADC_InitStruct)
	Initialize some features of ADC instance.
void	LL_ADC_StructInit (LL_ADC_InitTypeDef *ADC_InitStruct)
	Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus	LL_ADC_REG_Init (ADC_TypeDef ADCx, LL_ADC_REG_InitTypeDef ADC_REG_InitStruct)
	Initialize some features of ADC group regular.
void	LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
	Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus	LL_ADC_INJ_Init (ADC_TypeDef ADCx, LL_ADC_INJ_InitTypeDef ADC_INJ_InitStruct)
	Initialize some features of ADC group injected.
void	LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
	Set each LL_ADC_INJ_InitTypeDef field to default value.

Detailed Description

Header file of ADC LL module.

Author:: MCD Application Team

Attention:

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32l4xx_ll_adc.h.

Data Structures

Defines

Functions

Detailed Description

© COPYRIGHT(c) 2017 STMicroelectronics