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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_tsc.h 00004 * @author MCD Application Team 00005 * @brief Header file of TSC HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_HAL_TSC_H 00038 #define __STM32L4xx_HAL_TSC_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx_hal_def.h" 00046 00047 /** @addtogroup STM32L4xx_HAL_Driver 00048 * @{ 00049 */ 00050 00051 /** @addtogroup TSC 00052 * @{ 00053 */ 00054 00055 /* Exported types ------------------------------------------------------------*/ 00056 /** @defgroup TSC_Exported_Types TSC Exported Types 00057 * @{ 00058 */ 00059 00060 /** 00061 * @brief TSC state structure definition 00062 */ 00063 typedef enum 00064 { 00065 HAL_TSC_STATE_RESET = 0x00U, /*!< TSC registers have their reset value */ 00066 HAL_TSC_STATE_READY = 0x01U, /*!< TSC registers are initialized or acquisition is completed with success */ 00067 HAL_TSC_STATE_BUSY = 0x02U, /*!< TSC initialization or acquisition is on-going */ 00068 HAL_TSC_STATE_ERROR = 0x03U /*!< Acquisition is completed with max count error */ 00069 } HAL_TSC_StateTypeDef; 00070 00071 /** 00072 * @brief TSC group status structure definition 00073 */ 00074 typedef enum 00075 { 00076 TSC_GROUP_ONGOING = 0x00U, /*!< Acquisition on group is on-going or not started */ 00077 TSC_GROUP_COMPLETED = 0x01U /*!< Acquisition on group is completed with success (no max count error) */ 00078 } TSC_GroupStatusTypeDef; 00079 00080 /** 00081 * @brief TSC init structure definition 00082 */ 00083 typedef struct 00084 { 00085 uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length 00086 This parameter can be a value of @ref TSC_CTPulseHL_Config */ 00087 uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length 00088 This parameter can be a value of @ref TSC_CTPulseLL_Config */ 00089 uint32_t SpreadSpectrum; /*!< Spread spectrum activation 00090 This parameter can be a value of @ref TSC_CTPulseLL_Config */ 00091 uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation 00092 This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ 00093 uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler 00094 This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */ 00095 uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler 00096 This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */ 00097 uint32_t MaxCountValue; /*!< Max count value 00098 This parameter can be a value of @ref TSC_MaxCount_Value */ 00099 uint32_t IODefaultMode; /*!< IO default mode 00100 This parameter can be a value of @ref TSC_IO_Default_Mode */ 00101 uint32_t SynchroPinPolarity; /*!< Synchro pin polarity 00102 This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */ 00103 uint32_t AcquisitionMode; /*!< Acquisition mode 00104 This parameter can be a value of @ref TSC_Acquisition_Mode */ 00105 uint32_t MaxCountInterrupt; /*!< Max count interrupt activation 00106 This parameter can be set to ENABLE or DISABLE. */ 00107 uint32_t ChannelIOs; /*!< Channel IOs mask */ 00108 uint32_t ShieldIOs; /*!< Shield IOs mask */ 00109 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 00110 } TSC_InitTypeDef; 00111 00112 /** 00113 * @brief TSC IOs configuration structure definition 00114 */ 00115 typedef struct 00116 { 00117 uint32_t ChannelIOs; /*!< Channel IOs mask */ 00118 uint32_t ShieldIOs; /*!< Shield IOs mask */ 00119 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 00120 } TSC_IOConfigTypeDef; 00121 00122 /** 00123 * @brief TSC handle Structure definition 00124 */ 00125 typedef struct __TSC_HandleTypeDef 00126 { 00127 TSC_TypeDef *Instance; /*!< Register base address */ 00128 TSC_InitTypeDef Init; /*!< Initialization parameters */ 00129 __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ 00130 HAL_LockTypeDef Lock; /*!< Lock feature */ 00131 __IO uint32_t ErrorCode; /*!< I2C Error code */ 00132 00133 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 00134 void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */ 00135 void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */ 00136 00137 void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */ 00138 void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */ 00139 00140 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 00141 } TSC_HandleTypeDef; 00142 00143 /** 00144 * @brief TSC Group Index Structure definition 00145 */ 00146 typedef enum 00147 { 00148 TSC_GROUP1_IDX = 0x00U, 00149 TSC_GROUP2_IDX, 00150 TSC_GROUP3_IDX, 00151 TSC_GROUP4_IDX, 00152 #if defined(TSC_IOCCR_G5_IO1) 00153 TSC_GROUP5_IDX, 00154 #endif 00155 #if defined(TSC_IOCCR_G6_IO1) 00156 TSC_GROUP6_IDX, 00157 #endif 00158 #if defined(TSC_IOCCR_G7_IO1) 00159 TSC_GROUP7_IDX, 00160 #endif 00161 #if defined(TSC_IOCCR_G8_IO1) 00162 TSC_GROUP8_IDX, 00163 #endif 00164 TSC_NB_OF_GROUPS 00165 }TSC_GroupIndexTypeDef; 00166 00167 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 00168 /** 00169 * @brief HAL TSC Callback ID enumeration definition 00170 */ 00171 typedef enum 00172 { 00173 HAL_TSC_CONV_COMPLETE_CB_ID = 0x00U, /*!< TSC Conversion completed callback ID */ 00174 HAL_TSC_ERROR_CB_ID = 0x01U, /*!< TSC Error callback ID */ 00175 00176 HAL_TSC_MSPINIT_CB_ID = 0x02U, /*!< TSC Msp Init callback ID */ 00177 HAL_TSC_MSPDEINIT_CB_ID = 0x03U /*!< TSC Msp DeInit callback ID */ 00178 00179 } HAL_TSC_CallbackIDTypeDef; 00180 00181 /** 00182 * @brief HAL TSC Callback pointer definition 00183 */ 00184 typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */ 00185 00186 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 00187 00188 /** 00189 * @} 00190 */ 00191 00192 /* Exported constants --------------------------------------------------------*/ 00193 /** @defgroup TSC_Exported_Constants TSC Exported Constants 00194 * @{ 00195 */ 00196 00197 /** @defgroup TSC_Error_Code_definition TSC Error Code definition 00198 * @brief TSC Error Code definition 00199 * @{ 00200 */ 00201 #define HAL_TSC_ERROR_NONE 0x00000000U /*!< No error */ 00202 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 00203 #define HAL_TSC_ERROR_INVALID_CALLBACK (0x00000001U) /*!< Invalid Callback error */ 00204 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 00205 /** 00206 * @} 00207 */ 00208 00209 /** @defgroup TSC_CTPulseHL_Config CTPulse High Length 00210 * @{ 00211 */ 00212 #define TSC_CTPH_1CYCLE 0x00000000U /*!< Charge transfer pulse high during 1 cycle (PGCLK) */ 00213 #define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */ 00214 #define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */ 00215 #define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 4 cycles (PGCLK) */ 00216 #define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */ 00217 #define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 6 cycles (PGCLK) */ 00218 #define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 7 cycles (PGCLK) */ 00219 #define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 8 cycles (PGCLK) */ 00220 #define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */ 00221 #define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 10 cycles (PGCLK) */ 00222 #define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 11 cycles (PGCLK) */ 00223 #define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 12 cycles (PGCLK) */ 00224 #define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) /*!< Charge transfer pulse high during 13 cycles (PGCLK) */ 00225 #define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 14 cycles (PGCLK) */ 00226 #define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 15 cycles (PGCLK) */ 00227 #define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */ 00228 /** 00229 * @} 00230 */ 00231 00232 /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length 00233 * @{ 00234 */ 00235 #define TSC_CTPL_1CYCLE 0x00000000U /*!< Charge transfer pulse low during 1 cycle (PGCLK) */ 00236 #define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */ 00237 #define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */ 00238 #define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 4 cycles (PGCLK) */ 00239 #define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */ 00240 #define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 6 cycles (PGCLK) */ 00241 #define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 7 cycles (PGCLK) */ 00242 #define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 8 cycles (PGCLK) */ 00243 #define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */ 00244 #define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 10 cycles (PGCLK) */ 00245 #define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 11 cycles (PGCLK) */ 00246 #define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 12 cycles (PGCLK) */ 00247 #define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) /*!< Charge transfer pulse low during 13 cycles (PGCLK) */ 00248 #define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 14 cycles (PGCLK) */ 00249 #define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 15 cycles (PGCLK) */ 00250 #define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 16 cycles (PGCLK) */ 00251 /** 00252 * @} 00253 */ 00254 00255 /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler 00256 * @{ 00257 */ 00258 #define TSC_SS_PRESC_DIV1 0x00000000U /*!< Spread Spectrum Prescaler Div1 */ 00259 #define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */ 00260 /** 00261 * @} 00262 */ 00263 00264 /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler 00265 * @{ 00266 */ 00267 #define TSC_PG_PRESC_DIV1 0x00000000U /*!< Pulse Generator HCLK Div1 */ 00268 #define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */ 00269 #define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */ 00270 #define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */ 00271 #define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */ 00272 #define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */ 00273 #define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */ 00274 #define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */ 00275 /** 00276 * @} 00277 */ 00278 00279 /** @defgroup TSC_MaxCount_Value Max Count Value 00280 * @{ 00281 */ 00282 #define TSC_MCV_255 0x00000000U /*!< 255 maximum number of charge transfer pulses */ 00283 #define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */ 00284 #define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */ 00285 #define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */ 00286 #define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */ 00287 #define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */ 00288 #define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */ 00289 /** 00290 * @} 00291 */ 00292 00293 /** @defgroup TSC_IO_Default_Mode IO Default Mode 00294 * @{ 00295 */ 00296 #define TSC_IODEF_OUT_PP_LOW 0x00000000U /*!< I/Os are forced to output push-pull low */ 00297 #define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */ 00298 /** 00299 * @} 00300 */ 00301 00302 /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity 00303 * @{ 00304 */ 00305 #define TSC_SYNC_POLARITY_FALLING 0x00000000U /*!< Falling edge only */ 00306 #define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */ 00307 /** 00308 * @} 00309 */ 00310 00311 /** @defgroup TSC_Acquisition_Mode Acquisition Mode 00312 * @{ 00313 */ 00314 #define TSC_ACQ_MODE_NORMAL 0x00000000U /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ 00315 #define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */ 00316 /** 00317 * @} 00318 */ 00319 00320 /** @defgroup TSC_interrupts_definition Interrupts definition 00321 * @{ 00322 */ 00323 #define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */ 00324 #define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */ 00325 /** 00326 * @} 00327 */ 00328 00329 /** @defgroup TSC_flags_definition Flags definition 00330 * @{ 00331 */ 00332 #define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */ 00333 #define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */ 00334 /** 00335 * @} 00336 */ 00337 00338 /** @defgroup TSC_Group_definition Group definition 00339 * @{ 00340 */ 00341 #define TSC_GROUP1 (uint32_t)(0x1U << TSC_GROUP1_IDX) 00342 #define TSC_GROUP2 (uint32_t)(0x1U << TSC_GROUP2_IDX) 00343 #define TSC_GROUP3 (uint32_t)(0x1U << TSC_GROUP3_IDX) 00344 #define TSC_GROUP4 (uint32_t)(0x1U << TSC_GROUP4_IDX) 00345 #if defined(TSC_IOCCR_G5_IO1) 00346 #define TSC_GROUP5 (uint32_t)(0x1U << TSC_GROUP5_IDX) 00347 #endif 00348 #if defined(TSC_IOCCR_G6_IO1) 00349 #define TSC_GROUP6 (uint32_t)(0x1U << TSC_GROUP6_IDX) 00350 #endif 00351 #if defined(TSC_IOCCR_G7_IO1) 00352 #define TSC_GROUP7 (uint32_t)(0x1U << TSC_GROUP7_IDX) 00353 #endif 00354 #if defined(TSC_IOCCR_G8_IO1) 00355 #define TSC_GROUP8 (uint32_t)(0x1U << TSC_GROUP8_IDX) 00356 #endif 00357 00358 #define TSC_GROUPX_NOT_SUPPORTED 0xFF000000U /*!< TSC GroupX not supported */ 00359 00360 #define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ 00361 #define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ 00362 #define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */ 00363 #define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */ 00364 00365 #define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */ 00366 #define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */ 00367 #define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */ 00368 #define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */ 00369 00370 #define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */ 00371 #define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */ 00372 #define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */ 00373 #define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */ 00374 00375 #define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */ 00376 #define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */ 00377 #define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */ 00378 #define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */ 00379 #if defined(TSC_IOCCR_G5_IO1) 00380 00381 #define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */ 00382 #define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */ 00383 #define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */ 00384 #define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */ 00385 #else 00386 00387 #define TSC_GROUP5_IO1 (uint32_t)(0x00000010U | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group5 IO1 not supported */ 00388 #define TSC_GROUP5_IO2 TSC_GROUP5_IO1 /*!< TSC Group5 IO2 not supported */ 00389 #define TSC_GROUP5_IO3 TSC_GROUP5_IO1 /*!< TSC Group5 IO3 not supported */ 00390 #define TSC_GROUP5_IO4 TSC_GROUP5_IO1 /*!< TSC Group5 IO4 not supported */ 00391 #endif 00392 #if defined(TSC_IOCCR_G6_IO1) 00393 00394 #define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ 00395 #define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ 00396 #define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */ 00397 #define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */ 00398 #else 00399 00400 #define TSC_GROUP6_IO1 (uint32_t)(0x00000020U | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group6 IO1 not supported */ 00401 #define TSC_GROUP6_IO2 TSC_GROUP6_IO1 /*!< TSC Group6 IO2 not supported */ 00402 #define TSC_GROUP6_IO3 TSC_GROUP6_IO1 /*!< TSC Group6 IO3 not supported */ 00403 #define TSC_GROUP6_IO4 TSC_GROUP6_IO1 /*!< TSC Group6 IO4 not supported */ 00404 #endif 00405 #if defined(TSC_IOCCR_G7_IO1) 00406 00407 #define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */ 00408 #define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */ 00409 #define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */ 00410 #define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */ 00411 #else 00412 00413 #define TSC_GROUP7_IO1 (uint32_t)(0x00000040U | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group7 IO1 not supported */ 00414 #define TSC_GROUP7_IO2 TSC_GROUP7_IO1 /*!< TSC Group7 IO2 not supported */ 00415 #define TSC_GROUP7_IO3 TSC_GROUP7_IO1 /*!< TSC Group7 IO3 not supported */ 00416 #define TSC_GROUP7_IO4 TSC_GROUP7_IO1 /*!< TSC Group7 IO4 not supported */ 00417 #endif 00418 #if defined(TSC_IOCCR_G8_IO1) 00419 00420 #define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */ 00421 #define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */ 00422 #define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */ 00423 #define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */ 00424 #else 00425 00426 #define TSC_GROUP8_IO1 (uint32_t)(0x00000080U | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group8 IO1 not supported */ 00427 #define TSC_GROUP8_IO2 TSC_GROUP8_IO1 /*!< TSC Group8 IO2 not supported */ 00428 #define TSC_GROUP8_IO3 TSC_GROUP8_IO1 /*!< TSC Group8 IO3 not supported */ 00429 #define TSC_GROUP8_IO4 TSC_GROUP8_IO1 /*!< TSC Group8 IO4 not supported */ 00430 #endif 00431 /** 00432 * @} 00433 */ 00434 00435 /** 00436 * @} 00437 */ 00438 00439 /* Exported macros -----------------------------------------------------------*/ 00440 00441 /** @defgroup TSC_Exported_Macros TSC Exported Macros 00442 * @{ 00443 */ 00444 00445 /** @brief Reset TSC handle state. 00446 * @param __HANDLE__ TSC handle 00447 * @retval None 00448 */ 00449 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 00450 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00451 (__HANDLE__)->State = HAL_TSC_STATE_RESET; \ 00452 (__HANDLE__)->MspInitCallback = NULL; \ 00453 (__HANDLE__)->MspDeInitCallback = NULL; \ 00454 } while(0) 00455 #else 00456 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) 00457 #endif 00458 00459 /** 00460 * @brief Enable the TSC peripheral. 00461 * @param __HANDLE__ TSC handle 00462 * @retval None 00463 */ 00464 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) 00465 00466 /** 00467 * @brief Disable the TSC peripheral. 00468 * @param __HANDLE__ TSC handle 00469 * @retval None 00470 */ 00471 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE)) 00472 00473 /** 00474 * @brief Start acquisition. 00475 * @param __HANDLE__ TSC handle 00476 * @retval None 00477 */ 00478 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) 00479 00480 /** 00481 * @brief Stop acquisition. 00482 * @param __HANDLE__ TSC handle 00483 * @retval None 00484 */ 00485 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START)) 00486 00487 /** 00488 * @brief Set IO default mode to output push-pull low. 00489 * @param __HANDLE__ TSC handle 00490 * @retval None 00491 */ 00492 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF)) 00493 00494 /** 00495 * @brief Set IO default mode to input floating. 00496 * @param __HANDLE__ TSC handle 00497 * @retval None 00498 */ 00499 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) 00500 00501 /** 00502 * @brief Set synchronization polarity to falling edge. 00503 * @param __HANDLE__ TSC handle 00504 * @retval None 00505 */ 00506 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL)) 00507 00508 /** 00509 * @brief Set synchronization polarity to rising edge and high level. 00510 * @param __HANDLE__ TSC handle 00511 * @retval None 00512 */ 00513 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) 00514 00515 /** 00516 * @brief Enable TSC interrupt. 00517 * @param __HANDLE__ TSC handle 00518 * @param __INTERRUPT__ TSC interrupt 00519 * @retval None 00520 */ 00521 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 00522 00523 /** 00524 * @brief Disable TSC interrupt. 00525 * @param __HANDLE__ TSC handle 00526 * @param __INTERRUPT__ TSC interrupt 00527 * @retval None 00528 */ 00529 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__))) 00530 00531 /** @brief Check whether the specified TSC interrupt source is enabled or not. 00532 * @param __HANDLE__ TSC Handle 00533 * @param __INTERRUPT__ TSC interrupt 00534 * @retval SET or RESET 00535 */ 00536 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 00537 00538 /** 00539 * @brief Check whether the specified TSC flag is set or not. 00540 * @param __HANDLE__ TSC handle 00541 * @param __FLAG__ TSC flag 00542 * @retval SET or RESET 00543 */ 00544 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 00545 00546 /** 00547 * @brief Clear the TSC's pending flag. 00548 * @param __HANDLE__ TSC handle 00549 * @param __FLAG__ TSC flag 00550 * @retval None 00551 */ 00552 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 00553 00554 /** 00555 * @brief Enable schmitt trigger hysteresis on a group of IOs. 00556 * @param __HANDLE__ TSC handle 00557 * @param __GX_IOY_MASK__ IOs mask 00558 * @retval None 00559 */ 00560 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) 00561 00562 /** 00563 * @brief Disable schmitt trigger hysteresis on a group of IOs. 00564 * @param __HANDLE__ TSC handle 00565 * @param __GX_IOY_MASK__ IOs mask 00566 * @retval None 00567 */ 00568 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__))) 00569 00570 /** 00571 * @brief Open analog switch on a group of IOs. 00572 * @param __HANDLE__ TSC handle 00573 * @param __GX_IOY_MASK__ IOs mask 00574 * @retval None 00575 */ 00576 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__))) 00577 00578 /** 00579 * @brief Close analog switch on a group of IOs. 00580 * @param __HANDLE__ TSC handle 00581 * @param __GX_IOY_MASK__ IOs mask 00582 * @retval None 00583 */ 00584 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) 00585 00586 /** 00587 * @brief Enable a group of IOs in channel mode. 00588 * @param __HANDLE__ TSC handle 00589 * @param __GX_IOY_MASK__ IOs mask 00590 * @retval None 00591 */ 00592 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) 00593 00594 /** 00595 * @brief Disable a group of channel IOs. 00596 * @param __HANDLE__ TSC handle 00597 * @param __GX_IOY_MASK__ IOs mask 00598 * @retval None 00599 */ 00600 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__))) 00601 00602 /** 00603 * @brief Enable a group of IOs in sampling mode. 00604 * @param __HANDLE__ TSC handle 00605 * @param __GX_IOY_MASK__ IOs mask 00606 * @retval None 00607 */ 00608 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) 00609 00610 /** 00611 * @brief Disable a group of sampling IOs. 00612 * @param __HANDLE__ TSC handle 00613 * @param __GX_IOY_MASK__ IOs mask 00614 * @retval None 00615 */ 00616 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__))) 00617 00618 /** 00619 * @brief Enable acquisition groups. 00620 * @param __HANDLE__ TSC handle 00621 * @param __GX_MASK__ Groups mask 00622 * @retval None 00623 */ 00624 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) 00625 00626 /** 00627 * @brief Disable acquisition groups. 00628 * @param __HANDLE__ TSC handle 00629 * @param __GX_MASK__ Groups mask 00630 * @retval None 00631 */ 00632 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__))) 00633 00634 /** @brief Gets acquisition group status. 00635 * @param __HANDLE__ TSC Handle 00636 * @param __GX_INDEX__ Group index 00637 * @retval SET or RESET 00638 */ 00639 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ 00640 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) == (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) 00641 00642 /** 00643 * @} 00644 */ 00645 00646 /* Private macros ------------------------------------------------------------*/ 00647 00648 /** @defgroup TSC_Private_Macros TSC Private Macros 00649 * @{ 00650 */ 00651 00652 #define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \ 00653 ((__VALUE__) == TSC_CTPH_2CYCLES) || \ 00654 ((__VALUE__) == TSC_CTPH_3CYCLES) || \ 00655 ((__VALUE__) == TSC_CTPH_4CYCLES) || \ 00656 ((__VALUE__) == TSC_CTPH_5CYCLES) || \ 00657 ((__VALUE__) == TSC_CTPH_6CYCLES) || \ 00658 ((__VALUE__) == TSC_CTPH_7CYCLES) || \ 00659 ((__VALUE__) == TSC_CTPH_8CYCLES) || \ 00660 ((__VALUE__) == TSC_CTPH_9CYCLES) || \ 00661 ((__VALUE__) == TSC_CTPH_10CYCLES) || \ 00662 ((__VALUE__) == TSC_CTPH_11CYCLES) || \ 00663 ((__VALUE__) == TSC_CTPH_12CYCLES) || \ 00664 ((__VALUE__) == TSC_CTPH_13CYCLES) || \ 00665 ((__VALUE__) == TSC_CTPH_14CYCLES) || \ 00666 ((__VALUE__) == TSC_CTPH_15CYCLES) || \ 00667 ((__VALUE__) == TSC_CTPH_16CYCLES)) 00668 00669 #define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \ 00670 ((__VALUE__) == TSC_CTPL_2CYCLES) || \ 00671 ((__VALUE__) == TSC_CTPL_3CYCLES) || \ 00672 ((__VALUE__) == TSC_CTPL_4CYCLES) || \ 00673 ((__VALUE__) == TSC_CTPL_5CYCLES) || \ 00674 ((__VALUE__) == TSC_CTPL_6CYCLES) || \ 00675 ((__VALUE__) == TSC_CTPL_7CYCLES) || \ 00676 ((__VALUE__) == TSC_CTPL_8CYCLES) || \ 00677 ((__VALUE__) == TSC_CTPL_9CYCLES) || \ 00678 ((__VALUE__) == TSC_CTPL_10CYCLES) || \ 00679 ((__VALUE__) == TSC_CTPL_11CYCLES) || \ 00680 ((__VALUE__) == TSC_CTPL_12CYCLES) || \ 00681 ((__VALUE__) == TSC_CTPL_13CYCLES) || \ 00682 ((__VALUE__) == TSC_CTPL_14CYCLES) || \ 00683 ((__VALUE__) == TSC_CTPL_15CYCLES) || \ 00684 ((__VALUE__) == TSC_CTPL_16CYCLES)) 00685 00686 #define IS_TSC_SS(__VALUE__) (((__VALUE__) == DISABLE) || ((__VALUE__) == ENABLE)) 00687 00688 #define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0U) || (((__VALUE__) > 0U) && ((__VALUE__) < 128U))) 00689 00690 #define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2)) 00691 00692 #define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \ 00693 ((__VALUE__) == TSC_PG_PRESC_DIV2) || \ 00694 ((__VALUE__) == TSC_PG_PRESC_DIV4) || \ 00695 ((__VALUE__) == TSC_PG_PRESC_DIV8) || \ 00696 ((__VALUE__) == TSC_PG_PRESC_DIV16) || \ 00697 ((__VALUE__) == TSC_PG_PRESC_DIV32) || \ 00698 ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ 00699 ((__VALUE__) == TSC_PG_PRESC_DIV128)) 00700 00701 #define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ 00702 ((__VALUE__) == TSC_MCV_511) || \ 00703 ((__VALUE__) == TSC_MCV_1023) || \ 00704 ((__VALUE__) == TSC_MCV_2047) || \ 00705 ((__VALUE__) == TSC_MCV_4095) || \ 00706 ((__VALUE__) == TSC_MCV_8191) || \ 00707 ((__VALUE__) == TSC_MCV_16383)) 00708 00709 #define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT)) 00710 00711 #define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING) || ((__VALUE__) == TSC_SYNC_POLARITY_RISING)) 00712 00713 #define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO)) 00714 00715 #define IS_TSC_MCE_IT(__VALUE__) (((__VALUE__) == DISABLE) || ((__VALUE__) == ENABLE)) 00716 00717 #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0U) || (((__VALUE__) > 0U) && ((__VALUE__) < TSC_NB_OF_GROUPS))) 00718 00719 00720 #define IS_TSC_GROUP(__VALUE__) ((((__VALUE__) & TSC_GROUPX_NOT_SUPPORTED) != TSC_GROUPX_NOT_SUPPORTED) && \ 00721 ((((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ 00722 (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ 00723 (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ 00724 (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\ 00725 (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\ 00726 (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\ 00727 (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\ 00728 (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\ 00729 (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\ 00730 (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\ 00731 (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\ 00732 (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\ 00733 (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\ 00734 (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\ 00735 (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\ 00736 (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\ 00737 (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\ 00738 (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\ 00739 (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\ 00740 (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ 00741 (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ 00742 (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ 00743 (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\ 00744 (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\ 00745 (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ 00746 (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ 00747 (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ 00748 (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\ 00749 (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\ 00750 (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\ 00751 (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\ 00752 (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))) 00753 00754 /** 00755 * @} 00756 */ 00757 00758 /* Exported functions --------------------------------------------------------*/ 00759 /** @addtogroup TSC_Exported_Functions 00760 * @{ 00761 */ 00762 00763 /** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions 00764 * @{ 00765 */ 00766 /* Initialization and de-initialization functions *****************************/ 00767 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc); 00768 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); 00769 void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc); 00770 void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc); 00771 00772 /* Callbacks Register/UnRegister functions ***********************************/ 00773 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 00774 HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback); 00775 HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID); 00776 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 00777 /** 00778 * @} 00779 */ 00780 00781 /** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions 00782 * @{ 00783 */ 00784 /* IO operation functions *****************************************************/ 00785 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc); 00786 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc); 00787 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc); 00788 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc); 00789 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc); 00790 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index); 00791 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index); 00792 /** 00793 * @} 00794 */ 00795 00796 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions 00797 * @{ 00798 */ 00799 /* Peripheral Control functions ***********************************************/ 00800 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config); 00801 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, uint32_t choice); 00802 /** 00803 * @} 00804 */ 00805 00806 /** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions 00807 * @{ 00808 */ 00809 /* Peripheral State and Error functions ***************************************/ 00810 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc); 00811 /** 00812 * @} 00813 */ 00814 00815 /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 00816 * @{ 00817 */ 00818 /******* TSC IRQHandler and Callbacks used in Interrupt mode */ 00819 void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc); 00820 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc); 00821 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc); 00822 /** 00823 * @} 00824 */ 00825 00826 /** 00827 * @} 00828 */ 00829 00830 /** 00831 * @} 00832 */ 00833 00834 /** 00835 * @} 00836 */ 00837 00838 #ifdef __cplusplus 00839 } 00840 #endif 00841 00842 #endif /* __STM32L4xx_HAL_TSC_H */ 00843 00844 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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