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STM32L486xx HAL User Manual
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Defines | |
| #define | TSC_CTPL_1CYCLE 0x00000000U |
| #define | TSC_CTPL_2CYCLES TSC_CR_CTPL_0 |
| #define | TSC_CTPL_3CYCLES TSC_CR_CTPL_1 |
| #define | TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) |
| #define | TSC_CTPL_5CYCLES TSC_CR_CTPL_2 |
| #define | TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) |
| #define | TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) |
| #define | TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) |
| #define | TSC_CTPL_9CYCLES TSC_CR_CTPL_3 |
| #define | TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) |
| #define | TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) |
| #define | TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) |
| #define | TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) |
| #define | TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) |
| #define | TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) |
| #define | TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) |
| #define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) |
Charge transfer pulse low during 10 cycles (PGCLK)
Definition at line 244 of file stm32l4xx_hal_tsc.h.
| #define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) |
Charge transfer pulse low during 11 cycles (PGCLK)
Definition at line 245 of file stm32l4xx_hal_tsc.h.
| #define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) |
Charge transfer pulse low during 12 cycles (PGCLK)
Definition at line 246 of file stm32l4xx_hal_tsc.h.
| #define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) |
Charge transfer pulse low during 13 cycles (PGCLK)
Definition at line 247 of file stm32l4xx_hal_tsc.h.
| #define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) |
Charge transfer pulse low during 14 cycles (PGCLK)
Definition at line 248 of file stm32l4xx_hal_tsc.h.
| #define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) |
Charge transfer pulse low during 15 cycles (PGCLK)
Definition at line 249 of file stm32l4xx_hal_tsc.h.
| #define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) |
Charge transfer pulse low during 16 cycles (PGCLK)
Definition at line 250 of file stm32l4xx_hal_tsc.h.
| #define TSC_CTPL_1CYCLE 0x00000000U |
Charge transfer pulse low during 1 cycle (PGCLK)
Definition at line 235 of file stm32l4xx_hal_tsc.h.
| #define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 |
Charge transfer pulse low during 2 cycles (PGCLK)
Definition at line 236 of file stm32l4xx_hal_tsc.h.
| #define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 |
Charge transfer pulse low during 3 cycles (PGCLK)
Definition at line 237 of file stm32l4xx_hal_tsc.h.
| #define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) |
Charge transfer pulse low during 4 cycles (PGCLK)
Definition at line 238 of file stm32l4xx_hal_tsc.h.
| #define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 |
Charge transfer pulse low during 5 cycles (PGCLK)
Definition at line 239 of file stm32l4xx_hal_tsc.h.
| #define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) |
Charge transfer pulse low during 6 cycles (PGCLK)
Definition at line 240 of file stm32l4xx_hal_tsc.h.
| #define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) |
Charge transfer pulse low during 7 cycles (PGCLK)
Definition at line 241 of file stm32l4xx_hal_tsc.h.
| #define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) |
Charge transfer pulse low during 8 cycles (PGCLK)
Definition at line 242 of file stm32l4xx_hal_tsc.h.
| #define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 |
Charge transfer pulse low during 9 cycles (PGCLK)
Definition at line 243 of file stm32l4xx_hal_tsc.h.
1.7.6.1