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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_rcc_ex.h 00004 * @author MCD Application Team 00005 * @brief Header file of RCC HAL Extended module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_HAL_RCC_EX_H 00038 #define __STM32L4xx_HAL_RCC_EX_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx_hal_def.h" 00046 00047 /** @addtogroup STM32L4xx_HAL_Driver 00048 * @{ 00049 */ 00050 00051 /** @addtogroup RCCEx 00052 * @{ 00053 */ 00054 00055 /* Exported types ------------------------------------------------------------*/ 00056 00057 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 00058 * @{ 00059 */ 00060 00061 /** 00062 * @brief PLLSAI1 Clock structure definition 00063 */ 00064 typedef struct 00065 { 00066 00067 uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source. 00068 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 00069 00070 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 00071 uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. 00072 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 00073 #else 00074 uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. 00075 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ 00076 #endif 00077 00078 uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock. 00079 This parameter must be a number between 8 and 86 or 127 depending on devices. */ 00080 00081 uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock. 00082 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 00083 00084 uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock. 00085 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 00086 00087 uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock. 00088 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 00089 00090 uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled. 00091 This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ 00092 }RCC_PLLSAI1InitTypeDef; 00093 00094 #if defined(RCC_PLLSAI2_SUPPORT) 00095 00096 /** 00097 * @brief PLLSAI2 Clock structure definition 00098 */ 00099 typedef struct 00100 { 00101 00102 uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source. 00103 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 00104 00105 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 00106 uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. 00107 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 00108 #else 00109 uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. 00110 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ 00111 #endif 00112 00113 uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock. 00114 This parameter must be a number between 8 and 86 or 127 depending on devices. */ 00115 00116 uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock. 00117 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 00118 00119 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 00120 uint32_t PLLSAI2Q; /*!< PLLSAI2Q: specifies the division factor for DSI clock. 00121 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 00122 #endif 00123 00124 uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock. 00125 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 00126 00127 uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled. 00128 This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */ 00129 }RCC_PLLSAI2InitTypeDef; 00130 00131 #endif /* RCC_PLLSAI2_SUPPORT */ 00132 00133 /** 00134 * @brief RCC extended clocks structure definition 00135 */ 00136 typedef struct 00137 { 00138 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 00139 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 00140 00141 RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. 00142 This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */ 00143 00144 #if defined(RCC_PLLSAI2_SUPPORT) 00145 00146 RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters. 00147 This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */ 00148 00149 #endif /* RCC_PLLSAI2_SUPPORT */ 00150 00151 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 00152 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 00153 00154 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 00155 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 00156 00157 #if defined(USART3) 00158 00159 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. 00160 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 00161 00162 #endif /* USART3 */ 00163 00164 #if defined(UART4) 00165 00166 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. 00167 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 00168 00169 #endif /* UART4 */ 00170 00171 #if defined(UART5) 00172 00173 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. 00174 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 00175 00176 #endif /* UART5 */ 00177 00178 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 00179 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 00180 00181 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 00182 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 00183 00184 #if defined(I2C2) 00185 00186 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. 00187 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 00188 00189 #endif /* I2C2 */ 00190 00191 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 00192 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 00193 00194 #if defined(I2C4) 00195 00196 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. 00197 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 00198 00199 #endif /* I2C4 */ 00200 00201 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 00202 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 00203 00204 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. 00205 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ 00206 00207 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 00208 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 00209 00210 #if defined(SAI2) 00211 00212 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. 00213 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ 00214 00215 #endif /* SAI2 */ 00216 00217 #if defined(USB_OTG_FS) || defined(USB) 00218 00219 uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG). 00220 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 00221 00222 #endif /* USB_OTG_FS || USB */ 00223 00224 #if defined(SDMMC1) 00225 00226 uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG). 00227 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ 00228 00229 #endif /* SDMMC1 */ 00230 00231 uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1). 00232 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 00233 00234 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. 00235 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ 00236 00237 #if defined(SWPMI1) 00238 00239 uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source. 00240 This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */ 00241 00242 #endif /* SWPMI1 */ 00243 00244 #if defined(DFSDM1_Filter0) 00245 00246 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source. 00247 This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */ 00248 00249 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00250 uint32_t Dfsdm1AudioClockSelection; /*!< Specifies DFSDM1 audio clock source. 00251 This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ 00252 00253 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00254 00255 #endif /* DFSDM1_Filter0 */ 00256 00257 #if defined(LTDC) 00258 00259 uint32_t LtdcClockSelection; /*!< Specifies LTDC clock source. 00260 This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */ 00261 00262 #endif /* LTDC */ 00263 00264 #if defined(DSI) 00265 00266 uint32_t DsiClockSelection; /*!< Specifies DSI clock source. 00267 This parameter can be a value of @ref RCCEx_DSI_Clock_Source */ 00268 00269 #endif /* DSI */ 00270 00271 #if defined(OCTOSPI1) || defined(OCTOSPI2) 00272 00273 uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. 00274 This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ 00275 00276 #endif 00277 00278 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 00279 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 00280 }RCC_PeriphCLKInitTypeDef; 00281 00282 #if defined(CRS) 00283 00284 /** 00285 * @brief RCC_CRS Init structure definition 00286 */ 00287 typedef struct 00288 { 00289 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 00290 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 00291 00292 uint32_t Source; /*!< Specifies the SYNC signal source. 00293 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 00294 00295 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 00296 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 00297 00298 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 00299 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 00300 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 00301 00302 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 00303 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 00304 00305 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 00306 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 00307 00308 }RCC_CRSInitTypeDef; 00309 00310 /** 00311 * @brief RCC_CRS Synchronization structure definition 00312 */ 00313 typedef struct 00314 { 00315 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 00316 This parameter must be a number between 0 and 0xFFFF */ 00317 00318 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 00319 This parameter must be a number between 0 and 0x3F */ 00320 00321 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 00322 value latched in the time of the last SYNC event. 00323 This parameter must be a number between 0 and 0xFFFF */ 00324 00325 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 00326 frequency error counter latched in the time of the last SYNC event. 00327 It shows whether the actual frequency is below or above the target. 00328 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 00329 00330 }RCC_CRSSynchroInfoTypeDef; 00331 00332 #endif /* CRS */ 00333 /** 00334 * @} 00335 */ 00336 00337 /* Exported constants --------------------------------------------------------*/ 00338 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 00339 * @{ 00340 */ 00341 00342 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 00343 * @{ 00344 */ 00345 #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ 00346 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ 00347 /** 00348 * @} 00349 */ 00350 00351 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 00352 * @{ 00353 */ 00354 #define RCC_PERIPHCLK_USART1 0x00000001U 00355 #define RCC_PERIPHCLK_USART2 0x00000002U 00356 #if defined(USART3) 00357 #define RCC_PERIPHCLK_USART3 0x00000004U 00358 #endif 00359 #if defined(UART4) 00360 #define RCC_PERIPHCLK_UART4 0x00000008U 00361 #endif 00362 #if defined(UART5) 00363 #define RCC_PERIPHCLK_UART5 0x00000010U 00364 #endif 00365 #define RCC_PERIPHCLK_LPUART1 0x00000020U 00366 #define RCC_PERIPHCLK_I2C1 0x00000040U 00367 #if defined(I2C2) 00368 #define RCC_PERIPHCLK_I2C2 0x00000080U 00369 #endif 00370 #define RCC_PERIPHCLK_I2C3 0x00000100U 00371 #define RCC_PERIPHCLK_LPTIM1 0x00000200U 00372 #define RCC_PERIPHCLK_LPTIM2 0x00000400U 00373 #define RCC_PERIPHCLK_SAI1 0x00000800U 00374 #if defined(SAI2) 00375 #define RCC_PERIPHCLK_SAI2 0x00001000U 00376 #endif 00377 #if defined(USB_OTG_FS) || defined(USB) 00378 #define RCC_PERIPHCLK_USB 0x00002000U 00379 #endif 00380 #define RCC_PERIPHCLK_ADC 0x00004000U 00381 #if defined(SWPMI1) 00382 #define RCC_PERIPHCLK_SWPMI1 0x00008000U 00383 #endif 00384 #if defined(DFSDM1_Filter0) 00385 #define RCC_PERIPHCLK_DFSDM1 0x00010000U 00386 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00387 #define RCC_PERIPHCLK_DFSDM1AUDIO 0x00200000U 00388 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00389 #endif 00390 #define RCC_PERIPHCLK_RTC 0x00020000U 00391 #define RCC_PERIPHCLK_RNG 0x00040000U 00392 #if defined(SDMMC1) 00393 #define RCC_PERIPHCLK_SDMMC1 0x00080000U 00394 #endif 00395 #if defined(I2C4) 00396 #define RCC_PERIPHCLK_I2C4 0x00100000U 00397 #endif 00398 #if defined(LTDC) 00399 #define RCC_PERIPHCLK_LTDC 0x00400000U 00400 #endif 00401 #if defined(DSI) 00402 #define RCC_PERIPHCLK_DSI 0x00800000U 00403 #endif 00404 #if defined(OCTOSPI1) || defined(OCTOSPI2) 00405 #define RCC_PERIPHCLK_OSPI 0x01000000U 00406 #endif 00407 /** 00408 * @} 00409 */ 00410 00411 00412 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 00413 * @{ 00414 */ 00415 #define RCC_USART1CLKSOURCE_PCLK2 0x00000000U 00416 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 00417 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 00418 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) 00419 /** 00420 * @} 00421 */ 00422 00423 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source 00424 * @{ 00425 */ 00426 #define RCC_USART2CLKSOURCE_PCLK1 0x00000000U 00427 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 00428 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 00429 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) 00430 /** 00431 * @} 00432 */ 00433 00434 #if defined(USART3) 00435 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source 00436 * @{ 00437 */ 00438 #define RCC_USART3CLKSOURCE_PCLK1 0x00000000U 00439 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 00440 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 00441 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) 00442 /** 00443 * @} 00444 */ 00445 #endif /* USART3 */ 00446 00447 #if defined(UART4) 00448 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source 00449 * @{ 00450 */ 00451 #define RCC_UART4CLKSOURCE_PCLK1 0x00000000U 00452 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 00453 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 00454 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) 00455 /** 00456 * @} 00457 */ 00458 #endif /* UART4 */ 00459 00460 #if defined(UART5) 00461 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source 00462 * @{ 00463 */ 00464 #define RCC_UART5CLKSOURCE_PCLK1 0x00000000U 00465 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 00466 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 00467 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) 00468 /** 00469 * @} 00470 */ 00471 #endif /* UART5 */ 00472 00473 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 00474 * @{ 00475 */ 00476 #define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U 00477 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 00478 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 00479 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) 00480 /** 00481 * @} 00482 */ 00483 00484 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 00485 * @{ 00486 */ 00487 #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U 00488 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 00489 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 00490 /** 00491 * @} 00492 */ 00493 00494 #if defined(I2C2) 00495 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source 00496 * @{ 00497 */ 00498 #define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U 00499 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 00500 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 00501 /** 00502 * @} 00503 */ 00504 #endif /* I2C2 */ 00505 00506 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 00507 * @{ 00508 */ 00509 #define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U 00510 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 00511 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 00512 /** 00513 * @} 00514 */ 00515 00516 #if defined(I2C4) 00517 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source 00518 * @{ 00519 */ 00520 #define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U 00521 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 00522 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 00523 /** 00524 * @} 00525 */ 00526 #endif /* I2C4 */ 00527 00528 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 00529 * @{ 00530 */ 00531 #define RCC_SAI1CLKSOURCE_PLLSAI1 0x00000000U 00532 #if defined(RCC_PLLSAI2_SUPPORT) 00533 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00534 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI1SEL_0 00535 #else 00536 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0 00537 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00538 #endif /* RCC_PLLSAI2_SUPPORT */ 00539 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00540 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR2_SAI1SEL_1 00541 #define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0) 00542 #define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2 00543 #else 00544 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1 00545 #define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL 00546 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00547 /** 00548 * @} 00549 */ 00550 00551 #if defined(SAI2) 00552 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 00553 * @{ 00554 */ 00555 #define RCC_SAI2CLKSOURCE_PLLSAI1 0x00000000U 00556 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00557 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0 00558 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1 00559 #define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0) 00560 #define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2 00561 #else 00562 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0 00563 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1 00564 #define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL 00565 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00566 /** 00567 * @} 00568 */ 00569 #endif /* SAI2 */ 00570 00571 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 00572 * @{ 00573 */ 00574 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U 00575 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 00576 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 00577 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL 00578 /** 00579 * @} 00580 */ 00581 00582 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source 00583 * @{ 00584 */ 00585 #define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U 00586 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0 00587 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1 00588 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL 00589 /** 00590 * @} 00591 */ 00592 00593 #if defined(SDMMC1) 00594 /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source 00595 * @{ 00596 */ 00597 #if defined(RCC_HSI48_SUPPORT) 00598 #define RCC_SDMMC1CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock selected as SDMMC1 clock */ 00599 #else 00600 #define RCC_SDMMC1CLKSOURCE_NONE 0x00000000U /*!< No clock selected as SDMMC1 clock */ 00601 #endif /* RCC_HSI48_SUPPORT */ 00602 #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 "Q" clock selected as SDMMC1 clock */ 00603 #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL "Q" clock selected as SDMMC1 clock */ 00604 #define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock selected as SDMMC1 clock */ 00605 #if defined(RCC_CCIPR2_SDMMCSEL) 00606 #define RCC_SDMMC1CLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLL "P" clock selected as SDMMC1 kernel clock */ 00607 #endif /* RCC_CCIPR2_SDMMCSEL */ 00608 /** 00609 * @} 00610 */ 00611 #endif /* SDMMC1 */ 00612 00613 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source 00614 * @{ 00615 */ 00616 #if defined(RCC_HSI48_SUPPORT) 00617 #define RCC_RNGCLKSOURCE_HSI48 0x00000000U 00618 #else 00619 #define RCC_RNGCLKSOURCE_NONE 0x00000000U 00620 #endif /* RCC_HSI48_SUPPORT */ 00621 #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 00622 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 00623 #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL 00624 /** 00625 * @} 00626 */ 00627 00628 #if defined(USB_OTG_FS) || defined(USB) 00629 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source 00630 * @{ 00631 */ 00632 #if defined(RCC_HSI48_SUPPORT) 00633 #define RCC_USBCLKSOURCE_HSI48 0x00000000U 00634 #else 00635 #define RCC_USBCLKSOURCE_NONE 0x00000000U 00636 #endif /* RCC_HSI48_SUPPORT */ 00637 #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 00638 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 00639 #define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL 00640 /** 00641 * @} 00642 */ 00643 #endif /* USB_OTG_FS || USB */ 00644 00645 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source 00646 * @{ 00647 */ 00648 #define RCC_ADCCLKSOURCE_NONE 0x00000000U 00649 #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 00650 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 00651 #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 00652 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 00653 #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL 00654 /** 00655 * @} 00656 */ 00657 00658 #if defined(SWPMI1) 00659 /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source 00660 * @{ 00661 */ 00662 #define RCC_SWPMI1CLKSOURCE_PCLK1 0x00000000U 00663 #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL 00664 /** 00665 * @} 00666 */ 00667 #endif /* SWPMI1 */ 00668 00669 #if defined(DFSDM1_Filter0) 00670 /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source 00671 * @{ 00672 */ 00673 #define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U 00674 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00675 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL 00676 #else 00677 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL 00678 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00679 /** 00680 * @} 00681 */ 00682 00683 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00684 /** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source 00685 * @{ 00686 */ 00687 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 0x00000000U 00688 #define RCC_DFSDM1AUDIOCLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 00689 #define RCC_DFSDM1AUDIOCLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 00690 /** 00691 * @} 00692 */ 00693 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00694 #endif /* DFSDM1_Filter0 */ 00695 00696 #if defined(LTDC) 00697 /** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source 00698 * @{ 00699 */ 00700 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 0x00000000U 00701 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 00702 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 00703 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 RCC_CCIPR2_PLLSAI2DIVR 00704 /** 00705 * @} 00706 */ 00707 #endif /* LTDC */ 00708 00709 #if defined(DSI) 00710 /** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source 00711 * @{ 00712 */ 00713 #define RCC_DSICLKSOURCE_DSIPHY 0x00000000U 00714 #define RCC_DSICLKSOURCE_PLLSAI2 RCC_CCIPR2_DSISEL 00715 /** 00716 * @} 00717 */ 00718 #endif /* DSI */ 00719 00720 #if defined(OCTOSPI1) || defined(OCTOSPI2) 00721 /** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source 00722 * @{ 00723 */ 00724 #define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U 00725 #define RCC_OSPICLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 00726 #define RCC_OSPICLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 00727 /** 00728 * @} 00729 */ 00730 #endif /* OCTOSPI1 || OCTOSPI2 */ 00731 00732 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line 00733 * @{ 00734 */ 00735 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ 00736 /** 00737 * @} 00738 */ 00739 00740 #if defined(CRS) 00741 00742 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 00743 * @{ 00744 */ 00745 #define RCC_CRS_NONE 0x00000000U 00746 #define RCC_CRS_TIMEOUT 0x00000001U 00747 #define RCC_CRS_SYNCOK 0x00000002U 00748 #define RCC_CRS_SYNCWARN 0x00000004U 00749 #define RCC_CRS_SYNCERR 0x00000008U 00750 #define RCC_CRS_SYNCMISS 0x00000010U 00751 #define RCC_CRS_TRIMOVF 0x00000020U 00752 /** 00753 * @} 00754 */ 00755 00756 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 00757 * @{ 00758 */ 00759 #define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ 00760 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 00761 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 00762 /** 00763 * @} 00764 */ 00765 00766 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 00767 * @{ 00768 */ 00769 #define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ 00770 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 00771 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 00772 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 00773 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 00774 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 00775 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 00776 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 00777 /** 00778 * @} 00779 */ 00780 00781 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 00782 * @{ 00783 */ 00784 #define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ 00785 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 00786 /** 00787 * @} 00788 */ 00789 00790 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 00791 * @{ 00792 */ 00793 #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds 00794 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 00795 /** 00796 * @} 00797 */ 00798 00799 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 00800 * @{ 00801 */ 00802 #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ 00803 /** 00804 * @} 00805 */ 00806 00807 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 00808 * @{ 00809 */ 00810 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. 00811 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value 00812 corresponds to a higher output frequency */ 00813 /** 00814 * @} 00815 */ 00816 00817 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 00818 * @{ 00819 */ 00820 #define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ 00821 #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ 00822 /** 00823 * @} 00824 */ 00825 00826 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 00827 * @{ 00828 */ 00829 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 00830 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 00831 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 00832 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 00833 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 00834 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 00835 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 00836 00837 /** 00838 * @} 00839 */ 00840 00841 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 00842 * @{ 00843 */ 00844 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 00845 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 00846 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 00847 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 00848 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 00849 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 00850 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 00851 00852 /** 00853 * @} 00854 */ 00855 00856 #endif /* CRS */ 00857 00858 /** 00859 * @} 00860 */ 00861 00862 /* Exported macros -----------------------------------------------------------*/ 00863 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 00864 * @{ 00865 */ 00866 00867 00868 /** 00869 * @brief Macro to configure the PLLSAI1 clock multiplication and division factors. 00870 * 00871 * @note This function must be used only when the PLLSAI1 is disabled. 00872 * @note PLLSAI1 clock source is common with the main PLL (configured through 00873 * __HAL_RCC_PLL_CONFIG() macro) 00874 * 00875 @if STM32L4S9xx 00876 * @param __PLLSAI1M__ specifies the division factor of PLLSAI1 input clock. 00877 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 00878 * 00879 @endif 00880 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. 00881 * This parameter must be a number between 8 and 86. 00882 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO 00883 * output frequency is between 64 and 344 MHz. 00884 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N 00885 * 00886 * @param __PLLSAI1P__ specifies the division factor for SAI clock. 00887 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx 00888 * else (2 to 31). 00889 * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P 00890 * 00891 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. 00892 * This parameter must be in the range (2, 4, 6 or 8). 00893 * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q 00894 * 00895 * @param __PLLSAI1R__ specifies the division factor for SAR ADC clock. 00896 * This parameter must be in the range (2, 4, 6 or 8). 00897 * ADC clock frequency = f(PLLSAI1) / PLLSAI1R 00898 * 00899 * @retval None 00900 */ 00901 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 00902 00903 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 00904 00905 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 00906 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 00907 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 00908 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ 00909 ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) | \ 00910 (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)) 00911 00912 #else 00913 00914 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 00915 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 00916 (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \ 00917 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 00918 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ 00919 (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)) 00920 00921 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 00922 00923 #else 00924 00925 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 00926 00927 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 00928 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 00929 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 00930 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ 00931 ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) 00932 00933 #else 00934 00935 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ 00936 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ 00937 (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \ 00938 ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ 00939 ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)) 00940 00941 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 00942 00943 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 00944 00945 /** 00946 * @brief Macro to configure the PLLSAI1 clock multiplication factor N. 00947 * 00948 * @note This function must be used only when the PLLSAI1 is disabled. 00949 * @note PLLSAI1 clock source is common with the main PLL (configured through 00950 * __HAL_RCC_PLL_CONFIG() macro) 00951 * 00952 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. 00953 * This parameter must be a number between 8 and 86. 00954 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO 00955 * output frequency is between 64 and 344 MHz. 00956 * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N 00957 * 00958 * @retval None 00959 */ 00960 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \ 00961 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) 00962 00963 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 00964 00965 /** @brief Macro to configure the PLLSAI1 input clock division factor M. 00966 * 00967 * @note This function must be used only when the PLLSAI1 is disabled. 00968 * @note PLLSAI1 clock source is common with the main PLL (configured through 00969 * __HAL_RCC_PLL_CONFIG() macro) 00970 * 00971 * @param __PLLSAI1M__ specifies the division factor for PLLSAI1 clock. 00972 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 00973 * 00974 * @retval None 00975 */ 00976 00977 #define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \ 00978 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) 00979 00980 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 00981 00982 /** @brief Macro to configure the PLLSAI1 clock division factor P. 00983 * 00984 * @note This function must be used only when the PLLSAI1 is disabled. 00985 * @note PLLSAI1 clock source is common with the main PLL (configured through 00986 * __HAL_RCC_PLL_CONFIG() macro) 00987 * 00988 * @param __PLLSAI1P__ specifies the division factor for SAI clock. 00989 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx 00990 * else (2 to 31). 00991 * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P 00992 * 00993 * @retval None 00994 */ 00995 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 00996 00997 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ 00998 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) 00999 01000 #else 01001 01002 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ 01003 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) 01004 01005 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 01006 01007 /** @brief Macro to configure the PLLSAI1 clock division factor Q. 01008 * 01009 * @note This function must be used only when the PLLSAI1 is disabled. 01010 * @note PLLSAI1 clock source is common with the main PLL (configured through 01011 * __HAL_RCC_PLL_CONFIG() macro) 01012 * 01013 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. 01014 * This parameter must be in the range (2, 4, 6 or 8). 01015 * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q 01016 * 01017 * @retval None 01018 */ 01019 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \ 01020 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) 01021 01022 /** @brief Macro to configure the PLLSAI1 clock division factor R. 01023 * 01024 * @note This function must be used only when the PLLSAI1 is disabled. 01025 * @note PLLSAI1 clock source is common with the main PLL (configured through 01026 * __HAL_RCC_PLL_CONFIG() macro) 01027 * 01028 * @param __PLLSAI1R__ specifies the division factor for ADC clock. 01029 * This parameter must be in the range (2, 4, 6 or 8) 01030 * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R 01031 * 01032 * @retval None 01033 */ 01034 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \ 01035 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) 01036 01037 /** 01038 * @brief Macros to enable or disable the PLLSAI1. 01039 * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes. 01040 * @retval None 01041 */ 01042 01043 #define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON) 01044 01045 #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON) 01046 01047 /** 01048 * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). 01049 * @note Enabling and disabling those clocks can be done without the need to stop the PLL. 01050 * This is mainly used to save Power. 01051 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 01052 * This parameter can be one or a combination of the following values: 01053 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve 01054 * high-quality audio performance on SAI interface in case. 01055 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), 01056 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). 01057 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. 01058 * @retval None 01059 */ 01060 01061 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 01062 01063 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 01064 01065 /** 01066 * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). 01067 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. 01068 * This parameter can be one of the following values: 01069 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve 01070 * high-quality audio performance on SAI interface in case. 01071 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), 01072 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). 01073 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. 01074 * @retval SET / RESET 01075 */ 01076 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) 01077 01078 #if defined(RCC_PLLSAI2_SUPPORT) 01079 01080 /** 01081 * @brief Macro to configure the PLLSAI2 clock multiplication and division factors. 01082 * 01083 * @note This function must be used only when the PLLSAI2 is disabled. 01084 * @note PLLSAI2 clock source is common with the main PLL (configured through 01085 * __HAL_RCC_PLL_CONFIG() macro) 01086 * 01087 @if STM32L4S9xx 01088 * @param __PLLSAI2M__ specifies the division factor of PLLSAI2 input clock. 01089 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 01090 * 01091 @endif 01092 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. 01093 * This parameter must be a number between 8 and 86. 01094 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO 01095 * output frequency is between 64 and 344 MHz. 01096 * 01097 * @param __PLLSAI2P__ specifies the division factor for SAI clock. 01098 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx 01099 * else (2 to 31). 01100 * SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P 01101 * 01102 @if STM32L4S9xx 01103 * @param __PLLSAI2Q__ specifies the division factor for DSI clock. 01104 * This parameter must be in the range (2, 4, 6 or 8). 01105 * DSI clock frequency = f(PLLSAI2) / PLLSAI2Q 01106 * 01107 @endif 01108 * @param __PLLSAI2R__ specifies the division factor for SAR ADC clock. 01109 * This parameter must be in the range (2, 4, 6 or 8). 01110 * 01111 * @retval None 01112 */ 01113 01114 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 01115 01116 # if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) 01117 01118 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ 01119 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 01120 ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ 01121 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 01122 ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \ 01123 (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) 01124 01125 # elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 01126 01127 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ 01128 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 01129 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 01130 ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \ 01131 (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) 01132 01133 # else 01134 01135 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ 01136 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 01137 (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \ 01138 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 01139 (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) 01140 01141 # endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ 01142 01143 #else 01144 01145 # if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) 01146 01147 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ 01148 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 01149 ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ 01150 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 01151 ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) 01152 01153 # elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 01154 01155 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ 01156 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 01157 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ 01158 ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) 01159 01160 # else 01161 01162 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ 01163 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ 01164 (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \ 01165 ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)) 01166 01167 # endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ 01168 01169 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 01170 01171 01172 /** 01173 * @brief Macro to configure the PLLSAI2 clock multiplication factor N. 01174 * 01175 * @note This function must be used only when the PLLSAI2 is disabled. 01176 * @note PLLSAI2 clock source is common with the main PLL (configured through 01177 * __HAL_RCC_PLL_CONFIG() macro) 01178 * 01179 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. 01180 * This parameter must be a number between 8 and 86. 01181 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO 01182 * output frequency is between 64 and 344 MHz. 01183 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N 01184 * 01185 * @retval None 01186 */ 01187 #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \ 01188 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) 01189 01190 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 01191 01192 /** @brief Macro to configure the PLLSAI2 input clock division factor M. 01193 * 01194 * @note This function must be used only when the PLLSAI2 is disabled. 01195 * @note PLLSAI2 clock source is common with the main PLL (configured through 01196 * __HAL_RCC_PLL_CONFIG() macro) 01197 * 01198 * @param __PLLSAI2M__ specifies the division factor for PLLSAI2 clock. 01199 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 01200 * 01201 * @retval None 01202 */ 01203 01204 #define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \ 01205 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) 01206 01207 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 01208 01209 /** @brief Macro to configure the PLLSAI2 clock division factor P. 01210 * 01211 * @note This function must be used only when the PLLSAI2 is disabled. 01212 * @note PLLSAI2 clock source is common with the main PLL (configured through 01213 * __HAL_RCC_PLL_CONFIG() macro) 01214 * 01215 * @param __PLLSAI2P__ specifies the division factor. 01216 * This parameter must be a number in the range (7 or 17). 01217 * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__ 01218 * 01219 * @retval None 01220 */ 01221 #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \ 01222 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) 01223 01224 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 01225 01226 /** @brief Macro to configure the PLLSAI2 clock division factor Q. 01227 * 01228 * @note This function must be used only when the PLLSAI2 is disabled. 01229 * @note PLLSAI2 clock source is common with the main PLL (configured through 01230 * __HAL_RCC_PLL_CONFIG() macro) 01231 * 01232 * @param __PLLSAI2Q__ specifies the division factor for USB/RNG/SDMMC1 clock. 01233 * This parameter must be in the range (2, 4, 6 or 8). 01234 * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI2) / PLLSAI2Q 01235 * 01236 * @retval None 01237 */ 01238 #define __HAL_RCC_PLLSAI2_DIVQ_CONFIG(__PLLSAI2Q__) \ 01239 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q, (((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) 01240 01241 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 01242 01243 /** @brief Macro to configure the PLLSAI2 clock division factor R. 01244 * 01245 * @note This function must be used only when the PLLSAI2 is disabled. 01246 * @note PLLSAI2 clock source is common with the main PLL (configured through 01247 * __HAL_RCC_PLL_CONFIG() macro) 01248 * 01249 * @param __PLLSAI2R__ specifies the division factor. 01250 * This parameter must be in the range (2, 4, 6 or 8). 01251 * Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__ 01252 * 01253 * @retval None 01254 */ 01255 #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \ 01256 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) 01257 01258 /** 01259 * @brief Macros to enable or disable the PLLSAI2. 01260 * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes. 01261 * @retval None 01262 */ 01263 01264 #define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON) 01265 01266 #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON) 01267 01268 /** 01269 * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). 01270 * @note Enabling and disabling those clocks can be done without the need to stop the PLL. 01271 * This is mainly used to save Power. 01272 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. 01273 * This parameter can be one or a combination of the following values: 01274 @if STM32L486xx 01275 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 01276 * high-quality audio performance on SAI interface in case. 01277 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. 01278 @endif 01279 @if STM32L4A6xx 01280 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 01281 * high-quality audio performance on SAI interface in case. 01282 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. 01283 @endif 01284 @if STM32L4S9xx 01285 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 01286 * high-quality audio performance on SAI interface in case. 01287 * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. 01288 @endif 01289 * @retval None 01290 */ 01291 01292 #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 01293 01294 #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 01295 01296 /** 01297 * @brief Macro to get clock output enable status (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). 01298 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. 01299 * This parameter can be one of the following values: 01300 @if STM32L486xx 01301 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 01302 * high-quality audio performance on SAI interface in case. 01303 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. 01304 @endif 01305 @if STM32L4A6xx 01306 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 01307 * high-quality audio performance on SAI interface in case. 01308 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. 01309 @endif 01310 @if STM32L4S9xx 01311 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve 01312 * high-quality audio performance on SAI interface in case. 01313 * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. 01314 @endif 01315 * @retval SET / RESET 01316 */ 01317 #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) 01318 01319 #endif /* RCC_PLLSAI2_SUPPORT */ 01320 01321 /** 01322 * @brief Macro to configure the SAI1 clock source. 01323 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived 01324 * from the PLLSAI1, system PLL or external clock (through a dedicated pin). 01325 * This parameter can be one of the following values: 01326 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 01327 @if STM32L486xx 01328 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 01329 @endif 01330 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) 01331 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 01332 @if STM32L4S9xx 01333 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 01334 @endif 01335 * 01336 @if STM32L443xx 01337 * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2. 01338 @endif 01339 * 01340 * @retval None 01341 */ 01342 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01343 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 01344 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__)) 01345 #else 01346 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 01347 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__)) 01348 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01349 01350 /** @brief Macro to get the SAI1 clock source. 01351 * @retval The clock source can be one of the following values: 01352 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 01353 @if STM32L486xx 01354 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 01355 @endif 01356 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) 01357 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) 01358 * 01359 * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 01360 * clock source when PLLs are disabled for devices without PLLSAI2. 01361 * 01362 */ 01363 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01364 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL)) 01365 #else 01366 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) 01367 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01368 01369 #if defined(SAI2) 01370 01371 /** 01372 * @brief Macro to configure the SAI2 clock source. 01373 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived 01374 * from the PLLSAI2, system PLL or external clock (through a dedicated pin). 01375 * This parameter can be one of the following values: 01376 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 01377 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) 01378 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) 01379 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) 01380 @if STM32L4S9xx 01381 * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 01382 @endif 01383 * 01384 * @retval None 01385 */ 01386 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01387 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ 01388 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (__SAI2_CLKSOURCE__)) 01389 #else 01390 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ 01391 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__)) 01392 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01393 01394 /** @brief Macro to get the SAI2 clock source. 01395 * @retval The clock source can be one of the following values: 01396 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) 01397 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) 01398 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) 01399 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) 01400 */ 01401 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01402 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL)) 01403 #else 01404 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)) 01405 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01406 01407 #endif /* SAI2 */ 01408 01409 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 01410 * 01411 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 01412 * This parameter can be one of the following values: 01413 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 01414 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 01415 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 01416 * @retval None 01417 */ 01418 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 01419 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__)) 01420 01421 /** @brief Macro to get the I2C1 clock source. 01422 * @retval The clock source can be one of the following values: 01423 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 01424 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 01425 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 01426 */ 01427 #define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)) 01428 01429 #if defined(I2C2) 01430 01431 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 01432 * 01433 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. 01434 * This parameter can be one of the following values: 01435 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 01436 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 01437 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 01438 * @retval None 01439 */ 01440 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ 01441 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__)) 01442 01443 /** @brief Macro to get the I2C2 clock source. 01444 * @retval The clock source can be one of the following values: 01445 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 01446 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 01447 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 01448 */ 01449 #define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)) 01450 01451 #endif /* I2C2 */ 01452 01453 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 01454 * 01455 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 01456 * This parameter can be one of the following values: 01457 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 01458 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 01459 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 01460 * @retval None 01461 */ 01462 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 01463 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__)) 01464 01465 /** @brief Macro to get the I2C3 clock source. 01466 * @retval The clock source can be one of the following values: 01467 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 01468 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 01469 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 01470 */ 01471 #define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)) 01472 01473 #if defined(I2C4) 01474 01475 /** @brief Macro to configure the I2C4 clock (I2C4CLK). 01476 * 01477 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. 01478 * This parameter can be one of the following values: 01479 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 01480 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 01481 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 01482 * @retval None 01483 */ 01484 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ 01485 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__)) 01486 01487 /** @brief Macro to get the I2C4 clock source. 01488 * @retval The clock source can be one of the following values: 01489 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 01490 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 01491 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 01492 */ 01493 #define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)) 01494 01495 #endif /* I2C4 */ 01496 01497 01498 /** @brief Macro to configure the USART1 clock (USART1CLK). 01499 * 01500 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 01501 * This parameter can be one of the following values: 01502 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 01503 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 01504 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 01505 * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock 01506 * @retval None 01507 */ 01508 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 01509 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__)) 01510 01511 /** @brief Macro to get the USART1 clock source. 01512 * @retval The clock source can be one of the following values: 01513 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 01514 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 01515 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 01516 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 01517 */ 01518 #define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)) 01519 01520 /** @brief Macro to configure the USART2 clock (USART2CLK). 01521 * 01522 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 01523 * This parameter can be one of the following values: 01524 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 01525 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 01526 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 01527 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 01528 * @retval None 01529 */ 01530 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 01531 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__)) 01532 01533 /** @brief Macro to get the USART2 clock source. 01534 * @retval The clock source can be one of the following values: 01535 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 01536 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 01537 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 01538 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 01539 */ 01540 #define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)) 01541 01542 #if defined(USART3) 01543 01544 /** @brief Macro to configure the USART3 clock (USART3CLK). 01545 * 01546 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. 01547 * This parameter can be one of the following values: 01548 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 01549 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 01550 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 01551 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 01552 * @retval None 01553 */ 01554 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ 01555 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__)) 01556 01557 /** @brief Macro to get the USART3 clock source. 01558 * @retval The clock source can be one of the following values: 01559 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 01560 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 01561 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 01562 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 01563 */ 01564 #define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)) 01565 01566 #endif /* USART3 */ 01567 01568 #if defined(UART4) 01569 01570 /** @brief Macro to configure the UART4 clock (UART4CLK). 01571 * 01572 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. 01573 * This parameter can be one of the following values: 01574 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 01575 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 01576 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 01577 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 01578 * @retval None 01579 */ 01580 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ 01581 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__)) 01582 01583 /** @brief Macro to get the UART4 clock source. 01584 * @retval The clock source can be one of the following values: 01585 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 01586 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 01587 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 01588 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 01589 */ 01590 #define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)) 01591 01592 #endif /* UART4 */ 01593 01594 #if defined(UART5) 01595 01596 /** @brief Macro to configure the UART5 clock (UART5CLK). 01597 * 01598 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. 01599 * This parameter can be one of the following values: 01600 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 01601 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 01602 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 01603 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 01604 * @retval None 01605 */ 01606 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ 01607 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__)) 01608 01609 /** @brief Macro to get the UART5 clock source. 01610 * @retval The clock source can be one of the following values: 01611 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 01612 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 01613 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 01614 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 01615 */ 01616 #define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)) 01617 01618 #endif /* UART5 */ 01619 01620 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 01621 * 01622 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 01623 * This parameter can be one of the following values: 01624 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 01625 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 01626 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 01627 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 01628 * @retval None 01629 */ 01630 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 01631 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__)) 01632 01633 /** @brief Macro to get the LPUART1 clock source. 01634 * @retval The clock source can be one of the following values: 01635 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 01636 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 01637 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 01638 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 01639 */ 01640 #define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)) 01641 01642 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 01643 * 01644 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 01645 * This parameter can be one of the following values: 01646 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock 01647 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock 01648 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock 01649 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 01650 * @retval None 01651 */ 01652 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 01653 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) 01654 01655 /** @brief Macro to get the LPTIM1 clock source. 01656 * @retval The clock source can be one of the following values: 01657 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 01658 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock 01659 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock 01660 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock 01661 */ 01662 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)) 01663 01664 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). 01665 * 01666 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. 01667 * This parameter can be one of the following values: 01668 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock 01669 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock 01670 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock 01671 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock 01672 * @retval None 01673 */ 01674 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ 01675 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__)) 01676 01677 /** @brief Macro to get the LPTIM2 clock source. 01678 * @retval The clock source can be one of the following values: 01679 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 01680 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPUART1 clock 01681 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock 01682 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock 01683 */ 01684 #define __HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)) 01685 01686 #if defined(SDMMC1) 01687 01688 /** @brief Macro to configure the SDMMC1 clock. 01689 * 01690 @if STM32L486xx 01691 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 01692 @endif 01693 * 01694 @if STM32L443xx 01695 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 01696 @endif 01697 * 01698 * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. 01699 * This parameter can be one of the following values: 01700 @if STM32L486xx 01701 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 01702 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 01703 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock 01704 @endif 01705 @if STM32L443xx 01706 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 01707 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 01708 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock 01709 @endif 01710 @if STM32L4S9xx 01711 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 01712 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 01713 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock 01714 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" Clock selected as SDMMC1 clock 01715 @endif 01716 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" Clock selected as SDMMC1 clock 01717 * @retval None 01718 */ 01719 #if defined(RCC_CCIPR2_SDMMCSEL) 01720 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ 01721 do \ 01722 { \ 01723 if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \ 01724 { \ 01725 SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ 01726 } \ 01727 else \ 01728 { \ 01729 CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ 01730 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)); \ 01731 } \ 01732 } while(0) 01733 #else 01734 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ 01735 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)) 01736 #endif /* RCC_CCIPR2_SDMMCSEL */ 01737 01738 /** @brief Macro to get the SDMMC1 clock. 01739 * @retval The clock source can be one of the following values: 01740 @if STM32L486xx 01741 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 01742 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 01743 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock 01744 @endif 01745 @if STM32L443xx 01746 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 01747 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 01748 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock 01749 @endif 01750 @if STM32L4S9xx 01751 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 01752 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock 01753 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock 01754 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 kernel clock 01755 @endif 01756 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock 01757 */ 01758 #if defined(RCC_CCIPR2_SDMMCSEL) 01759 #define __HAL_RCC_GET_SDMMC1_SOURCE() \ 01760 ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != RESET) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) 01761 #else 01762 #define __HAL_RCC_GET_SDMMC1_SOURCE() \ 01763 (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 01764 #endif /* RCC_CCIPR2_SDMMCSEL */ 01765 01766 #endif /* SDMMC1 */ 01767 01768 /** @brief Macro to configure the RNG clock. 01769 * 01770 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 01771 * 01772 * @param __RNG_CLKSOURCE__ specifies the RNG clock source. 01773 * This parameter can be one of the following values: 01774 @if STM32L486xx 01775 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 01776 @endif 01777 @if STM32L443xx 01778 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 01779 @endif 01780 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock 01781 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock 01782 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock 01783 * @retval None 01784 */ 01785 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ 01786 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__)) 01787 01788 /** @brief Macro to get the RNG clock. 01789 * @retval The clock source can be one of the following values: 01790 @if STM32L486xx 01791 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 01792 @endif 01793 @if STM32L443xx 01794 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 01795 @endif 01796 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock 01797 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock 01798 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock 01799 */ 01800 #define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 01801 01802 #if defined(USB_OTG_FS) || defined(USB) 01803 01804 /** @brief Macro to configure the USB clock (USBCLK). 01805 * 01806 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. 01807 * 01808 * @param __USB_CLKSOURCE__ specifies the USB clock source. 01809 * This parameter can be one of the following values: 01810 @if STM32L486xx 01811 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 01812 @endif 01813 @if STM32L443xx 01814 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 01815 @endif 01816 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock 01817 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock 01818 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 01819 * @retval None 01820 */ 01821 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ 01822 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__)) 01823 01824 /** @brief Macro to get the USB clock source. 01825 * @retval The clock source can be one of the following values: 01826 @if STM32L486xx 01827 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 01828 @endif 01829 @if STM32L443xx 01830 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 01831 @endif 01832 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock 01833 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock 01834 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 01835 */ 01836 #define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 01837 01838 #endif /* USB_OTG_FS || USB */ 01839 01840 /** @brief Macro to configure the ADC interface clock. 01841 * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. 01842 * This parameter can be one of the following values: 01843 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 01844 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock 01845 @if STM32L486xx 01846 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices 01847 @endif 01848 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 01849 * @retval None 01850 */ 01851 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ 01852 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__)) 01853 01854 /** @brief Macro to get the ADC clock source. 01855 * @retval The clock source can be one of the following values: 01856 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock 01857 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock 01858 @if STM32L486xx 01859 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices 01860 @endif 01861 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock 01862 */ 01863 #define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)) 01864 01865 #if defined(SWPMI1) 01866 01867 /** @brief Macro to configure the SWPMI1 clock. 01868 * @param __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source. 01869 * This parameter can be one of the following values: 01870 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock 01871 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock 01872 * @retval None 01873 */ 01874 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \ 01875 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__)) 01876 01877 /** @brief Macro to get the SWPMI1 clock source. 01878 * @retval The clock source can be one of the following values: 01879 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock 01880 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock 01881 */ 01882 #define __HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)) 01883 01884 #endif /* SWPMI1 */ 01885 01886 #if defined(DFSDM1_Filter0) 01887 /** @brief Macro to configure the DFSDM1 clock. 01888 * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. 01889 * This parameter can be one of the following values: 01890 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock 01891 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock 01892 * @retval None 01893 */ 01894 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01895 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ 01896 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) 01897 #else 01898 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ 01899 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) 01900 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01901 01902 /** @brief Macro to get the DFSDM1 clock source. 01903 * @retval The clock source can be one of the following values: 01904 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock 01905 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock 01906 */ 01907 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01908 #define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL)) 01909 #else 01910 #define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)) 01911 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01912 01913 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 01914 01915 /** @brief Macro to configure the DFSDM1 audio clock. 01916 * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 audio clock source. 01917 * This parameter can be one of the following values: 01918 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock 01919 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock 01920 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock 01921 * @retval None 01922 */ 01923 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ 01924 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (__DFSDM1AUDIO_CLKSOURCE__)) 01925 01926 /** @brief Macro to get the DFSDM1 audio clock source. 01927 * @retval The clock source can be one of the following values: 01928 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock 01929 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock 01930 * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock 01931 */ 01932 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL)) 01933 01934 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01935 01936 #endif /* DFSDM1_Filter0 */ 01937 01938 #if defined(LTDC) 01939 01940 /** @brief Macro to configure the LTDC clock. 01941 * @param __LTDC_CLKSOURCE__ specifies the DSI clock source. 01942 * This parameter can be one of the following values: 01943 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock 01944 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock 01945 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock 01946 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock 01947 * @retval None 01948 */ 01949 #define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ 01950 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (__LTDC_CLKSOURCE__)) 01951 01952 /** @brief Macro to get the LTDC clock source. 01953 * @retval The clock source can be one of the following values: 01954 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock 01955 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock 01956 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock 01957 * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock 01958 */ 01959 #define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR)) 01960 01961 #endif /* LTDC */ 01962 01963 #if defined(DSI) 01964 01965 /** @brief Macro to configure the DSI clock. 01966 * @param __DSI_CLKSOURCE__ specifies the DSI clock source. 01967 * This parameter can be one of the following values: 01968 * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock 01969 * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock 01970 * @retval None 01971 */ 01972 #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \ 01973 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (__DSI_CLKSOURCE__)) 01974 01975 /** @brief Macro to get the DSI clock source. 01976 * @retval The clock source can be one of the following values: 01977 * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock 01978 * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock 01979 */ 01980 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL)) 01981 01982 #endif /* DSI */ 01983 01984 #if defined(OCTOSPI1) || defined(OCTOSPI2) 01985 01986 /** @brief Macro to configure the OctoSPI clock. 01987 * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. 01988 * This parameter can be one of the following values: 01989 * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock 01990 * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock 01991 * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock 01992 * @retval None 01993 */ 01994 #define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ 01995 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (__OSPI_CLKSOURCE__)) 01996 01997 /** @brief Macro to get the OctoSPI clock source. 01998 * @retval The clock source can be one of the following values: 01999 * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock 02000 * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock 02001 * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock 02002 */ 02003 #define __HAL_RCC_GET_OSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL)) 02004 02005 #endif /* OCTOSPI1 || OCTOSPI2 */ 02006 02007 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management 02008 * @brief macros to manage the specified RCC Flags and interrupts. 02009 * @{ 02010 */ 02011 02012 /** @brief Enable PLLSAI1RDY interrupt. 02013 * @retval None 02014 */ 02015 #define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) 02016 02017 /** @brief Disable PLLSAI1RDY interrupt. 02018 * @retval None 02019 */ 02020 #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) 02021 02022 /** @brief Clear the PLLSAI1RDY interrupt pending bit. 02023 * @retval None 02024 */ 02025 #define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC) 02026 02027 /** @brief Check whether PLLSAI1RDY interrupt has occurred or not. 02028 * @retval TRUE or FALSE. 02029 */ 02030 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) 02031 02032 /** @brief Check whether the PLLSAI1RDY flag is set or not. 02033 * @retval TRUE or FALSE. 02034 */ 02035 #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) 02036 02037 #if defined(RCC_PLLSAI2_SUPPORT) 02038 02039 /** @brief Enable PLLSAI2RDY interrupt. 02040 * @retval None 02041 */ 02042 #define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) 02043 02044 /** @brief Disable PLLSAI2RDY interrupt. 02045 * @retval None 02046 */ 02047 #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) 02048 02049 /** @brief Clear the PLLSAI2RDY interrupt pending bit. 02050 * @retval None 02051 */ 02052 #define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC) 02053 02054 /** @brief Check whether the PLLSAI2RDY interrupt has occurred or not. 02055 * @retval TRUE or FALSE. 02056 */ 02057 #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) 02058 02059 /** @brief Check whether the PLLSAI2RDY flag is set or not. 02060 * @retval TRUE or FALSE. 02061 */ 02062 #define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY)) 02063 02064 #endif /* RCC_PLLSAI2_SUPPORT */ 02065 02066 02067 /** 02068 * @brief Enable the RCC LSE CSS Extended Interrupt Line. 02069 * @retval None 02070 */ 02071 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 02072 02073 /** 02074 * @brief Disable the RCC LSE CSS Extended Interrupt Line. 02075 * @retval None 02076 */ 02077 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 02078 02079 /** 02080 * @brief Enable the RCC LSE CSS Event Line. 02081 * @retval None. 02082 */ 02083 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 02084 02085 /** 02086 * @brief Disable the RCC LSE CSS Event Line. 02087 * @retval None. 02088 */ 02089 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 02090 02091 02092 /** 02093 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. 02094 * @retval None. 02095 */ 02096 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 02097 02098 02099 /** 02100 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 02101 * @retval None. 02102 */ 02103 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 02104 02105 02106 /** 02107 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. 02108 * @retval None. 02109 */ 02110 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 02111 02112 /** 02113 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 02114 * @retval None. 02115 */ 02116 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 02117 02118 /** 02119 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 02120 * @retval None. 02121 */ 02122 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ 02123 do { \ 02124 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ 02125 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ 02126 } while(0) 02127 02128 /** 02129 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 02130 * @retval None. 02131 */ 02132 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ 02133 do { \ 02134 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ 02135 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ 02136 } while(0) 02137 02138 /** 02139 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 02140 * @retval EXTI RCC LSE CSS Line Status. 02141 */ 02142 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) 02143 02144 /** 02145 * @brief Clear the RCC LSE CSS EXTI flag. 02146 * @retval None. 02147 */ 02148 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) 02149 02150 /** 02151 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. 02152 * @retval None. 02153 */ 02154 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) 02155 02156 02157 #if defined(CRS) 02158 02159 /** 02160 * @brief Enable the specified CRS interrupts. 02161 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 02162 * This parameter can be any combination of the following values: 02163 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 02164 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 02165 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 02166 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 02167 * @retval None 02168 */ 02169 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 02170 02171 /** 02172 * @brief Disable the specified CRS interrupts. 02173 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 02174 * This parameter can be any combination of the following values: 02175 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 02176 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 02177 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 02178 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 02179 * @retval None 02180 */ 02181 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 02182 02183 /** @brief Check whether the CRS interrupt has occurred or not. 02184 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 02185 * This parameter can be one of the following values: 02186 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 02187 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 02188 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 02189 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 02190 * @retval The new state of __INTERRUPT__ (SET or RESET). 02191 */ 02192 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) 02193 02194 /** @brief Clear the CRS interrupt pending bits 02195 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 02196 * This parameter can be any combination of the following values: 02197 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 02198 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 02199 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 02200 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 02201 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 02202 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 02203 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 02204 */ 02205 /* CRS IT Error Mask */ 02206 #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) 02207 02208 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 02209 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ 02210 { \ 02211 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 02212 } \ 02213 else \ 02214 { \ 02215 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 02216 } \ 02217 } while(0) 02218 02219 /** 02220 * @brief Check whether the specified CRS flag is set or not. 02221 * @param __FLAG__ specifies the flag to check. 02222 * This parameter can be one of the following values: 02223 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 02224 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 02225 * @arg @ref RCC_CRS_FLAG_ERR Error 02226 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 02227 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 02228 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 02229 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 02230 * @retval The new state of _FLAG_ (TRUE or FALSE). 02231 */ 02232 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 02233 02234 /** 02235 * @brief Clear the CRS specified FLAG. 02236 * @param __FLAG__ specifies the flag to clear. 02237 * This parameter can be one of the following values: 02238 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 02239 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 02240 * @arg @ref RCC_CRS_FLAG_ERR Error 02241 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 02242 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 02243 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 02244 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 02245 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 02246 * @retval None 02247 */ 02248 02249 /* CRS Flag Error Mask */ 02250 #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) 02251 02252 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 02253 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ 02254 { \ 02255 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 02256 } \ 02257 else \ 02258 { \ 02259 WRITE_REG(CRS->ICR, (__FLAG__)); \ 02260 } \ 02261 } while(0) 02262 02263 #endif /* CRS */ 02264 02265 /** 02266 * @} 02267 */ 02268 02269 #if defined(CRS) 02270 02271 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 02272 * @{ 02273 */ 02274 /** 02275 * @brief Enable the oscillator clock for frequency error counter. 02276 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 02277 * @retval None 02278 */ 02279 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 02280 02281 /** 02282 * @brief Disable the oscillator clock for frequency error counter. 02283 * @retval None 02284 */ 02285 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 02286 02287 /** 02288 * @brief Enable the automatic hardware adjustement of TRIM bits. 02289 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 02290 * @retval None 02291 */ 02292 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 02293 02294 /** 02295 * @brief Enable or disable the automatic hardware adjustement of TRIM bits. 02296 * @retval None 02297 */ 02298 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 02299 02300 /** 02301 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 02302 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 02303 * of the synchronization source after prescaling. It is then decreased by one in order to 02304 * reach the expected synchronization on the zero value. The formula is the following: 02305 * RELOAD = (fTARGET / fSYNC) -1 02306 * @param __FTARGET__ Target frequency (value in Hz) 02307 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 02308 * @retval None 02309 */ 02310 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 02311 02312 /** 02313 * @} 02314 */ 02315 02316 #endif /* CRS */ 02317 02318 /** 02319 * @} 02320 */ 02321 02322 /* Exported functions --------------------------------------------------------*/ 02323 /** @addtogroup RCCEx_Exported_Functions 02324 * @{ 02325 */ 02326 02327 /** @addtogroup RCCEx_Exported_Functions_Group1 02328 * @{ 02329 */ 02330 02331 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 02332 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 02333 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 02334 02335 /** 02336 * @} 02337 */ 02338 02339 /** @addtogroup RCCEx_Exported_Functions_Group2 02340 * @{ 02341 */ 02342 02343 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); 02344 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); 02345 02346 #if defined(RCC_PLLSAI2_SUPPORT) 02347 02348 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init); 02349 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void); 02350 02351 #endif /* RCC_PLLSAI2_SUPPORT */ 02352 02353 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); 02354 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); 02355 void HAL_RCCEx_EnableLSECSS(void); 02356 void HAL_RCCEx_DisableLSECSS(void); 02357 void HAL_RCCEx_EnableLSECSS_IT(void); 02358 void HAL_RCCEx_LSECSS_IRQHandler(void); 02359 void HAL_RCCEx_LSECSS_Callback(void); 02360 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 02361 void HAL_RCCEx_DisableLSCO(void); 02362 void HAL_RCCEx_EnableMSIPLLMode(void); 02363 void HAL_RCCEx_DisableMSIPLLMode(void); 02364 02365 /** 02366 * @} 02367 */ 02368 02369 #if defined(CRS) 02370 02371 /** @addtogroup RCCEx_Exported_Functions_Group3 02372 * @{ 02373 */ 02374 02375 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 02376 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 02377 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 02378 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 02379 void HAL_RCCEx_CRS_IRQHandler(void); 02380 void HAL_RCCEx_CRS_SyncOkCallback(void); 02381 void HAL_RCCEx_CRS_SyncWarnCallback(void); 02382 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 02383 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 02384 02385 /** 02386 * @} 02387 */ 02388 02389 #endif /* CRS */ 02390 02391 /** 02392 * @} 02393 */ 02394 02395 /* Private macros ------------------------------------------------------------*/ 02396 /** @addtogroup RCCEx_Private_Macros 02397 * @{ 02398 */ 02399 02400 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 02401 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 02402 02403 #if defined(STM32L431xx) 02404 02405 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 02406 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 02407 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 02408 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 02409 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 02410 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 02411 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 02412 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 02413 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 02414 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 02415 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 02416 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 02417 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ 02418 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 02419 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 02420 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) 02421 02422 #elif defined(STM32L432xx) || defined(STM32L442xx) 02423 02424 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 02425 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 02426 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 02427 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 02428 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 02429 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 02430 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 02431 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 02432 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 02433 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 02434 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 02435 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ 02436 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 02437 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)) 02438 02439 #elif defined(STM32L433xx) || defined(STM32L443xx) 02440 02441 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 02442 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 02443 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 02444 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 02445 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 02446 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 02447 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 02448 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 02449 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 02450 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 02451 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 02452 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 02453 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 02454 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ 02455 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 02456 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 02457 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) 02458 02459 #elif defined(STM32L451xx) 02460 02461 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 02462 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 02463 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 02464 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 02465 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 02466 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 02467 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 02468 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 02469 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 02470 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 02471 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 02472 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 02473 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 02474 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 02475 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 02476 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 02477 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 02478 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) 02479 02480 #elif defined(STM32L452xx) || defined(STM32L462xx) 02481 02482 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 02483 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 02484 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 02485 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 02486 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 02487 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 02488 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 02489 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 02490 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 02491 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 02492 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 02493 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 02494 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 02495 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 02496 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 02497 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 02498 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 02499 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 02500 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) 02501 02502 #elif defined(STM32L471xx) 02503 02504 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 02505 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 02506 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 02507 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 02508 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 02509 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 02510 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 02511 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 02512 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 02513 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 02514 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 02515 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 02516 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 02517 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 02518 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 02519 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ 02520 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 02521 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 02522 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 02523 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) 02524 02525 #elif defined(STM32L496xx) || defined(STM32L4A6xx) 02526 02527 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 02528 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 02529 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 02530 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 02531 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 02532 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 02533 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 02534 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 02535 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 02536 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 02537 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 02538 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 02539 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 02540 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 02541 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 02542 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 02543 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 02544 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ 02545 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 02546 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 02547 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 02548 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) 02549 02550 #elif defined(STM32L4R5xx) || defined(STM32L4S5xx) 02551 02552 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 02553 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 02554 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 02555 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 02556 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 02557 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 02558 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 02559 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 02560 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 02561 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 02562 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 02563 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 02564 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 02565 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 02566 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 02567 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 02568 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 02569 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 02570 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ 02571 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 02572 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 02573 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ 02574 (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)) 02575 02576 #elif defined(STM32L4R7xx) || defined(STM32L4S7xx) 02577 02578 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 02579 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 02580 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 02581 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 02582 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 02583 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 02584 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 02585 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 02586 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 02587 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 02588 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 02589 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 02590 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 02591 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 02592 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 02593 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 02594 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 02595 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 02596 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ 02597 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 02598 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 02599 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ 02600 (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \ 02601 (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) 02602 02603 #elif defined(STM32L4R9xx) || defined(STM32L4S9xx) 02604 02605 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 02606 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 02607 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 02608 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 02609 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 02610 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 02611 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 02612 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 02613 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 02614 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 02615 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 02616 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 02617 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 02618 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 02619 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 02620 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 02621 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 02622 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 02623 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ 02624 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 02625 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 02626 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ 02627 (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \ 02628 (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ 02629 (((__SELECTION__) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)) 02630 02631 #else 02632 02633 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 02634 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 02635 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 02636 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 02637 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 02638 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 02639 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 02640 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 02641 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 02642 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 02643 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 02644 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ 02645 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 02646 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 02647 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 02648 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 02649 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ 02650 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 02651 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 02652 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 02653 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) 02654 02655 #endif /* STM32L431xx */ 02656 02657 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 02658 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 02659 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 02660 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 02661 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) 02662 02663 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 02664 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 02665 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ 02666 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ 02667 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) 02668 02669 #if defined(USART3) 02670 02671 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ 02672 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 02673 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ 02674 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ 02675 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) 02676 02677 #endif /* USART3 */ 02678 02679 #if defined(UART4) 02680 02681 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ 02682 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ 02683 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ 02684 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ 02685 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) 02686 02687 #endif /* UART4 */ 02688 02689 #if defined(UART5) 02690 02691 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ 02692 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ 02693 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ 02694 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ 02695 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) 02696 02697 #endif /* UART5 */ 02698 02699 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 02700 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ 02701 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ 02702 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 02703 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) 02704 02705 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 02706 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 02707 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ 02708 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) 02709 02710 #if defined(I2C2) 02711 02712 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 02713 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 02714 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ 02715 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) 02716 02717 #endif /* I2C2 */ 02718 02719 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ 02720 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ 02721 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ 02722 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) 02723 02724 #if defined(I2C4) 02725 02726 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ 02727 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ 02728 ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ 02729 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) 02730 02731 #endif /* I2C4 */ 02732 02733 #if defined(RCC_PLLSAI2_SUPPORT) 02734 02735 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 02736 #define IS_RCC_SAI1CLK(__SOURCE__) \ 02737 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ 02738 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ 02739 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 02740 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ 02741 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) 02742 #else 02743 #define IS_RCC_SAI1CLK(__SOURCE__) \ 02744 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ 02745 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ 02746 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 02747 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) 02748 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 02749 02750 #else 02751 02752 #define IS_RCC_SAI1CLK(__SOURCE__) \ 02753 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ 02754 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 02755 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) 02756 02757 #endif /* RCC_PLLSAI2_SUPPORT */ 02758 02759 #if defined(RCC_PLLSAI2_SUPPORT) 02760 02761 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 02762 #define IS_RCC_SAI2CLK(__SOURCE__) \ 02763 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ 02764 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ 02765 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ 02766 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ 02767 ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)) 02768 #else 02769 #define IS_RCC_SAI2CLK(__SOURCE__) \ 02770 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ 02771 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ 02772 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ 02773 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) 02774 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 02775 02776 #endif /* RCC_PLLSAI2_SUPPORT */ 02777 02778 #define IS_RCC_LPTIM1CLK(__SOURCE__) \ 02779 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 02780 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 02781 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ 02782 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) 02783 02784 #define IS_RCC_LPTIM2CLK(__SOURCE__) \ 02785 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ 02786 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ 02787 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ 02788 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) 02789 02790 #if defined(SDMMC1) 02791 #if defined(RCC_HSI48_SUPPORT) && defined(RCC_CCIPR2_SDMMCSEL) 02792 02793 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 02794 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) || \ 02795 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ 02796 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ 02797 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ 02798 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) 02799 02800 #elif defined(RCC_HSI48_SUPPORT) 02801 02802 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 02803 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ 02804 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ 02805 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ 02806 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) 02807 #else 02808 02809 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ 02810 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) || \ 02811 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ 02812 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ 02813 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) 02814 02815 #endif /* RCC_HSI48_SUPPORT */ 02816 #endif /* SDMMC1 */ 02817 02818 #if defined(RCC_HSI48_SUPPORT) 02819 02820 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 02821 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 02822 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ 02823 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ 02824 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) 02825 02826 #else 02827 02828 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 02829 (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \ 02830 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ 02831 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ 02832 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) 02833 02834 #endif /* RCC_HSI48_SUPPORT */ 02835 02836 #if defined(USB_OTG_FS) || defined(USB) 02837 #if defined(RCC_HSI48_SUPPORT) 02838 02839 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 02840 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 02841 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ 02842 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ 02843 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) 02844 02845 #else 02846 02847 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 02848 (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \ 02849 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ 02850 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ 02851 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) 02852 02853 #endif /* RCC_HSI48_SUPPORT */ 02854 #endif /* USB_OTG_FS || USB */ 02855 02856 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 02857 02858 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 02859 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 02860 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ 02861 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \ 02862 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 02863 02864 #else 02865 02866 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ 02867 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ 02868 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ 02869 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) 02870 02871 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ 02872 02873 #if defined(SWPMI1) 02874 02875 #define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \ 02876 (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK1) || \ 02877 ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI)) 02878 02879 #endif /* SWPMI1 */ 02880 02881 #if defined(DFSDM1_Filter0) 02882 02883 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \ 02884 (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ 02885 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) 02886 02887 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 02888 02889 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) \ 02890 (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ 02891 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \ 02892 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI)) 02893 02894 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 02895 02896 #endif /* DFSDM1_Filter0 */ 02897 02898 #if defined(LTDC) 02899 02900 #define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ 02901 (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV2) || \ 02902 ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV4) || \ 02903 ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV8) || \ 02904 ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV16)) 02905 02906 #endif /* LTDC */ 02907 02908 #if defined(DSI) 02909 02910 #define IS_RCC_DSICLKSOURCE(__SOURCE__) \ 02911 (((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY) || \ 02912 ((__SOURCE__) == RCC_DSICLKSOURCE_PLLSAI2)) 02913 02914 #endif /* DSI */ 02915 02916 #if defined(OCTOSPI1) || defined(OCTOSPI2) 02917 02918 #define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ 02919 (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \ 02920 ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \ 02921 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)) 02922 02923 #endif /* OCTOSPI1 || OCTOSPI2 */ 02924 02925 #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) 02926 02927 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 02928 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 02929 #else 02930 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) 02931 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 02932 02933 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 02934 02935 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 02936 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 02937 #else 02938 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) 02939 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 02940 02941 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 02942 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 02943 02944 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 02945 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 02946 02947 #if defined(RCC_PLLSAI2_SUPPORT) 02948 02949 #define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) 02950 02951 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 02952 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 02953 #else 02954 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) 02955 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 02956 02957 #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 02958 02959 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 02960 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 02961 #else 02962 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) 02963 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ 02964 02965 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 02966 #define IS_RCC_PLLSAI2Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 02967 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 02968 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 02969 02970 #define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 02971 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 02972 02973 #endif /* RCC_PLLSAI2_SUPPORT */ 02974 02975 #if defined(CRS) 02976 02977 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 02978 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 02979 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) 02980 02981 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 02982 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 02983 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 02984 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 02985 02986 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 02987 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 02988 02989 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 02990 02991 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 02992 02993 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) 02994 02995 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 02996 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 02997 02998 #endif /* CRS */ 02999 03000 /** 03001 * @} 03002 */ 03003 03004 /** 03005 * @} 03006 */ 03007 03008 /** 03009 * @} 03010 */ 03011 03012 #ifdef __cplusplus 03013 } 03014 #endif 03015 03016 #endif /* __STM32L4xx_HAL_RCC_EX_H */ 03017 03018 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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