STM32L486xx HAL User Manual
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Defines | |
#define | __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) |
Helper macro to calculate the PLLCLK frequency on system domain. | |
#define | __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) |
Helper macro to calculate the PLLCLK frequency used on SAI domain. | |
#define | __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) |
Helper macro to calculate the PLLCLK frequency used on 48M domain. | |
#define | __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) |
Helper macro to calculate the PLLSAI1 frequency used for SAI domain. | |
#define | __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) |
Helper macro to calculate the PLLSAI1 frequency used on 48M domain. | |
#define | __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) |
Helper macro to calculate the PLLSAI1 frequency used on ADC domain. | |
#define | __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) |
Helper macro to calculate the PLLSAI2 frequency used for SAI domain. | |
#define | __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) |
Helper macro to calculate the PLLSAI2 frequency used on ADC domain. | |
#define | __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) |
Helper macro to calculate the HCLK frequency. | |
#define | __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) |
Helper macro to calculate the PCLK1 frequency (ABP1) | |
#define | __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) |
Helper macro to calculate the PCLK2 frequency (ABP2) | |
#define | __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) |
Helper macro to calculate the MSI frequency (in Hz) |
#define __LL_RCC_CALC_HCLK_FREQ | ( | __SYSCLKFREQ__, | |
__AHBPRESCALER__ | |||
) | ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) |
Helper macro to calculate the HCLK frequency.
__SYSCLKFREQ__ | SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) |
__AHBPRESCALER__ | This parameter can be one of the following values: |
HCLK | clock frequency (in Hz) |
Definition at line 1921 of file stm32l4xx_ll_rcc.h.
Referenced by RCC_GetHCLKClockFreq(), and UTILS_EnablePLLAndSwitchSystem().
#define __LL_RCC_CALC_MSI_FREQ | ( | __MSISEL__, | |
__MSIRANGE__ | |||
) |
(((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \ (MSIRangeTable[(__MSIRANGE__) >> 8U]) : \ (MSIRangeTable[(__MSIRANGE__) >> 4U]))
Helper macro to calculate the MSI frequency (in Hz)
__MSISEL__ | This parameter can be one of the following values: |
__MSIRANGE__ | This parameter can be one of the following values: |
MSI | clock frequency (in Hz) |
Definition at line 1981 of file stm32l4xx_ll_rcc.h.
Referenced by LL_PLL_ConfigSystemClock_MSI(), LL_RCC_GetRNGClockFreq(), LL_RCC_GetSDMMCClockFreq(), LL_RCC_GetUSBClockFreq(), RCC_GetSystemClockFreq(), RCC_PLL_GetFreqDomain_48M(), RCC_PLL_GetFreqDomain_SAI(), RCC_PLL_GetFreqDomain_SYS(), RCC_PLLSAI1_GetFreqDomain_48M(), RCC_PLLSAI1_GetFreqDomain_ADC(), RCC_PLLSAI1_GetFreqDomain_SAI(), RCC_PLLSAI2_GetFreqDomain_ADC(), and RCC_PLLSAI2_GetFreqDomain_SAI().
#define __LL_RCC_CALC_PCLK1_FREQ | ( | __HCLKFREQ__, | |
__APB1PRESCALER__ | |||
) | ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) |
Helper macro to calculate the PCLK1 frequency (ABP1)
__HCLKFREQ__ | HCLK frequency |
__APB1PRESCALER__ | This parameter can be one of the following values: |
PCLK1 | clock frequency (in Hz) |
Definition at line 1934 of file stm32l4xx_ll_rcc.h.
Referenced by RCC_GetPCLK1ClockFreq().
#define __LL_RCC_CALC_PCLK2_FREQ | ( | __HCLKFREQ__, | |
__APB2PRESCALER__ | |||
) | ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) |
Helper macro to calculate the PCLK2 frequency (ABP2)
__HCLKFREQ__ | HCLK frequency |
__APB2PRESCALER__ | This parameter can be one of the following values: |
PCLK2 | clock frequency (in Hz) |
Definition at line 1947 of file stm32l4xx_ll_rcc.h.
Referenced by RCC_GetPCLK2ClockFreq().
#define __LL_RCC_CALC_PLLCLK_48M_FREQ | ( | __INPUTFREQ__, | |
__PLLM__, | |||
__PLLN__, | |||
__PLLQ__ | |||
) |
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
Helper macro to calculate the PLLCLK frequency used on 48M domain.
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI) |
__PLLM__ | This parameter can be one of the following values:
|
__PLLN__ | Between 8 and 86 |
__PLLQ__ | This parameter can be one of the following values: |
PLL | clock frequency (in Hz) |
Definition at line 1387 of file stm32l4xx_ll_rcc.h.
Referenced by RCC_PLL_GetFreqDomain_48M().
#define __LL_RCC_CALC_PLLCLK_FREQ | ( | __INPUTFREQ__, | |
__PLLM__, | |||
__PLLN__, | |||
__PLLR__ | |||
) |
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
Helper macro to calculate the PLLCLK frequency on system domain.
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI) |
__PLLM__ | This parameter can be one of the following values:
|
__PLLN__ | Between 8 and 86 |
__PLLR__ | This parameter can be one of the following values: |
PLL | clock frequency (in Hz) |
Definition at line 1264 of file stm32l4xx_ll_rcc.h.
Referenced by RCC_PLL_GetFreqDomain_SYS().
#define __LL_RCC_CALC_PLLCLK_SAI_FREQ | ( | __INPUTFREQ__, | |
__PLLM__, | |||
__PLLN__, | |||
__PLLP__ | |||
) |
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U))
Helper macro to calculate the PLLCLK frequency used on SAI domain.
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI) |
__PLLM__ | This parameter can be one of the following values: |
__PLLN__ | Between 8 and 86 |
__PLLP__ | This parameter can be one of the following values: |
PLL | clock frequency (in Hz) |
Definition at line 1350 of file stm32l4xx_ll_rcc.h.
Referenced by RCC_PLL_GetFreqDomain_SAI().
#define __LL_RCC_CALC_PLLSAI1_48M_FREQ | ( | __INPUTFREQ__, | |
__PLLM__, | |||
__PLLSAI1N__, | |||
__PLLSAI1Q__ | |||
) |
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
Helper macro to calculate the PLLSAI1 frequency used on 48M domain.
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI) |
__PLLM__ | This parameter can be one of the following values: |
__PLLSAI1N__ | Between 8 and 86 |
__PLLSAI1Q__ | This parameter can be one of the following values: |
PLLSAI1 | clock frequency (in Hz) |
Definition at line 1589 of file stm32l4xx_ll_rcc.h.
Referenced by RCC_PLLSAI1_GetFreqDomain_48M().
#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ | ( | __INPUTFREQ__, | |
__PLLM__, | |||
__PLLSAI1N__, | |||
__PLLSAI1R__ | |||
) |
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
Helper macro to calculate the PLLSAI1 frequency used on ADC domain.
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI) |
__PLLM__ | This parameter can be one of the following values: |
__PLLSAI1N__ | Between 8 and 86 |
__PLLSAI1R__ | This parameter can be one of the following values: |
PLLSAI1 | clock frequency (in Hz) |
Definition at line 1653 of file stm32l4xx_ll_rcc.h.
Referenced by RCC_PLLSAI1_GetFreqDomain_ADC().
#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ | ( | __INPUTFREQ__, | |
__PLLM__, | |||
__PLLSAI1N__, | |||
__PLLSAI1P__ | |||
) |
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ (((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7U : 17U))
Helper macro to calculate the PLLSAI1 frequency used for SAI domain.
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI) |
__PLLM__ | This parameter can be one of the following values: |
__PLLSAI1N__ | Between 8 and 86 |
__PLLSAI1P__ | This parameter can be one of the following values: |
PLLSAI1 | clock frequency (in Hz) |
Definition at line 1525 of file stm32l4xx_ll_rcc.h.
Referenced by RCC_PLLSAI1_GetFreqDomain_SAI().
#define __LL_RCC_CALC_PLLSAI2_ADC_FREQ | ( | __INPUTFREQ__, | |
__PLLM__, | |||
__PLLSAI2N__, | |||
__PLLSAI2R__ | |||
) |
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \ ((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U))
Helper macro to calculate the PLLSAI2 frequency used on ADC domain.
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI) |
__PLLM__ | This parameter can be one of the following values: |
__PLLSAI2N__ | Between 8 and 86 |
__PLLSAI2R__ | This parameter can be one of the following values: |
PLLSAI2 | clock frequency (in Hz) |
Definition at line 1862 of file stm32l4xx_ll_rcc.h.
Referenced by RCC_PLLSAI2_GetFreqDomain_ADC().
#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ | ( | __INPUTFREQ__, | |
__PLLM__, | |||
__PLLSAI2N__, | |||
__PLLSAI2P__ | |||
) |
((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \ (((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U))
Helper macro to calculate the PLLSAI2 frequency used for SAI domain.
__INPUTFREQ__ | PLL Input frequency (based on MSI/HSE/HSI) |
__PLLM__ | This parameter can be one of the following values: |
__PLLSAI2N__ | Between 8 and 86 |
__PLLSAI2P__ | This parameter can be one of the following values: |
PLLSAI2 | clock frequency (in Hz) |
Definition at line 1794 of file stm32l4xx_ll_rcc.h.
Referenced by RCC_PLLSAI2_GetFreqDomain_SAI().