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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_rcc.h 00004 * @author MCD Application Team 00005 * @brief Header file of RCC LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_LL_RCC_H 00038 #define __STM32L4xx_LL_RCC_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx.h" 00046 00047 /** @addtogroup STM32L4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined(RCC) 00052 00053 /** @defgroup RCC_LL RCC 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 /** @defgroup RCC_LL_Private_Variables RCC Private Variables 00060 * @{ 00061 */ 00062 00063 #if defined(RCC_CCIPR2_PLLSAI2DIVR) 00064 static const uint8_t aRCC_PLLSAI2DIVRPrescTable[4] = {2, 4, 8, 16}; 00065 #endif /* RCC_CCIPR2_PLLSAI2DIVR */ 00066 00067 /** 00068 * @} 00069 */ 00070 00071 /* Private constants ---------------------------------------------------------*/ 00072 /** @defgroup RCC_LL_Private_Constants RCC Private Constants 00073 * @{ 00074 */ 00075 /* Defines used to perform offsets*/ 00076 /* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */ 00077 #define RCC_OFFSET_CCIPR 0U 00078 #define RCC_OFFSET_CCIPR2 0x14U 00079 00080 /** 00081 * @} 00082 */ 00083 00084 /* Private macros ------------------------------------------------------------*/ 00085 #if defined(USE_FULL_LL_DRIVER) 00086 /** @defgroup RCC_LL_Private_Macros RCC Private Macros 00087 * @{ 00088 */ 00089 /** 00090 * @} 00091 */ 00092 #endif /*USE_FULL_LL_DRIVER*/ 00093 00094 /* Exported types ------------------------------------------------------------*/ 00095 #if defined(USE_FULL_LL_DRIVER) 00096 /** @defgroup RCC_LL_Exported_Types RCC Exported Types 00097 * @{ 00098 */ 00099 00100 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure 00101 * @{ 00102 */ 00103 00104 /** 00105 * @brief RCC Clocks Frequency Structure 00106 */ 00107 typedef struct 00108 { 00109 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ 00110 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ 00111 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ 00112 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ 00113 } LL_RCC_ClocksTypeDef; 00114 00115 /** 00116 * @} 00117 */ 00118 00119 /** 00120 * @} 00121 */ 00122 #endif /* USE_FULL_LL_DRIVER */ 00123 00124 /* Exported constants --------------------------------------------------------*/ 00125 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants 00126 * @{ 00127 */ 00128 00129 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation 00130 * @brief Defines used to adapt values of different oscillators 00131 * @note These values could be modified in the user environment according to 00132 * HW set-up. 00133 * @{ 00134 */ 00135 #if !defined (HSE_VALUE) 00136 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ 00137 #endif /* HSE_VALUE */ 00138 00139 #if !defined (HSI_VALUE) 00140 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ 00141 #endif /* HSI_VALUE */ 00142 00143 #if !defined (LSE_VALUE) 00144 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ 00145 #endif /* LSE_VALUE */ 00146 00147 #if !defined (LSI_VALUE) 00148 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ 00149 #endif /* LSI_VALUE */ 00150 #if defined(RCC_HSI48_SUPPORT) 00151 00152 #if !defined (HSI48_VALUE) 00153 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ 00154 #endif /* HSI48_VALUE */ 00155 #endif /* RCC_HSI48_SUPPORT */ 00156 00157 #if !defined (EXTERNAL_SAI1_CLOCK_VALUE) 00158 #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */ 00159 #endif /* EXTERNAL_SAI1_CLOCK_VALUE */ 00160 00161 #if !defined (EXTERNAL_SAI2_CLOCK_VALUE) 00162 #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */ 00163 #endif /* EXTERNAL_SAI2_CLOCK_VALUE */ 00164 /** 00165 * @} 00166 */ 00167 00168 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines 00169 * @brief Flags defines which can be used with LL_RCC_WriteReg function 00170 * @{ 00171 */ 00172 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */ 00173 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ 00174 #define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */ 00175 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ 00176 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ 00177 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ 00178 #if defined(RCC_HSI48_SUPPORT) 00179 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ 00180 #endif /* RCC_HSI48_SUPPORT */ 00181 #define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */ 00182 #if defined(RCC_PLLSAI2_SUPPORT) 00183 #define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC /*!< PLLSAI2 Ready Interrupt Clear */ 00184 #endif /* RCC_PLLSAI2_SUPPORT */ 00185 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */ 00186 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */ 00187 /** 00188 * @} 00189 */ 00190 00191 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines 00192 * @brief Flags defines which can be used with LL_RCC_ReadReg function 00193 * @{ 00194 */ 00195 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 00196 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 00197 #define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 00198 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ 00199 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 00200 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 00201 #if defined(RCC_HSI48_SUPPORT) 00202 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 00203 #endif /* RCC_HSI48_SUPPORT */ 00204 #define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ 00205 #if defined(RCC_PLLSAI2_SUPPORT) 00206 #define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ 00207 #endif /* RCC_PLLSAI2_SUPPORT */ 00208 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 00209 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ 00210 #define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /*!< Firewall reset flag */ 00211 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ 00212 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ 00213 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ 00214 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ 00215 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 00216 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 00217 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ 00218 /** 00219 * @} 00220 */ 00221 00222 /** @defgroup RCC_LL_EC_IT IT Defines 00223 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions 00224 * @{ 00225 */ 00226 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */ 00227 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */ 00228 #define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */ 00229 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */ 00230 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */ 00231 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */ 00232 #if defined(RCC_HSI48_SUPPORT) 00233 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ 00234 #endif /* RCC_HSI48_SUPPORT */ 00235 #define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */ 00236 #if defined(RCC_PLLSAI2_SUPPORT) 00237 #define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE /*!< PLLSAI2 Ready Interrupt Enable */ 00238 #endif /* RCC_PLLSAI2_SUPPORT */ 00239 #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */ 00240 /** 00241 * @} 00242 */ 00243 00244 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability 00245 * @{ 00246 */ 00247 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */ 00248 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */ 00249 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */ 00250 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ 00251 /** 00252 * @} 00253 */ 00254 00255 /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges 00256 * @{ 00257 */ 00258 #define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */ 00259 #define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */ 00260 #define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */ 00261 #define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */ 00262 #define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */ 00263 #define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */ 00264 #define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */ 00265 #define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */ 00266 #define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */ 00267 #define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */ 00268 #define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */ 00269 #define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */ 00270 /** 00271 * @} 00272 */ 00273 00274 /** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode 00275 * @{ 00276 */ 00277 #define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1 /*!< MSI = 1 MHz */ 00278 #define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2 /*!< MSI = 2 MHz */ 00279 #define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4 /*!< MSI = 4 MHz */ 00280 #define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8 /*!< MSI = 8 MHz */ 00281 /** 00282 * @} 00283 */ 00284 00285 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection 00286 * @{ 00287 */ 00288 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */ 00289 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */ 00290 /** 00291 * @} 00292 */ 00293 00294 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch 00295 * @{ 00296 */ 00297 #define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ 00298 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ 00299 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ 00300 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ 00301 /** 00302 * @} 00303 */ 00304 00305 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status 00306 * @{ 00307 */ 00308 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ 00309 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 00310 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 00311 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 00312 /** 00313 * @} 00314 */ 00315 00316 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler 00317 * @{ 00318 */ 00319 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 00320 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 00321 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 00322 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 00323 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 00324 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 00325 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 00326 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 00327 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 00328 /** 00329 * @} 00330 */ 00331 00332 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) 00333 * @{ 00334 */ 00335 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 00336 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 00337 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 00338 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 00339 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 00340 /** 00341 * @} 00342 */ 00343 00344 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) 00345 * @{ 00346 */ 00347 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ 00348 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ 00349 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ 00350 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ 00351 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ 00352 /** 00353 * @} 00354 */ 00355 00356 /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection 00357 * @{ 00358 */ 00359 #define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ 00360 #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ 00361 /** 00362 * @} 00363 */ 00364 00365 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection 00366 * @{ 00367 */ 00368 #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */ 00369 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 00370 #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ 00371 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */ 00372 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ 00373 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */ 00374 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ 00375 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ 00376 #if defined(RCC_HSI48_SUPPORT) 00377 #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ 00378 #endif /* RCC_HSI48_SUPPORT */ 00379 /** 00380 * @} 00381 */ 00382 00383 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler 00384 * @{ 00385 */ 00386 #define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ 00387 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ 00388 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ 00389 #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ 00390 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */ 00391 /** 00392 * @} 00393 */ 00394 00395 #if defined(USE_FULL_LL_DRIVER) 00396 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency 00397 * @{ 00398 */ 00399 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ 00400 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ 00401 /** 00402 * @} 00403 */ 00404 #endif /* USE_FULL_LL_DRIVER */ 00405 00406 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection 00407 * @{ 00408 */ 00409 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */ 00410 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */ 00411 #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */ 00412 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */ 00413 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */ 00414 #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */ 00415 #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */ 00416 #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */ 00417 #if defined(RCC_CCIPR_USART3SEL) 00418 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U) /*!< PCLK1 clock used as USART3 clock source */ 00419 #define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */ 00420 #define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */ 00421 #define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */ 00422 #endif /* RCC_CCIPR_USART3SEL */ 00423 /** 00424 * @} 00425 */ 00426 00427 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL) 00428 /** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection 00429 * @{ 00430 */ 00431 #if defined(RCC_CCIPR_UART4SEL) 00432 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */ 00433 #define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */ 00434 #define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1) /*!< HSI clock used as UART4 clock source */ 00435 #define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL) /*!< LSE clock used as UART4 clock source */ 00436 #endif /* RCC_CCIPR_UART4SEL */ 00437 #if defined(RCC_CCIPR_UART5SEL) 00438 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */ 00439 #define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */ 00440 #define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_1) /*!< HSI clock used as UART5 clock source */ 00441 #define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL) /*!< LSE clock used as UART5 clock source */ 00442 #endif /* RCC_CCIPR_UART5SEL */ 00443 /** 00444 * @} 00445 */ 00446 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */ 00447 00448 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection 00449 * @{ 00450 */ 00451 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPUART1 clock source */ 00452 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */ 00453 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */ 00454 #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE clock used as LPUART1 clock source */ 00455 /** 00456 * @} 00457 */ 00458 00459 /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection 00460 * @{ 00461 */ 00462 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */ 00463 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */ 00464 #define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */ 00465 #if defined(RCC_CCIPR_I2C2SEL) 00466 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */ 00467 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */ 00468 #define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */ 00469 #endif /* RCC_CCIPR_I2C2SEL */ 00470 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */ 00471 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */ 00472 #define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */ 00473 #if defined(RCC_CCIPR2_I2C4SEL) 00474 #define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */ 00475 #define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */ 00476 #define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */ 00477 #endif /* RCC_CCIPR2_I2C4SEL */ 00478 /** 00479 * @} 00480 */ 00481 00482 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection 00483 * @{ 00484 */ 00485 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM1SEL /*!< PCLK1 clock used as LPTIM1 clock source */ 00486 #define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /*!< LSI clock used as LPTIM1 clock source */ 00487 #define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /*!< HSI clock used as LPTIM1 clock source */ 00488 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U)) /*!< LSE clock used as LPTIM1 clock source */ 00489 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM2SEL /*!< PCLK1 clock used as LPTIM2 clock source */ 00490 #define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /*!< LSI clock used as LPTIM2 clock source */ 00491 #define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /*!< HSI clock used as LPTIM2 clock source */ 00492 #define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U)) /*!< LSE clock used as LPTIM2 clock source */ 00493 /** 00494 * @} 00495 */ 00496 00497 /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection 00498 * @{ 00499 */ 00500 #if defined(RCC_CCIPR2_SAI1SEL) 00501 #define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLL clock used as SAI1 clock source */ 00502 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLLSAI1 clock used as SAI1 clock source */ 00503 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLLSAI2 clock used as SAI1 clock source */ 00504 #define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */ 00505 #define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */ 00506 #else 00507 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL /*!< PLLSAI1 clock used as SAI1 clock source */ 00508 #if defined(RCC_PLLSAI2_SUPPORT) 00509 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI1 clock source */ 00510 #endif /* RCC_PLLSAI2_SUPPORT */ 00511 #define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16U)) /*!< PLL clock used as SAI1 clock source */ 00512 #define LL_RCC_SAI1_CLKSOURCE_PIN (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16U)) /*!< External input clock used as SAI1 clock source */ 00513 #endif /* RCC_CCIPR2_SAI1SEL */ 00514 00515 #if defined(RCC_CCIPR2_SAI2SEL) 00516 #define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLL clock used as SAI2 clock source */ 00517 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLLSAI1 clock used as SAI2 clock source */ 00518 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLLSAI2 clock used as SAI2 clock source */ 00519 #define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */ 00520 #define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0)) /*!< External input clock used as SAI2 clock source */ 00521 #elif defined(RCC_CCIPR_SAI2SEL) 00522 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI2SEL /*!< PLLSAI1 clock used as SAI2 clock source */ 00523 #if defined(RCC_PLLSAI2_SUPPORT) 00524 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16U)) /*!< PLLSAI2 clock used as SAI2 clock source */ 00525 #endif /* RCC_PLLSAI2_SUPPORT */ 00526 #define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16U)) /*!< PLL clock used as SAI2 clock source */ 00527 #define LL_RCC_SAI2_CLKSOURCE_PIN (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16U)) /*!< External input clock used as SAI2 clock source */ 00528 #endif /* RCC_CCIPR2_SAI2SEL */ 00529 /** 00530 * @} 00531 */ 00532 00533 #if defined(RCC_CCIPR2_SDMMCSEL) 00534 /** @defgroup RCC_LL_EC_SDMMC1_KERNELCLKSOURCE Peripheral SDMMC kernel clock source selection 00535 * @{ 00536 */ 00537 #define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK 0x00000000U /*!< 48MHz clock from internal multiplexor used as SDMMC1 clock source */ 00538 #define LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLLSAI3CLK clock used as SDMMC1 clock source */ 00539 /** 00540 * @} 00541 */ 00542 #endif /* RCC_CCIPR2_SDMMCSEL */ 00543 00544 /** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection 00545 * @{ 00546 */ 00547 #if defined(RCC_HSI48_SUPPORT) 00548 #define LL_RCC_SDMMC1_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as SDMMC1 clock source */ 00549 #else 00550 #define LL_RCC_SDMMC1_CLKSOURCE_NONE 0x00000000U /*!< No clock used as SDMMC1 clock source */ 00551 #endif 00552 #define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as SDMMC1 clock source */ 00553 #define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as SDMMC1 clock source */ 00554 #define LL_RCC_SDMMC1_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as SDMMC1 clock source */ 00555 /** 00556 * @} 00557 */ 00558 00559 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection 00560 * @{ 00561 */ 00562 #if defined(RCC_HSI48_SUPPORT) 00563 #define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */ 00564 #else 00565 #define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RNG clock source */ 00566 #endif 00567 #define LL_RCC_RNG_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as RNG clock source */ 00568 #define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock source */ 00569 #define LL_RCC_RNG_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as RNG clock source */ 00570 /** 00571 * @} 00572 */ 00573 00574 #if defined(USB_OTG_FS) || defined(USB) 00575 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection 00576 * @{ 00577 */ 00578 #if defined(RCC_HSI48_SUPPORT) 00579 #define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */ 00580 #else 00581 #define LL_RCC_USB_CLKSOURCE_NONE 0x00000000U /*!< No clock used as USB clock source */ 00582 #endif 00583 #define LL_RCC_USB_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as USB clock source */ 00584 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock source */ 00585 #define LL_RCC_USB_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock used as USB clock source */ 00586 /** 00587 * @} 00588 */ 00589 00590 #endif /* USB_OTG_FS || USB */ 00591 00592 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection 00593 * @{ 00594 */ 00595 #define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as ADC clock source */ 00596 #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 clock used as ADC clock source */ 00597 #if defined(RCC_PLLSAI2_SUPPORT) && !defined(LTDC) 00598 #define LL_RCC_ADC_CLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 /*!< PLLSAI2 clock used as ADC clock source */ 00599 #endif /* RCC_PLLSAI2_SUPPORT */ 00600 #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK clock used as ADC clock source */ 00601 /** 00602 * @} 00603 */ 00604 00605 #if defined(SWPMI1) 00606 /** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE Peripheral SWPMI1 clock source selection 00607 * @{ 00608 */ 00609 #define LL_RCC_SWPMI1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 used as SWPMI1 clock source */ 00610 #define LL_RCC_SWPMI1_CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL /*!< HSI used as SWPMI1 clock source */ 00611 /** 00612 * @} 00613 */ 00614 #endif /* SWPMI1 */ 00615 00616 #if defined(DFSDM1_Channel0) 00617 #if defined(RCC_CCIPR2_ADFSDM1SEL) 00618 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM1 Audio clock source selection 00619 * @{ 00620 */ 00621 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as DFSDM1 Audio clock */ 00622 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 /*!< HSI clock used as DFSDM1 Audio clock */ 00623 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 /*!< MSI clock used as DFSDM1 Audio clock */ 00624 /** 00625 * @} 00626 */ 00627 #endif /* RCC_CCIPR2_ADFSDM1SEL */ 00628 00629 /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM1 clock source selection 00630 * @{ 00631 */ 00632 #if defined(RCC_CCIPR2_DFSDM1SEL) 00633 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */ 00634 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */ 00635 #else 00636 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 used as DFSDM1 clock source */ 00637 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */ 00638 #endif /* RCC_CCIPR2_DFSDM1SEL */ 00639 /** 00640 * @} 00641 */ 00642 #endif /* DFSDM1_Channel0 */ 00643 00644 #if defined(DSI) 00645 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection 00646 * @{ 00647 */ 00648 #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */ 00649 #define LL_RCC_DSI_CLKSOURCE_PLL RCC_CCIPR2_DSISEL /*!< PLL clock used as DSI byte lane clock source */ 00650 /** 00651 * @} 00652 */ 00653 #endif /* DSI */ 00654 00655 #if defined(LTDC) 00656 /** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection 00657 * @{ 00658 */ 00659 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 0x00000000U /*!< PLLSAI2DIVR divided by 2 used as LTDC clock source */ 00660 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2DIVR divided by 4 used as LTDC clock source */ 00661 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2DIVR divided by 8 used as LTDC clock source */ 00662 #define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 RCC_CCIPR2_PLLSAI2DIVR /*!< PLLSAI2DIVR divided by 16 used as LTDC clock source */ 00663 /** 00664 * @} 00665 */ 00666 #endif /* LTDC */ 00667 00668 #if defined(OCTOSPI1) 00669 /** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source 00670 * @{ 00671 */ 00672 #define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as OctoSPI clock source */ 00673 #define LL_RCC_OCTOSPI_CLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 /*!< MSI used as OctoSPI clock source */ 00674 #define LL_RCC_OCTOSPI_CLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 /*!< PLL used as OctoSPI clock source */ 00675 /** 00676 * @} 00677 */ 00678 #endif /* OCTOSPI1 */ 00679 00680 /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source 00681 * @{ 00682 */ 00683 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */ 00684 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */ 00685 #if defined(RCC_CCIPR_USART3SEL) 00686 #define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */ 00687 #endif /* RCC_CCIPR_USART3SEL */ 00688 /** 00689 * @} 00690 */ 00691 00692 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL) 00693 /** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source 00694 * @{ 00695 */ 00696 #if defined(RCC_CCIPR_UART4SEL) 00697 #define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */ 00698 #endif /* RCC_CCIPR_UART4SEL */ 00699 #if defined(RCC_CCIPR_UART5SEL) 00700 #define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */ 00701 #endif /* RCC_CCIPR_UART5SEL */ 00702 /** 00703 * @} 00704 */ 00705 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */ 00706 00707 /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source 00708 * @{ 00709 */ 00710 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */ 00711 /** 00712 * @} 00713 */ 00714 00715 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source 00716 * @{ 00717 */ 00718 #define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */ 00719 #if defined(RCC_CCIPR_I2C2SEL) 00720 #define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */ 00721 #endif /* RCC_CCIPR_I2C2SEL */ 00722 #define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */ 00723 #if defined(RCC_CCIPR2_I2C4SEL) 00724 #define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */ 00725 #endif /* RCC_CCIPR2_I2C4SEL */ 00726 /** 00727 * @} 00728 */ 00729 00730 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source 00731 * @{ 00732 */ 00733 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */ 00734 #define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */ 00735 /** 00736 * @} 00737 */ 00738 00739 /** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source 00740 * @{ 00741 */ 00742 #if defined(RCC_CCIPR2_SAI1SEL) 00743 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */ 00744 #else 00745 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */ 00746 #endif /* RCC_CCIPR2_SAI1SEL */ 00747 #if defined(RCC_CCIPR2_SAI2SEL) 00748 #define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /*!< SAI2 Clock source selection */ 00749 #elif defined(RCC_CCIPR_SAI2SEL) 00750 #define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL /*!< SAI2 Clock source selection */ 00751 #endif /* RCC_CCIPR2_SAI2SEL */ 00752 /** 00753 * @} 00754 */ 00755 00756 #if defined(RCC_CCIPR2_SDMMCSEL) 00757 /** @defgroup RCC_LL_EC_SDMMC1_KERNEL Peripheral SDMMC get kernel clock source 00758 * @{ 00759 */ 00760 #define LL_RCC_SDMMC1_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /*!< SDMMC1 Kernel Clock source selection */ 00761 /** 00762 * @} 00763 */ 00764 #endif /* RCC_CCIPR2_SDMMCSEL */ 00765 00766 /** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source 00767 * @{ 00768 */ 00769 #define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< SDMMC1 Clock source selection */ 00770 /** 00771 * @} 00772 */ 00773 00774 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source 00775 * @{ 00776 */ 00777 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */ 00778 /** 00779 * @} 00780 */ 00781 00782 #if defined(USB_OTG_FS) || defined(USB) 00783 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source 00784 * @{ 00785 */ 00786 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */ 00787 /** 00788 * @} 00789 */ 00790 #endif /* USB_OTG_FS || USB */ 00791 00792 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source 00793 * @{ 00794 */ 00795 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */ 00796 /** 00797 * @} 00798 */ 00799 00800 #if defined(SWPMI1) 00801 /** @defgroup RCC_LL_EC_SWPMI1 Peripheral SWPMI1 get clock source 00802 * @{ 00803 */ 00804 #define LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL /*!< SWPMI1 Clock source selection */ 00805 /** 00806 * @} 00807 */ 00808 #endif /* SWPMI1 */ 00809 00810 #if defined(DFSDM1_Channel0) 00811 #if defined(RCC_CCIPR2_ADFSDM1SEL) 00812 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO Peripheral DFSDM1 Audio get clock source 00813 * @{ 00814 */ 00815 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_CCIPR2_ADFSDM1SEL /* DFSDM1 Audio Clock source selection */ 00816 /** 00817 * @} 00818 */ 00819 00820 #endif /* RCC_CCIPR2_ADFSDM1SEL */ 00821 /** @defgroup RCC_LL_EC_DFSDM1 Peripheral DFSDM1 get clock source 00822 * @{ 00823 */ 00824 #if defined(RCC_CCIPR2_DFSDM1SEL) 00825 #define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR2_DFSDM1SEL /*!< DFSDM1 Clock source selection */ 00826 #else 00827 #define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL /*!< DFSDM1 Clock source selection */ 00828 #endif /* RCC_CCIPR2_DFSDM1SEL */ 00829 /** 00830 * @} 00831 */ 00832 #endif /* DFSDM1_Channel0 */ 00833 00834 #if defined(DSI) 00835 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source 00836 * @{ 00837 */ 00838 #define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSISEL /*!< DSI Clock source selection */ 00839 /** 00840 * @} 00841 */ 00842 #endif /* DSI */ 00843 00844 #if defined(LTDC) 00845 /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source 00846 * @{ 00847 */ 00848 #define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_PLLSAI2DIVR /*!< LTDC Clock source selection */ 00849 /** 00850 * @} 00851 */ 00852 #endif /* LTDC */ 00853 00854 #if defined(OCTOSPI1) 00855 /** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source 00856 * @{ 00857 */ 00858 #define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OSPISEL /*!< OctoSPI Clock source selection */ 00859 /** 00860 * @} 00861 */ 00862 #endif /* OCTOSPI1 */ 00863 00864 00865 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection 00866 * @{ 00867 */ 00868 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ 00869 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 00870 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 00871 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 00872 /** 00873 * @} 00874 */ 00875 00876 00877 /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLSAI1 and PLLSAI2 entry clock source 00878 * @{ 00879 */ 00880 #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */ 00881 #define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */ 00882 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */ 00883 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ 00884 /** 00885 * @} 00886 */ 00887 00888 /** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor 00889 * @{ 00890 */ 00891 #define LL_RCC_PLLM_DIV_1 0x00000000U /*!< Main PLL division factor for PLLM input by 1 */ 00892 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 2 */ 00893 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 3 */ 00894 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 4 */ 00895 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 5 */ 00896 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 6 */ 00897 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 7 */ 00898 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 8 */ 00899 #if defined(RCC_PLLM_DIV_1_16_SUPPORT) 00900 #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3) /*!< Main PLL division factor for PLLM input by 9 */ 00901 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 10 */ 00902 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 11 */ 00903 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 12 */ 00904 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< Main PLL division factor for PLLM input by 13 */ 00905 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 14 */ 00906 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 15 */ 00907 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 16 */ 00908 #endif /* RCC_PLLM_DIV_1_16_SUPPORT */ 00909 /** 00910 * @} 00911 */ 00912 00913 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) 00914 * @{ 00915 */ 00916 #define LL_RCC_PLLR_DIV_2 0x00000000U /*!< Main PLL division factor for PLLCLK (system clock) by 2 */ 00917 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */ 00918 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */ 00919 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */ 00920 /** 00921 * @} 00922 */ 00923 00924 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) 00925 * @{ 00926 */ 00927 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 00928 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 */ 00929 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 3 */ 00930 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 */ 00931 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 5 */ 00932 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 6 */ 00933 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 7 */ 00934 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 */ 00935 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 9 */ 00936 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 10 */ 00937 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 11 */ 00938 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 12 */ 00939 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 13 */ 00940 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 14 */ 00941 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 */ 00942 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 */ 00943 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 17 */ 00944 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 18 */ 00945 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 19 */ 00946 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 20 */ 00947 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 21 */ 00948 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 22 */ 00949 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 */ 00950 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 24 */ 00951 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 25 */ 00952 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 26 */ 00953 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 */ 00954 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 28 */ 00955 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 */ 00956 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 */ 00957 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 */ 00958 #else 00959 #define LL_RCC_PLLP_DIV_7 0x00000000U /*!< Main PLL division factor for PLLP output by 7 */ 00960 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP) /*!< Main PLL division factor for PLLP output by 17 */ 00961 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 00962 /** 00963 * @} 00964 */ 00965 00966 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) 00967 * @{ 00968 */ 00969 #define LL_RCC_PLLQ_DIV_2 0x00000000U /*!< Main PLL division factor for PLLQ output by 2 */ 00970 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */ 00971 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */ 00972 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */ 00973 /** 00974 * @} 00975 */ 00976 00977 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 00978 /** @defgroup RCC_LL_EC_PLLSAI1M PLLSAI1 division factor (PLLSAI1M) 00979 * @{ 00980 */ 00981 #define LL_RCC_PLLSAI1M_DIV_1 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1M input by 1 */ 00982 #define LL_RCC_PLLSAI1M_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 2 */ 00983 #define LL_RCC_PLLSAI1M_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 3 */ 00984 #define LL_RCC_PLLSAI1M_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 4 */ 00985 #define LL_RCC_PLLSAI1M_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 5 */ 00986 #define LL_RCC_PLLSAI1M_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 6 */ 00987 #define LL_RCC_PLLSAI1M_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 7 */ 00988 #define LL_RCC_PLLSAI1M_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 8 */ 00989 #define LL_RCC_PLLSAI1M_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1M_3) /*!< PLLSAI1 division factor for PLLSAI1M input by 9 */ 00990 #define LL_RCC_PLLSAI1M_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 10 */ 00991 #define LL_RCC_PLLSAI1M_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 11 */ 00992 #define LL_RCC_PLLSAI1M_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 12 */ 00993 #define LL_RCC_PLLSAI1M_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 13 */ 00994 #define LL_RCC_PLLSAI1M_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 14 */ 00995 #define LL_RCC_PLLSAI1M_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 15 */ 00996 #define LL_RCC_PLLSAI1M_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 16 */ 00997 /** 00998 * @} 00999 */ 01000 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 01001 01002 /** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q) 01003 * @{ 01004 */ 01005 #define LL_RCC_PLLSAI1Q_DIV_2 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */ 01006 #define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */ 01007 #define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */ 01008 #define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q) /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */ 01009 /** 01010 * @} 01011 */ 01012 01013 /** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLSAI1P) 01014 * @{ 01015 */ 01016 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 01017 #define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 2 */ 01018 #define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */ 01019 #define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 4 */ 01020 #define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */ 01021 #define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */ 01022 #define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */ 01023 #define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 8 */ 01024 #define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */ 01025 #define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */ 01026 #define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */ 01027 #define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */ 01028 #define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */ 01029 #define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */ 01030 #define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */ 01031 #define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /*!< PLLSAI1 division factor for PLLSAI1P output by 16 */ 01032 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */ 01033 #define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */ 01034 #define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */ 01035 #define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */ 01036 #define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */ 01037 #define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */ 01038 #define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */ 01039 #define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */ 01040 #define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */ 01041 #define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */ 01042 #define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */ 01043 #define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */ 01044 #define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */ 01045 #define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */ 01046 #define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */ 01047 #else 01048 #define LL_RCC_PLLSAI1P_DIV_7 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */ 01049 #define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */ 01050 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 01051 /** 01052 * @} 01053 */ 01054 01055 /** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLSAI1R) 01056 * @{ 01057 */ 01058 #define LL_RCC_PLLSAI1R_DIV_2 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */ 01059 #define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */ 01060 #define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */ 01061 #define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R) /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */ 01062 /** 01063 * @} 01064 */ 01065 01066 #if defined(RCC_PLLSAI2_SUPPORT) 01067 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 01068 /** @defgroup RCC_LL_EC_PLLSAI2M PLLSAI1 division factor (PLLSAI2M) 01069 * @{ 01070 */ 01071 #define LL_RCC_PLLSAI2M_DIV_1 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2M input by 1 */ 01072 #define LL_RCC_PLLSAI2M_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 2 */ 01073 #define LL_RCC_PLLSAI2M_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 3 */ 01074 #define LL_RCC_PLLSAI2M_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 4 */ 01075 #define LL_RCC_PLLSAI2M_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 5 */ 01076 #define LL_RCC_PLLSAI2M_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 6 */ 01077 #define LL_RCC_PLLSAI2M_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 7 */ 01078 #define LL_RCC_PLLSAI2M_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 8 */ 01079 #define LL_RCC_PLLSAI2M_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2M_3) /*!< PLLSAI2 division factor for PLLSAI2M input by 9 */ 01080 #define LL_RCC_PLLSAI2M_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 10 */ 01081 #define LL_RCC_PLLSAI2M_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 11 */ 01082 #define LL_RCC_PLLSAI2M_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 12 */ 01083 #define LL_RCC_PLLSAI2M_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 13 */ 01084 #define LL_RCC_PLLSAI2M_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 14 */ 01085 #define LL_RCC_PLLSAI2M_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 15 */ 01086 #define LL_RCC_PLLSAI2M_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 16 */ 01087 /** 01088 * @} 01089 */ 01090 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 01091 01092 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 01093 /** @defgroup RCC_LL_EC_PLLSAI2Q PLLSAI2 division factor (PLLSAI2Q) 01094 * @{ 01095 */ 01096 #define LL_RCC_PLLSAI2Q_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2Q output by 2 */ 01097 #define LL_RCC_PLLSAI2Q_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2Q_0) /*!< PLLSAI2 division factor for PLLSAI2Q output by 4 */ 01098 #define LL_RCC_PLLSAI2Q_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2Q_1) /*!< PLLSAI2 division factor for PLLSAI2Q output by 6 */ 01099 #define LL_RCC_PLLSAI2Q_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2Q) /*!< PLLSAI2 division factor for PLLSAI2Q output by 8 */ 01100 /** 01101 * @} 01102 */ 01103 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 01104 01105 /** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P) 01106 * @{ 01107 */ 01108 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 01109 #define LL_RCC_PLLSAI2P_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 2 */ 01110 #define LL_RCC_PLLSAI2P_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 3 */ 01111 #define LL_RCC_PLLSAI2P_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 4 */ 01112 #define LL_RCC_PLLSAI2P_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 5 */ 01113 #define LL_RCC_PLLSAI2P_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 6 */ 01114 #define LL_RCC_PLLSAI2P_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */ 01115 #define LL_RCC_PLLSAI2P_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 8 */ 01116 #define LL_RCC_PLLSAI2P_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 9 */ 01117 #define LL_RCC_PLLSAI2P_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 10 */ 01118 #define LL_RCC_PLLSAI2P_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 1 */ 01119 #define LL_RCC_PLLSAI2P_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 12 */ 01120 #define LL_RCC_PLLSAI2P_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 13 */ 01121 #define LL_RCC_PLLSAI2P_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 14 */ 01122 #define LL_RCC_PLLSAI2P_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 15 */ 01123 #define LL_RCC_PLLSAI2P_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4) /*!< PLLSAI2 division factor for PLLSAI2P output by 16 */ 01124 #define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */ 01125 #define LL_RCC_PLLSAI2P_DIV_18 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 18 */ 01126 #define LL_RCC_PLLSAI2P_DIV_19 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 19 */ 01127 #define LL_RCC_PLLSAI2P_DIV_20 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 20 */ 01128 #define LL_RCC_PLLSAI2P_DIV_21 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division fctor for PLLSAI2P output by 21 */ 01129 #define LL_RCC_PLLSAI2P_DIV_22 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 22 */ 01130 #define LL_RCC_PLLSAI2P_DIV_23 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 23 */ 01131 #define LL_RCC_PLLSAI2P_DIV_24 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 24 */ 01132 #define LL_RCC_PLLSAI2P_DIV_25 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 25 */ 01133 #define LL_RCC_PLLSAI2P_DIV_26 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 26 */ 01134 #define LL_RCC_PLLSAI2P_DIV_27 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 27 */ 01135 #define LL_RCC_PLLSAI2P_DIV_28 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 28 */ 01136 #define LL_RCC_PLLSAI2P_DIV_29 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 29 */ 01137 #define LL_RCC_PLLSAI2P_DIV_30 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 30 */ 01138 #define LL_RCC_PLLSAI2P_DIV_31 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */ 01139 #else 01140 #define LL_RCC_PLLSAI2P_DIV_7 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */ 01141 #define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */ 01142 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ 01143 /** 01144 * @} 01145 */ 01146 01147 /** @defgroup RCC_LL_EC_PLLSAI2R PLLSAI2 division factor (PLLSAI2R) 01148 * @{ 01149 */ 01150 #define LL_RCC_PLLSAI2R_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2R output by 2 */ 01151 #define LL_RCC_PLLSAI2R_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2R_0) /*!< PLLSAI2 division factor for PLLSAI2R output by 4 */ 01152 #define LL_RCC_PLLSAI2R_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2R_1) /*!< PLLSAI2 division factor for PLLSAI2R output by 6 */ 01153 #define LL_RCC_PLLSAI2R_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2R) /*!< PLLSAI2 division factor for PLLSAI2R output by 8 */ 01154 /** 01155 * @} 01156 */ 01157 01158 #if defined(RCC_CCIPR2_PLLSAI2DIVR) 01159 /** @defgroup RCC_LL_EC_PLLSAI2DIVR PLLSAI2DIVR division factor (PLLSAI2DIVR) 01160 * @{ 01161 */ 01162 #define LL_RCC_PLLSAI2DIVR_DIV_2 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 2 */ 01163 #define LL_RCC_PLLSAI2DIVR_DIV_4 RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 4 */ 01164 #define LL_RCC_PLLSAI2DIVR_DIV_8 RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 8 */ 01165 #define LL_RCC_PLLSAI2DIVR_DIV_16 (RCC_CCIPR2_PLLSAI2DIVR_1 | RCC_CCIPR2_PLLSAI2DIVR_0) /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 16 */ 01166 /** 01167 * @} 01168 */ 01169 #endif /* RCC_CCIPR2_PLLSAI2DIVR */ 01170 #endif /* RCC_PLLSAI2_SUPPORT */ 01171 01172 /** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection 01173 * @{ 01174 */ 01175 #define LL_RCC_MSIRANGESEL_STANDBY 0U /*!< MSI Range is provided by MSISRANGE */ 01176 #define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSIRANGE */ 01177 /** 01178 * @} 01179 */ 01180 01181 /** Legacy definitions for compatibility purpose 01182 @cond 0 01183 */ 01184 #if defined(DFSDM1_Channel0) 01185 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2 01186 #define LL_RCC_DFSDM_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2 01187 #define LL_RCC_DFSDM_CLKSOURCE_SYSCLK LL_RCC_DFSDM1_CLKSOURCE_SYSCLK 01188 #define LL_RCC_DFSDM_CLKSOURCE LL_RCC_DFSDM1_CLKSOURCE 01189 #endif /* DFSDM1_Channel0 */ 01190 #if defined(SWPMI1) 01191 #define LL_RCC_SWPMI1_CLKSOURCE_PCLK LL_RCC_SWPMI1_CLKSOURCE_PCLK1 01192 #endif /* SWPMI1 */ 01193 /** 01194 @endcond 01195 */ 01196 01197 /** 01198 * @} 01199 */ 01200 01201 /* Exported macro ------------------------------------------------------------*/ 01202 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros 01203 * @{ 01204 */ 01205 01206 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros 01207 * @{ 01208 */ 01209 01210 /** 01211 * @brief Write a value in RCC register 01212 * @param __REG__ Register to be written 01213 * @param __VALUE__ Value to be written in the register 01214 * @retval None 01215 */ 01216 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) 01217 01218 /** 01219 * @brief Read a value in RCC register 01220 * @param __REG__ Register to be read 01221 * @retval Register value 01222 */ 01223 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) 01224 /** 01225 * @} 01226 */ 01227 01228 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies 01229 * @{ 01230 */ 01231 01232 /** 01233 * @brief Helper macro to calculate the PLLCLK frequency on system domain 01234 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01235 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); 01236 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01237 * @param __PLLM__ This parameter can be one of the following values: 01238 * @arg @ref LL_RCC_PLLM_DIV_1 01239 * @arg @ref LL_RCC_PLLM_DIV_2 01240 * @arg @ref LL_RCC_PLLM_DIV_3 01241 * @arg @ref LL_RCC_PLLM_DIV_4 01242 * @arg @ref LL_RCC_PLLM_DIV_5 01243 * @arg @ref LL_RCC_PLLM_DIV_6 01244 * @arg @ref LL_RCC_PLLM_DIV_7 01245 * @arg @ref LL_RCC_PLLM_DIV_8 01246 * @arg @ref LL_RCC_PLLM_DIV_9 (*) 01247 * @arg @ref LL_RCC_PLLM_DIV_10 (*) 01248 * @arg @ref LL_RCC_PLLM_DIV_11 (*) 01249 * @arg @ref LL_RCC_PLLM_DIV_12 (*) 01250 * @arg @ref LL_RCC_PLLM_DIV_13 (*) 01251 * @arg @ref LL_RCC_PLLM_DIV_14 (*) 01252 * @arg @ref LL_RCC_PLLM_DIV_15 (*) 01253 * @arg @ref LL_RCC_PLLM_DIV_16 (*) 01254 * 01255 * (*) value not defined in all devices. 01256 * @param __PLLN__ Between 8 and 86 01257 * @param __PLLR__ This parameter can be one of the following values: 01258 * @arg @ref LL_RCC_PLLR_DIV_2 01259 * @arg @ref LL_RCC_PLLR_DIV_4 01260 * @arg @ref LL_RCC_PLLR_DIV_6 01261 * @arg @ref LL_RCC_PLLR_DIV_8 01262 * @retval PLL clock frequency (in Hz) 01263 */ 01264 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ 01265 ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U)) 01266 01267 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 01268 /** 01269 * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain 01270 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01271 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); 01272 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01273 * @param __PLLM__ This parameter can be one of the following values: 01274 * @arg @ref LL_RCC_PLLM_DIV_1 01275 * @arg @ref LL_RCC_PLLM_DIV_2 01276 * @arg @ref LL_RCC_PLLM_DIV_3 01277 * @arg @ref LL_RCC_PLLM_DIV_4 01278 * @arg @ref LL_RCC_PLLM_DIV_5 01279 * @arg @ref LL_RCC_PLLM_DIV_6 01280 * @arg @ref LL_RCC_PLLM_DIV_7 01281 * @arg @ref LL_RCC_PLLM_DIV_8 01282 * @arg @ref LL_RCC_PLLM_DIV_9 (*) 01283 * @arg @ref LL_RCC_PLLM_DIV_10 (*) 01284 * @arg @ref LL_RCC_PLLM_DIV_11 (*) 01285 * @arg @ref LL_RCC_PLLM_DIV_12 (*) 01286 * @arg @ref LL_RCC_PLLM_DIV_13 (*) 01287 * @arg @ref LL_RCC_PLLM_DIV_14 (*) 01288 * @arg @ref LL_RCC_PLLM_DIV_15 (*) 01289 * @arg @ref LL_RCC_PLLM_DIV_16 (*) 01290 * 01291 * (*) value not defined in all devices. 01292 * @param __PLLN__ Between 8 and 86 01293 * @param __PLLP__ This parameter can be one of the following values: 01294 * @arg @ref LL_RCC_PLLP_DIV_2 01295 * @arg @ref LL_RCC_PLLP_DIV_3 01296 * @arg @ref LL_RCC_PLLP_DIV_4 01297 * @arg @ref LL_RCC_PLLP_DIV_5 01298 * @arg @ref LL_RCC_PLLP_DIV_6 01299 * @arg @ref LL_RCC_PLLP_DIV_7 01300 * @arg @ref LL_RCC_PLLP_DIV_8 01301 * @arg @ref LL_RCC_PLLP_DIV_9 01302 * @arg @ref LL_RCC_PLLP_DIV_10 01303 * @arg @ref LL_RCC_PLLP_DIV_11 01304 * @arg @ref LL_RCC_PLLP_DIV_12 01305 * @arg @ref LL_RCC_PLLP_DIV_13 01306 * @arg @ref LL_RCC_PLLP_DIV_14 01307 * @arg @ref LL_RCC_PLLP_DIV_15 01308 * @arg @ref LL_RCC_PLLP_DIV_16 01309 * @arg @ref LL_RCC_PLLP_DIV_17 01310 * @arg @ref LL_RCC_PLLP_DIV_18 01311 * @arg @ref LL_RCC_PLLP_DIV_19 01312 * @arg @ref LL_RCC_PLLP_DIV_20 01313 * @arg @ref LL_RCC_PLLP_DIV_21 01314 * @arg @ref LL_RCC_PLLP_DIV_22 01315 * @arg @ref LL_RCC_PLLP_DIV_23 01316 * @arg @ref LL_RCC_PLLP_DIV_24 01317 * @arg @ref LL_RCC_PLLP_DIV_25 01318 * @arg @ref LL_RCC_PLLP_DIV_26 01319 * @arg @ref LL_RCC_PLLP_DIV_27 01320 * @arg @ref LL_RCC_PLLP_DIV_28 01321 * @arg @ref LL_RCC_PLLP_DIV_29 01322 * @arg @ref LL_RCC_PLLP_DIV_30 01323 * @arg @ref LL_RCC_PLLP_DIV_31 01324 * @retval PLL clock frequency (in Hz) 01325 */ 01326 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ 01327 ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos)) 01328 01329 #else 01330 /** 01331 * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain 01332 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01333 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); 01334 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01335 * @param __PLLM__ This parameter can be one of the following values: 01336 * @arg @ref LL_RCC_PLLM_DIV_1 01337 * @arg @ref LL_RCC_PLLM_DIV_2 01338 * @arg @ref LL_RCC_PLLM_DIV_3 01339 * @arg @ref LL_RCC_PLLM_DIV_4 01340 * @arg @ref LL_RCC_PLLM_DIV_5 01341 * @arg @ref LL_RCC_PLLM_DIV_6 01342 * @arg @ref LL_RCC_PLLM_DIV_7 01343 * @arg @ref LL_RCC_PLLM_DIV_8 01344 * @param __PLLN__ Between 8 and 86 01345 * @param __PLLP__ This parameter can be one of the following values: 01346 * @arg @ref LL_RCC_PLLP_DIV_7 01347 * @arg @ref LL_RCC_PLLP_DIV_17 01348 * @retval PLL clock frequency (in Hz) 01349 */ 01350 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ 01351 (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U)) 01352 01353 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 01354 01355 /** 01356 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain 01357 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01358 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); 01359 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01360 * @param __PLLM__ This parameter can be one of the following values: 01361 * @arg @ref LL_RCC_PLLM_DIV_1 01362 * @arg @ref LL_RCC_PLLM_DIV_2 01363 * @arg @ref LL_RCC_PLLM_DIV_3 01364 * @arg @ref LL_RCC_PLLM_DIV_4 01365 * @arg @ref LL_RCC_PLLM_DIV_5 01366 * @arg @ref LL_RCC_PLLM_DIV_6 01367 * @arg @ref LL_RCC_PLLM_DIV_7 01368 * @arg @ref LL_RCC_PLLM_DIV_8 01369 * @arg @ref LL_RCC_PLLM_DIV_9 (*) 01370 * @arg @ref LL_RCC_PLLM_DIV_10 (*) 01371 * @arg @ref LL_RCC_PLLM_DIV_11 (*) 01372 * @arg @ref LL_RCC_PLLM_DIV_12 (*) 01373 * @arg @ref LL_RCC_PLLM_DIV_13 (*) 01374 * @arg @ref LL_RCC_PLLM_DIV_14 (*) 01375 * @arg @ref LL_RCC_PLLM_DIV_15 (*) 01376 * @arg @ref LL_RCC_PLLM_DIV_16 (*) 01377 * 01378 * (*) value not defined in all devices. 01379 * @param __PLLN__ Between 8 and 86 01380 * @param __PLLQ__ This parameter can be one of the following values: 01381 * @arg @ref LL_RCC_PLLQ_DIV_2 01382 * @arg @ref LL_RCC_PLLQ_DIV_4 01383 * @arg @ref LL_RCC_PLLQ_DIV_6 01384 * @arg @ref LL_RCC_PLLQ_DIV_8 01385 * @retval PLL clock frequency (in Hz) 01386 */ 01387 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ 01388 ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U)) 01389 01390 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 01391 /** 01392 * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain 01393 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (), 01394 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ()); 01395 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01396 * @param __PLLSAI1M__ This parameter can be one of the following values: 01397 * @arg @ref LL_RCC_PLLSAI1M_DIV_1 01398 * @arg @ref LL_RCC_PLLSAI1M_DIV_2 01399 * @arg @ref LL_RCC_PLLSAI1M_DIV_3 01400 * @arg @ref LL_RCC_PLLSAI1M_DIV_4 01401 * @arg @ref LL_RCC_PLLSAI1M_DIV_5 01402 * @arg @ref LL_RCC_PLLSAI1M_DIV_6 01403 * @arg @ref LL_RCC_PLLSAI1M_DIV_7 01404 * @arg @ref LL_RCC_PLLSAI1M_DIV_8 01405 * @arg @ref LL_RCC_PLLSAI1M_DIV_9 01406 * @arg @ref LL_RCC_PLLSAI1M_DIV_10 01407 * @arg @ref LL_RCC_PLLSAI1M_DIV_11 01408 * @arg @ref LL_RCC_PLLSAI1M_DIV_12 01409 * @arg @ref LL_RCC_PLLSAI1M_DIV_13 01410 * @arg @ref LL_RCC_PLLSAI1M_DIV_14 01411 * @arg @ref LL_RCC_PLLSAI1M_DIV_15 01412 * @arg @ref LL_RCC_PLLSAI1M_DIV_16 01413 * @param __PLLSAI1N__ Between 8 and 86 01414 * @param __PLLSAI1P__ This parameter can be one of the following values: 01415 * @arg @ref LL_RCC_PLLSAI1P_DIV_2 01416 * @arg @ref LL_RCC_PLLSAI1P_DIV_3 01417 * @arg @ref LL_RCC_PLLSAI1P_DIV_4 01418 * @arg @ref LL_RCC_PLLSAI1P_DIV_5 01419 * @arg @ref LL_RCC_PLLSAI1P_DIV_6 01420 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 01421 * @arg @ref LL_RCC_PLLSAI1P_DIV_8 01422 * @arg @ref LL_RCC_PLLSAI1P_DIV_9 01423 * @arg @ref LL_RCC_PLLSAI1P_DIV_10 01424 * @arg @ref LL_RCC_PLLSAI1P_DIV_11 01425 * @arg @ref LL_RCC_PLLSAI1P_DIV_12 01426 * @arg @ref LL_RCC_PLLSAI1P_DIV_13 01427 * @arg @ref LL_RCC_PLLSAI1P_DIV_14 01428 * @arg @ref LL_RCC_PLLSAI1P_DIV_15 01429 * @arg @ref LL_RCC_PLLSAI1P_DIV_16 01430 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 01431 * @arg @ref LL_RCC_PLLSAI1P_DIV_18 01432 * @arg @ref LL_RCC_PLLSAI1P_DIV_19 01433 * @arg @ref LL_RCC_PLLSAI1P_DIV_20 01434 * @arg @ref LL_RCC_PLLSAI1P_DIV_21 01435 * @arg @ref LL_RCC_PLLSAI1P_DIV_22 01436 * @arg @ref LL_RCC_PLLSAI1P_DIV_23 01437 * @arg @ref LL_RCC_PLLSAI1P_DIV_24 01438 * @arg @ref LL_RCC_PLLSAI1P_DIV_25 01439 * @arg @ref LL_RCC_PLLSAI1P_DIV_26 01440 * @arg @ref LL_RCC_PLLSAI1P_DIV_27 01441 * @arg @ref LL_RCC_PLLSAI1P_DIV_28 01442 * @arg @ref LL_RCC_PLLSAI1P_DIV_29 01443 * @arg @ref LL_RCC_PLLSAI1P_DIV_30 01444 * @arg @ref LL_RCC_PLLSAI1P_DIV_31 01445 * @retval PLLSAI1 clock frequency (in Hz) 01446 */ 01447 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__) \ 01448 ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ 01449 ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) 01450 01451 #elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 01452 /** 01453 * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain 01454 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01455 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ()); 01456 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01457 * @param __PLLM__ This parameter can be one of the following values: 01458 * @arg @ref LL_RCC_PLLM_DIV_1 01459 * @arg @ref LL_RCC_PLLM_DIV_2 01460 * @arg @ref LL_RCC_PLLM_DIV_3 01461 * @arg @ref LL_RCC_PLLM_DIV_4 01462 * @arg @ref LL_RCC_PLLM_DIV_5 01463 * @arg @ref LL_RCC_PLLM_DIV_6 01464 * @arg @ref LL_RCC_PLLM_DIV_7 01465 * @arg @ref LL_RCC_PLLM_DIV_8 01466 * @param __PLLSAI1N__ Between 8 and 86 01467 * @param __PLLSAI1P__ This parameter can be one of the following values: 01468 * @arg @ref LL_RCC_PLLSAI1P_DIV_2 01469 * @arg @ref LL_RCC_PLLSAI1P_DIV_3 01470 * @arg @ref LL_RCC_PLLSAI1P_DIV_4 01471 * @arg @ref LL_RCC_PLLSAI1P_DIV_5 01472 * @arg @ref LL_RCC_PLLSAI1P_DIV_6 01473 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 01474 * @arg @ref LL_RCC_PLLSAI1P_DIV_8 01475 * @arg @ref LL_RCC_PLLSAI1P_DIV_9 01476 * @arg @ref LL_RCC_PLLSAI1P_DIV_10 01477 * @arg @ref LL_RCC_PLLSAI1P_DIV_11 01478 * @arg @ref LL_RCC_PLLSAI1P_DIV_12 01479 * @arg @ref LL_RCC_PLLSAI1P_DIV_13 01480 * @arg @ref LL_RCC_PLLSAI1P_DIV_14 01481 * @arg @ref LL_RCC_PLLSAI1P_DIV_15 01482 * @arg @ref LL_RCC_PLLSAI1P_DIV_16 01483 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 01484 * @arg @ref LL_RCC_PLLSAI1P_DIV_18 01485 * @arg @ref LL_RCC_PLLSAI1P_DIV_19 01486 * @arg @ref LL_RCC_PLLSAI1P_DIV_20 01487 * @arg @ref LL_RCC_PLLSAI1P_DIV_21 01488 * @arg @ref LL_RCC_PLLSAI1P_DIV_22 01489 * @arg @ref LL_RCC_PLLSAI1P_DIV_23 01490 * @arg @ref LL_RCC_PLLSAI1P_DIV_24 01491 * @arg @ref LL_RCC_PLLSAI1P_DIV_25 01492 * @arg @ref LL_RCC_PLLSAI1P_DIV_26 01493 * @arg @ref LL_RCC_PLLSAI1P_DIV_27 01494 * @arg @ref LL_RCC_PLLSAI1P_DIV_28 01495 * @arg @ref LL_RCC_PLLSAI1P_DIV_29 01496 * @arg @ref LL_RCC_PLLSAI1P_DIV_30 01497 * @arg @ref LL_RCC_PLLSAI1P_DIV_31 01498 * @retval PLLSAI1 clock frequency (in Hz) 01499 */ 01500 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \ 01501 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ 01502 ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) 01503 01504 #else 01505 /** 01506 * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain 01507 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01508 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ()); 01509 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01510 * @param __PLLM__ This parameter can be one of the following values: 01511 * @arg @ref LL_RCC_PLLM_DIV_1 01512 * @arg @ref LL_RCC_PLLM_DIV_2 01513 * @arg @ref LL_RCC_PLLM_DIV_3 01514 * @arg @ref LL_RCC_PLLM_DIV_4 01515 * @arg @ref LL_RCC_PLLM_DIV_5 01516 * @arg @ref LL_RCC_PLLM_DIV_6 01517 * @arg @ref LL_RCC_PLLM_DIV_7 01518 * @arg @ref LL_RCC_PLLM_DIV_8 01519 * @param __PLLSAI1N__ Between 8 and 86 01520 * @param __PLLSAI1P__ This parameter can be one of the following values: 01521 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 01522 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 01523 * @retval PLLSAI1 clock frequency (in Hz) 01524 */ 01525 #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \ 01526 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ 01527 (((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7U : 17U)) 01528 01529 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 01530 01531 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 01532 /** 01533 * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain 01534 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (), 01535 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ()); 01536 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01537 * @param __PLLSAI1M__ This parameter can be one of the following values: 01538 * @arg @ref LL_RCC_PLLSAI1M_DIV_1 01539 * @arg @ref LL_RCC_PLLSAI1M_DIV_2 01540 * @arg @ref LL_RCC_PLLSAI1M_DIV_3 01541 * @arg @ref LL_RCC_PLLSAI1M_DIV_4 01542 * @arg @ref LL_RCC_PLLSAI1M_DIV_5 01543 * @arg @ref LL_RCC_PLLSAI1M_DIV_6 01544 * @arg @ref LL_RCC_PLLSAI1M_DIV_7 01545 * @arg @ref LL_RCC_PLLSAI1M_DIV_8 01546 * @arg @ref LL_RCC_PLLSAI1M_DIV_9 01547 * @arg @ref LL_RCC_PLLSAI1M_DIV_10 01548 * @arg @ref LL_RCC_PLLSAI1M_DIV_11 01549 * @arg @ref LL_RCC_PLLSAI1M_DIV_12 01550 * @arg @ref LL_RCC_PLLSAI1M_DIV_13 01551 * @arg @ref LL_RCC_PLLSAI1M_DIV_14 01552 * @arg @ref LL_RCC_PLLSAI1M_DIV_15 01553 * @arg @ref LL_RCC_PLLSAI1M_DIV_16 01554 * @param __PLLSAI1N__ Between 8 and 86 01555 * @param __PLLSAI1Q__ This parameter can be one of the following values: 01556 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 01557 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 01558 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 01559 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 01560 * @retval PLLSAI1 clock frequency (in Hz) 01561 */ 01562 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1Q__) \ 01563 ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ 01564 ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U)) 01565 01566 #else 01567 /** 01568 * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain 01569 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01570 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ()); 01571 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01572 * @param __PLLM__ This parameter can be one of the following values: 01573 * @arg @ref LL_RCC_PLLM_DIV_1 01574 * @arg @ref LL_RCC_PLLM_DIV_2 01575 * @arg @ref LL_RCC_PLLM_DIV_3 01576 * @arg @ref LL_RCC_PLLM_DIV_4 01577 * @arg @ref LL_RCC_PLLM_DIV_5 01578 * @arg @ref LL_RCC_PLLM_DIV_6 01579 * @arg @ref LL_RCC_PLLM_DIV_7 01580 * @arg @ref LL_RCC_PLLM_DIV_8 01581 * @param __PLLSAI1N__ Between 8 and 86 01582 * @param __PLLSAI1Q__ This parameter can be one of the following values: 01583 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 01584 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 01585 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 01586 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 01587 * @retval PLLSAI1 clock frequency (in Hz) 01588 */ 01589 #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) \ 01590 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ 01591 ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U)) 01592 01593 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 01594 01595 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 01596 /** 01597 * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain 01598 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (), 01599 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ()); 01600 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01601 * @param __PLLSAI1M__ This parameter can be one of the following values: 01602 * @arg @ref LL_RCC_PLLSAI1M_DIV_1 01603 * @arg @ref LL_RCC_PLLSAI1M_DIV_2 01604 * @arg @ref LL_RCC_PLLSAI1M_DIV_3 01605 * @arg @ref LL_RCC_PLLSAI1M_DIV_4 01606 * @arg @ref LL_RCC_PLLSAI1M_DIV_5 01607 * @arg @ref LL_RCC_PLLSAI1M_DIV_6 01608 * @arg @ref LL_RCC_PLLSAI1M_DIV_7 01609 * @arg @ref LL_RCC_PLLSAI1M_DIV_8 01610 * @arg @ref LL_RCC_PLLSAI1M_DIV_9 01611 * @arg @ref LL_RCC_PLLSAI1M_DIV_10 01612 * @arg @ref LL_RCC_PLLSAI1M_DIV_11 01613 * @arg @ref LL_RCC_PLLSAI1M_DIV_12 01614 * @arg @ref LL_RCC_PLLSAI1M_DIV_13 01615 * @arg @ref LL_RCC_PLLSAI1M_DIV_14 01616 * @arg @ref LL_RCC_PLLSAI1M_DIV_15 01617 * @arg @ref LL_RCC_PLLSAI1M_DIV_16 01618 * @param __PLLSAI1N__ Between 8 and 86 01619 * @param __PLLSAI1R__ This parameter can be one of the following values: 01620 * @arg @ref LL_RCC_PLLSAI1R_DIV_2 01621 * @arg @ref LL_RCC_PLLSAI1R_DIV_4 01622 * @arg @ref LL_RCC_PLLSAI1R_DIV_6 01623 * @arg @ref LL_RCC_PLLSAI1R_DIV_8 01624 * @retval PLLSAI1 clock frequency (in Hz) 01625 */ 01626 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1R__) \ 01627 ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ 01628 ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U)) 01629 01630 #else 01631 /** 01632 * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain 01633 * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01634 * @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ()); 01635 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01636 * @param __PLLM__ This parameter can be one of the following values: 01637 * @arg @ref LL_RCC_PLLM_DIV_1 01638 * @arg @ref LL_RCC_PLLM_DIV_2 01639 * @arg @ref LL_RCC_PLLM_DIV_3 01640 * @arg @ref LL_RCC_PLLM_DIV_4 01641 * @arg @ref LL_RCC_PLLM_DIV_5 01642 * @arg @ref LL_RCC_PLLM_DIV_6 01643 * @arg @ref LL_RCC_PLLM_DIV_7 01644 * @arg @ref LL_RCC_PLLM_DIV_8 01645 * @param __PLLSAI1N__ Between 8 and 86 01646 * @param __PLLSAI1R__ This parameter can be one of the following values: 01647 * @arg @ref LL_RCC_PLLSAI1R_DIV_2 01648 * @arg @ref LL_RCC_PLLSAI1R_DIV_4 01649 * @arg @ref LL_RCC_PLLSAI1R_DIV_6 01650 * @arg @ref LL_RCC_PLLSAI1R_DIV_8 01651 * @retval PLLSAI1 clock frequency (in Hz) 01652 */ 01653 #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \ 01654 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \ 01655 ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U)) 01656 01657 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 01658 01659 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 01660 /** 01661 * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain 01662 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (), 01663 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ()); 01664 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01665 * @param __PLLSAI2M__ This parameter can be one of the following values: 01666 * @arg @ref LL_RCC_PLLSAI2M_DIV_1 01667 * @arg @ref LL_RCC_PLLSAI2M_DIV_2 01668 * @arg @ref LL_RCC_PLLSAI2M_DIV_3 01669 * @arg @ref LL_RCC_PLLSAI2M_DIV_4 01670 * @arg @ref LL_RCC_PLLSAI2M_DIV_5 01671 * @arg @ref LL_RCC_PLLSAI2M_DIV_6 01672 * @arg @ref LL_RCC_PLLSAI2M_DIV_7 01673 * @arg @ref LL_RCC_PLLSAI2M_DIV_8 01674 * @arg @ref LL_RCC_PLLSAI2M_DIV_9 01675 * @arg @ref LL_RCC_PLLSAI2M_DIV_10 01676 * @arg @ref LL_RCC_PLLSAI2M_DIV_11 01677 * @arg @ref LL_RCC_PLLSAI2M_DIV_12 01678 * @arg @ref LL_RCC_PLLSAI2M_DIV_13 01679 * @arg @ref LL_RCC_PLLSAI2M_DIV_14 01680 * @arg @ref LL_RCC_PLLSAI2M_DIV_15 01681 * @arg @ref LL_RCC_PLLSAI2M_DIV_16 01682 * @param __PLLSAI2N__ Between 8 and 86 01683 * @param __PLLSAI2P__ This parameter can be one of the following values: 01684 * @arg @ref LL_RCC_PLLSAI2P_DIV_2 01685 * @arg @ref LL_RCC_PLLSAI2P_DIV_3 01686 * @arg @ref LL_RCC_PLLSAI2P_DIV_4 01687 * @arg @ref LL_RCC_PLLSAI2P_DIV_5 01688 * @arg @ref LL_RCC_PLLSAI2P_DIV_6 01689 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 01690 * @arg @ref LL_RCC_PLLSAI2P_DIV_8 01691 * @arg @ref LL_RCC_PLLSAI2P_DIV_9 01692 * @arg @ref LL_RCC_PLLSAI2P_DIV_10 01693 * @arg @ref LL_RCC_PLLSAI2P_DIV_11 01694 * @arg @ref LL_RCC_PLLSAI2P_DIV_12 01695 * @arg @ref LL_RCC_PLLSAI2P_DIV_13 01696 * @arg @ref LL_RCC_PLLSAI2P_DIV_14 01697 * @arg @ref LL_RCC_PLLSAI2P_DIV_15 01698 * @arg @ref LL_RCC_PLLSAI2P_DIV_16 01699 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 01700 * @arg @ref LL_RCC_PLLSAI2P_DIV_18 01701 * @arg @ref LL_RCC_PLLSAI2P_DIV_19 01702 * @arg @ref LL_RCC_PLLSAI2P_DIV_20 01703 * @arg @ref LL_RCC_PLLSAI2P_DIV_21 01704 * @arg @ref LL_RCC_PLLSAI2P_DIV_22 01705 * @arg @ref LL_RCC_PLLSAI2P_DIV_23 01706 * @arg @ref LL_RCC_PLLSAI2P_DIV_24 01707 * @arg @ref LL_RCC_PLLSAI2P_DIV_25 01708 * @arg @ref LL_RCC_PLLSAI2P_DIV_26 01709 * @arg @ref LL_RCC_PLLSAI2P_DIV_27 01710 * @arg @ref LL_RCC_PLLSAI2P_DIV_28 01711 * @arg @ref LL_RCC_PLLSAI2P_DIV_29 01712 * @arg @ref LL_RCC_PLLSAI2P_DIV_30 01713 * @arg @ref LL_RCC_PLLSAI2P_DIV_31 01714 * @retval PLLSAI2 clock frequency (in Hz) 01715 */ 01716 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \ 01717 ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ 01718 ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) 01719 01720 #elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 01721 /** 01722 * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain 01723 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01724 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ()); 01725 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01726 * @param __PLLM__ This parameter can be one of the following values: 01727 * @arg @ref LL_RCC_PLLM_DIV_1 01728 * @arg @ref LL_RCC_PLLM_DIV_2 01729 * @arg @ref LL_RCC_PLLM_DIV_3 01730 * @arg @ref LL_RCC_PLLM_DIV_4 01731 * @arg @ref LL_RCC_PLLM_DIV_5 01732 * @arg @ref LL_RCC_PLLM_DIV_6 01733 * @arg @ref LL_RCC_PLLM_DIV_7 01734 * @arg @ref LL_RCC_PLLM_DIV_8 01735 * @param __PLLSAI2N__ Between 8 and 86 01736 * @param __PLLSAI2P__ This parameter can be one of the following values: 01737 * @arg @ref LL_RCC_PLLSAI2P_DIV_2 01738 * @arg @ref LL_RCC_PLLSAI2P_DIV_3 01739 * @arg @ref LL_RCC_PLLSAI2P_DIV_4 01740 * @arg @ref LL_RCC_PLLSAI2P_DIV_5 01741 * @arg @ref LL_RCC_PLLSAI2P_DIV_6 01742 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 01743 * @arg @ref LL_RCC_PLLSAI2P_DIV_8 01744 * @arg @ref LL_RCC_PLLSAI2P_DIV_9 01745 * @arg @ref LL_RCC_PLLSAI2P_DIV_10 01746 * @arg @ref LL_RCC_PLLSAI2P_DIV_11 01747 * @arg @ref LL_RCC_PLLSAI2P_DIV_12 01748 * @arg @ref LL_RCC_PLLSAI2P_DIV_13 01749 * @arg @ref LL_RCC_PLLSAI2P_DIV_14 01750 * @arg @ref LL_RCC_PLLSAI2P_DIV_15 01751 * @arg @ref LL_RCC_PLLSAI2P_DIV_16 01752 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 01753 * @arg @ref LL_RCC_PLLSAI2P_DIV_18 01754 * @arg @ref LL_RCC_PLLSAI2P_DIV_19 01755 * @arg @ref LL_RCC_PLLSAI2P_DIV_20 01756 * @arg @ref LL_RCC_PLLSAI2P_DIV_21 01757 * @arg @ref LL_RCC_PLLSAI2P_DIV_22 01758 * @arg @ref LL_RCC_PLLSAI2P_DIV_23 01759 * @arg @ref LL_RCC_PLLSAI2P_DIV_24 01760 * @arg @ref LL_RCC_PLLSAI2P_DIV_25 01761 * @arg @ref LL_RCC_PLLSAI2P_DIV_26 01762 * @arg @ref LL_RCC_PLLSAI2P_DIV_27 01763 * @arg @ref LL_RCC_PLLSAI2P_DIV_28 01764 * @arg @ref LL_RCC_PLLSAI2P_DIV_29 01765 * @arg @ref LL_RCC_PLLSAI2P_DIV_30 01766 * @arg @ref LL_RCC_PLLSAI2P_DIV_31 01767 * @retval PLLSAI2 clock frequency (in Hz) 01768 */ 01769 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \ 01770 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \ 01771 ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) 01772 01773 #else 01774 /** 01775 * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain 01776 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01777 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ()); 01778 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01779 * @param __PLLM__ This parameter can be one of the following values: 01780 * @arg @ref LL_RCC_PLLM_DIV_1 01781 * @arg @ref LL_RCC_PLLM_DIV_2 01782 * @arg @ref LL_RCC_PLLM_DIV_3 01783 * @arg @ref LL_RCC_PLLM_DIV_4 01784 * @arg @ref LL_RCC_PLLM_DIV_5 01785 * @arg @ref LL_RCC_PLLM_DIV_6 01786 * @arg @ref LL_RCC_PLLM_DIV_7 01787 * @arg @ref LL_RCC_PLLM_DIV_8 01788 * @param __PLLSAI2N__ Between 8 and 86 01789 * @param __PLLSAI2P__ This parameter can be one of the following values: 01790 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 01791 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 01792 * @retval PLLSAI2 clock frequency (in Hz) 01793 */ 01794 #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \ 01795 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \ 01796 (((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U)) 01797 01798 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ 01799 01800 #if defined(LTDC) 01801 /** 01802 * @brief Helper macro to calculate the PLLSAI2 frequency used for LTDC domain 01803 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (), 01804 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR (), @ref LL_RCC_PLLSAI2_GetDIVR ()); 01805 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI) 01806 * @param __PLLSAI2M__ This parameter can be one of the following values: 01807 * @arg @ref LL_RCC_PLLSAI2M_DIV_1 01808 * @arg @ref LL_RCC_PLLSAI2M_DIV_2 01809 * @arg @ref LL_RCC_PLLSAI2M_DIV_3 01810 * @arg @ref LL_RCC_PLLSAI2M_DIV_4 01811 * @arg @ref LL_RCC_PLLSAI2M_DIV_5 01812 * @arg @ref LL_RCC_PLLSAI2M_DIV_6 01813 * @arg @ref LL_RCC_PLLSAI2M_DIV_7 01814 * @arg @ref LL_RCC_PLLSAI2M_DIV_8 01815 * @arg @ref LL_RCC_PLLSAI2M_DIV_9 01816 * @arg @ref LL_RCC_PLLSAI2M_DIV_10 01817 * @arg @ref LL_RCC_PLLSAI2M_DIV_11 01818 * @arg @ref LL_RCC_PLLSAI2M_DIV_12 01819 * @arg @ref LL_RCC_PLLSAI2M_DIV_13 01820 * @arg @ref LL_RCC_PLLSAI2M_DIV_14 01821 * @arg @ref LL_RCC_PLLSAI2M_DIV_15 01822 * @arg @ref LL_RCC_PLLSAI2M_DIV_16 01823 * @param __PLLSAI2N__ Between 8 and 86 01824 * @param __PLLSAI2R__ This parameter can be one of the following values: 01825 * @arg @ref LL_RCC_PLLSAI2R_DIV_2 01826 * @arg @ref LL_RCC_PLLSAI2R_DIV_4 01827 * @arg @ref LL_RCC_PLLSAI2R_DIV_6 01828 * @arg @ref LL_RCC_PLLSAI2R_DIV_8 01829 * @param __PLLSAI2DIVR__ This parameter can be one of the following values: 01830 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2 01831 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4 01832 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8 01833 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16 01834 * @retval PLLSAI2 clock frequency (in Hz) 01835 */ 01836 #define __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2R__, __PLLSAI2DIVR__) \ 01837 (((__INPUTFREQ__) / (((__PLLSAI2M__)>> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ 01838 (((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (aRCC_PLLSAI2DIVRPrescTable[(__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos]))) 01839 #else 01840 /** 01841 * @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain 01842 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01843 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR ()); 01844 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) 01845 * @param __PLLM__ This parameter can be one of the following values: 01846 * @arg @ref LL_RCC_PLLM_DIV_1 01847 * @arg @ref LL_RCC_PLLM_DIV_2 01848 * @arg @ref LL_RCC_PLLM_DIV_3 01849 * @arg @ref LL_RCC_PLLM_DIV_4 01850 * @arg @ref LL_RCC_PLLM_DIV_5 01851 * @arg @ref LL_RCC_PLLM_DIV_6 01852 * @arg @ref LL_RCC_PLLM_DIV_7 01853 * @arg @ref LL_RCC_PLLM_DIV_8 01854 * @param __PLLSAI2N__ Between 8 and 86 01855 * @param __PLLSAI2R__ This parameter can be one of the following values: 01856 * @arg @ref LL_RCC_PLLSAI2R_DIV_2 01857 * @arg @ref LL_RCC_PLLSAI2R_DIV_4 01858 * @arg @ref LL_RCC_PLLSAI2R_DIV_6 01859 * @arg @ref LL_RCC_PLLSAI2R_DIV_8 01860 * @retval PLLSAI2 clock frequency (in Hz) 01861 */ 01862 #define __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) \ 01863 ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \ 01864 ((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U)) 01865 01866 #endif /* LTDC */ 01867 01868 #if defined(DSI) 01869 /** 01870 * @brief Helper macro to calculate the PLLDSICLK frequency used on DSI 01871 * @note ex: @ref __LL_RCC_CALC_PLLSAI2_DSI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (), 01872 * @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetQ ()); 01873 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI) 01874 * @param __PLLSAI2M__ This parameter can be one of the following values: 01875 * @arg @ref LL_RCC_PLLSAI2M_DIV_1 01876 * @arg @ref LL_RCC_PLLSAI2M_DIV_2 01877 * @arg @ref LL_RCC_PLLSAI2M_DIV_3 01878 * @arg @ref LL_RCC_PLLSAI2M_DIV_4 01879 * @arg @ref LL_RCC_PLLSAI2M_DIV_5 01880 * @arg @ref LL_RCC_PLLSAI2M_DIV_6 01881 * @arg @ref LL_RCC_PLLSAI2M_DIV_7 01882 * @arg @ref LL_RCC_PLLSAI2M_DIV_8 01883 * @arg @ref LL_RCC_PLLSAI2M_DIV_9 01884 * @arg @ref LL_RCC_PLLSAI2M_DIV_10 01885 * @arg @ref LL_RCC_PLLSAI2M_DIV_11 01886 * @arg @ref LL_RCC_PLLSAI2M_DIV_12 01887 * @arg @ref LL_RCC_PLLSAI2M_DIV_13 01888 * @arg @ref LL_RCC_PLLSAI2M_DIV_14 01889 * @arg @ref LL_RCC_PLLSAI2M_DIV_15 01890 * @arg @ref LL_RCC_PLLSAI2M_DIV_16 01891 * @param __PLLSAI2N__ Between 8 and 86 01892 * @param __PLLSAI2Q__ This parameter can be one of the following values: 01893 * @arg @ref LL_RCC_PLLSAI2Q_DIV_2 01894 * @arg @ref LL_RCC_PLLSAI2Q_DIV_4 01895 * @arg @ref LL_RCC_PLLSAI2Q_DIV_6 01896 * @arg @ref LL_RCC_PLLSAI2Q_DIV_8 01897 * @retval PLL clock frequency (in Hz) 01898 */ 01899 #define __LL_RCC_CALC_PLLSAI2_DSI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2Q__) \ 01900 ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ 01901 ((((__PLLSAI2Q__) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) << 1U)) 01902 #endif /* DSI */ 01903 01904 01905 01906 /** 01907 * @brief Helper macro to calculate the HCLK frequency 01908 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) 01909 * @param __AHBPRESCALER__ This parameter can be one of the following values: 01910 * @arg @ref LL_RCC_SYSCLK_DIV_1 01911 * @arg @ref LL_RCC_SYSCLK_DIV_2 01912 * @arg @ref LL_RCC_SYSCLK_DIV_4 01913 * @arg @ref LL_RCC_SYSCLK_DIV_8 01914 * @arg @ref LL_RCC_SYSCLK_DIV_16 01915 * @arg @ref LL_RCC_SYSCLK_DIV_64 01916 * @arg @ref LL_RCC_SYSCLK_DIV_128 01917 * @arg @ref LL_RCC_SYSCLK_DIV_256 01918 * @arg @ref LL_RCC_SYSCLK_DIV_512 01919 * @retval HCLK clock frequency (in Hz) 01920 */ 01921 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) 01922 01923 /** 01924 * @brief Helper macro to calculate the PCLK1 frequency (ABP1) 01925 * @param __HCLKFREQ__ HCLK frequency 01926 * @param __APB1PRESCALER__ This parameter can be one of the following values: 01927 * @arg @ref LL_RCC_APB1_DIV_1 01928 * @arg @ref LL_RCC_APB1_DIV_2 01929 * @arg @ref LL_RCC_APB1_DIV_4 01930 * @arg @ref LL_RCC_APB1_DIV_8 01931 * @arg @ref LL_RCC_APB1_DIV_16 01932 * @retval PCLK1 clock frequency (in Hz) 01933 */ 01934 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) 01935 01936 /** 01937 * @brief Helper macro to calculate the PCLK2 frequency (ABP2) 01938 * @param __HCLKFREQ__ HCLK frequency 01939 * @param __APB2PRESCALER__ This parameter can be one of the following values: 01940 * @arg @ref LL_RCC_APB2_DIV_1 01941 * @arg @ref LL_RCC_APB2_DIV_2 01942 * @arg @ref LL_RCC_APB2_DIV_4 01943 * @arg @ref LL_RCC_APB2_DIV_8 01944 * @arg @ref LL_RCC_APB2_DIV_16 01945 * @retval PCLK2 clock frequency (in Hz) 01946 */ 01947 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) 01948 01949 /** 01950 * @brief Helper macro to calculate the MSI frequency (in Hz) 01951 * @note __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect() 01952 * @note if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY, 01953 * __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby() 01954 * else by LL_RCC_MSI_GetRange() 01955 * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01956 * (LL_RCC_MSI_IsEnabledRangeSelect()? 01957 * LL_RCC_MSI_GetRange(): 01958 * LL_RCC_MSI_GetRangeAfterStandby())) 01959 * @param __MSISEL__ This parameter can be one of the following values: 01960 * @arg @ref LL_RCC_MSIRANGESEL_STANDBY 01961 * @arg @ref LL_RCC_MSIRANGESEL_RUN 01962 * @param __MSIRANGE__ This parameter can be one of the following values: 01963 * @arg @ref LL_RCC_MSIRANGE_0 01964 * @arg @ref LL_RCC_MSIRANGE_1 01965 * @arg @ref LL_RCC_MSIRANGE_2 01966 * @arg @ref LL_RCC_MSIRANGE_3 01967 * @arg @ref LL_RCC_MSIRANGE_4 01968 * @arg @ref LL_RCC_MSIRANGE_5 01969 * @arg @ref LL_RCC_MSIRANGE_6 01970 * @arg @ref LL_RCC_MSIRANGE_7 01971 * @arg @ref LL_RCC_MSIRANGE_8 01972 * @arg @ref LL_RCC_MSIRANGE_9 01973 * @arg @ref LL_RCC_MSIRANGE_10 01974 * @arg @ref LL_RCC_MSIRANGE_11 01975 * @arg @ref LL_RCC_MSISRANGE_4 01976 * @arg @ref LL_RCC_MSISRANGE_5 01977 * @arg @ref LL_RCC_MSISRANGE_6 01978 * @arg @ref LL_RCC_MSISRANGE_7 01979 * @retval MSI clock frequency (in Hz) 01980 */ 01981 #define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \ 01982 (MSIRangeTable[(__MSIRANGE__) >> 8U]) : \ 01983 (MSIRangeTable[(__MSIRANGE__) >> 4U])) 01984 01985 /** 01986 * @} 01987 */ 01988 01989 /** 01990 * @} 01991 */ 01992 01993 /* Exported functions --------------------------------------------------------*/ 01994 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions 01995 * @{ 01996 */ 01997 01998 /** @defgroup RCC_LL_EF_HSE HSE 01999 * @{ 02000 */ 02001 02002 /** 02003 * @brief Enable the Clock Security System. 02004 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS 02005 * @retval None 02006 */ 02007 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) 02008 { 02009 SET_BIT(RCC->CR, RCC_CR_CSSON); 02010 } 02011 02012 /** 02013 * @brief Enable HSE external oscillator (HSE Bypass) 02014 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass 02015 * @retval None 02016 */ 02017 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) 02018 { 02019 SET_BIT(RCC->CR, RCC_CR_HSEBYP); 02020 } 02021 02022 /** 02023 * @brief Disable HSE external oscillator (HSE Bypass) 02024 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass 02025 * @retval None 02026 */ 02027 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) 02028 { 02029 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 02030 } 02031 02032 /** 02033 * @brief Enable HSE crystal oscillator (HSE ON) 02034 * @rmtoll CR HSEON LL_RCC_HSE_Enable 02035 * @retval None 02036 */ 02037 __STATIC_INLINE void LL_RCC_HSE_Enable(void) 02038 { 02039 SET_BIT(RCC->CR, RCC_CR_HSEON); 02040 } 02041 02042 /** 02043 * @brief Disable HSE crystal oscillator (HSE ON) 02044 * @rmtoll CR HSEON LL_RCC_HSE_Disable 02045 * @retval None 02046 */ 02047 __STATIC_INLINE void LL_RCC_HSE_Disable(void) 02048 { 02049 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); 02050 } 02051 02052 /** 02053 * @brief Check if HSE oscillator Ready 02054 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady 02055 * @retval State of bit (1 or 0). 02056 */ 02057 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) 02058 { 02059 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); 02060 } 02061 02062 /** 02063 * @} 02064 */ 02065 02066 /** @defgroup RCC_LL_EF_HSI HSI 02067 * @{ 02068 */ 02069 02070 /** 02071 * @brief Enable HSI even in stop mode 02072 * @note HSI oscillator is forced ON even in Stop mode 02073 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode 02074 * @retval None 02075 */ 02076 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) 02077 { 02078 SET_BIT(RCC->CR, RCC_CR_HSIKERON); 02079 } 02080 02081 /** 02082 * @brief Disable HSI in stop mode 02083 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode 02084 * @retval None 02085 */ 02086 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) 02087 { 02088 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); 02089 } 02090 02091 /** 02092 * @brief Check if HSI is enabled in stop mode 02093 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode 02094 * @retval State of bit (1 or 0). 02095 */ 02096 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) 02097 { 02098 return (READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)); 02099 } 02100 02101 /** 02102 * @brief Enable HSI oscillator 02103 * @rmtoll CR HSION LL_RCC_HSI_Enable 02104 * @retval None 02105 */ 02106 __STATIC_INLINE void LL_RCC_HSI_Enable(void) 02107 { 02108 SET_BIT(RCC->CR, RCC_CR_HSION); 02109 } 02110 02111 /** 02112 * @brief Disable HSI oscillator 02113 * @rmtoll CR HSION LL_RCC_HSI_Disable 02114 * @retval None 02115 */ 02116 __STATIC_INLINE void LL_RCC_HSI_Disable(void) 02117 { 02118 CLEAR_BIT(RCC->CR, RCC_CR_HSION); 02119 } 02120 02121 /** 02122 * @brief Check if HSI clock is ready 02123 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady 02124 * @retval State of bit (1 or 0). 02125 */ 02126 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) 02127 { 02128 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); 02129 } 02130 02131 /** 02132 * @brief Enable HSI Automatic from stop mode 02133 * @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop 02134 * @retval None 02135 */ 02136 __STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void) 02137 { 02138 SET_BIT(RCC->CR, RCC_CR_HSIASFS); 02139 } 02140 02141 /** 02142 * @brief Disable HSI Automatic from stop mode 02143 * @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop 02144 * @retval None 02145 */ 02146 __STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void) 02147 { 02148 CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS); 02149 } 02150 /** 02151 * @brief Get HSI Calibration value 02152 * @note When HSITRIM is written, HSICAL is updated with the sum of 02153 * HSITRIM and the factory trim value 02154 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration 02155 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF 02156 */ 02157 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) 02158 { 02159 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos); 02160 } 02161 02162 /** 02163 * @brief Set HSI Calibration trimming 02164 * @note user-programmable trimming value that is added to the HSICAL 02165 * @note Default value is 16, which, when added to the HSICAL value, 02166 * should trim the HSI to 16 MHz +/- 1 % 02167 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming 02168 * @param Value Between Min_Data = 0 and Max_Data = 31 02169 * @retval None 02170 */ 02171 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) 02172 { 02173 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); 02174 } 02175 02176 /** 02177 * @brief Get HSI Calibration trimming 02178 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming 02179 * @retval Between Min_Data = 0 and Max_Data = 31 02180 */ 02181 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) 02182 { 02183 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); 02184 } 02185 02186 /** 02187 * @} 02188 */ 02189 02190 #if defined(RCC_HSI48_SUPPORT) 02191 /** @defgroup RCC_LL_EF_HSI48 HSI48 02192 * @{ 02193 */ 02194 02195 /** 02196 * @brief Enable HSI48 02197 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable 02198 * @retval None 02199 */ 02200 __STATIC_INLINE void LL_RCC_HSI48_Enable(void) 02201 { 02202 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); 02203 } 02204 02205 /** 02206 * @brief Disable HSI48 02207 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable 02208 * @retval None 02209 */ 02210 __STATIC_INLINE void LL_RCC_HSI48_Disable(void) 02211 { 02212 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); 02213 } 02214 02215 /** 02216 * @brief Check if HSI48 oscillator Ready 02217 * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady 02218 * @retval State of bit (1 or 0). 02219 */ 02220 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) 02221 { 02222 return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)); 02223 } 02224 02225 /** 02226 * @brief Get HSI48 Calibration value 02227 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration 02228 * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF 02229 */ 02230 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) 02231 { 02232 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos); 02233 } 02234 02235 /** 02236 * @} 02237 */ 02238 #endif /* RCC_HSI48_SUPPORT */ 02239 02240 /** @defgroup RCC_LL_EF_LSE LSE 02241 * @{ 02242 */ 02243 02244 /** 02245 * @brief Enable Low Speed External (LSE) crystal. 02246 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable 02247 * @retval None 02248 */ 02249 __STATIC_INLINE void LL_RCC_LSE_Enable(void) 02250 { 02251 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); 02252 } 02253 02254 /** 02255 * @brief Disable Low Speed External (LSE) crystal. 02256 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable 02257 * @retval None 02258 */ 02259 __STATIC_INLINE void LL_RCC_LSE_Disable(void) 02260 { 02261 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); 02262 } 02263 02264 /** 02265 * @brief Enable external clock source (LSE bypass). 02266 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass 02267 * @retval None 02268 */ 02269 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) 02270 { 02271 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 02272 } 02273 02274 /** 02275 * @brief Disable external clock source (LSE bypass). 02276 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass 02277 * @retval None 02278 */ 02279 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) 02280 { 02281 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 02282 } 02283 02284 /** 02285 * @brief Set LSE oscillator drive capability 02286 * @note The oscillator is in Xtal mode when it is not in bypass mode. 02287 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability 02288 * @param LSEDrive This parameter can be one of the following values: 02289 * @arg @ref LL_RCC_LSEDRIVE_LOW 02290 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW 02291 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH 02292 * @arg @ref LL_RCC_LSEDRIVE_HIGH 02293 * @retval None 02294 */ 02295 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) 02296 { 02297 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); 02298 } 02299 02300 /** 02301 * @brief Get LSE oscillator drive capability 02302 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability 02303 * @retval Returned value can be one of the following values: 02304 * @arg @ref LL_RCC_LSEDRIVE_LOW 02305 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW 02306 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH 02307 * @arg @ref LL_RCC_LSEDRIVE_HIGH 02308 */ 02309 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) 02310 { 02311 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); 02312 } 02313 02314 /** 02315 * @brief Enable Clock security system on LSE. 02316 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS 02317 * @retval None 02318 */ 02319 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) 02320 { 02321 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); 02322 } 02323 02324 /** 02325 * @brief Disable Clock security system on LSE. 02326 * @note Clock security system can be disabled only after a LSE 02327 * failure detection. In that case it MUST be disabled by software. 02328 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS 02329 * @retval None 02330 */ 02331 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) 02332 { 02333 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); 02334 } 02335 02336 /** 02337 * @brief Check if LSE oscillator Ready 02338 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady 02339 * @retval State of bit (1 or 0). 02340 */ 02341 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) 02342 { 02343 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); 02344 } 02345 02346 /** 02347 * @brief Check if CSS on LSE failure Detection 02348 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected 02349 * @retval State of bit (1 or 0). 02350 */ 02351 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) 02352 { 02353 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)); 02354 } 02355 02356 /** 02357 * @} 02358 */ 02359 02360 /** @defgroup RCC_LL_EF_LSI LSI 02361 * @{ 02362 */ 02363 02364 /** 02365 * @brief Enable LSI Oscillator 02366 * @rmtoll CSR LSION LL_RCC_LSI_Enable 02367 * @retval None 02368 */ 02369 __STATIC_INLINE void LL_RCC_LSI_Enable(void) 02370 { 02371 SET_BIT(RCC->CSR, RCC_CSR_LSION); 02372 } 02373 02374 /** 02375 * @brief Disable LSI Oscillator 02376 * @rmtoll CSR LSION LL_RCC_LSI_Disable 02377 * @retval None 02378 */ 02379 __STATIC_INLINE void LL_RCC_LSI_Disable(void) 02380 { 02381 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); 02382 } 02383 02384 /** 02385 * @brief Check if LSI is Ready 02386 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady 02387 * @retval State of bit (1 or 0). 02388 */ 02389 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) 02390 { 02391 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); 02392 } 02393 02394 /** 02395 * @} 02396 */ 02397 02398 /** @defgroup RCC_LL_EF_MSI MSI 02399 * @{ 02400 */ 02401 02402 /** 02403 * @brief Enable MSI oscillator 02404 * @rmtoll CR MSION LL_RCC_MSI_Enable 02405 * @retval None 02406 */ 02407 __STATIC_INLINE void LL_RCC_MSI_Enable(void) 02408 { 02409 SET_BIT(RCC->CR, RCC_CR_MSION); 02410 } 02411 02412 /** 02413 * @brief Disable MSI oscillator 02414 * @rmtoll CR MSION LL_RCC_MSI_Disable 02415 * @retval None 02416 */ 02417 __STATIC_INLINE void LL_RCC_MSI_Disable(void) 02418 { 02419 CLEAR_BIT(RCC->CR, RCC_CR_MSION); 02420 } 02421 02422 /** 02423 * @brief Check if MSI oscillator Ready 02424 * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady 02425 * @retval State of bit (1 or 0). 02426 */ 02427 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void) 02428 { 02429 return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)); 02430 } 02431 02432 /** 02433 * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE) 02434 * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) 02435 * and ready (LSERDY set by hardware) 02436 * @note hardware protection to avoid enabling MSIPLLEN if LSE is not 02437 * ready 02438 * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode 02439 * @retval None 02440 */ 02441 __STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void) 02442 { 02443 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN); 02444 } 02445 02446 /** 02447 * @brief Disable MSI-PLL mode 02448 * @note cleared by hardware when LSE is disabled (LSEON = 0) or when 02449 * the Clock Security System on LSE detects a LSE failure 02450 * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode 02451 * @retval None 02452 */ 02453 __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void) 02454 { 02455 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN); 02456 } 02457 02458 /** 02459 * @brief Enable MSI clock range selection with MSIRANGE register 02460 * @note Write 0 has no effect. After a standby or a reset 02461 * MSIRGSEL is at 0 and the MSI range value is provided by 02462 * MSISRANGE 02463 * @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection 02464 * @retval None 02465 */ 02466 __STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void) 02467 { 02468 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); 02469 } 02470 02471 /** 02472 * @brief Check if MSI clock range is selected with MSIRANGE register 02473 * @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect 02474 * @retval State of bit (1 or 0). 02475 */ 02476 __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void) 02477 { 02478 return (READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL)); 02479 } 02480 02481 /** 02482 * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode. 02483 * @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange 02484 * @param Range This parameter can be one of the following values: 02485 * @arg @ref LL_RCC_MSIRANGE_0 02486 * @arg @ref LL_RCC_MSIRANGE_1 02487 * @arg @ref LL_RCC_MSIRANGE_2 02488 * @arg @ref LL_RCC_MSIRANGE_3 02489 * @arg @ref LL_RCC_MSIRANGE_4 02490 * @arg @ref LL_RCC_MSIRANGE_5 02491 * @arg @ref LL_RCC_MSIRANGE_6 02492 * @arg @ref LL_RCC_MSIRANGE_7 02493 * @arg @ref LL_RCC_MSIRANGE_8 02494 * @arg @ref LL_RCC_MSIRANGE_9 02495 * @arg @ref LL_RCC_MSIRANGE_10 02496 * @arg @ref LL_RCC_MSIRANGE_11 02497 * @retval None 02498 */ 02499 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range) 02500 { 02501 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range); 02502 } 02503 02504 /** 02505 * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode. 02506 * @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange 02507 * @retval Returned value can be one of the following values: 02508 * @arg @ref LL_RCC_MSIRANGE_0 02509 * @arg @ref LL_RCC_MSIRANGE_1 02510 * @arg @ref LL_RCC_MSIRANGE_2 02511 * @arg @ref LL_RCC_MSIRANGE_3 02512 * @arg @ref LL_RCC_MSIRANGE_4 02513 * @arg @ref LL_RCC_MSIRANGE_5 02514 * @arg @ref LL_RCC_MSIRANGE_6 02515 * @arg @ref LL_RCC_MSIRANGE_7 02516 * @arg @ref LL_RCC_MSIRANGE_8 02517 * @arg @ref LL_RCC_MSIRANGE_9 02518 * @arg @ref LL_RCC_MSIRANGE_10 02519 * @arg @ref LL_RCC_MSIRANGE_11 02520 */ 02521 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void) 02522 { 02523 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)); 02524 } 02525 02526 /** 02527 * @brief Configure MSI range used after standby 02528 * @rmtoll CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby 02529 * @param Range This parameter can be one of the following values: 02530 * @arg @ref LL_RCC_MSISRANGE_4 02531 * @arg @ref LL_RCC_MSISRANGE_5 02532 * @arg @ref LL_RCC_MSISRANGE_6 02533 * @arg @ref LL_RCC_MSISRANGE_7 02534 * @retval None 02535 */ 02536 __STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range) 02537 { 02538 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range); 02539 } 02540 02541 /** 02542 * @brief Get MSI range used after standby 02543 * @rmtoll CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby 02544 * @retval Returned value can be one of the following values: 02545 * @arg @ref LL_RCC_MSISRANGE_4 02546 * @arg @ref LL_RCC_MSISRANGE_5 02547 * @arg @ref LL_RCC_MSISRANGE_6 02548 * @arg @ref LL_RCC_MSISRANGE_7 02549 */ 02550 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void) 02551 { 02552 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE)); 02553 } 02554 02555 /** 02556 * @brief Get MSI Calibration value 02557 * @note When MSITRIM is written, MSICAL is updated with the sum of 02558 * MSITRIM and the factory trim value 02559 * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration 02560 * @retval Between Min_Data = 0 and Max_Data = 255 02561 */ 02562 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void) 02563 { 02564 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos); 02565 } 02566 02567 /** 02568 * @brief Set MSI Calibration trimming 02569 * @note user-programmable trimming value that is added to the MSICAL 02570 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming 02571 * @param Value Between Min_Data = 0 and Max_Data = 255 02572 * @retval None 02573 */ 02574 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value) 02575 { 02576 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos); 02577 } 02578 02579 /** 02580 * @brief Get MSI Calibration trimming 02581 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming 02582 * @retval Between 0 and 255 02583 */ 02584 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void) 02585 { 02586 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos); 02587 } 02588 02589 /** 02590 * @} 02591 */ 02592 02593 /** @defgroup RCC_LL_EF_LSCO LSCO 02594 * @{ 02595 */ 02596 02597 /** 02598 * @brief Enable Low speed clock 02599 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable 02600 * @retval None 02601 */ 02602 __STATIC_INLINE void LL_RCC_LSCO_Enable(void) 02603 { 02604 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); 02605 } 02606 02607 /** 02608 * @brief Disable Low speed clock 02609 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable 02610 * @retval None 02611 */ 02612 __STATIC_INLINE void LL_RCC_LSCO_Disable(void) 02613 { 02614 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); 02615 } 02616 02617 /** 02618 * @brief Configure Low speed clock selection 02619 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource 02620 * @param Source This parameter can be one of the following values: 02621 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI 02622 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE 02623 * @retval None 02624 */ 02625 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) 02626 { 02627 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source); 02628 } 02629 02630 /** 02631 * @brief Get Low speed clock selection 02632 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource 02633 * @retval Returned value can be one of the following values: 02634 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI 02635 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE 02636 */ 02637 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) 02638 { 02639 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL)); 02640 } 02641 02642 /** 02643 * @} 02644 */ 02645 02646 /** @defgroup RCC_LL_EF_System System 02647 * @{ 02648 */ 02649 02650 /** 02651 * @brief Configure the system clock source 02652 * @rmtoll CFGR SW LL_RCC_SetSysClkSource 02653 * @param Source This parameter can be one of the following values: 02654 * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI 02655 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI 02656 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE 02657 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL 02658 * @retval None 02659 */ 02660 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) 02661 { 02662 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); 02663 } 02664 02665 /** 02666 * @brief Get the system clock source 02667 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource 02668 * @retval Returned value can be one of the following values: 02669 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI 02670 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI 02671 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE 02672 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL 02673 */ 02674 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) 02675 { 02676 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); 02677 } 02678 02679 /** 02680 * @brief Set AHB prescaler 02681 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler 02682 * @param Prescaler This parameter can be one of the following values: 02683 * @arg @ref LL_RCC_SYSCLK_DIV_1 02684 * @arg @ref LL_RCC_SYSCLK_DIV_2 02685 * @arg @ref LL_RCC_SYSCLK_DIV_4 02686 * @arg @ref LL_RCC_SYSCLK_DIV_8 02687 * @arg @ref LL_RCC_SYSCLK_DIV_16 02688 * @arg @ref LL_RCC_SYSCLK_DIV_64 02689 * @arg @ref LL_RCC_SYSCLK_DIV_128 02690 * @arg @ref LL_RCC_SYSCLK_DIV_256 02691 * @arg @ref LL_RCC_SYSCLK_DIV_512 02692 * @retval None 02693 */ 02694 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) 02695 { 02696 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); 02697 } 02698 02699 /** 02700 * @brief Set APB1 prescaler 02701 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler 02702 * @param Prescaler This parameter can be one of the following values: 02703 * @arg @ref LL_RCC_APB1_DIV_1 02704 * @arg @ref LL_RCC_APB1_DIV_2 02705 * @arg @ref LL_RCC_APB1_DIV_4 02706 * @arg @ref LL_RCC_APB1_DIV_8 02707 * @arg @ref LL_RCC_APB1_DIV_16 02708 * @retval None 02709 */ 02710 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) 02711 { 02712 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); 02713 } 02714 02715 /** 02716 * @brief Set APB2 prescaler 02717 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler 02718 * @param Prescaler This parameter can be one of the following values: 02719 * @arg @ref LL_RCC_APB2_DIV_1 02720 * @arg @ref LL_RCC_APB2_DIV_2 02721 * @arg @ref LL_RCC_APB2_DIV_4 02722 * @arg @ref LL_RCC_APB2_DIV_8 02723 * @arg @ref LL_RCC_APB2_DIV_16 02724 * @retval None 02725 */ 02726 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) 02727 { 02728 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); 02729 } 02730 02731 /** 02732 * @brief Get AHB prescaler 02733 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler 02734 * @retval Returned value can be one of the following values: 02735 * @arg @ref LL_RCC_SYSCLK_DIV_1 02736 * @arg @ref LL_RCC_SYSCLK_DIV_2 02737 * @arg @ref LL_RCC_SYSCLK_DIV_4 02738 * @arg @ref LL_RCC_SYSCLK_DIV_8 02739 * @arg @ref LL_RCC_SYSCLK_DIV_16 02740 * @arg @ref LL_RCC_SYSCLK_DIV_64 02741 * @arg @ref LL_RCC_SYSCLK_DIV_128 02742 * @arg @ref LL_RCC_SYSCLK_DIV_256 02743 * @arg @ref LL_RCC_SYSCLK_DIV_512 02744 */ 02745 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) 02746 { 02747 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); 02748 } 02749 02750 /** 02751 * @brief Get APB1 prescaler 02752 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler 02753 * @retval Returned value can be one of the following values: 02754 * @arg @ref LL_RCC_APB1_DIV_1 02755 * @arg @ref LL_RCC_APB1_DIV_2 02756 * @arg @ref LL_RCC_APB1_DIV_4 02757 * @arg @ref LL_RCC_APB1_DIV_8 02758 * @arg @ref LL_RCC_APB1_DIV_16 02759 */ 02760 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) 02761 { 02762 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); 02763 } 02764 02765 /** 02766 * @brief Get APB2 prescaler 02767 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler 02768 * @retval Returned value can be one of the following values: 02769 * @arg @ref LL_RCC_APB2_DIV_1 02770 * @arg @ref LL_RCC_APB2_DIV_2 02771 * @arg @ref LL_RCC_APB2_DIV_4 02772 * @arg @ref LL_RCC_APB2_DIV_8 02773 * @arg @ref LL_RCC_APB2_DIV_16 02774 */ 02775 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) 02776 { 02777 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); 02778 } 02779 02780 /** 02781 * @brief Set Clock After Wake-Up From Stop mode 02782 * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop 02783 * @param Clock This parameter can be one of the following values: 02784 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI 02785 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI 02786 * @retval None 02787 */ 02788 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock) 02789 { 02790 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); 02791 } 02792 02793 /** 02794 * @brief Get Clock After Wake-Up From Stop mode 02795 * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop 02796 * @retval Returned value can be one of the following values: 02797 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI 02798 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI 02799 */ 02800 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void) 02801 { 02802 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK)); 02803 } 02804 02805 /** 02806 * @} 02807 */ 02808 02809 /** @defgroup RCC_LL_EF_MCO MCO 02810 * @{ 02811 */ 02812 02813 /** 02814 * @brief Configure MCOx 02815 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n 02816 * CFGR MCOPRE LL_RCC_ConfigMCO 02817 * @param MCOxSource This parameter can be one of the following values: 02818 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK 02819 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK 02820 * @arg @ref LL_RCC_MCO1SOURCE_MSI 02821 * @arg @ref LL_RCC_MCO1SOURCE_HSI 02822 * @arg @ref LL_RCC_MCO1SOURCE_HSE 02823 * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) 02824 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK 02825 * @arg @ref LL_RCC_MCO1SOURCE_LSI 02826 * @arg @ref LL_RCC_MCO1SOURCE_LSE 02827 * 02828 * (*) value not defined in all devices. 02829 * @param MCOxPrescaler This parameter can be one of the following values: 02830 * @arg @ref LL_RCC_MCO1_DIV_1 02831 * @arg @ref LL_RCC_MCO1_DIV_2 02832 * @arg @ref LL_RCC_MCO1_DIV_4 02833 * @arg @ref LL_RCC_MCO1_DIV_8 02834 * @arg @ref LL_RCC_MCO1_DIV_16 02835 * @retval None 02836 */ 02837 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) 02838 { 02839 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); 02840 } 02841 02842 /** 02843 * @} 02844 */ 02845 02846 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source 02847 * @{ 02848 */ 02849 02850 /** 02851 * @brief Configure USARTx clock source 02852 * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource 02853 * @param USARTxSource This parameter can be one of the following values: 02854 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 02855 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK 02856 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI 02857 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE 02858 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 02859 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK 02860 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI 02861 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE 02862 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) 02863 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) 02864 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) 02865 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) 02866 * 02867 * (*) value not defined in all devices. 02868 * @retval None 02869 */ 02870 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) 02871 { 02872 MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFF)); 02873 } 02874 02875 #if defined(UART4) || defined(UART5) 02876 /** 02877 * @brief Configure UARTx clock source 02878 * @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource 02879 * @param UARTxSource This parameter can be one of the following values: 02880 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 02881 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK 02882 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI 02883 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE 02884 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 02885 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK 02886 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI 02887 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE 02888 * @retval None 02889 */ 02890 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) 02891 { 02892 MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16), (UARTxSource & 0x0000FFFF)); 02893 } 02894 #endif /* UART4 || UART5 */ 02895 02896 /** 02897 * @brief Configure LPUART1x clock source 02898 * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource 02899 * @param LPUARTxSource This parameter can be one of the following values: 02900 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 02901 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK 02902 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI 02903 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE 02904 * @retval None 02905 */ 02906 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) 02907 { 02908 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); 02909 } 02910 02911 /** 02912 * @brief Configure I2Cx clock source 02913 * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource 02914 * @param I2CxSource This parameter can be one of the following values: 02915 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 02916 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK 02917 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI 02918 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*) 02919 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) 02920 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) 02921 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 02922 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK 02923 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI 02924 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) 02925 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) 02926 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) 02927 * 02928 * (*) value not defined in all devices. 02929 * @retval None 02930 */ 02931 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) 02932 { 02933 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U)); 02934 MODIFY_REG(*reg, 3U << ((I2CxSource & 0x00FF0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x00FF0000U) >> 16U))); 02935 } 02936 02937 /** 02938 * @brief Configure LPTIMx clock source 02939 * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource 02940 * @param LPTIMxSource This parameter can be one of the following values: 02941 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 02942 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI 02943 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI 02944 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE 02945 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 02946 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI 02947 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI 02948 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE 02949 * @retval None 02950 */ 02951 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) 02952 { 02953 MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U)); 02954 } 02955 02956 /** 02957 * @brief Configure SAIx clock source 02958 @if STM32L4S9xx 02959 * @rmtoll CCIPR2 SAIxSEL LL_RCC_SetSAIClockSource 02960 @else 02961 * @rmtoll CCIPR SAIxSEL LL_RCC_SetSAIClockSource 02962 @endif 02963 * @param SAIxSource This parameter can be one of the following values: 02964 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1 02965 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*) 02966 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL 02967 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN 02968 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*) 02969 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*) 02970 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) 02971 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) 02972 * 02973 * (*) value not defined in all devices. 02974 * @retval None 02975 */ 02976 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) 02977 { 02978 #if defined(RCC_CCIPR2_SAI1SEL) 02979 MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU)); 02980 #else 02981 MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); 02982 #endif /* RCC_CCIPR2_SAI1SEL */ 02983 } 02984 02985 #if defined(RCC_CCIPR2_SDMMCSEL) 02986 /** 02987 * @brief Configure SDMMC1 kernel clock source 02988 * @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource 02989 * @param SDMMCxSource This parameter can be one of the following values: 02990 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*) 02991 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP (*) 02992 * 02993 * (*) value not defined in all devices. 02994 * @retval None 02995 */ 02996 __STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource) 02997 { 02998 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource); 02999 } 03000 #endif /* RCC_CCIPR2_SDMMCSEL */ 03001 03002 /** 03003 * @brief Configure SDMMC1 clock source 03004 * @rmtoll CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource 03005 * @param SDMMCxSource This parameter can be one of the following values: 03006 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*) 03007 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*) 03008 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*) 03009 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL 03010 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*) 03011 * 03012 * (*) value not defined in all devices. 03013 * @retval None 03014 */ 03015 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource) 03016 { 03017 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource); 03018 } 03019 03020 /** 03021 * @brief Configure RNG clock source 03022 * @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource 03023 * @param RNGxSource This parameter can be one of the following values: 03024 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*) 03025 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*) 03026 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 03027 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL 03028 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI 03029 * 03030 * (*) value not defined in all devices. 03031 * @retval None 03032 */ 03033 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) 03034 { 03035 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource); 03036 } 03037 03038 #if defined(USB_OTG_FS) || defined(USB) 03039 /** 03040 * @brief Configure USB clock source 03041 * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource 03042 * @param USBxSource This parameter can be one of the following values: 03043 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) 03044 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) 03045 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 03046 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL 03047 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI 03048 * 03049 * (*) value not defined in all devices. 03050 * @retval None 03051 */ 03052 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) 03053 { 03054 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource); 03055 } 03056 #endif /* USB_OTG_FS || USB */ 03057 03058 /** 03059 * @brief Configure ADC clock source 03060 * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource 03061 * @param ADCxSource This parameter can be one of the following values: 03062 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE 03063 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 03064 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*) 03065 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK 03066 * 03067 * (*) value not defined in all devices. 03068 * @retval None 03069 */ 03070 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) 03071 { 03072 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); 03073 } 03074 03075 #if defined(SWPMI1) 03076 /** 03077 * @brief Configure SWPMI clock source 03078 * @rmtoll CCIPR SWPMI1SEL LL_RCC_SetSWPMIClockSource 03079 * @param SWPMIxSource This parameter can be one of the following values: 03080 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1 03081 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI 03082 * @retval None 03083 */ 03084 __STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource) 03085 { 03086 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource); 03087 } 03088 #endif /* SWPMI1 */ 03089 03090 #if defined(DFSDM1_Channel0) 03091 #if defined(RCC_CCIPR2_ADFSDM1SEL) 03092 /** 03093 * @brief Configure DFSDM Audio clock source 03094 * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource 03095 * @param Source This parameter can be one of the following values: 03096 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 03097 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI 03098 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI 03099 * @retval None 03100 */ 03101 __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source) 03102 { 03103 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, Source); 03104 } 03105 #endif /* RCC_CCIPR2_ADFSDM1SEL */ 03106 03107 /** 03108 * @brief Configure DFSDM Kernel clock source 03109 @if STM32L4S9xx 03110 * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_SetDFSDMClockSource 03111 @else 03112 * @rmtoll CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource 03113 @endif 03114 * @param DFSDMxSource This parameter can be one of the following values: 03115 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 03116 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK 03117 * @retval None 03118 */ 03119 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource) 03120 { 03121 #if defined(RCC_CCIPR2_DFSDM1SEL) 03122 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, DFSDMxSource); 03123 #else 03124 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource); 03125 #endif /* RCC_CCIPR2_DFSDM1SEL */ 03126 } 03127 #endif /* DFSDM1_Channel0 */ 03128 03129 #if defined(DSI) 03130 /** 03131 * @brief Configure DSI clock source 03132 * @rmtoll CCIPR2 DSISEL LL_RCC_SetDSIClockSource 03133 * @param Source This parameter can be one of the following values: 03134 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY 03135 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL 03136 * @retval None 03137 */ 03138 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) 03139 { 03140 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, Source); 03141 } 03142 #endif /* DSI */ 03143 03144 #if defined(LTDC) 03145 /** 03146 * @brief Configure LTDC Clock Source 03147 * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_SetLTDCClockSource 03148 * @param Source This parameter can be one of the following values: 03149 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 03150 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 03151 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 03152 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 03153 * @retval None 03154 */ 03155 __STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source) 03156 { 03157 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, Source); 03158 } 03159 #endif /* LTDC */ 03160 03161 #if defined(OCTOSPI1) 03162 /** 03163 * @brief Configure OCTOSPI clock source 03164 * @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource 03165 * @param Source This parameter can be one of the following values: 03166 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 03167 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI 03168 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL 03169 * @retval None 03170 */ 03171 __STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source) 03172 { 03173 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, Source); 03174 } 03175 #endif /* OCTOSPI1 */ 03176 03177 /** 03178 * @brief Get USARTx clock source 03179 * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource 03180 * @param USARTx This parameter can be one of the following values: 03181 * @arg @ref LL_RCC_USART1_CLKSOURCE 03182 * @arg @ref LL_RCC_USART2_CLKSOURCE 03183 * @arg @ref LL_RCC_USART3_CLKSOURCE (*) 03184 * 03185 * (*) value not defined in all devices. 03186 * @retval Returned value can be one of the following values: 03187 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 03188 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK 03189 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI 03190 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE 03191 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 03192 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK 03193 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI 03194 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE 03195 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) 03196 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) 03197 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) 03198 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) 03199 * 03200 * (*) value not defined in all devices. 03201 */ 03202 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) 03203 { 03204 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U)); 03205 } 03206 03207 #if defined(UART4) || defined(UART5) 03208 /** 03209 * @brief Get UARTx clock source 03210 * @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource 03211 * @param UARTx This parameter can be one of the following values: 03212 * @arg @ref LL_RCC_UART4_CLKSOURCE 03213 * @arg @ref LL_RCC_UART5_CLKSOURCE 03214 * @retval Returned value can be one of the following values: 03215 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 03216 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK 03217 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI 03218 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE 03219 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 03220 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK 03221 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI 03222 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE 03223 */ 03224 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) 03225 { 03226 return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16U)); 03227 } 03228 #endif /* UART4 || UART5 */ 03229 03230 /** 03231 * @brief Get LPUARTx clock source 03232 * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource 03233 * @param LPUARTx This parameter can be one of the following values: 03234 * @arg @ref LL_RCC_LPUART1_CLKSOURCE 03235 * @retval Returned value can be one of the following values: 03236 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 03237 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK 03238 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI 03239 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE 03240 */ 03241 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) 03242 { 03243 return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx)); 03244 } 03245 03246 /** 03247 * @brief Get I2Cx clock source 03248 * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource 03249 * @param I2Cx This parameter can be one of the following values: 03250 * @arg @ref LL_RCC_I2C1_CLKSOURCE 03251 * @arg @ref LL_RCC_I2C2_CLKSOURCE (*) 03252 * @arg @ref LL_RCC_I2C3_CLKSOURCE 03253 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*) 03254 * 03255 * (*) value not defined in all devices. 03256 * @retval Returned value can be one of the following values: 03257 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 03258 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK 03259 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI 03260 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*) 03261 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) 03262 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) 03263 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 03264 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK 03265 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI 03266 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) 03267 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) 03268 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) 03269 * 03270 * (*) value not defined in all devices. 03271 */ 03272 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) 03273 { 03274 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U)); 03275 return (uint32_t)((READ_BIT(*reg, 3U << ((I2Cx & 0x00FF0000U) >> 16U)) >> ((I2Cx & 0x00FF0000U) >> 16U)) | (I2Cx & 0xFFFF0000U)); 03276 } 03277 03278 /** 03279 * @brief Get LPTIMx clock source 03280 * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource 03281 * @param LPTIMx This parameter can be one of the following values: 03282 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE 03283 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE 03284 * @retval Returned value can be one of the following values: 03285 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 03286 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI 03287 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI 03288 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE 03289 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 03290 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI 03291 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI 03292 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE 03293 */ 03294 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) 03295 { 03296 return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx) >> 16U | LPTIMx); 03297 } 03298 03299 /** 03300 * @brief Get SAIx clock source 03301 @if STM32L4S9xx 03302 * @rmtoll CCIPR2 SAIxSEL LL_RCC_GetSAIClockSource 03303 @else 03304 * @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource 03305 @endif 03306 * @param SAIx This parameter can be one of the following values: 03307 * @arg @ref LL_RCC_SAI1_CLKSOURCE 03308 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) 03309 * 03310 * (*) value not defined in all devices. 03311 * @retval Returned value can be one of the following values: 03312 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1 03313 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*) 03314 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL 03315 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN 03316 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*) 03317 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*) 03318 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) 03319 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) 03320 * 03321 * (*) value not defined in all devices. 03322 */ 03323 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) 03324 { 03325 #if defined(RCC_CCIPR2_SAI1SEL) 03326 return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U)); 03327 #else 03328 return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U | SAIx); 03329 #endif /* RCC_CCIPR2_SAI1SEL */ 03330 } 03331 03332 #if defined(RCC_CCIPR2_SDMMCSEL) 03333 /** 03334 * @brief Get SDMMCx kernel clock source 03335 * @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource 03336 * @param SDMMCx This parameter can be one of the following values: 03337 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE 03338 * @retval Returned value can be one of the following values: 03339 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*) 03340 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLL (*) 03341 * 03342 * (*) value not defined in all devices. 03343 */ 03344 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx) 03345 { 03346 return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx)); 03347 } 03348 #endif /* RCC_CCIPR2_SDMMCSEL */ 03349 03350 /** 03351 * @brief Get SDMMCx clock source 03352 * @rmtoll CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource 03353 * @param SDMMCx This parameter can be one of the following values: 03354 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE 03355 * @retval Returned value can be one of the following values: 03356 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*) 03357 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*) 03358 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*) 03359 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL 03360 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*) 03361 * 03362 * (*) value not defined in all devices. 03363 */ 03364 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx) 03365 { 03366 return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx)); 03367 } 03368 03369 /** 03370 * @brief Get RNGx clock source 03371 * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource 03372 * @param RNGx This parameter can be one of the following values: 03373 * @arg @ref LL_RCC_RNG_CLKSOURCE 03374 * @retval Returned value can be one of the following values: 03375 * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*) 03376 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*) 03377 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1 03378 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL 03379 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI 03380 * 03381 * (*) value not defined in all devices. 03382 */ 03383 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) 03384 { 03385 return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx)); 03386 } 03387 03388 #if defined(USB_OTG_FS) || defined(USB) 03389 /** 03390 * @brief Get USBx clock source 03391 * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource 03392 * @param USBx This parameter can be one of the following values: 03393 * @arg @ref LL_RCC_USB_CLKSOURCE 03394 * @retval Returned value can be one of the following values: 03395 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*) 03396 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*) 03397 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1 03398 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL 03399 * @arg @ref LL_RCC_USB_CLKSOURCE_MSI 03400 * 03401 * (*) value not defined in all devices. 03402 */ 03403 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) 03404 { 03405 return (uint32_t)(READ_BIT(RCC->CCIPR, USBx)); 03406 } 03407 #endif /* USB_OTG_FS || USB */ 03408 03409 /** 03410 * @brief Get ADCx clock source 03411 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource 03412 * @param ADCx This parameter can be one of the following values: 03413 * @arg @ref LL_RCC_ADC_CLKSOURCE 03414 * @retval Returned value can be one of the following values: 03415 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE 03416 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 03417 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*) 03418 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK 03419 * 03420 * (*) value not defined in all devices. 03421 */ 03422 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) 03423 { 03424 return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx)); 03425 } 03426 03427 #if defined(SWPMI1) 03428 /** 03429 * @brief Get SWPMIx clock source 03430 * @rmtoll CCIPR SWPMI1SEL LL_RCC_GetSWPMIClockSource 03431 * @param SPWMIx This parameter can be one of the following values: 03432 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE 03433 * @retval Returned value can be one of the following values: 03434 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1 03435 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI 03436 */ 03437 __STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx) 03438 { 03439 return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx)); 03440 } 03441 #endif /* SWPMI1 */ 03442 03443 #if defined(DFSDM1_Channel0) 03444 #if defined(RCC_CCIPR2_ADFSDM1SEL) 03445 /** 03446 * @brief Get DFSDM Audio Clock Source 03447 * @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource 03448 * @param DFSDMx This parameter can be one of the following values: 03449 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE 03450 * @retval Returned value can be one of the following values: 03451 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 03452 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI 03453 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI 03454 */ 03455 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx) 03456 { 03457 return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx)); 03458 } 03459 #endif /* RCC_CCIPR2_ADFSDM1SEL */ 03460 03461 /** 03462 * @brief Get DFSDMx Kernel clock source 03463 @if STM32L4S9xx 03464 * @rmtoll CCIPR2 DFSDM1SEL LL_RCC_GetDFSDMClockSource 03465 @else 03466 * @rmtoll CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource 03467 @endif 03468 * @param DFSDMx This parameter can be one of the following values: 03469 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE 03470 * @retval Returned value can be one of the following values: 03471 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 03472 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK 03473 */ 03474 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx) 03475 { 03476 #if defined(RCC_CCIPR2_DFSDM1SEL) 03477 return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx)); 03478 #else 03479 return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx)); 03480 #endif /* RCC_CCIPR2_DFSDM1SEL */ 03481 } 03482 #endif /* DFSDM1_Channel0 */ 03483 03484 #if defined(DSI) 03485 /** 03486 * @brief Get DSI Clock Source 03487 * @rmtoll CCIPR2 DSISEL LL_RCC_GetDSIClockSource 03488 * @param DSIx This parameter can be one of the following values: 03489 * @arg @ref LL_RCC_DSI_CLKSOURCE 03490 * @retval Returned value can be one of the following values: 03491 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY 03492 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL 03493 */ 03494 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) 03495 { 03496 return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx)); 03497 } 03498 #endif /* DSI */ 03499 03500 #if defined(LTDC) 03501 /** 03502 * @brief Get LTDC Clock Source 03503 * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_GetLTDCClockSource 03504 * @param LTDCx This parameter can be one of the following values: 03505 * @arg @ref LL_RCC_LTDC_CLKSOURCE 03506 * @retval Returned value can be one of the following values: 03507 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 03508 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 03509 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 03510 * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 03511 */ 03512 __STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx) 03513 { 03514 return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx)); 03515 } 03516 #endif /* LTDC */ 03517 03518 #if defined(OCTOSPI1) 03519 /** 03520 * @brief Get OCTOSPI clock source 03521 * @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource 03522 * @param OCTOSPIx This parameter can be one of the following values: 03523 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE 03524 * @retval Returned value can be one of the following values: 03525 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 03526 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI 03527 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL 03528 */ 03529 __STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx) 03530 { 03531 return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx)); 03532 } 03533 #endif /* OCTOSPI1 */ 03534 /** 03535 * @} 03536 */ 03537 03538 /** @defgroup RCC_LL_EF_RTC RTC 03539 * @{ 03540 */ 03541 03542 /** 03543 * @brief Set RTC Clock Source 03544 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless 03545 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is 03546 * set). The BDRST bit can be used to reset them. 03547 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource 03548 * @param Source This parameter can be one of the following values: 03549 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 03550 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 03551 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 03552 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 03553 * @retval None 03554 */ 03555 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) 03556 { 03557 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); 03558 } 03559 03560 /** 03561 * @brief Get RTC Clock Source 03562 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource 03563 * @retval Returned value can be one of the following values: 03564 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 03565 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 03566 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 03567 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 03568 */ 03569 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) 03570 { 03571 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); 03572 } 03573 03574 /** 03575 * @brief Enable RTC 03576 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC 03577 * @retval None 03578 */ 03579 __STATIC_INLINE void LL_RCC_EnableRTC(void) 03580 { 03581 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 03582 } 03583 03584 /** 03585 * @brief Disable RTC 03586 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC 03587 * @retval None 03588 */ 03589 __STATIC_INLINE void LL_RCC_DisableRTC(void) 03590 { 03591 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 03592 } 03593 03594 /** 03595 * @brief Check if RTC has been enabled or not 03596 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC 03597 * @retval State of bit (1 or 0). 03598 */ 03599 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) 03600 { 03601 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); 03602 } 03603 03604 /** 03605 * @brief Force the Backup domain reset 03606 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset 03607 * @retval None 03608 */ 03609 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) 03610 { 03611 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); 03612 } 03613 03614 /** 03615 * @brief Release the Backup domain reset 03616 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset 03617 * @retval None 03618 */ 03619 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) 03620 { 03621 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); 03622 } 03623 03624 /** 03625 * @} 03626 */ 03627 03628 03629 /** @defgroup RCC_LL_EF_PLL PLL 03630 * @{ 03631 */ 03632 03633 /** 03634 * @brief Enable PLL 03635 * @rmtoll CR PLLON LL_RCC_PLL_Enable 03636 * @retval None 03637 */ 03638 __STATIC_INLINE void LL_RCC_PLL_Enable(void) 03639 { 03640 SET_BIT(RCC->CR, RCC_CR_PLLON); 03641 } 03642 03643 /** 03644 * @brief Disable PLL 03645 * @note Cannot be disabled if the PLL clock is used as the system clock 03646 * @rmtoll CR PLLON LL_RCC_PLL_Disable 03647 * @retval None 03648 */ 03649 __STATIC_INLINE void LL_RCC_PLL_Disable(void) 03650 { 03651 CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 03652 } 03653 03654 /** 03655 * @brief Check if PLL Ready 03656 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady 03657 * @retval State of bit (1 or 0). 03658 */ 03659 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) 03660 { 03661 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); 03662 } 03663 03664 /** 03665 * @brief Configure PLL used for SYSCLK Domain 03666 * @note PLL Source and PLLM Divider can be written only when PLL, 03667 * PLLSAI1 and PLLSAI2 (*) are disabled. 03668 * @note PLLN/PLLR can be written only when PLL is disabled. 03669 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n 03670 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n 03671 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n 03672 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS 03673 * @param Source This parameter can be one of the following values: 03674 * @arg @ref LL_RCC_PLLSOURCE_NONE 03675 * @arg @ref LL_RCC_PLLSOURCE_MSI 03676 * @arg @ref LL_RCC_PLLSOURCE_HSI 03677 * @arg @ref LL_RCC_PLLSOURCE_HSE 03678 * @param PLLM This parameter can be one of the following values: 03679 * @arg @ref LL_RCC_PLLM_DIV_1 03680 * @arg @ref LL_RCC_PLLM_DIV_2 03681 * @arg @ref LL_RCC_PLLM_DIV_3 03682 * @arg @ref LL_RCC_PLLM_DIV_4 03683 * @arg @ref LL_RCC_PLLM_DIV_5 03684 * @arg @ref LL_RCC_PLLM_DIV_6 03685 * @arg @ref LL_RCC_PLLM_DIV_7 03686 * @arg @ref LL_RCC_PLLM_DIV_8 03687 * @arg @ref LL_RCC_PLLM_DIV_9 (*) 03688 * @arg @ref LL_RCC_PLLM_DIV_10 (*) 03689 * @arg @ref LL_RCC_PLLM_DIV_11 (*) 03690 * @arg @ref LL_RCC_PLLM_DIV_12 (*) 03691 * @arg @ref LL_RCC_PLLM_DIV_13 (*) 03692 * @arg @ref LL_RCC_PLLM_DIV_14 (*) 03693 * @arg @ref LL_RCC_PLLM_DIV_15 (*) 03694 * @arg @ref LL_RCC_PLLM_DIV_16 (*) 03695 * 03696 * (*) value not defined in all devices. 03697 * @param PLLN Between 8 and 86 03698 * @param PLLR This parameter can be one of the following values: 03699 * @arg @ref LL_RCC_PLLR_DIV_2 03700 * @arg @ref LL_RCC_PLLR_DIV_4 03701 * @arg @ref LL_RCC_PLLR_DIV_6 03702 * @arg @ref LL_RCC_PLLR_DIV_8 03703 * @retval None 03704 */ 03705 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 03706 { 03707 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, 03708 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); 03709 } 03710 03711 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 03712 /** 03713 * @brief Configure PLL used for SAI domain clock 03714 * @note PLL Source and PLLM Divider can be written only when PLL, 03715 * PLLSAI1 and PLLSAI2 (*) are disabled. 03716 * @note PLLN/PLLP can be written only when PLL is disabled. 03717 * @note This can be selected for SAI1 or SAI2 (*) 03718 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n 03719 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n 03720 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n 03721 * PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_SAI 03722 * @param Source This parameter can be one of the following values: 03723 * @arg @ref LL_RCC_PLLSOURCE_NONE 03724 * @arg @ref LL_RCC_PLLSOURCE_MSI 03725 * @arg @ref LL_RCC_PLLSOURCE_HSI 03726 * @arg @ref LL_RCC_PLLSOURCE_HSE 03727 * @param PLLM This parameter can be one of the following values: 03728 * @arg @ref LL_RCC_PLLM_DIV_1 03729 * @arg @ref LL_RCC_PLLM_DIV_2 03730 * @arg @ref LL_RCC_PLLM_DIV_3 03731 * @arg @ref LL_RCC_PLLM_DIV_4 03732 * @arg @ref LL_RCC_PLLM_DIV_5 03733 * @arg @ref LL_RCC_PLLM_DIV_6 03734 * @arg @ref LL_RCC_PLLM_DIV_7 03735 * @arg @ref LL_RCC_PLLM_DIV_8 03736 * @arg @ref LL_RCC_PLLM_DIV_9 (*) 03737 * @arg @ref LL_RCC_PLLM_DIV_10 (*) 03738 * @arg @ref LL_RCC_PLLM_DIV_11 (*) 03739 * @arg @ref LL_RCC_PLLM_DIV_12 (*) 03740 * @arg @ref LL_RCC_PLLM_DIV_13 (*) 03741 * @arg @ref LL_RCC_PLLM_DIV_14 (*) 03742 * @arg @ref LL_RCC_PLLM_DIV_15 (*) 03743 * @arg @ref LL_RCC_PLLM_DIV_16 (*) 03744 * 03745 * (*) value not defined in all devices. 03746 * @param PLLN Between 8 and 86 03747 * @param PLLP This parameter can be one of the following values: 03748 * @arg @ref LL_RCC_PLLP_DIV_2 03749 * @arg @ref LL_RCC_PLLP_DIV_3 03750 * @arg @ref LL_RCC_PLLP_DIV_4 03751 * @arg @ref LL_RCC_PLLP_DIV_5 03752 * @arg @ref LL_RCC_PLLP_DIV_6 03753 * @arg @ref LL_RCC_PLLP_DIV_7 03754 * @arg @ref LL_RCC_PLLP_DIV_8 03755 * @arg @ref LL_RCC_PLLP_DIV_9 03756 * @arg @ref LL_RCC_PLLP_DIV_10 03757 * @arg @ref LL_RCC_PLLP_DIV_11 03758 * @arg @ref LL_RCC_PLLP_DIV_12 03759 * @arg @ref LL_RCC_PLLP_DIV_13 03760 * @arg @ref LL_RCC_PLLP_DIV_14 03761 * @arg @ref LL_RCC_PLLP_DIV_15 03762 * @arg @ref LL_RCC_PLLP_DIV_16 03763 * @arg @ref LL_RCC_PLLP_DIV_17 03764 * @arg @ref LL_RCC_PLLP_DIV_18 03765 * @arg @ref LL_RCC_PLLP_DIV_19 03766 * @arg @ref LL_RCC_PLLP_DIV_20 03767 * @arg @ref LL_RCC_PLLP_DIV_21 03768 * @arg @ref LL_RCC_PLLP_DIV_22 03769 * @arg @ref LL_RCC_PLLP_DIV_23 03770 * @arg @ref LL_RCC_PLLP_DIV_24 03771 * @arg @ref LL_RCC_PLLP_DIV_25 03772 * @arg @ref LL_RCC_PLLP_DIV_26 03773 * @arg @ref LL_RCC_PLLP_DIV_27 03774 * @arg @ref LL_RCC_PLLP_DIV_28 03775 * @arg @ref LL_RCC_PLLP_DIV_29 03776 * @arg @ref LL_RCC_PLLP_DIV_30 03777 * @arg @ref LL_RCC_PLLP_DIV_31 03778 * @retval None 03779 */ 03780 #else 03781 /** 03782 * @brief Configure PLL used for SAI domain clock 03783 * @note PLL Source and PLLM Divider can be written only when PLL, 03784 * PLLSAI1 and PLLSAI2 (*) are disabled. 03785 * @note PLLN/PLLP can be written only when PLL is disabled. 03786 * @note This can be selected for SAI1 or SAI2 (*) 03787 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n 03788 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n 03789 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n 03790 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI 03791 * @param Source This parameter can be one of the following values: 03792 * @arg @ref LL_RCC_PLLSOURCE_NONE 03793 * @arg @ref LL_RCC_PLLSOURCE_MSI 03794 * @arg @ref LL_RCC_PLLSOURCE_HSI 03795 * @arg @ref LL_RCC_PLLSOURCE_HSE 03796 * @param PLLM This parameter can be one of the following values: 03797 * @arg @ref LL_RCC_PLLM_DIV_1 03798 * @arg @ref LL_RCC_PLLM_DIV_2 03799 * @arg @ref LL_RCC_PLLM_DIV_3 03800 * @arg @ref LL_RCC_PLLM_DIV_4 03801 * @arg @ref LL_RCC_PLLM_DIV_5 03802 * @arg @ref LL_RCC_PLLM_DIV_6 03803 * @arg @ref LL_RCC_PLLM_DIV_7 03804 * @arg @ref LL_RCC_PLLM_DIV_8 03805 * @param PLLN Between 8 and 86 03806 * @param PLLP This parameter can be one of the following values: 03807 * @arg @ref LL_RCC_PLLP_DIV_7 03808 * @arg @ref LL_RCC_PLLP_DIV_17 03809 * @retval None 03810 */ 03811 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 03812 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 03813 { 03814 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 03815 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV, 03816 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); 03817 #else 03818 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, 03819 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); 03820 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 03821 } 03822 03823 /** 03824 * @brief Configure PLL used for 48Mhz domain clock 03825 * @note PLL Source and PLLM Divider can be written only when PLL, 03826 * PLLSAI1 and PLLSAI2 (*) are disabled. 03827 * @note PLLN/PLLQ can be written only when PLL is disabled. 03828 * @note This can be selected for USB, RNG, SDMMC 03829 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n 03830 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n 03831 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n 03832 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M 03833 * @param Source This parameter can be one of the following values: 03834 * @arg @ref LL_RCC_PLLSOURCE_NONE 03835 * @arg @ref LL_RCC_PLLSOURCE_MSI 03836 * @arg @ref LL_RCC_PLLSOURCE_HSI 03837 * @arg @ref LL_RCC_PLLSOURCE_HSE 03838 * @param PLLM This parameter can be one of the following values: 03839 * @arg @ref LL_RCC_PLLM_DIV_1 03840 * @arg @ref LL_RCC_PLLM_DIV_2 03841 * @arg @ref LL_RCC_PLLM_DIV_3 03842 * @arg @ref LL_RCC_PLLM_DIV_4 03843 * @arg @ref LL_RCC_PLLM_DIV_5 03844 * @arg @ref LL_RCC_PLLM_DIV_6 03845 * @arg @ref LL_RCC_PLLM_DIV_7 03846 * @arg @ref LL_RCC_PLLM_DIV_8 03847 * @arg @ref LL_RCC_PLLM_DIV_9 (*) 03848 * @arg @ref LL_RCC_PLLM_DIV_10 (*) 03849 * @arg @ref LL_RCC_PLLM_DIV_11 (*) 03850 * @arg @ref LL_RCC_PLLM_DIV_12 (*) 03851 * @arg @ref LL_RCC_PLLM_DIV_13 (*) 03852 * @arg @ref LL_RCC_PLLM_DIV_14 (*) 03853 * @arg @ref LL_RCC_PLLM_DIV_15 (*) 03854 * @arg @ref LL_RCC_PLLM_DIV_16 (*) 03855 * 03856 * (*) value not defined in all devices. 03857 * @param PLLN Between 8 and 86 03858 * @param PLLQ This parameter can be one of the following values: 03859 * @arg @ref LL_RCC_PLLQ_DIV_2 03860 * @arg @ref LL_RCC_PLLQ_DIV_4 03861 * @arg @ref LL_RCC_PLLQ_DIV_6 03862 * @arg @ref LL_RCC_PLLQ_DIV_8 03863 * @retval None 03864 */ 03865 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) 03866 { 03867 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, 03868 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); 03869 } 03870 03871 /** 03872 * @brief Configure PLL clock source 03873 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource 03874 * @param PLLSource This parameter can be one of the following values: 03875 * @arg @ref LL_RCC_PLLSOURCE_NONE 03876 * @arg @ref LL_RCC_PLLSOURCE_MSI 03877 * @arg @ref LL_RCC_PLLSOURCE_HSI 03878 * @arg @ref LL_RCC_PLLSOURCE_HSE 03879 * @retval None 03880 */ 03881 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) 03882 { 03883 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); 03884 } 03885 03886 /** 03887 * @brief Get the oscillator used as PLL clock source. 03888 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource 03889 * @retval Returned value can be one of the following values: 03890 * @arg @ref LL_RCC_PLLSOURCE_NONE 03891 * @arg @ref LL_RCC_PLLSOURCE_MSI 03892 * @arg @ref LL_RCC_PLLSOURCE_HSI 03893 * @arg @ref LL_RCC_PLLSOURCE_HSE 03894 */ 03895 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) 03896 { 03897 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); 03898 } 03899 03900 /** 03901 * @brief Get Main PLL multiplication factor for VCO 03902 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN 03903 * @retval Between 8 and 86 03904 */ 03905 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) 03906 { 03907 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 03908 } 03909 03910 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 03911 /** 03912 * @brief Get Main PLL division factor for PLLP 03913 * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock) 03914 * @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP 03915 * @retval Returned value can be one of the following values: 03916 * @arg @ref LL_RCC_PLLP_DIV_2 03917 * @arg @ref LL_RCC_PLLP_DIV_3 03918 * @arg @ref LL_RCC_PLLP_DIV_4 03919 * @arg @ref LL_RCC_PLLP_DIV_5 03920 * @arg @ref LL_RCC_PLLP_DIV_6 03921 * @arg @ref LL_RCC_PLLP_DIV_7 03922 * @arg @ref LL_RCC_PLLP_DIV_8 03923 * @arg @ref LL_RCC_PLLP_DIV_9 03924 * @arg @ref LL_RCC_PLLP_DIV_10 03925 * @arg @ref LL_RCC_PLLP_DIV_11 03926 * @arg @ref LL_RCC_PLLP_DIV_12 03927 * @arg @ref LL_RCC_PLLP_DIV_13 03928 * @arg @ref LL_RCC_PLLP_DIV_14 03929 * @arg @ref LL_RCC_PLLP_DIV_15 03930 * @arg @ref LL_RCC_PLLP_DIV_16 03931 * @arg @ref LL_RCC_PLLP_DIV_17 03932 * @arg @ref LL_RCC_PLLP_DIV_18 03933 * @arg @ref LL_RCC_PLLP_DIV_19 03934 * @arg @ref LL_RCC_PLLP_DIV_20 03935 * @arg @ref LL_RCC_PLLP_DIV_21 03936 * @arg @ref LL_RCC_PLLP_DIV_22 03937 * @arg @ref LL_RCC_PLLP_DIV_23 03938 * @arg @ref LL_RCC_PLLP_DIV_24 03939 * @arg @ref LL_RCC_PLLP_DIV_25 03940 * @arg @ref LL_RCC_PLLP_DIV_26 03941 * @arg @ref LL_RCC_PLLP_DIV_27 03942 * @arg @ref LL_RCC_PLLP_DIV_28 03943 * @arg @ref LL_RCC_PLLP_DIV_29 03944 * @arg @ref LL_RCC_PLLP_DIV_30 03945 * @arg @ref LL_RCC_PLLP_DIV_31 03946 */ 03947 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) 03948 { 03949 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV)); 03950 } 03951 #else 03952 /** 03953 * @brief Get Main PLL division factor for PLLP 03954 * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock) 03955 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP 03956 * @retval Returned value can be one of the following values: 03957 * @arg @ref LL_RCC_PLLP_DIV_7 03958 * @arg @ref LL_RCC_PLLP_DIV_17 03959 */ 03960 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) 03961 { 03962 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); 03963 } 03964 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 03965 03966 /** 03967 * @brief Get Main PLL division factor for PLLQ 03968 * @note Used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock) 03969 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ 03970 * @retval Returned value can be one of the following values: 03971 * @arg @ref LL_RCC_PLLQ_DIV_2 03972 * @arg @ref LL_RCC_PLLQ_DIV_4 03973 * @arg @ref LL_RCC_PLLQ_DIV_6 03974 * @arg @ref LL_RCC_PLLQ_DIV_8 03975 */ 03976 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) 03977 { 03978 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); 03979 } 03980 03981 /** 03982 * @brief Get Main PLL division factor for PLLR 03983 * @note Used for PLLCLK (system clock) 03984 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR 03985 * @retval Returned value can be one of the following values: 03986 * @arg @ref LL_RCC_PLLR_DIV_2 03987 * @arg @ref LL_RCC_PLLR_DIV_4 03988 * @arg @ref LL_RCC_PLLR_DIV_6 03989 * @arg @ref LL_RCC_PLLR_DIV_8 03990 */ 03991 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) 03992 { 03993 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); 03994 } 03995 03996 /** 03997 * @brief Get Division factor for the main PLL and other PLL 03998 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider 03999 * @retval Returned value can be one of the following values: 04000 * @arg @ref LL_RCC_PLLM_DIV_1 04001 * @arg @ref LL_RCC_PLLM_DIV_2 04002 * @arg @ref LL_RCC_PLLM_DIV_3 04003 * @arg @ref LL_RCC_PLLM_DIV_4 04004 * @arg @ref LL_RCC_PLLM_DIV_5 04005 * @arg @ref LL_RCC_PLLM_DIV_6 04006 * @arg @ref LL_RCC_PLLM_DIV_7 04007 * @arg @ref LL_RCC_PLLM_DIV_8 04008 * @arg @ref LL_RCC_PLLM_DIV_9 (*) 04009 * @arg @ref LL_RCC_PLLM_DIV_10 (*) 04010 * @arg @ref LL_RCC_PLLM_DIV_11 (*) 04011 * @arg @ref LL_RCC_PLLM_DIV_12 (*) 04012 * @arg @ref LL_RCC_PLLM_DIV_13 (*) 04013 * @arg @ref LL_RCC_PLLM_DIV_14 (*) 04014 * @arg @ref LL_RCC_PLLM_DIV_15 (*) 04015 * @arg @ref LL_RCC_PLLM_DIV_16 (*) 04016 * 04017 * (*) value not defined in all devices. 04018 */ 04019 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) 04020 { 04021 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); 04022 } 04023 04024 /** 04025 * @brief Enable PLL output mapped on SAI domain clock 04026 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI 04027 * @retval None 04028 */ 04029 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void) 04030 { 04031 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); 04032 } 04033 04034 /** 04035 * @brief Disable PLL output mapped on SAI domain clock 04036 * @note Cannot be disabled if the PLL clock is used as the system 04037 * clock 04038 * @note In order to save power, when the PLLCLK of the PLL is 04039 * not used, should be 0 04040 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI 04041 * @retval None 04042 */ 04043 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void) 04044 { 04045 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); 04046 } 04047 04048 /** 04049 * @brief Enable PLL output mapped on 48MHz domain clock 04050 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M 04051 * @retval None 04052 */ 04053 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void) 04054 { 04055 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); 04056 } 04057 04058 /** 04059 * @brief Disable PLL output mapped on 48MHz domain clock 04060 * @note Cannot be disabled if the PLL clock is used as the system 04061 * clock 04062 * @note In order to save power, when the PLLCLK of the PLL is 04063 * not used, should be 0 04064 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M 04065 * @retval None 04066 */ 04067 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void) 04068 { 04069 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); 04070 } 04071 04072 /** 04073 * @brief Enable PLL output mapped on SYSCLK domain 04074 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS 04075 * @retval None 04076 */ 04077 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void) 04078 { 04079 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); 04080 } 04081 04082 /** 04083 * @brief Disable PLL output mapped on SYSCLK domain 04084 * @note Cannot be disabled if the PLL clock is used as the system 04085 * clock 04086 * @note In order to save power, when the PLLCLK of the PLL is 04087 * not used, Main PLL should be 0 04088 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS 04089 * @retval None 04090 */ 04091 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void) 04092 { 04093 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); 04094 } 04095 04096 /** 04097 * @} 04098 */ 04099 04100 /** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1 04101 * @{ 04102 */ 04103 04104 /** 04105 * @brief Enable PLLSAI1 04106 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable 04107 * @retval None 04108 */ 04109 __STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void) 04110 { 04111 SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON); 04112 } 04113 04114 /** 04115 * @brief Disable PLLSAI1 04116 * @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable 04117 * @retval None 04118 */ 04119 __STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void) 04120 { 04121 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON); 04122 } 04123 04124 /** 04125 * @brief Check if PLLSAI1 Ready 04126 * @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady 04127 * @retval State of bit (1 or 0). 04128 */ 04129 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void) 04130 { 04131 return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)); 04132 } 04133 04134 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 04135 /** 04136 * @brief Configure PLLSAI1 used for 48Mhz domain clock 04137 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. 04138 * @note PLLSAI1M/PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled. 04139 * @note This can be selected for USB, RNG, SDMMC 04140 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n 04141 * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_48M\n 04142 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n 04143 * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M 04144 * @param Source This parameter can be one of the following values: 04145 * @arg @ref LL_RCC_PLLSOURCE_NONE 04146 * @arg @ref LL_RCC_PLLSOURCE_MSI 04147 * @arg @ref LL_RCC_PLLSOURCE_HSI 04148 * @arg @ref LL_RCC_PLLSOURCE_HSE 04149 * @param PLLM This parameter can be one of the following values: 04150 * @arg @ref LL_RCC_PLLSAI1M_DIV_1 04151 * @arg @ref LL_RCC_PLLSAI1M_DIV_2 04152 * @arg @ref LL_RCC_PLLSAI1M_DIV_3 04153 * @arg @ref LL_RCC_PLLSAI1M_DIV_4 04154 * @arg @ref LL_RCC_PLLSAI1M_DIV_5 04155 * @arg @ref LL_RCC_PLLSAI1M_DIV_6 04156 * @arg @ref LL_RCC_PLLSAI1M_DIV_7 04157 * @arg @ref LL_RCC_PLLSAI1M_DIV_8 04158 * @arg @ref LL_RCC_PLLSAI1M_DIV_9 04159 * @arg @ref LL_RCC_PLLSAI1M_DIV_10 04160 * @arg @ref LL_RCC_PLLSAI1M_DIV_11 04161 * @arg @ref LL_RCC_PLLSAI1M_DIV_12 04162 * @arg @ref LL_RCC_PLLSAI1M_DIV_13 04163 * @arg @ref LL_RCC_PLLSAI1M_DIV_14 04164 * @arg @ref LL_RCC_PLLSAI1M_DIV_15 04165 * @arg @ref LL_RCC_PLLSAI1M_DIV_16 04166 * @param PLLN Between 8 and 86 04167 * @param PLLQ This parameter can be one of the following values: 04168 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 04169 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 04170 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 04171 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 04172 * @retval None 04173 */ 04174 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) 04175 { 04176 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 04177 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, 04178 PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ); 04179 } 04180 #else 04181 /** 04182 * @brief Configure PLLSAI1 used for 48Mhz domain clock 04183 * @note PLL Source and PLLM Divider can be written only when PLL, 04184 * PLLSAI1 and PLLSAI2 (*) are disabled. 04185 * @note PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled. 04186 * @note This can be selected for USB, RNG, SDMMC 04187 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n 04188 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n 04189 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n 04190 * PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M 04191 * @param Source This parameter can be one of the following values: 04192 * @arg @ref LL_RCC_PLLSOURCE_NONE 04193 * @arg @ref LL_RCC_PLLSOURCE_MSI 04194 * @arg @ref LL_RCC_PLLSOURCE_HSI 04195 * @arg @ref LL_RCC_PLLSOURCE_HSE 04196 * @param PLLM This parameter can be one of the following values: 04197 * @arg @ref LL_RCC_PLLM_DIV_1 04198 * @arg @ref LL_RCC_PLLM_DIV_2 04199 * @arg @ref LL_RCC_PLLM_DIV_3 04200 * @arg @ref LL_RCC_PLLM_DIV_4 04201 * @arg @ref LL_RCC_PLLM_DIV_5 04202 * @arg @ref LL_RCC_PLLM_DIV_6 04203 * @arg @ref LL_RCC_PLLM_DIV_7 04204 * @arg @ref LL_RCC_PLLM_DIV_8 04205 * @param PLLN Between 8 and 86 04206 * @param PLLQ This parameter can be one of the following values: 04207 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 04208 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 04209 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 04210 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 04211 * @retval None 04212 */ 04213 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) 04214 { 04215 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 04216 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ); 04217 } 04218 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 04219 04220 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 04221 /** 04222 * @brief Configure PLLSAI1 used for SAI domain clock 04223 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. 04224 * @note PLLSAI1M/PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled. 04225 * @note This can be selected for SAI1 or SAI2 04226 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04227 * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04228 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04229 * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI 04230 * @param Source This parameter can be one of the following values: 04231 * @arg @ref LL_RCC_PLLSOURCE_NONE 04232 * @arg @ref LL_RCC_PLLSOURCE_MSI 04233 * @arg @ref LL_RCC_PLLSOURCE_HSI 04234 * @arg @ref LL_RCC_PLLSOURCE_HSE 04235 * @param PLLM This parameter can be one of the following values: 04236 * @arg @ref LL_RCC_PLLSAI1M_DIV_1 04237 * @arg @ref LL_RCC_PLLSAI1M_DIV_2 04238 * @arg @ref LL_RCC_PLLSAI1M_DIV_3 04239 * @arg @ref LL_RCC_PLLSAI1M_DIV_4 04240 * @arg @ref LL_RCC_PLLSAI1M_DIV_5 04241 * @arg @ref LL_RCC_PLLSAI1M_DIV_6 04242 * @arg @ref LL_RCC_PLLSAI1M_DIV_7 04243 * @arg @ref LL_RCC_PLLSAI1M_DIV_8 04244 * @arg @ref LL_RCC_PLLSAI1M_DIV_9 04245 * @arg @ref LL_RCC_PLLSAI1M_DIV_10 04246 * @arg @ref LL_RCC_PLLSAI1M_DIV_11 04247 * @arg @ref LL_RCC_PLLSAI1M_DIV_12 04248 * @arg @ref LL_RCC_PLLSAI1M_DIV_13 04249 * @arg @ref LL_RCC_PLLSAI1M_DIV_14 04250 * @arg @ref LL_RCC_PLLSAI1M_DIV_15 04251 * @arg @ref LL_RCC_PLLSAI1M_DIV_16 04252 * @param PLLN Between 8 and 86 04253 * @param PLLP This parameter can be one of the following values: 04254 * @arg @ref LL_RCC_PLLSAI1P_DIV_2 04255 * @arg @ref LL_RCC_PLLSAI1P_DIV_3 04256 * @arg @ref LL_RCC_PLLSAI1P_DIV_4 04257 * @arg @ref LL_RCC_PLLSAI1P_DIV_5 04258 * @arg @ref LL_RCC_PLLSAI1P_DIV_6 04259 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 04260 * @arg @ref LL_RCC_PLLSAI1P_DIV_8 04261 * @arg @ref LL_RCC_PLLSAI1P_DIV_9 04262 * @arg @ref LL_RCC_PLLSAI1P_DIV_10 04263 * @arg @ref LL_RCC_PLLSAI1P_DIV_11 04264 * @arg @ref LL_RCC_PLLSAI1P_DIV_12 04265 * @arg @ref LL_RCC_PLLSAI1P_DIV_13 04266 * @arg @ref LL_RCC_PLLSAI1P_DIV_14 04267 * @arg @ref LL_RCC_PLLSAI1P_DIV_15 04268 * @arg @ref LL_RCC_PLLSAI1P_DIV_16 04269 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 04270 * @arg @ref LL_RCC_PLLSAI1P_DIV_18 04271 * @arg @ref LL_RCC_PLLSAI1P_DIV_19 04272 * @arg @ref LL_RCC_PLLSAI1P_DIV_20 04273 * @arg @ref LL_RCC_PLLSAI1P_DIV_21 04274 * @arg @ref LL_RCC_PLLSAI1P_DIV_22 04275 * @arg @ref LL_RCC_PLLSAI1P_DIV_23 04276 * @arg @ref LL_RCC_PLLSAI1P_DIV_24 04277 * @arg @ref LL_RCC_PLLSAI1P_DIV_25 04278 * @arg @ref LL_RCC_PLLSAI1P_DIV_26 04279 * @arg @ref LL_RCC_PLLSAI1P_DIV_27 04280 * @arg @ref LL_RCC_PLLSAI1P_DIV_28 04281 * @arg @ref LL_RCC_PLLSAI1P_DIV_29 04282 * @arg @ref LL_RCC_PLLSAI1P_DIV_30 04283 * @arg @ref LL_RCC_PLLSAI1P_DIV_31 04284 * @retval None 04285 */ 04286 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 04287 { 04288 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 04289 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, 04290 PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP); 04291 } 04292 #elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 04293 /** 04294 * @brief Configure PLLSAI1 used for SAI domain clock 04295 * @note PLL Source and PLLM Divider can be written only when PLL, 04296 * PLLSAI1 and PLLSAI2 (*) are disabled. 04297 * @note PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled. 04298 * @note This can be selected for SAI1 or SAI2 (*) 04299 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04300 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04301 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04302 * PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI 04303 * @param Source This parameter can be one of the following values: 04304 * @arg @ref LL_RCC_PLLSOURCE_NONE 04305 * @arg @ref LL_RCC_PLLSOURCE_MSI 04306 * @arg @ref LL_RCC_PLLSOURCE_HSI 04307 * @arg @ref LL_RCC_PLLSOURCE_HSE 04308 * @param PLLM This parameter can be one of the following values: 04309 * @arg @ref LL_RCC_PLLM_DIV_1 04310 * @arg @ref LL_RCC_PLLM_DIV_2 04311 * @arg @ref LL_RCC_PLLM_DIV_3 04312 * @arg @ref LL_RCC_PLLM_DIV_4 04313 * @arg @ref LL_RCC_PLLM_DIV_5 04314 * @arg @ref LL_RCC_PLLM_DIV_6 04315 * @arg @ref LL_RCC_PLLM_DIV_7 04316 * @arg @ref LL_RCC_PLLM_DIV_8 04317 * @param PLLN Between 8 and 86 04318 * @param PLLP This parameter can be one of the following values: 04319 * @arg @ref LL_RCC_PLLSAI1P_DIV_2 04320 * @arg @ref LL_RCC_PLLSAI1P_DIV_3 04321 * @arg @ref LL_RCC_PLLSAI1P_DIV_4 04322 * @arg @ref LL_RCC_PLLSAI1P_DIV_5 04323 * @arg @ref LL_RCC_PLLSAI1P_DIV_6 04324 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 04325 * @arg @ref LL_RCC_PLLSAI1P_DIV_8 04326 * @arg @ref LL_RCC_PLLSAI1P_DIV_9 04327 * @arg @ref LL_RCC_PLLSAI1P_DIV_10 04328 * @arg @ref LL_RCC_PLLSAI1P_DIV_11 04329 * @arg @ref LL_RCC_PLLSAI1P_DIV_12 04330 * @arg @ref LL_RCC_PLLSAI1P_DIV_13 04331 * @arg @ref LL_RCC_PLLSAI1P_DIV_14 04332 * @arg @ref LL_RCC_PLLSAI1P_DIV_15 04333 * @arg @ref LL_RCC_PLLSAI1P_DIV_16 04334 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 04335 * @arg @ref LL_RCC_PLLSAI1P_DIV_18 04336 * @arg @ref LL_RCC_PLLSAI1P_DIV_19 04337 * @arg @ref LL_RCC_PLLSAI1P_DIV_20 04338 * @arg @ref LL_RCC_PLLSAI1P_DIV_21 04339 * @arg @ref LL_RCC_PLLSAI1P_DIV_22 04340 * @arg @ref LL_RCC_PLLSAI1P_DIV_23 04341 * @arg @ref LL_RCC_PLLSAI1P_DIV_24 04342 * @arg @ref LL_RCC_PLLSAI1P_DIV_25 04343 * @arg @ref LL_RCC_PLLSAI1P_DIV_26 04344 * @arg @ref LL_RCC_PLLSAI1P_DIV_27 04345 * @arg @ref LL_RCC_PLLSAI1P_DIV_28 04346 * @arg @ref LL_RCC_PLLSAI1P_DIV_29 04347 * @arg @ref LL_RCC_PLLSAI1P_DIV_30 04348 * @arg @ref LL_RCC_PLLSAI1P_DIV_31 04349 * @retval None 04350 */ 04351 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 04352 { 04353 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 04354 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, 04355 PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP); 04356 } 04357 #else 04358 /** 04359 * @brief Configure PLLSAI1 used for SAI domain clock 04360 * @note PLL Source and PLLM Divider can be written only when PLL, 04361 * PLLSAI1 and PLLSAI2 (*) are disabled. 04362 * @note PLLSAI1N/PLLSAI1P can be written only when PLLSAI1 is disabled. 04363 * @note This can be selected for SAI1 or SAI2 (*) 04364 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04365 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04366 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n 04367 * PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_ConfigDomain_SAI 04368 * @param Source This parameter can be one of the following values: 04369 * @arg @ref LL_RCC_PLLSOURCE_NONE 04370 * @arg @ref LL_RCC_PLLSOURCE_MSI 04371 * @arg @ref LL_RCC_PLLSOURCE_HSI 04372 * @arg @ref LL_RCC_PLLSOURCE_HSE 04373 * @param PLLM This parameter can be one of the following values: 04374 * @arg @ref LL_RCC_PLLM_DIV_1 04375 * @arg @ref LL_RCC_PLLM_DIV_2 04376 * @arg @ref LL_RCC_PLLM_DIV_3 04377 * @arg @ref LL_RCC_PLLM_DIV_4 04378 * @arg @ref LL_RCC_PLLM_DIV_5 04379 * @arg @ref LL_RCC_PLLM_DIV_6 04380 * @arg @ref LL_RCC_PLLM_DIV_7 04381 * @arg @ref LL_RCC_PLLM_DIV_8 04382 * @param PLLN Between 8 and 86 04383 * @param PLLP This parameter can be one of the following values: 04384 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 04385 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 04386 * @retval None 04387 */ 04388 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 04389 { 04390 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 04391 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP); 04392 } 04393 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT && RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 04394 04395 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 04396 /** 04397 * @brief Configure PLLSAI1 used for ADC domain clock 04398 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. 04399 * @note PLLSAI1M/PLLSAI1N/PLLSAI1R can be written only when PLLSAI1 is disabled. 04400 * @note This can be selected for ADC 04401 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n 04402 * PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_ADC\n 04403 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n 04404 * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC 04405 * @param Source This parameter can be one of the following values: 04406 * @arg @ref LL_RCC_PLLSOURCE_NONE 04407 * @arg @ref LL_RCC_PLLSOURCE_MSI 04408 * @arg @ref LL_RCC_PLLSOURCE_HSI 04409 * @arg @ref LL_RCC_PLLSOURCE_HSE 04410 * @param PLLM This parameter can be one of the following values: 04411 * @arg @ref LL_RCC_PLLSAI1M_DIV_1 04412 * @arg @ref LL_RCC_PLLSAI1M_DIV_2 04413 * @arg @ref LL_RCC_PLLSAI1M_DIV_3 04414 * @arg @ref LL_RCC_PLLSAI1M_DIV_4 04415 * @arg @ref LL_RCC_PLLSAI1M_DIV_5 04416 * @arg @ref LL_RCC_PLLSAI1M_DIV_6 04417 * @arg @ref LL_RCC_PLLSAI1M_DIV_7 04418 * @arg @ref LL_RCC_PLLSAI1M_DIV_8 04419 * @arg @ref LL_RCC_PLLSAI1M_DIV_9 04420 * @arg @ref LL_RCC_PLLSAI1M_DIV_10 04421 * @arg @ref LL_RCC_PLLSAI1M_DIV_11 04422 * @arg @ref LL_RCC_PLLSAI1M_DIV_12 04423 * @arg @ref LL_RCC_PLLSAI1M_DIV_13 04424 * @arg @ref LL_RCC_PLLSAI1M_DIV_14 04425 * @arg @ref LL_RCC_PLLSAI1M_DIV_15 04426 * @arg @ref LL_RCC_PLLSAI1M_DIV_16 04427 * @param PLLN Between 8 and 86 04428 * @param PLLR This parameter can be one of the following values: 04429 * @arg @ref LL_RCC_PLLSAI1R_DIV_2 04430 * @arg @ref LL_RCC_PLLSAI1R_DIV_4 04431 * @arg @ref LL_RCC_PLLSAI1R_DIV_6 04432 * @arg @ref LL_RCC_PLLSAI1R_DIV_8 04433 * @retval None 04434 */ 04435 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 04436 { 04437 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 04438 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, 04439 PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR); 04440 } 04441 #else 04442 /** 04443 * @brief Configure PLLSAI1 used for ADC domain clock 04444 * @note PLL Source and PLLM Divider can be written only when PLL, 04445 * PLLSAI1 and PLLSAI2 (*) are disabled. 04446 * @note PLLN/PLLR can be written only when PLLSAI1 is disabled. 04447 * @note This can be selected for ADC 04448 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n 04449 * PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n 04450 * PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n 04451 * PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC 04452 * @param Source This parameter can be one of the following values: 04453 * @arg @ref LL_RCC_PLLSOURCE_NONE 04454 * @arg @ref LL_RCC_PLLSOURCE_MSI 04455 * @arg @ref LL_RCC_PLLSOURCE_HSI 04456 * @arg @ref LL_RCC_PLLSOURCE_HSE 04457 * @param PLLM This parameter can be one of the following values: 04458 * @arg @ref LL_RCC_PLLM_DIV_1 04459 * @arg @ref LL_RCC_PLLM_DIV_2 04460 * @arg @ref LL_RCC_PLLM_DIV_3 04461 * @arg @ref LL_RCC_PLLM_DIV_4 04462 * @arg @ref LL_RCC_PLLM_DIV_5 04463 * @arg @ref LL_RCC_PLLM_DIV_6 04464 * @arg @ref LL_RCC_PLLM_DIV_7 04465 * @arg @ref LL_RCC_PLLM_DIV_8 04466 * @param PLLN Between 8 and 86 04467 * @param PLLR This parameter can be one of the following values: 04468 * @arg @ref LL_RCC_PLLSAI1R_DIV_2 04469 * @arg @ref LL_RCC_PLLSAI1R_DIV_4 04470 * @arg @ref LL_RCC_PLLSAI1R_DIV_6 04471 * @arg @ref LL_RCC_PLLSAI1R_DIV_8 04472 * @retval None 04473 */ 04474 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 04475 { 04476 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 04477 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR); 04478 } 04479 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 04480 04481 /** 04482 * @brief Get SAI1PLL multiplication factor for VCO 04483 * @rmtoll PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN 04484 * @retval Between 8 and 86 04485 */ 04486 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void) 04487 { 04488 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos); 04489 } 04490 04491 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) 04492 /** 04493 * @brief Get SAI1PLL division factor for PLLSAI1P 04494 * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). 04495 * @rmtoll PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP 04496 * @retval Returned value can be one of the following values: 04497 * @arg @ref LL_RCC_PLLSAI1P_DIV_2 04498 * @arg @ref LL_RCC_PLLSAI1P_DIV_3 04499 * @arg @ref LL_RCC_PLLSAI1P_DIV_4 04500 * @arg @ref LL_RCC_PLLSAI1P_DIV_5 04501 * @arg @ref LL_RCC_PLLSAI1P_DIV_6 04502 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 04503 * @arg @ref LL_RCC_PLLSAI1P_DIV_8 04504 * @arg @ref LL_RCC_PLLSAI1P_DIV_9 04505 * @arg @ref LL_RCC_PLLSAI1P_DIV_10 04506 * @arg @ref LL_RCC_PLLSAI1P_DIV_11 04507 * @arg @ref LL_RCC_PLLSAI1P_DIV_12 04508 * @arg @ref LL_RCC_PLLSAI1P_DIV_13 04509 * @arg @ref LL_RCC_PLLSAI1P_DIV_14 04510 * @arg @ref LL_RCC_PLLSAI1P_DIV_15 04511 * @arg @ref LL_RCC_PLLSAI1P_DIV_16 04512 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 04513 * @arg @ref LL_RCC_PLLSAI1P_DIV_18 04514 * @arg @ref LL_RCC_PLLSAI1P_DIV_19 04515 * @arg @ref LL_RCC_PLLSAI1P_DIV_20 04516 * @arg @ref LL_RCC_PLLSAI1P_DIV_21 04517 * @arg @ref LL_RCC_PLLSAI1P_DIV_22 04518 * @arg @ref LL_RCC_PLLSAI1P_DIV_23 04519 * @arg @ref LL_RCC_PLLSAI1P_DIV_24 04520 * @arg @ref LL_RCC_PLLSAI1P_DIV_25 04521 * @arg @ref LL_RCC_PLLSAI1P_DIV_26 04522 * @arg @ref LL_RCC_PLLSAI1P_DIV_27 04523 * @arg @ref LL_RCC_PLLSAI1P_DIV_28 04524 * @arg @ref LL_RCC_PLLSAI1P_DIV_29 04525 * @arg @ref LL_RCC_PLLSAI1P_DIV_30 04526 * @arg @ref LL_RCC_PLLSAI1P_DIV_31 04527 */ 04528 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void) 04529 { 04530 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV)); 04531 } 04532 #else 04533 /** 04534 * @brief Get SAI1PLL division factor for PLLSAI1P 04535 * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock). 04536 * @rmtoll PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP 04537 * @retval Returned value can be one of the following values: 04538 * @arg @ref LL_RCC_PLLSAI1P_DIV_7 04539 * @arg @ref LL_RCC_PLLSAI1P_DIV_17 04540 */ 04541 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void) 04542 { 04543 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P)); 04544 } 04545 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ 04546 04547 /** 04548 * @brief Get SAI1PLL division factor for PLLSAI1Q 04549 * @note Used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock) 04550 * @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ 04551 * @retval Returned value can be one of the following values: 04552 * @arg @ref LL_RCC_PLLSAI1Q_DIV_2 04553 * @arg @ref LL_RCC_PLLSAI1Q_DIV_4 04554 * @arg @ref LL_RCC_PLLSAI1Q_DIV_6 04555 * @arg @ref LL_RCC_PLLSAI1Q_DIV_8 04556 */ 04557 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void) 04558 { 04559 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q)); 04560 } 04561 04562 /** 04563 * @brief Get PLLSAI1 division factor for PLLSAIR 04564 * @note Used for PLLADC1CLK (ADC clock) 04565 * @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR 04566 * @retval Returned value can be one of the following values: 04567 * @arg @ref LL_RCC_PLLSAI1R_DIV_2 04568 * @arg @ref LL_RCC_PLLSAI1R_DIV_4 04569 * @arg @ref LL_RCC_PLLSAI1R_DIV_6 04570 * @arg @ref LL_RCC_PLLSAI1R_DIV_8 04571 */ 04572 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void) 04573 { 04574 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R)); 04575 } 04576 04577 #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) 04578 /** 04579 * @brief Get Division factor for the PLLSAI1 04580 * @rmtoll PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_GetDivider 04581 * @retval Returned value can be one of the following values: 04582 * @arg @ref LL_RCC_PLLSAI1M_DIV_1 04583 * @arg @ref LL_RCC_PLLSAI1M_DIV_2 04584 * @arg @ref LL_RCC_PLLSAI1M_DIV_3 04585 * @arg @ref LL_RCC_PLLSAI1M_DIV_4 04586 * @arg @ref LL_RCC_PLLSAI1M_DIV_5 04587 * @arg @ref LL_RCC_PLLSAI1M_DIV_6 04588 * @arg @ref LL_RCC_PLLSAI1M_DIV_7 04589 * @arg @ref LL_RCC_PLLSAI1M_DIV_8 04590 * @arg @ref LL_RCC_PLLSAI1M_DIV_9 04591 * @arg @ref LL_RCC_PLLSAI1M_DIV_10 04592 * @arg @ref LL_RCC_PLLSAI1M_DIV_11 04593 * @arg @ref LL_RCC_PLLSAI1M_DIV_12 04594 * @arg @ref LL_RCC_PLLSAI1M_DIV_13 04595 * @arg @ref LL_RCC_PLLSAI1M_DIV_14 04596 * @arg @ref LL_RCC_PLLSAI1M_DIV_15 04597 * @arg @ref LL_RCC_PLLSAI1M_DIV_16 04598 */ 04599 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetDivider(void) 04600 { 04601 return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M)); 04602 } 04603 #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ 04604 04605 /** 04606 * @brief Enable PLLSAI1 output mapped on SAI domain clock 04607 * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI 04608 * @retval None 04609 */ 04610 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void) 04611 { 04612 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN); 04613 } 04614 04615 /** 04616 * @brief Disable PLLSAI1 output mapped on SAI domain clock 04617 * @note In order to save power, when of the PLLSAI1 is 04618 * not used, should be 0 04619 * @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI 04620 * @retval None 04621 */ 04622 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void) 04623 { 04624 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN); 04625 } 04626 04627 /** 04628 * @brief Enable PLLSAI1 output mapped on 48MHz domain clock 04629 * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M 04630 * @retval None 04631 */ 04632 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void) 04633 { 04634 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN); 04635 } 04636 04637 /** 04638 * @brief Disable PLLSAI1 output mapped on 48MHz domain clock 04639 * @note In order to save power, when of the PLLSAI1 is 04640 * not used, should be 0 04641 * @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M 04642 * @retval None 04643 */ 04644 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void) 04645 { 04646 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN); 04647 } 04648 04649 /** 04650 * @brief Enable PLLSAI1 output mapped on ADC domain clock 04651 * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC 04652 * @retval None 04653 */ 04654 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void) 04655 { 04656 SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN); 04657 } 04658 04659 /** 04660 * @brief Disable PLLSAI1 output mapped on ADC domain clock 04661 * @note In order to save power, when of the PLLSAI1 is 04662 * not used, Main PLLSAI1 should be 0 04663 * @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC 04664 * @retval None 04665 */ 04666 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void) 04667 { 04668 CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN); 04669 } 04670 04671 /** 04672 * @} 04673 */ 04674 04675 #if defined(RCC_PLLSAI2_SUPPORT) 04676 /** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2 04677 * @{ 04678 */ 04679 04680 /** 04681 * @brief Enable PLLSAI2 04682 * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Enable 04683 * @retval None 04684 */ 04685 __STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void) 04686 { 04687 SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON); 04688 } 04689 04690 /** 04691 * @brief Disable PLLSAI2 04692 * @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Disable 04693 * @retval None 04694 */ 04695 __STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void) 04696 { 04697 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON); 04698 } 04699 04700 /** 04701 * @brief Check if PLLSAI2 Ready 04702 * @rmtoll CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady 04703 * @retval State of bit (1 or 0). 04704 */ 04705 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void) 04706 { 04707 return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY)); 04708 } 04709 04710 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 04711 /** 04712 * @brief Configure PLLSAI2 used for SAI domain clock 04713 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. 04714 * @note PLLSAI2M/PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled. 04715 * @note This can be selected for SAI1 or SAI2 04716 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n 04717 * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_SAI\n 04718 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n 04719 * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI 04720 * @param Source This parameter can be one of the following values: 04721 * @arg @ref LL_RCC_PLLSOURCE_NONE 04722 * @arg @ref LL_RCC_PLLSOURCE_MSI 04723 * @arg @ref LL_RCC_PLLSOURCE_HSI 04724 * @arg @ref LL_RCC_PLLSOURCE_HSE 04725 * @param PLLM This parameter can be one of the following values: 04726 * @arg @ref LL_RCC_PLLSAI2M_DIV_1 04727 * @arg @ref LL_RCC_PLLSAI2M_DIV_2 04728 * @arg @ref LL_RCC_PLLSAI2M_DIV_3 04729 * @arg @ref LL_RCC_PLLSAI2M_DIV_4 04730 * @arg @ref LL_RCC_PLLSAI2M_DIV_5 04731 * @arg @ref LL_RCC_PLLSAI2M_DIV_6 04732 * @arg @ref LL_RCC_PLLSAI2M_DIV_7 04733 * @arg @ref LL_RCC_PLLSAI2M_DIV_8 04734 * @arg @ref LL_RCC_PLLSAI2M_DIV_9 04735 * @arg @ref LL_RCC_PLLSAI2M_DIV_10 04736 * @arg @ref LL_RCC_PLLSAI2M_DIV_11 04737 * @arg @ref LL_RCC_PLLSAI2M_DIV_12 04738 * @arg @ref LL_RCC_PLLSAI2M_DIV_13 04739 * @arg @ref LL_RCC_PLLSAI2M_DIV_14 04740 * @arg @ref LL_RCC_PLLSAI2M_DIV_15 04741 * @arg @ref LL_RCC_PLLSAI2M_DIV_16 04742 * @param PLLN Between 8 and 86 04743 * @param PLLP This parameter can be one of the following values: 04744 * @arg @ref LL_RCC_PLLSAI2P_DIV_2 04745 * @arg @ref LL_RCC_PLLSAI2P_DIV_3 04746 * @arg @ref LL_RCC_PLLSAI2P_DIV_4 04747 * @arg @ref LL_RCC_PLLSAI2P_DIV_5 04748 * @arg @ref LL_RCC_PLLSAI2P_DIV_6 04749 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 04750 * @arg @ref LL_RCC_PLLSAI2P_DIV_8 04751 * @arg @ref LL_RCC_PLLSAI2P_DIV_9 04752 * @arg @ref LL_RCC_PLLSAI2P_DIV_10 04753 * @arg @ref LL_RCC_PLLSAI2P_DIV_11 04754 * @arg @ref LL_RCC_PLLSAI2P_DIV_12 04755 * @arg @ref LL_RCC_PLLSAI2P_DIV_13 04756 * @arg @ref LL_RCC_PLLSAI2P_DIV_14 04757 * @arg @ref LL_RCC_PLLSAI2P_DIV_15 04758 * @arg @ref LL_RCC_PLLSAI2P_DIV_16 04759 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 04760 * @arg @ref LL_RCC_PLLSAI2P_DIV_18 04761 * @arg @ref LL_RCC_PLLSAI2P_DIV_19 04762 * @arg @ref LL_RCC_PLLSAI2P_DIV_20 04763 * @arg @ref LL_RCC_PLLSAI2P_DIV_21 04764 * @arg @ref LL_RCC_PLLSAI2P_DIV_22 04765 * @arg @ref LL_RCC_PLLSAI2P_DIV_23 04766 * @arg @ref LL_RCC_PLLSAI2P_DIV_24 04767 * @arg @ref LL_RCC_PLLSAI2P_DIV_25 04768 * @arg @ref LL_RCC_PLLSAI2P_DIV_26 04769 * @arg @ref LL_RCC_PLLSAI2P_DIV_27 04770 * @arg @ref LL_RCC_PLLSAI2P_DIV_28 04771 * @arg @ref LL_RCC_PLLSAI2P_DIV_29 04772 * @arg @ref LL_RCC_PLLSAI2P_DIV_30 04773 * @arg @ref LL_RCC_PLLSAI2P_DIV_31 04774 * @retval None 04775 */ 04776 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 04777 { 04778 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 04779 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, 04780 PLLM | PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP); 04781 } 04782 #elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 04783 /** 04784 * @brief Configure PLLSAI2 used for SAI domain clock 04785 * @note PLL Source and PLLM Divider can be written only when PLL, 04786 * PLLSAI1 and PLLSAI2 are disabled. 04787 * @note PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled. 04788 * @note This can be selected for SAI1 or SAI2 04789 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n 04790 * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n 04791 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n 04792 * PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI 04793 * @param Source This parameter can be one of the following values: 04794 * @arg @ref LL_RCC_PLLSOURCE_NONE 04795 * @arg @ref LL_RCC_PLLSOURCE_MSI 04796 * @arg @ref LL_RCC_PLLSOURCE_HSI 04797 * @arg @ref LL_RCC_PLLSOURCE_HSE 04798 * @param PLLM This parameter can be one of the following values: 04799 * @arg @ref LL_RCC_PLLM_DIV_1 04800 * @arg @ref LL_RCC_PLLM_DIV_2 04801 * @arg @ref LL_RCC_PLLM_DIV_3 04802 * @arg @ref LL_RCC_PLLM_DIV_4 04803 * @arg @ref LL_RCC_PLLM_DIV_5 04804 * @arg @ref LL_RCC_PLLM_DIV_6 04805 * @arg @ref LL_RCC_PLLM_DIV_7 04806 * @arg @ref LL_RCC_PLLM_DIV_8 04807 * @param PLLN Between 8 and 86 04808 * @param PLLP This parameter can be one of the following values: 04809 * @arg @ref LL_RCC_PLLSAI2P_DIV_2 04810 * @arg @ref LL_RCC_PLLSAI2P_DIV_3 04811 * @arg @ref LL_RCC_PLLSAI2P_DIV_4 04812 * @arg @ref LL_RCC_PLLSAI2P_DIV_5 04813 * @arg @ref LL_RCC_PLLSAI2P_DIV_6 04814 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 04815 * @arg @ref LL_RCC_PLLSAI2P_DIV_8 04816 * @arg @ref LL_RCC_PLLSAI2P_DIV_9 04817 * @arg @ref LL_RCC_PLLSAI2P_DIV_10 04818 * @arg @ref LL_RCC_PLLSAI2P_DIV_11 04819 * @arg @ref LL_RCC_PLLSAI2P_DIV_12 04820 * @arg @ref LL_RCC_PLLSAI2P_DIV_13 04821 * @arg @ref LL_RCC_PLLSAI2P_DIV_14 04822 * @arg @ref LL_RCC_PLLSAI2P_DIV_15 04823 * @arg @ref LL_RCC_PLLSAI2P_DIV_16 04824 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 04825 * @arg @ref LL_RCC_PLLSAI2P_DIV_18 04826 * @arg @ref LL_RCC_PLLSAI2P_DIV_19 04827 * @arg @ref LL_RCC_PLLSAI2P_DIV_20 04828 * @arg @ref LL_RCC_PLLSAI2P_DIV_21 04829 * @arg @ref LL_RCC_PLLSAI2P_DIV_22 04830 * @arg @ref LL_RCC_PLLSAI2P_DIV_23 04831 * @arg @ref LL_RCC_PLLSAI2P_DIV_24 04832 * @arg @ref LL_RCC_PLLSAI2P_DIV_25 04833 * @arg @ref LL_RCC_PLLSAI2P_DIV_26 04834 * @arg @ref LL_RCC_PLLSAI2P_DIV_27 04835 * @arg @ref LL_RCC_PLLSAI2P_DIV_28 04836 * @arg @ref LL_RCC_PLLSAI2P_DIV_29 04837 * @arg @ref LL_RCC_PLLSAI2P_DIV_30 04838 * @arg @ref LL_RCC_PLLSAI2P_DIV_31 04839 * @retval None 04840 */ 04841 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 04842 { 04843 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 04844 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP); 04845 } 04846 #else 04847 /** 04848 * @brief Configure PLLSAI2 used for SAI domain clock 04849 * @note PLL Source and PLLM Divider can be written only when PLL, 04850 * PLLSAI2 and PLLSAI2 are disabled. 04851 * @note PLLSAI2N/PLLSAI2P can be written only when PLLSAI2 is disabled. 04852 * @note This can be selected for SAI1 or SAI2 04853 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n 04854 * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n 04855 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n 04856 * PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_ConfigDomain_SAI 04857 * @param Source This parameter can be one of the following values: 04858 * @arg @ref LL_RCC_PLLSOURCE_NONE 04859 * @arg @ref LL_RCC_PLLSOURCE_MSI 04860 * @arg @ref LL_RCC_PLLSOURCE_HSI 04861 * @arg @ref LL_RCC_PLLSOURCE_HSE 04862 * @param PLLM This parameter can be one of the following values: 04863 * @arg @ref LL_RCC_PLLM_DIV_1 04864 * @arg @ref LL_RCC_PLLM_DIV_2 04865 * @arg @ref LL_RCC_PLLM_DIV_3 04866 * @arg @ref LL_RCC_PLLM_DIV_4 04867 * @arg @ref LL_RCC_PLLM_DIV_5 04868 * @arg @ref LL_RCC_PLLM_DIV_6 04869 * @arg @ref LL_RCC_PLLM_DIV_7 04870 * @arg @ref LL_RCC_PLLM_DIV_8 04871 * @param PLLN Between 8 and 86 04872 * @param PLLP This parameter can be one of the following values: 04873 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 04874 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 04875 * @retval None 04876 */ 04877 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 04878 { 04879 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 04880 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP); 04881 } 04882 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2P_DIV_2_31_SUPPORT */ 04883 04884 #if defined(DSI) 04885 /** 04886 * @brief Configure PLLSAI2 used for DSI domain clock 04887 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. 04888 * @note PLLSAI2M/PLLSAI2N/PLLSAI2Q can be written only when PLLSAI2 is disabled. 04889 * @note This can be selected for DSI 04890 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_DSI\n 04891 * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_DSI\n 04892 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_DSI\n 04893 * PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_ConfigDomain_DSI 04894 * @param Source This parameter can be one of the following values: 04895 * @arg @ref LL_RCC_PLLSOURCE_NONE 04896 * @arg @ref LL_RCC_PLLSOURCE_MSI 04897 * @arg @ref LL_RCC_PLLSOURCE_HSI 04898 * @arg @ref LL_RCC_PLLSOURCE_HSE 04899 * @param PLLM This parameter can be one of the following values: 04900 * @arg @ref LL_RCC_PLLSAI2M_DIV_1 04901 * @arg @ref LL_RCC_PLLSAI2M_DIV_2 04902 * @arg @ref LL_RCC_PLLSAI2M_DIV_3 04903 * @arg @ref LL_RCC_PLLSAI2M_DIV_4 04904 * @arg @ref LL_RCC_PLLSAI2M_DIV_5 04905 * @arg @ref LL_RCC_PLLSAI2M_DIV_6 04906 * @arg @ref LL_RCC_PLLSAI2M_DIV_7 04907 * @arg @ref LL_RCC_PLLSAI2M_DIV_8 04908 * @arg @ref LL_RCC_PLLSAI2M_DIV_9 04909 * @arg @ref LL_RCC_PLLSAI2M_DIV_10 04910 * @arg @ref LL_RCC_PLLSAI2M_DIV_11 04911 * @arg @ref LL_RCC_PLLSAI2M_DIV_12 04912 * @arg @ref LL_RCC_PLLSAI2M_DIV_13 04913 * @arg @ref LL_RCC_PLLSAI2M_DIV_14 04914 * @arg @ref LL_RCC_PLLSAI2M_DIV_15 04915 * @arg @ref LL_RCC_PLLSAI2M_DIV_16 04916 * @param PLLN Between 8 and 86 04917 * @param PLLQ This parameter can be one of the following values: 04918 * @arg @ref LL_RCC_PLLSAI2Q_DIV_2 04919 * @arg @ref LL_RCC_PLLSAI2Q_DIV_4 04920 * @arg @ref LL_RCC_PLLSAI2Q_DIV_6 04921 * @arg @ref LL_RCC_PLLSAI2Q_DIV_8 04922 * @retval None 04923 */ 04924 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) 04925 { 04926 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 04927 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLQ | PLLM); 04928 } 04929 #endif /* DSI */ 04930 04931 #if defined(LTDC) 04932 /** 04933 * @brief Configure PLLSAI2 used for LTDC domain clock 04934 * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled. 04935 * @note PLLSAI2M/PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled. 04936 * @note This can be selected for LTDC 04937 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_LTDC\n 04938 * PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_LTDC\n 04939 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_LTDC\n 04940 * PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_LTDC\n 04941 * CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_ConfigDomain_LTDC 04942 * @param Source This parameter can be one of the following values: 04943 * @arg @ref LL_RCC_PLLSOURCE_NONE 04944 * @arg @ref LL_RCC_PLLSOURCE_MSI 04945 * @arg @ref LL_RCC_PLLSOURCE_HSI 04946 * @arg @ref LL_RCC_PLLSOURCE_HSE 04947 * @param PLLM This parameter can be one of the following values: 04948 * @arg @ref LL_RCC_PLLSAI2M_DIV_1 04949 * @arg @ref LL_RCC_PLLSAI2M_DIV_2 04950 * @arg @ref LL_RCC_PLLSAI2M_DIV_3 04951 * @arg @ref LL_RCC_PLLSAI2M_DIV_4 04952 * @arg @ref LL_RCC_PLLSAI2M_DIV_5 04953 * @arg @ref LL_RCC_PLLSAI2M_DIV_6 04954 * @arg @ref LL_RCC_PLLSAI2M_DIV_7 04955 * @arg @ref LL_RCC_PLLSAI2M_DIV_8 04956 * @arg @ref LL_RCC_PLLSAI2M_DIV_9 04957 * @arg @ref LL_RCC_PLLSAI2M_DIV_10 04958 * @arg @ref LL_RCC_PLLSAI2M_DIV_11 04959 * @arg @ref LL_RCC_PLLSAI2M_DIV_12 04960 * @arg @ref LL_RCC_PLLSAI2M_DIV_13 04961 * @arg @ref LL_RCC_PLLSAI2M_DIV_14 04962 * @arg @ref LL_RCC_PLLSAI2M_DIV_15 04963 * @arg @ref LL_RCC_PLLSAI2M_DIV_16 04964 * @param PLLN Between 8 and 86 04965 * @param PLLR This parameter can be one of the following values: 04966 * @arg @ref LL_RCC_PLLSAI2R_DIV_2 04967 * @arg @ref LL_RCC_PLLSAI2R_DIV_4 04968 * @arg @ref LL_RCC_PLLSAI2R_DIV_6 04969 * @arg @ref LL_RCC_PLLSAI2R_DIV_8 04970 * @param PLLDIVR This parameter can be one of the following values: 04971 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2 04972 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4 04973 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8 04974 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16 04975 * @retval None 04976 */ 04977 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) 04978 { 04979 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 04980 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR | PLLM); 04981 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, PLLDIVR); 04982 } 04983 #else 04984 /** 04985 * @brief Configure PLLSAI2 used for ADC domain clock 04986 * @note PLL Source and PLLM Divider can be written only when PLL, 04987 * PLLSAI2 and PLLSAI2 are disabled. 04988 * @note PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled. 04989 * @note This can be selected for ADC 04990 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC\n 04991 * PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC\n 04992 * PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_ADC\n 04993 * PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_ADC 04994 * @param Source This parameter can be one of the following values: 04995 * @arg @ref LL_RCC_PLLSOURCE_NONE 04996 * @arg @ref LL_RCC_PLLSOURCE_MSI 04997 * @arg @ref LL_RCC_PLLSOURCE_HSI 04998 * @arg @ref LL_RCC_PLLSOURCE_HSE 04999 * @param PLLM This parameter can be one of the following values: 05000 * @arg @ref LL_RCC_PLLM_DIV_1 05001 * @arg @ref LL_RCC_PLLM_DIV_2 05002 * @arg @ref LL_RCC_PLLM_DIV_3 05003 * @arg @ref LL_RCC_PLLM_DIV_4 05004 * @arg @ref LL_RCC_PLLM_DIV_5 05005 * @arg @ref LL_RCC_PLLM_DIV_6 05006 * @arg @ref LL_RCC_PLLM_DIV_7 05007 * @arg @ref LL_RCC_PLLM_DIV_8 05008 * @param PLLN Between 8 and 86 05009 * @param PLLR This parameter can be one of the following values: 05010 * @arg @ref LL_RCC_PLLSAI2R_DIV_2 05011 * @arg @ref LL_RCC_PLLSAI2R_DIV_4 05012 * @arg @ref LL_RCC_PLLSAI2R_DIV_6 05013 * @arg @ref LL_RCC_PLLSAI2R_DIV_8 05014 * @retval None 05015 */ 05016 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 05017 { 05018 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 05019 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR); 05020 } 05021 #endif /* LTDC */ 05022 05023 /** 05024 * @brief Get SAI2PLL multiplication factor for VCO 05025 * @rmtoll PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN 05026 * @retval Between 8 and 86 05027 */ 05028 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void) 05029 { 05030 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos); 05031 } 05032 05033 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) 05034 /** 05035 * @brief Get SAI2PLL division factor for PLLSAI2P 05036 * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock). 05037 * @rmtoll PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_GetP 05038 * @retval Returned value can be one of the following values: 05039 * @arg @ref LL_RCC_PLLSAI2P_DIV_2 05040 * @arg @ref LL_RCC_PLLSAI2P_DIV_3 05041 * @arg @ref LL_RCC_PLLSAI2P_DIV_4 05042 * @arg @ref LL_RCC_PLLSAI2P_DIV_5 05043 * @arg @ref LL_RCC_PLLSAI2P_DIV_6 05044 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 05045 * @arg @ref LL_RCC_PLLSAI2P_DIV_8 05046 * @arg @ref LL_RCC_PLLSAI2P_DIV_9 05047 * @arg @ref LL_RCC_PLLSAI2P_DIV_10 05048 * @arg @ref LL_RCC_PLLSAI2P_DIV_11 05049 * @arg @ref LL_RCC_PLLSAI2P_DIV_12 05050 * @arg @ref LL_RCC_PLLSAI2P_DIV_13 05051 * @arg @ref LL_RCC_PLLSAI2P_DIV_14 05052 * @arg @ref LL_RCC_PLLSAI2P_DIV_15 05053 * @arg @ref LL_RCC_PLLSAI2P_DIV_16 05054 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 05055 * @arg @ref LL_RCC_PLLSAI2P_DIV_18 05056 * @arg @ref LL_RCC_PLLSAI2P_DIV_19 05057 * @arg @ref LL_RCC_PLLSAI2P_DIV_20 05058 * @arg @ref LL_RCC_PLLSAI2P_DIV_21 05059 * @arg @ref LL_RCC_PLLSAI2P_DIV_22 05060 * @arg @ref LL_RCC_PLLSAI2P_DIV_23 05061 * @arg @ref LL_RCC_PLLSAI2P_DIV_24 05062 * @arg @ref LL_RCC_PLLSAI2P_DIV_25 05063 * @arg @ref LL_RCC_PLLSAI2P_DIV_26 05064 * @arg @ref LL_RCC_PLLSAI2P_DIV_27 05065 * @arg @ref LL_RCC_PLLSAI2P_DIV_28 05066 * @arg @ref LL_RCC_PLLSAI2P_DIV_29 05067 * @arg @ref LL_RCC_PLLSAI2P_DIV_30 05068 * @arg @ref LL_RCC_PLLSAI2P_DIV_31 05069 */ 05070 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void) 05071 { 05072 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV)); 05073 } 05074 #else 05075 /** 05076 * @brief Get SAI2PLL division factor for PLLSAI2P 05077 * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock). 05078 * @rmtoll PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP 05079 * @retval Returned value can be one of the following values: 05080 * @arg @ref LL_RCC_PLLSAI2P_DIV_7 05081 * @arg @ref LL_RCC_PLLSAI2P_DIV_17 05082 */ 05083 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void) 05084 { 05085 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P)); 05086 } 05087 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ 05088 05089 #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) 05090 /** 05091 * @brief Get division factor for PLLSAI2Q 05092 * @note Used for PLLDSICLK (DSI clock) 05093 * @rmtoll PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_GetQ 05094 * @retval Returned value can be one of the following values: 05095 * @arg @ref LL_RCC_PLLSAI2Q_DIV_2 05096 * @arg @ref LL_RCC_PLLSAI2Q_DIV_4 05097 * @arg @ref LL_RCC_PLLSAI2Q_DIV_6 05098 * @arg @ref LL_RCC_PLLSAI2Q_DIV_8 05099 */ 05100 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetQ(void) 05101 { 05102 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q)); 05103 } 05104 #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ 05105 05106 /** 05107 * @brief Get SAI2PLL division factor for PLLSAI2R 05108 * @note Used for PLLADC2CLK (ADC clock) or PLLLCDCLK (LTDC clock) depending on devices 05109 * @rmtoll PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR 05110 * @retval Returned value can be one of the following values: 05111 * @arg @ref LL_RCC_PLLSAI2R_DIV_2 05112 * @arg @ref LL_RCC_PLLSAI2R_DIV_4 05113 * @arg @ref LL_RCC_PLLSAI2R_DIV_6 05114 * @arg @ref LL_RCC_PLLSAI2R_DIV_8 05115 */ 05116 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void) 05117 { 05118 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)); 05119 } 05120 05121 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 05122 /** 05123 * @brief Get Division factor for the PLLSAI2 05124 * @rmtoll PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_GetDivider 05125 * @retval Returned value can be one of the following values: 05126 * @arg @ref LL_RCC_PLLSAI2M_DIV_1 05127 * @arg @ref LL_RCC_PLLSAI2M_DIV_2 05128 * @arg @ref LL_RCC_PLLSAI2M_DIV_3 05129 * @arg @ref LL_RCC_PLLSAI2M_DIV_4 05130 * @arg @ref LL_RCC_PLLSAI2M_DIV_5 05131 * @arg @ref LL_RCC_PLLSAI2M_DIV_6 05132 * @arg @ref LL_RCC_PLLSAI2M_DIV_7 05133 * @arg @ref LL_RCC_PLLSAI2M_DIV_8 05134 * @arg @ref LL_RCC_PLLSAI2M_DIV_9 05135 * @arg @ref LL_RCC_PLLSAI2M_DIV_10 05136 * @arg @ref LL_RCC_PLLSAI2M_DIV_11 05137 * @arg @ref LL_RCC_PLLSAI2M_DIV_12 05138 * @arg @ref LL_RCC_PLLSAI2M_DIV_13 05139 * @arg @ref LL_RCC_PLLSAI2M_DIV_14 05140 * @arg @ref LL_RCC_PLLSAI2M_DIV_15 05141 * @arg @ref LL_RCC_PLLSAI2M_DIV_16 05142 */ 05143 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider(void) 05144 { 05145 return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M)); 05146 } 05147 #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ 05148 05149 #if defined(RCC_CCIPR2_PLLSAI2DIVR) 05150 /** 05151 * @brief Get PLLSAI2 division factor for PLLSAI2DIVR 05152 * @note Used for LTDC domain clock 05153 * @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_GetDIVR 05154 * @retval Returned value can be one of the following values: 05155 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2 05156 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4 05157 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8 05158 * @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16 05159 */ 05160 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDIVR(void) 05161 { 05162 return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR)); 05163 } 05164 #endif /* RCC_CCIPR2_PLLSAI2DIVR */ 05165 05166 /** 05167 * @brief Enable PLLSAI2 output mapped on SAI domain clock 05168 * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI 05169 * @retval None 05170 */ 05171 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void) 05172 { 05173 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN); 05174 } 05175 05176 /** 05177 * @brief Disable PLLSAI2 output mapped on SAI domain clock 05178 * @note In order to save power, when of the PLLSAI2 is 05179 * not used, should be 0 05180 * @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_DisableDomain_SAI 05181 * @retval None 05182 */ 05183 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void) 05184 { 05185 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN); 05186 } 05187 05188 #if defined(DSI) 05189 /** 05190 * @brief Enable PLLSAI2 output mapped on DSI domain clock 05191 * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_EnableDomain_DSI 05192 * @retval None 05193 */ 05194 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_DSI(void) 05195 { 05196 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN); 05197 } 05198 05199 /** 05200 * @brief Disable PLLSAI2 output mapped on DSI domain clock 05201 * @note In order to save power, when of the PLLSAI2 is 05202 * not used, Main PLLSAI2 should be 0 05203 * @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_DisableDomain_DSI 05204 * @retval None 05205 */ 05206 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_DSI(void) 05207 { 05208 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN); 05209 } 05210 #endif /* DSI */ 05211 05212 #if defined(LTDC) 05213 /** 05214 * @brief Enable PLLSAI2 output mapped on LTDC domain clock 05215 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_LTDC 05216 * @retval None 05217 */ 05218 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_LTDC(void) 05219 { 05220 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); 05221 } 05222 05223 /** 05224 * @brief Disable PLLSAI2 output mapped on LTDC domain clock 05225 * @note In order to save power, when of the PLLSAI2 is 05226 * not used, Main PLLSAI2 should be 0 05227 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_LTDC 05228 * @retval None 05229 */ 05230 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_LTDC(void) 05231 { 05232 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); 05233 } 05234 #else 05235 /** 05236 * @brief Enable PLLSAI2 output mapped on ADC domain clock 05237 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC 05238 * @retval None 05239 */ 05240 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void) 05241 { 05242 SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); 05243 } 05244 05245 /** 05246 * @brief Disable PLLSAI2 output mapped on ADC domain clock 05247 * @note In order to save power, when of the PLLSAI2 is 05248 * not used, Main PLLSAI2 should be 0 05249 * @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_ADC 05250 * @retval None 05251 */ 05252 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void) 05253 { 05254 CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN); 05255 } 05256 #endif /* LTDC */ 05257 05258 /** 05259 * @} 05260 */ 05261 #endif /* RCC_PLLSAI2_SUPPORT */ 05262 05263 05264 05265 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management 05266 * @{ 05267 */ 05268 05269 /** 05270 * @brief Clear LSI ready interrupt flag 05271 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY 05272 * @retval None 05273 */ 05274 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) 05275 { 05276 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); 05277 } 05278 05279 /** 05280 * @brief Clear LSE ready interrupt flag 05281 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY 05282 * @retval None 05283 */ 05284 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) 05285 { 05286 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); 05287 } 05288 05289 /** 05290 * @brief Clear MSI ready interrupt flag 05291 * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY 05292 * @retval None 05293 */ 05294 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void) 05295 { 05296 SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC); 05297 } 05298 05299 /** 05300 * @brief Clear HSI ready interrupt flag 05301 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY 05302 * @retval None 05303 */ 05304 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) 05305 { 05306 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); 05307 } 05308 05309 /** 05310 * @brief Clear HSE ready interrupt flag 05311 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY 05312 * @retval None 05313 */ 05314 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) 05315 { 05316 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); 05317 } 05318 05319 /** 05320 * @brief Clear PLL ready interrupt flag 05321 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY 05322 * @retval None 05323 */ 05324 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) 05325 { 05326 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC); 05327 } 05328 05329 #if defined(RCC_HSI48_SUPPORT) 05330 /** 05331 * @brief Clear HSI48 ready interrupt flag 05332 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY 05333 * @retval None 05334 */ 05335 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) 05336 { 05337 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); 05338 } 05339 #endif /* RCC_HSI48_SUPPORT */ 05340 05341 /** 05342 * @brief Clear PLLSAI1 ready interrupt flag 05343 * @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY 05344 * @retval None 05345 */ 05346 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void) 05347 { 05348 SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC); 05349 } 05350 05351 #if defined(RCC_PLLSAI2_SUPPORT) 05352 /** 05353 * @brief Clear PLLSAI1 ready interrupt flag 05354 * @rmtoll CICR PLLSAI2RDYC LL_RCC_ClearFlag_PLLSAI2RDY 05355 * @retval None 05356 */ 05357 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void) 05358 { 05359 SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC); 05360 } 05361 #endif /* RCC_PLLSAI2_SUPPORT */ 05362 05363 /** 05364 * @brief Clear Clock security system interrupt flag 05365 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS 05366 * @retval None 05367 */ 05368 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) 05369 { 05370 SET_BIT(RCC->CICR, RCC_CICR_CSSC); 05371 } 05372 05373 /** 05374 * @brief Clear LSE Clock security system interrupt flag 05375 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS 05376 * @retval None 05377 */ 05378 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) 05379 { 05380 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); 05381 } 05382 05383 /** 05384 * @brief Check if LSI ready interrupt occurred or not 05385 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY 05386 * @retval State of bit (1 or 0). 05387 */ 05388 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) 05389 { 05390 return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)); 05391 } 05392 05393 /** 05394 * @brief Check if LSE ready interrupt occurred or not 05395 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY 05396 * @retval State of bit (1 or 0). 05397 */ 05398 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) 05399 { 05400 return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)); 05401 } 05402 05403 /** 05404 * @brief Check if MSI ready interrupt occurred or not 05405 * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY 05406 * @retval State of bit (1 or 0). 05407 */ 05408 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void) 05409 { 05410 return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF)); 05411 } 05412 05413 /** 05414 * @brief Check if HSI ready interrupt occurred or not 05415 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY 05416 * @retval State of bit (1 or 0). 05417 */ 05418 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) 05419 { 05420 return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)); 05421 } 05422 05423 /** 05424 * @brief Check if HSE ready interrupt occurred or not 05425 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY 05426 * @retval State of bit (1 or 0). 05427 */ 05428 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) 05429 { 05430 return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)); 05431 } 05432 05433 /** 05434 * @brief Check if PLL ready interrupt occurred or not 05435 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY 05436 * @retval State of bit (1 or 0). 05437 */ 05438 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) 05439 { 05440 return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)); 05441 } 05442 05443 #if defined(RCC_HSI48_SUPPORT) 05444 /** 05445 * @brief Check if HSI48 ready interrupt occurred or not 05446 * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY 05447 * @retval State of bit (1 or 0). 05448 */ 05449 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) 05450 { 05451 return (READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)); 05452 } 05453 #endif /* RCC_HSI48_SUPPORT */ 05454 05455 /** 05456 * @brief Check if PLLSAI1 ready interrupt occurred or not 05457 * @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY 05458 * @retval State of bit (1 or 0). 05459 */ 05460 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void) 05461 { 05462 return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF)); 05463 } 05464 05465 #if defined(RCC_PLLSAI2_SUPPORT) 05466 /** 05467 * @brief Check if PLLSAI1 ready interrupt occurred or not 05468 * @rmtoll CIFR PLLSAI2RDYF LL_RCC_IsActiveFlag_PLLSAI2RDY 05469 * @retval State of bit (1 or 0). 05470 */ 05471 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void) 05472 { 05473 return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == (RCC_CIFR_PLLSAI2RDYF)); 05474 } 05475 #endif /* RCC_PLLSAI2_SUPPORT */ 05476 05477 /** 05478 * @brief Check if Clock security system interrupt occurred or not 05479 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS 05480 * @retval State of bit (1 or 0). 05481 */ 05482 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) 05483 { 05484 return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)); 05485 } 05486 05487 /** 05488 * @brief Check if LSE Clock security system interrupt occurred or not 05489 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS 05490 * @retval State of bit (1 or 0). 05491 */ 05492 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) 05493 { 05494 return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)); 05495 } 05496 05497 /** 05498 * @brief Check if RCC flag FW reset is set or not. 05499 * @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST 05500 * @retval State of bit (1 or 0). 05501 */ 05502 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void) 05503 { 05504 return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF)); 05505 } 05506 05507 /** 05508 * @brief Check if RCC flag Independent Watchdog reset is set or not. 05509 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST 05510 * @retval State of bit (1 or 0). 05511 */ 05512 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) 05513 { 05514 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); 05515 } 05516 05517 /** 05518 * @brief Check if RCC flag Low Power reset is set or not. 05519 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST 05520 * @retval State of bit (1 or 0). 05521 */ 05522 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) 05523 { 05524 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); 05525 } 05526 05527 /** 05528 * @brief Check if RCC flag is set or not. 05529 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST 05530 * @retval State of bit (1 or 0). 05531 */ 05532 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) 05533 { 05534 return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)); 05535 } 05536 05537 /** 05538 * @brief Check if RCC flag Pin reset is set or not. 05539 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST 05540 * @retval State of bit (1 or 0). 05541 */ 05542 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) 05543 { 05544 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); 05545 } 05546 05547 /** 05548 * @brief Check if RCC flag Software reset is set or not. 05549 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST 05550 * @retval State of bit (1 or 0). 05551 */ 05552 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) 05553 { 05554 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); 05555 } 05556 05557 /** 05558 * @brief Check if RCC flag Window Watchdog reset is set or not. 05559 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST 05560 * @retval State of bit (1 or 0). 05561 */ 05562 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) 05563 { 05564 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); 05565 } 05566 05567 /** 05568 * @brief Check if RCC flag BOR reset is set or not. 05569 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST 05570 * @retval State of bit (1 or 0). 05571 */ 05572 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) 05573 { 05574 return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)); 05575 } 05576 05577 /** 05578 * @brief Set RMVF bit to clear the reset flags. 05579 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags 05580 * @retval None 05581 */ 05582 __STATIC_INLINE void LL_RCC_ClearResetFlags(void) 05583 { 05584 SET_BIT(RCC->CSR, RCC_CSR_RMVF); 05585 } 05586 05587 /** 05588 * @} 05589 */ 05590 05591 /** @defgroup RCC_LL_EF_IT_Management IT Management 05592 * @{ 05593 */ 05594 05595 /** 05596 * @brief Enable LSI ready interrupt 05597 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY 05598 * @retval None 05599 */ 05600 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) 05601 { 05602 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); 05603 } 05604 05605 /** 05606 * @brief Enable LSE ready interrupt 05607 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY 05608 * @retval None 05609 */ 05610 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) 05611 { 05612 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); 05613 } 05614 05615 /** 05616 * @brief Enable MSI ready interrupt 05617 * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY 05618 * @retval None 05619 */ 05620 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void) 05621 { 05622 SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE); 05623 } 05624 05625 /** 05626 * @brief Enable HSI ready interrupt 05627 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY 05628 * @retval None 05629 */ 05630 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) 05631 { 05632 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); 05633 } 05634 05635 /** 05636 * @brief Enable HSE ready interrupt 05637 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY 05638 * @retval None 05639 */ 05640 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) 05641 { 05642 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); 05643 } 05644 05645 /** 05646 * @brief Enable PLL ready interrupt 05647 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY 05648 * @retval None 05649 */ 05650 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) 05651 { 05652 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); 05653 } 05654 05655 #if defined(RCC_HSI48_SUPPORT) 05656 /** 05657 * @brief Enable HSI48 ready interrupt 05658 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY 05659 * @retval None 05660 */ 05661 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) 05662 { 05663 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); 05664 } 05665 #endif /* RCC_HSI48_SUPPORT */ 05666 05667 /** 05668 * @brief Enable PLLSAI1 ready interrupt 05669 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY 05670 * @retval None 05671 */ 05672 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void) 05673 { 05674 SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE); 05675 } 05676 05677 #if defined(RCC_PLLSAI2_SUPPORT) 05678 /** 05679 * @brief Enable PLLSAI2 ready interrupt 05680 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_EnableIT_PLLSAI2RDY 05681 * @retval None 05682 */ 05683 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void) 05684 { 05685 SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE); 05686 } 05687 #endif /* RCC_PLLSAI2_SUPPORT */ 05688 05689 /** 05690 * @brief Enable LSE clock security system interrupt 05691 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS 05692 * @retval None 05693 */ 05694 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void) 05695 { 05696 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE); 05697 } 05698 05699 /** 05700 * @brief Disable LSI ready interrupt 05701 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY 05702 * @retval None 05703 */ 05704 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) 05705 { 05706 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); 05707 } 05708 05709 /** 05710 * @brief Disable LSE ready interrupt 05711 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY 05712 * @retval None 05713 */ 05714 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) 05715 { 05716 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); 05717 } 05718 05719 /** 05720 * @brief Disable MSI ready interrupt 05721 * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY 05722 * @retval None 05723 */ 05724 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void) 05725 { 05726 CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE); 05727 } 05728 05729 /** 05730 * @brief Disable HSI ready interrupt 05731 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY 05732 * @retval None 05733 */ 05734 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) 05735 { 05736 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); 05737 } 05738 05739 /** 05740 * @brief Disable HSE ready interrupt 05741 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY 05742 * @retval None 05743 */ 05744 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) 05745 { 05746 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); 05747 } 05748 05749 /** 05750 * @brief Disable PLL ready interrupt 05751 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY 05752 * @retval None 05753 */ 05754 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) 05755 { 05756 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); 05757 } 05758 05759 #if defined(RCC_HSI48_SUPPORT) 05760 /** 05761 * @brief Disable HSI48 ready interrupt 05762 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY 05763 * @retval None 05764 */ 05765 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) 05766 { 05767 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); 05768 } 05769 #endif /* RCC_HSI48_SUPPORT */ 05770 05771 /** 05772 * @brief Disable PLLSAI1 ready interrupt 05773 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY 05774 * @retval None 05775 */ 05776 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void) 05777 { 05778 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE); 05779 } 05780 05781 #if defined(RCC_PLLSAI2_SUPPORT) 05782 /** 05783 * @brief Disable PLLSAI2 ready interrupt 05784 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_DisableIT_PLLSAI2RDY 05785 * @retval None 05786 */ 05787 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void) 05788 { 05789 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE); 05790 } 05791 #endif /* RCC_PLLSAI2_SUPPORT */ 05792 05793 /** 05794 * @brief Disable LSE clock security system interrupt 05795 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS 05796 * @retval None 05797 */ 05798 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) 05799 { 05800 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE); 05801 } 05802 05803 /** 05804 * @brief Checks if LSI ready interrupt source is enabled or disabled. 05805 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY 05806 * @retval State of bit (1 or 0). 05807 */ 05808 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) 05809 { 05810 return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)); 05811 } 05812 05813 /** 05814 * @brief Checks if LSE ready interrupt source is enabled or disabled. 05815 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY 05816 * @retval State of bit (1 or 0). 05817 */ 05818 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) 05819 { 05820 return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)); 05821 } 05822 05823 /** 05824 * @brief Checks if MSI ready interrupt source is enabled or disabled. 05825 * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY 05826 * @retval State of bit (1 or 0). 05827 */ 05828 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void) 05829 { 05830 return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE)); 05831 } 05832 05833 /** 05834 * @brief Checks if HSI ready interrupt source is enabled or disabled. 05835 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY 05836 * @retval State of bit (1 or 0). 05837 */ 05838 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) 05839 { 05840 return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)); 05841 } 05842 05843 /** 05844 * @brief Checks if HSE ready interrupt source is enabled or disabled. 05845 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY 05846 * @retval State of bit (1 or 0). 05847 */ 05848 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) 05849 { 05850 return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)); 05851 } 05852 05853 /** 05854 * @brief Checks if PLL ready interrupt source is enabled or disabled. 05855 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY 05856 * @retval State of bit (1 or 0). 05857 */ 05858 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) 05859 { 05860 return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)); 05861 } 05862 05863 #if defined(RCC_HSI48_SUPPORT) 05864 /** 05865 * @brief Checks if HSI48 ready interrupt source is enabled or disabled. 05866 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY 05867 * @retval State of bit (1 or 0). 05868 */ 05869 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) 05870 { 05871 return (READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)); 05872 } 05873 #endif /* RCC_HSI48_SUPPORT */ 05874 05875 /** 05876 * @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled. 05877 * @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY 05878 * @retval State of bit (1 or 0). 05879 */ 05880 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void) 05881 { 05882 return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE)); 05883 } 05884 05885 #if defined(RCC_PLLSAI2_SUPPORT) 05886 /** 05887 * @brief Checks if PLLSAI2 ready interrupt source is enabled or disabled. 05888 * @rmtoll CIER PLLSAI2RDYIE LL_RCC_IsEnabledIT_PLLSAI2RDY 05889 * @retval State of bit (1 or 0). 05890 */ 05891 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void) 05892 { 05893 return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == (RCC_CIER_PLLSAI2RDYIE)); 05894 } 05895 #endif /* RCC_PLLSAI2_SUPPORT */ 05896 05897 /** 05898 * @brief Checks if LSECSS interrupt source is enabled or disabled. 05899 * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS 05900 * @retval State of bit (1 or 0). 05901 */ 05902 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void) 05903 { 05904 return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)); 05905 } 05906 05907 /** 05908 * @} 05909 */ 05910 05911 #if defined(USE_FULL_LL_DRIVER) 05912 /** @defgroup RCC_LL_EF_Init De-initialization function 05913 * @{ 05914 */ 05915 ErrorStatus LL_RCC_DeInit(void); 05916 /** 05917 * @} 05918 */ 05919 05920 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions 05921 * @{ 05922 */ 05923 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); 05924 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); 05925 #if defined(UART4) || defined(UART5) 05926 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); 05927 #endif /* UART4 || UART5 */ 05928 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); 05929 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); 05930 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); 05931 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); 05932 #if defined(RCC_CCIPR2_SDMMCSEL) 05933 uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource); 05934 #endif 05935 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); 05936 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); 05937 #if defined(USB_OTG_FS) || defined(USB) 05938 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); 05939 #endif /* USB_OTG_FS || USB */ 05940 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); 05941 #if defined(SWPMI1) 05942 uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource); 05943 #endif /* SWPMI1 */ 05944 #if defined(DFSDM1_Channel0) 05945 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); 05946 #if defined(RCC_CCIPR2_DFSDM1SEL) 05947 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource); 05948 #endif /* RCC_CCIPR2_DFSDM1SEL */ 05949 #endif /* DFSDM1_Channel0 */ 05950 #if defined(LTDC) 05951 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); 05952 #endif /* LTDC */ 05953 #if defined(DSI) 05954 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); 05955 #endif /* DSI */ 05956 #if defined(OCTOSPI1) 05957 uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource); 05958 #endif /* OCTOSPI1 */ 05959 /** 05960 * @} 05961 */ 05962 #endif /* USE_FULL_LL_DRIVER */ 05963 05964 /** 05965 * @} 05966 */ 05967 05968 /** 05969 * @} 05970 */ 05971 05972 #endif /* defined(RCC) */ 05973 05974 /** 05975 * @} 05976 */ 05977 05978 #ifdef __cplusplus 05979 } 05980 #endif 05981 05982 #endif /* __STM32L4xx_LL_RCC_H */ 05983 05984 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1