STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_rcc.c 00004 * @author MCD Application Team 00005 * @brief RCC LL module driver. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 #if defined(USE_FULL_LL_DRIVER) 00036 00037 /* Includes ------------------------------------------------------------------*/ 00038 #include "stm32l4xx_ll_rcc.h" 00039 #ifdef USE_FULL_ASSERT 00040 #include "stm32_assert.h" 00041 #else 00042 #define assert_param(expr) ((void)0U) 00043 #endif 00044 /** @addtogroup STM32L4xx_LL_Driver 00045 * @{ 00046 */ 00047 00048 #if defined(RCC) 00049 00050 /** @addtogroup RCC_LL 00051 * @{ 00052 */ 00053 00054 /* Private types -------------------------------------------------------------*/ 00055 /* Private variables ---------------------------------------------------------*/ 00056 /* Private constants ---------------------------------------------------------*/ 00057 /* Private macros ------------------------------------------------------------*/ 00058 /** @addtogroup RCC_LL_Private_Macros 00059 * @{ 00060 */ 00061 #if defined(RCC_CCIPR_USART3SEL) 00062 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ 00063 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ 00064 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) 00065 #else 00066 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ 00067 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) 00068 00069 #endif /* RCC_CCIPR_USART3SEL */ 00070 #if defined(RCC_CCIPR_UART4SEL) && defined(RCC_CCIPR_UART5SEL) 00071 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \ 00072 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)) 00073 #elif defined(RCC_CCIPR_UART4SEL) 00074 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE) 00075 #elif defined(RCC_CCIPR_UART5SEL) 00076 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_UART5_CLKSOURCE) 00077 #endif /* RCC_CCIPR_UART4SEL && RCC_CCIPR_UART5SEL*/ 00078 00079 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)) 00080 00081 #if defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL) && defined(RCC_CCIPR2_I2C4SEL) 00082 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ 00083 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ 00084 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \ 00085 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE)) 00086 #elif defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL) 00087 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ 00088 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ 00089 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) 00090 00091 #elif !defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL) 00092 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ 00093 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) 00094 00095 #else 00096 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) 00097 00098 #endif /* RCC_CCIPR_I2C2SEL && RCC_CCIPR_I2C3SEL && RCC_CCIPR2_I2C4SEL */ 00099 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ 00100 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)) 00101 00102 #if defined(RCC_CCIPR_SAI2SEL) 00103 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \ 00104 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE)) 00105 #else 00106 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) 00107 #endif /* RCC_CCIPR_SAI2SEL */ 00108 00109 #if defined(RCC_CCIPR2_SDMMCSEL) 00110 #define IS_LL_RCC_SDMMC_KERNELCLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_KERNELCLKSOURCE)) 00111 #endif /* RCC_CCIPR2_SDMMCSEL */ 00112 00113 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE)) 00114 00115 00116 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE)) 00117 00118 #if defined(USB_OTG_FS) || defined(USB) 00119 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) 00120 #endif /* USB_OTG_FS || USB */ 00121 00122 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE)) 00123 00124 #if defined(SWPMI1) 00125 #define IS_LL_RCC_SWPMI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SWPMI1_CLKSOURCE)) 00126 #endif /* SWPMI1 */ 00127 00128 #if defined(DFSDM1_Channel0) 00129 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE)) 00130 #if defined(RCC_CCIPR2_DFSDM1SEL) 00131 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE)) 00132 #endif /* RCC_CCIPR2_DFSDM1SEL */ 00133 #endif /* DFSDM1_Channel0 */ 00134 00135 #if defined(DSI) 00136 #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE)) 00137 #endif /* DSI */ 00138 00139 #if defined(LTDC) 00140 #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE)) 00141 #endif /* LTDC */ 00142 00143 #if defined(OCTOSPI1) 00144 #define IS_LL_RCC_OCTOSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OCTOSPI_CLKSOURCE)) 00145 #endif /* OCTOSPI */ 00146 00147 /** 00148 * @} 00149 */ 00150 00151 /* Private function prototypes -----------------------------------------------*/ 00152 /** @defgroup RCC_LL_Private_Functions RCC Private functions 00153 * @{ 00154 */ 00155 uint32_t RCC_GetSystemClockFreq(void); 00156 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); 00157 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); 00158 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); 00159 uint32_t RCC_PLL_GetFreqDomain_SYS(void); 00160 uint32_t RCC_PLL_GetFreqDomain_SAI(void); 00161 uint32_t RCC_PLL_GetFreqDomain_48M(void); 00162 uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void); 00163 uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void); 00164 uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void); 00165 #if defined(RCC_PLLSAI2_SUPPORT) 00166 uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void); 00167 #if defined(LTDC) 00168 uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void); 00169 #else 00170 uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void); 00171 #endif /* LTDC */ 00172 #if defined(DSI) 00173 uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void); 00174 #endif /* DSI */ 00175 #endif /*RCC_PLLSAI2_SUPPORT*/ 00176 /** 00177 * @} 00178 */ 00179 00180 00181 /* Exported functions --------------------------------------------------------*/ 00182 /** @addtogroup RCC_LL_Exported_Functions 00183 * @{ 00184 */ 00185 00186 /** @addtogroup RCC_LL_EF_Init 00187 * @{ 00188 */ 00189 00190 /** 00191 * @brief Reset the RCC clock configuration to the default reset state. 00192 * @note The default reset state of the clock configuration is given below: 00193 * - MSI ON and used as system clock source 00194 * - HSE, HSI, PLL, PLLSAI1 and PLLSAI2 OFF 00195 * - AHB, APB1 and APB2 prescaler set to 1. 00196 * - CSS, MCO OFF 00197 * - All interrupts disabled 00198 * @note This function doesn't modify the configuration of the 00199 * - Peripheral clocks 00200 * - LSI, LSE and RTC clocks 00201 * @retval An ErrorStatus enumeration value: 00202 * - SUCCESS: RCC registers are de-initialized 00203 * - ERROR: not applicable 00204 */ 00205 ErrorStatus LL_RCC_DeInit(void) 00206 { 00207 uint32_t vl_mask = 0U; 00208 00209 /* Set MSION bit */ 00210 LL_RCC_MSI_Enable(); 00211 00212 /* Insure MSIRDY bit is set before writing default MSIRANGE value */ 00213 while (LL_RCC_MSI_IsReady() == 0U) 00214 { 00215 } 00216 00217 /* Set MSIRANGE default value */ 00218 LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6); 00219 00220 /* Set MSITRIM bits to the reset value*/ 00221 LL_RCC_MSI_SetCalibTrimming(0); 00222 00223 /* Set HSITRIM bits to the reset value*/ 00224 LL_RCC_HSI_SetCalibTrimming(0x10U); 00225 00226 /* Reset CFGR register */ 00227 LL_RCC_WriteReg(CFGR, 0x00000000U); 00228 00229 vl_mask = 0xFFFFFFFFU; 00230 00231 /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLON bits */ 00232 CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON | RCC_CR_HSEON | 00233 RCC_CR_PLLON)); 00234 00235 /* Reset PLLSAI1ON bit */ 00236 CLEAR_BIT(vl_mask, RCC_CR_PLLSAI1ON); 00237 00238 #if defined(RCC_PLLSAI2_SUPPORT) 00239 /* Reset PLLSAI2ON bit */ 00240 CLEAR_BIT(vl_mask, RCC_CR_PLLSAI2ON); 00241 #endif /*RCC_PLLSAI2_SUPPORT*/ 00242 00243 /* Write new mask in CR register */ 00244 LL_RCC_WriteReg(CR, vl_mask); 00245 00246 #if defined(RCC_PLLSAI2_SUPPORT) 00247 /* Wait for PLLRDY, PLLSAI1RDY and PLLSAI2RDY bits to be reset */ 00248 while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) 00249 { 00250 } 00251 #else 00252 /* Wait for PLLRDY, PLLSAI1RDY bits to be reset */ 00253 while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U) 00254 { 00255 } 00256 #endif 00257 00258 /* Reset PLLCFGR register */ 00259 LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos); 00260 00261 /* Reset PLLSAI1CFGR register */ 00262 LL_RCC_WriteReg(PLLSAI1CFGR, 16U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos); 00263 00264 #if defined(RCC_PLLSAI2_SUPPORT) 00265 /* Reset PLLSAI2CFGR register */ 00266 LL_RCC_WriteReg(PLLSAI2CFGR, 16U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos); 00267 #endif /*RCC_PLLSAI2_SUPPORT*/ 00268 00269 /* Reset HSEBYP bit */ 00270 LL_RCC_HSE_DisableBypass(); 00271 00272 /* Disable all interrupts */ 00273 LL_RCC_WriteReg(CIER, 0x00000000U); 00274 00275 /* Clear all interrupt flags */ 00276 vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \ 00277 RCC_CICR_PLLSAI1RDYC | RCC_CICR_CSSC | RCC_CICR_LSECSSC; 00278 #if defined(RCC_HSI48_SUPPORT) 00279 vl_mask |= RCC_CICR_HSI48RDYC; 00280 #endif 00281 #if defined(RCC_PLLSAI2_SUPPORT) 00282 vl_mask |= RCC_CICR_PLLSAI2RDYC; 00283 #endif 00284 LL_RCC_WriteReg(CICR, vl_mask); 00285 00286 /* Clear reset flags */ 00287 LL_RCC_ClearResetFlags(); 00288 00289 return SUCCESS; 00290 } 00291 00292 /** 00293 * @} 00294 */ 00295 00296 /** @addtogroup RCC_LL_EF_Get_Freq 00297 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks 00298 * and different peripheral clocks available on the device. 00299 * @note If SYSCLK source is MSI, function returns values based on MSI_VALUE(*) 00300 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) 00301 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) 00302 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***) 00303 * or HSI_VALUE(**) or MSI_VALUE(*) multiplied/divided by the PLL factors. 00304 * @note (*) MSI_VALUE is a constant defined in this file (default value 00305 * 4 MHz) but the real value may vary depending on the variations 00306 * in voltage and temperature. 00307 * @note (**) HSI_VALUE is a constant defined in this file (default value 00308 * 16 MHz) but the real value may vary depending on the variations 00309 * in voltage and temperature. 00310 * @note (***) HSE_VALUE is a constant defined in this file (default value 00311 * 8 MHz), user has to ensure that HSE_VALUE is same as the real 00312 * frequency of the crystal used. Otherwise, this function may 00313 * have wrong result. 00314 * @note The result of this function could be incorrect when using fractional 00315 * value for HSE crystal. 00316 * @note This function can be used by the user application to compute the 00317 * baud-rate for the communication peripherals or configure other parameters. 00318 * @{ 00319 */ 00320 00321 /** 00322 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks 00323 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function 00324 * must be called to update structure fields. Otherwise, any 00325 * configuration based on this function will be incorrect. 00326 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies 00327 * @retval None 00328 */ 00329 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) 00330 { 00331 /* Get SYSCLK frequency */ 00332 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); 00333 00334 /* HCLK clock frequency */ 00335 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); 00336 00337 /* PCLK1 clock frequency */ 00338 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); 00339 00340 /* PCLK2 clock frequency */ 00341 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency); 00342 } 00343 00344 /** 00345 * @brief Return USARTx clock frequency 00346 * @param USARTxSource This parameter can be one of the following values: 00347 * @arg @ref LL_RCC_USART1_CLKSOURCE 00348 * @arg @ref LL_RCC_USART2_CLKSOURCE 00349 * @arg @ref LL_RCC_USART3_CLKSOURCE (*) 00350 * 00351 * (*) value not defined in all devices. 00352 * @retval USART clock frequency (in Hz) 00353 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready 00354 */ 00355 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) 00356 { 00357 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00358 00359 /* Check parameter */ 00360 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); 00361 00362 if (USARTxSource == LL_RCC_USART1_CLKSOURCE) 00363 { 00364 /* USART1CLK clock frequency */ 00365 switch (LL_RCC_GetUSARTClockSource(USARTxSource)) 00366 { 00367 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ 00368 usart_frequency = RCC_GetSystemClockFreq(); 00369 break; 00370 00371 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ 00372 if (LL_RCC_HSI_IsReady()) 00373 { 00374 usart_frequency = HSI_VALUE; 00375 } 00376 break; 00377 00378 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ 00379 if (LL_RCC_LSE_IsReady()) 00380 { 00381 usart_frequency = LSE_VALUE; 00382 } 00383 break; 00384 00385 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */ 00386 default: 00387 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 00388 break; 00389 } 00390 } 00391 else if (USARTxSource == LL_RCC_USART2_CLKSOURCE) 00392 { 00393 /* USART2CLK clock frequency */ 00394 switch (LL_RCC_GetUSARTClockSource(USARTxSource)) 00395 { 00396 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ 00397 usart_frequency = RCC_GetSystemClockFreq(); 00398 break; 00399 00400 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ 00401 if (LL_RCC_HSI_IsReady()) 00402 { 00403 usart_frequency = HSI_VALUE; 00404 } 00405 break; 00406 00407 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ 00408 if (LL_RCC_LSE_IsReady()) 00409 { 00410 usart_frequency = LSE_VALUE; 00411 } 00412 break; 00413 00414 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ 00415 default: 00416 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 00417 break; 00418 } 00419 } 00420 else 00421 { 00422 #if defined(RCC_CCIPR_USART3SEL) 00423 if (USARTxSource == LL_RCC_USART3_CLKSOURCE) 00424 { 00425 /* USART3CLK clock frequency */ 00426 switch (LL_RCC_GetUSARTClockSource(USARTxSource)) 00427 { 00428 case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */ 00429 usart_frequency = RCC_GetSystemClockFreq(); 00430 break; 00431 00432 case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */ 00433 if (LL_RCC_HSI_IsReady()) 00434 { 00435 usart_frequency = HSI_VALUE; 00436 } 00437 break; 00438 00439 case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */ 00440 if (LL_RCC_LSE_IsReady()) 00441 { 00442 usart_frequency = LSE_VALUE; 00443 } 00444 break; 00445 00446 case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */ 00447 default: 00448 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 00449 break; 00450 } 00451 } 00452 #endif /* RCC_CCIPR_USART3SEL */ 00453 } 00454 return usart_frequency; 00455 } 00456 00457 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL) 00458 /** 00459 * @brief Return UARTx clock frequency 00460 * @param UARTxSource This parameter can be one of the following values: 00461 * @arg @ref LL_RCC_UART4_CLKSOURCE 00462 * @arg @ref LL_RCC_UART5_CLKSOURCE 00463 * @retval UART clock frequency (in Hz) 00464 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready 00465 */ 00466 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) 00467 { 00468 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00469 00470 /* Check parameter */ 00471 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource)); 00472 00473 #if defined(RCC_CCIPR_UART4SEL) 00474 if (UARTxSource == LL_RCC_UART4_CLKSOURCE) 00475 { 00476 /* UART4CLK clock frequency */ 00477 switch (LL_RCC_GetUARTClockSource(UARTxSource)) 00478 { 00479 case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */ 00480 uart_frequency = RCC_GetSystemClockFreq(); 00481 break; 00482 00483 case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */ 00484 if (LL_RCC_HSI_IsReady()) 00485 { 00486 uart_frequency = HSI_VALUE; 00487 } 00488 break; 00489 00490 case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */ 00491 if (LL_RCC_LSE_IsReady()) 00492 { 00493 uart_frequency = LSE_VALUE; 00494 } 00495 break; 00496 00497 case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */ 00498 default: 00499 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 00500 break; 00501 } 00502 } 00503 #endif /* RCC_CCIPR_UART4SEL */ 00504 00505 #if defined(RCC_CCIPR_UART5SEL) 00506 if (UARTxSource == LL_RCC_UART5_CLKSOURCE) 00507 { 00508 /* UART5CLK clock frequency */ 00509 switch (LL_RCC_GetUARTClockSource(UARTxSource)) 00510 { 00511 case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */ 00512 uart_frequency = RCC_GetSystemClockFreq(); 00513 break; 00514 00515 case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */ 00516 if (LL_RCC_HSI_IsReady()) 00517 { 00518 uart_frequency = HSI_VALUE; 00519 } 00520 break; 00521 00522 case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */ 00523 if (LL_RCC_LSE_IsReady()) 00524 { 00525 uart_frequency = LSE_VALUE; 00526 } 00527 break; 00528 00529 case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */ 00530 default: 00531 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 00532 break; 00533 } 00534 } 00535 #endif /* RCC_CCIPR_UART5SEL */ 00536 00537 return uart_frequency; 00538 } 00539 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */ 00540 00541 /** 00542 * @brief Return I2Cx clock frequency 00543 * @param I2CxSource This parameter can be one of the following values: 00544 * @arg @ref LL_RCC_I2C1_CLKSOURCE 00545 * @arg @ref LL_RCC_I2C2_CLKSOURCE (*) 00546 * @arg @ref LL_RCC_I2C3_CLKSOURCE 00547 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*) 00548 * 00549 * (*) value not defined in all devices. 00550 * @retval I2C clock frequency (in Hz) 00551 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready 00552 */ 00553 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) 00554 { 00555 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00556 00557 /* Check parameter */ 00558 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); 00559 00560 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) 00561 { 00562 /* I2C1 CLK clock frequency */ 00563 switch (LL_RCC_GetI2CClockSource(I2CxSource)) 00564 { 00565 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ 00566 i2c_frequency = RCC_GetSystemClockFreq(); 00567 break; 00568 00569 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ 00570 if (LL_RCC_HSI_IsReady()) 00571 { 00572 i2c_frequency = HSI_VALUE; 00573 } 00574 break; 00575 00576 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */ 00577 default: 00578 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 00579 break; 00580 } 00581 } 00582 #if defined(RCC_CCIPR_I2C2SEL) 00583 else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE) 00584 { 00585 /* I2C2 CLK clock frequency */ 00586 switch (LL_RCC_GetI2CClockSource(I2CxSource)) 00587 { 00588 case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */ 00589 i2c_frequency = RCC_GetSystemClockFreq(); 00590 break; 00591 00592 case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */ 00593 if (LL_RCC_HSI_IsReady()) 00594 { 00595 i2c_frequency = HSI_VALUE; 00596 } 00597 break; 00598 00599 case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */ 00600 default: 00601 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 00602 break; 00603 } 00604 } 00605 #endif /*RCC_CCIPR_I2C2SEL*/ 00606 else 00607 { 00608 if (I2CxSource == LL_RCC_I2C3_CLKSOURCE) 00609 { 00610 /* I2C3 CLK clock frequency */ 00611 switch (LL_RCC_GetI2CClockSource(I2CxSource)) 00612 { 00613 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */ 00614 i2c_frequency = RCC_GetSystemClockFreq(); 00615 break; 00616 00617 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ 00618 if (LL_RCC_HSI_IsReady()) 00619 { 00620 i2c_frequency = HSI_VALUE; 00621 } 00622 break; 00623 00624 case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */ 00625 default: 00626 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 00627 break; 00628 } 00629 } 00630 #if defined(RCC_CCIPR2_I2C4SEL) 00631 else 00632 { 00633 if (I2CxSource == LL_RCC_I2C4_CLKSOURCE) 00634 { 00635 /* I2C4 CLK clock frequency */ 00636 switch (LL_RCC_GetI2CClockSource(I2CxSource)) 00637 { 00638 case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */ 00639 i2c_frequency = RCC_GetSystemClockFreq(); 00640 break; 00641 00642 case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */ 00643 if (LL_RCC_HSI_IsReady()) 00644 { 00645 i2c_frequency = HSI_VALUE; 00646 } 00647 break; 00648 00649 case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */ 00650 default: 00651 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 00652 break; 00653 } 00654 } 00655 } 00656 #endif /*RCC_CCIPR2_I2C4SEL*/ 00657 } 00658 00659 return i2c_frequency; 00660 } 00661 00662 00663 /** 00664 * @brief Return LPUARTx clock frequency 00665 * @param LPUARTxSource This parameter can be one of the following values: 00666 * @arg @ref LL_RCC_LPUART1_CLKSOURCE 00667 * @retval LPUART clock frequency (in Hz) 00668 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready 00669 */ 00670 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource) 00671 { 00672 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00673 00674 /* Check parameter */ 00675 assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource)); 00676 00677 /* LPUART1CLK clock frequency */ 00678 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource)) 00679 { 00680 case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */ 00681 lpuart_frequency = RCC_GetSystemClockFreq(); 00682 break; 00683 00684 case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */ 00685 if (LL_RCC_HSI_IsReady()) 00686 { 00687 lpuart_frequency = HSI_VALUE; 00688 } 00689 break; 00690 00691 case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */ 00692 if (LL_RCC_LSE_IsReady()) 00693 { 00694 lpuart_frequency = LSE_VALUE; 00695 } 00696 break; 00697 00698 case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */ 00699 default: 00700 lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 00701 break; 00702 } 00703 00704 return lpuart_frequency; 00705 } 00706 00707 /** 00708 * @brief Return LPTIMx clock frequency 00709 * @param LPTIMxSource This parameter can be one of the following values: 00710 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE 00711 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE 00712 * @retval LPTIM clock frequency (in Hz) 00713 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready 00714 */ 00715 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) 00716 { 00717 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00718 00719 /* Check parameter */ 00720 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource)); 00721 00722 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE) 00723 { 00724 /* LPTIM1CLK clock frequency */ 00725 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) 00726 { 00727 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ 00728 if (LL_RCC_LSI_IsReady()) 00729 { 00730 lptim_frequency = LSI_VALUE; 00731 } 00732 break; 00733 00734 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */ 00735 if (LL_RCC_HSI_IsReady()) 00736 { 00737 lptim_frequency = HSI_VALUE; 00738 } 00739 break; 00740 00741 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ 00742 if (LL_RCC_LSE_IsReady()) 00743 { 00744 lptim_frequency = LSE_VALUE; 00745 } 00746 break; 00747 00748 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */ 00749 default: 00750 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 00751 break; 00752 } 00753 } 00754 else 00755 { 00756 if (LPTIMxSource == LL_RCC_LPTIM2_CLKSOURCE) 00757 { 00758 /* LPTIM2CLK clock frequency */ 00759 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) 00760 { 00761 case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */ 00762 if (LL_RCC_LSI_IsReady()) 00763 { 00764 lptim_frequency = LSI_VALUE; 00765 } 00766 break; 00767 00768 case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */ 00769 if (LL_RCC_HSI_IsReady()) 00770 { 00771 lptim_frequency = HSI_VALUE; 00772 } 00773 break; 00774 00775 case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */ 00776 if (LL_RCC_LSE_IsReady()) 00777 { 00778 lptim_frequency = LSE_VALUE; 00779 } 00780 break; 00781 00782 case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */ 00783 default: 00784 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 00785 break; 00786 } 00787 } 00788 } 00789 00790 return lptim_frequency; 00791 } 00792 00793 /** 00794 * @brief Return SAIx clock frequency 00795 * @param SAIxSource This parameter can be one of the following values: 00796 * @arg @ref LL_RCC_SAI1_CLKSOURCE 00797 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) 00798 * 00799 * (*) value not defined in all devices. 00800 * @retval SAI clock frequency (in Hz) 00801 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready 00802 00803 */ 00804 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) 00805 { 00806 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00807 00808 /* Check parameter */ 00809 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource)); 00810 00811 if (SAIxSource == LL_RCC_SAI1_CLKSOURCE) 00812 { 00813 /* SAI1CLK clock frequency */ 00814 switch (LL_RCC_GetSAIClockSource(SAIxSource)) 00815 { 00816 case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */ 00817 if (LL_RCC_PLLSAI1_IsReady()) 00818 { 00819 sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI(); 00820 } 00821 break; 00822 00823 #if defined(RCC_PLLSAI2_SUPPORT) 00824 case LL_RCC_SAI1_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI1 clock source */ 00825 if (LL_RCC_PLLSAI2_IsReady()) 00826 { 00827 sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI(); 00828 } 00829 break; 00830 00831 #endif /* RCC_PLLSAI2_SUPPORT */ 00832 case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */ 00833 if (LL_RCC_PLL_IsReady()) 00834 { 00835 sai_frequency = RCC_PLL_GetFreqDomain_SAI(); 00836 } 00837 break; 00838 00839 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */ 00840 sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE; 00841 break; 00842 00843 default: 00844 break; 00845 } 00846 } 00847 else 00848 { 00849 #if defined(RCC_CCIPR_SAI2SEL) 00850 if (SAIxSource == LL_RCC_SAI2_CLKSOURCE) 00851 { 00852 /* SAI2CLK clock frequency */ 00853 switch (LL_RCC_GetSAIClockSource(SAIxSource)) 00854 { 00855 case LL_RCC_SAI2_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI2 clock source */ 00856 if (LL_RCC_PLLSAI1_IsReady()) 00857 { 00858 sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI(); 00859 } 00860 break; 00861 00862 #if defined(RCC_PLLSAI2_SUPPORT) 00863 case LL_RCC_SAI2_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI2 clock source */ 00864 if (LL_RCC_PLLSAI2_IsReady()) 00865 { 00866 sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI(); 00867 } 00868 break; 00869 00870 #endif /* RCC_PLLSAI2_SUPPORT */ 00871 case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */ 00872 if (LL_RCC_PLL_IsReady()) 00873 { 00874 sai_frequency = RCC_PLL_GetFreqDomain_SAI(); 00875 } 00876 break; 00877 00878 case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */ 00879 sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE; 00880 break; 00881 00882 default: 00883 break; 00884 } 00885 } 00886 #endif /* RCC_CCIPR_SAI2SEL */ 00887 } 00888 00889 return sai_frequency; 00890 } 00891 00892 #if defined(RCC_CCIPR2_SDMMCSEL) 00893 /** 00894 * @brief Return SDMMCx kernel clock frequency 00895 * @param SDMMCxSource This parameter can be one of the following values: 00896 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE 00897 * @retval SDMMC clock frequency (in Hz) 00898 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready 00899 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected 00900 */ 00901 uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource) 00902 { 00903 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00904 00905 /* Check parameter */ 00906 assert_param(IS_LL_RCC_SDMMC_KERNELCLKSOURCE(SDMMCxSource)); 00907 00908 /* SDMMC1CLK kernel clock frequency */ 00909 switch (LL_RCC_GetSDMMCKernelClockSource(SDMMCxSource)) 00910 { 00911 case LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK: /* 48MHz clock from internal multiplexor used as SDMMC1 clock source */ 00912 sdmmc_frequency = LL_RCC_GetSDMMCClockFreq(LL_RCC_SDMMC1_CLKSOURCE); 00913 break; 00914 00915 case LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP: /* PLL "P" output (PLLSAI3CLK) clock used as SDMMC1 clock source */ 00916 if (LL_RCC_PLL_IsReady()) 00917 { 00918 sdmmc_frequency = RCC_PLL_GetFreqDomain_SAI(); 00919 } 00920 break; 00921 00922 default: 00923 sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA; 00924 break; 00925 } 00926 00927 return sdmmc_frequency; 00928 } 00929 #endif 00930 00931 /** 00932 * @brief Return SDMMCx clock frequency 00933 * @param SDMMCxSource This parameter can be one of the following values: 00934 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE 00935 * @retval SDMMC clock frequency (in Hz) 00936 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready 00937 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected 00938 */ 00939 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) 00940 { 00941 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 00942 00943 /* Check parameter */ 00944 assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource)); 00945 00946 /* SDMMC1CLK clock frequency */ 00947 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource)) 00948 { 00949 #if defined(LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1) 00950 case LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SDMMC1 clock source */ 00951 if (LL_RCC_PLLSAI1_IsReady()) 00952 { 00953 sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M(); 00954 } 00955 break; 00956 #endif 00957 00958 case LL_RCC_SDMMC1_CLKSOURCE_PLL: /* PLL clock used as SDMMC1 clock source */ 00959 if (LL_RCC_PLL_IsReady()) 00960 { 00961 sdmmc_frequency = RCC_PLL_GetFreqDomain_48M(); 00962 } 00963 break; 00964 00965 #if defined(LL_RCC_SDMMC1_CLKSOURCE_MSI) 00966 case LL_RCC_SDMMC1_CLKSOURCE_MSI: /* MSI clock used as SDMMC1 clock source */ 00967 if (LL_RCC_MSI_IsReady()) 00968 { 00969 sdmmc_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 00970 (LL_RCC_MSI_IsEnabledRangeSelect() ? 00971 LL_RCC_MSI_GetRange() : 00972 LL_RCC_MSI_GetRangeAfterStandby())); 00973 } 00974 break; 00975 #endif 00976 00977 #if defined(RCC_HSI48_SUPPORT) 00978 case LL_RCC_SDMMC1_CLKSOURCE_HSI48: /* HSI48 used as SDMMC1 clock source */ 00979 if (LL_RCC_HSI48_IsReady()) 00980 { 00981 sdmmc_frequency = HSI48_VALUE; 00982 } 00983 break; 00984 #else 00985 case LL_RCC_SDMMC1_CLKSOURCE_NONE: /* No clock used as SDMMC1 clock source */ 00986 #endif 00987 default: 00988 sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA; 00989 break; 00990 } 00991 00992 return sdmmc_frequency; 00993 } 00994 00995 /** 00996 * @brief Return RNGx clock frequency 00997 * @param RNGxSource This parameter can be one of the following values: 00998 * @arg @ref LL_RCC_RNG_CLKSOURCE 00999 * @retval RNG clock frequency (in Hz) 01000 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready 01001 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected 01002 */ 01003 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) 01004 { 01005 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 01006 01007 /* Check parameter */ 01008 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource)); 01009 01010 /* RNGCLK clock frequency */ 01011 switch (LL_RCC_GetRNGClockSource(RNGxSource)) 01012 { 01013 case LL_RCC_RNG_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as RNG clock source */ 01014 if (LL_RCC_PLLSAI1_IsReady()) 01015 { 01016 rng_frequency = RCC_PLLSAI1_GetFreqDomain_48M(); 01017 } 01018 break; 01019 01020 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */ 01021 if (LL_RCC_PLL_IsReady()) 01022 { 01023 rng_frequency = RCC_PLL_GetFreqDomain_48M(); 01024 } 01025 break; 01026 01027 case LL_RCC_RNG_CLKSOURCE_MSI: /* MSI clock used as RNG clock source */ 01028 if (LL_RCC_MSI_IsReady()) 01029 { 01030 rng_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01031 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01032 LL_RCC_MSI_GetRange() : 01033 LL_RCC_MSI_GetRangeAfterStandby())); 01034 } 01035 break; 01036 01037 01038 #if defined(RCC_HSI48_SUPPORT) 01039 case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 used as RNG clock source */ 01040 if (LL_RCC_HSI48_IsReady()) 01041 { 01042 rng_frequency = HSI48_VALUE; 01043 } 01044 break; 01045 #else 01046 case LL_RCC_RNG_CLKSOURCE_NONE: /* No clock used as RNG clock source */ 01047 #endif 01048 default: 01049 rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA; 01050 break; 01051 01052 } 01053 01054 return rng_frequency; 01055 } 01056 01057 01058 #if defined(USB_OTG_FS)||defined(USB) 01059 /** 01060 * @brief Return USBx clock frequency 01061 * @param USBxSource This parameter can be one of the following values: 01062 * @arg @ref LL_RCC_USB_CLKSOURCE 01063 * @retval USB clock frequency (in Hz) 01064 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready 01065 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected 01066 */ 01067 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) 01068 { 01069 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 01070 01071 /* Check parameter */ 01072 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); 01073 01074 /* USBCLK clock frequency */ 01075 switch (LL_RCC_GetUSBClockSource(USBxSource)) 01076 { 01077 case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */ 01078 if (LL_RCC_PLLSAI1_IsReady()) 01079 { 01080 usb_frequency = RCC_PLLSAI1_GetFreqDomain_48M(); 01081 } 01082 break; 01083 01084 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ 01085 if (LL_RCC_PLL_IsReady()) 01086 { 01087 usb_frequency = RCC_PLL_GetFreqDomain_48M(); 01088 } 01089 break; 01090 01091 case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */ 01092 if (LL_RCC_MSI_IsReady()) 01093 { 01094 usb_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01095 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01096 LL_RCC_MSI_GetRange() : 01097 LL_RCC_MSI_GetRangeAfterStandby())); 01098 } 01099 break; 01100 01101 #if defined(RCC_HSI48_SUPPORT) 01102 case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 used as USB clock source */ 01103 if (LL_RCC_HSI48_IsReady()) 01104 { 01105 usb_frequency = HSI48_VALUE; 01106 } 01107 break; 01108 #else 01109 case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */ 01110 #endif 01111 default: 01112 usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA; 01113 break; 01114 } 01115 01116 return usb_frequency; 01117 } 01118 #endif /* USB_OTG_FS || USB */ 01119 01120 /** 01121 * @brief Return ADCx clock frequency 01122 * @param ADCxSource This parameter can be one of the following values: 01123 * @arg @ref LL_RCC_ADC_CLKSOURCE 01124 * @retval ADC clock frequency (in Hz) 01125 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready 01126 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected 01127 */ 01128 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) 01129 { 01130 uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 01131 01132 /* Check parameter */ 01133 assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource)); 01134 01135 /* ADCCLK clock frequency */ 01136 switch (LL_RCC_GetADCClockSource(ADCxSource)) 01137 { 01138 case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */ 01139 if (LL_RCC_PLLSAI1_IsReady()) 01140 { 01141 adc_frequency = RCC_PLLSAI1_GetFreqDomain_ADC(); 01142 } 01143 break; 01144 01145 #if defined(RCC_PLLSAI2_SUPPORT) && defined(LL_RCC_ADC_CLKSOURCE_PLLSAI2) 01146 case LL_RCC_ADC_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as ADC clock source */ 01147 if (LL_RCC_PLLSAI2_IsReady()) 01148 { 01149 adc_frequency = RCC_PLLSAI2_GetFreqDomain_ADC(); 01150 } 01151 break; 01152 #endif /* RCC_PLLSAI2_SUPPORT && LL_RCC_ADC_CLKSOURCE_PLLSAI2 */ 01153 01154 case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */ 01155 adc_frequency = RCC_GetSystemClockFreq(); 01156 break; 01157 case LL_RCC_ADC_CLKSOURCE_NONE: /* No clock used as ADC clock source */ 01158 default: 01159 adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA; 01160 break; 01161 } 01162 01163 return adc_frequency; 01164 } 01165 01166 #if defined(SWPMI1) 01167 /** 01168 * @brief Return SWPMIx clock frequency 01169 * @param SWPMIxSource This parameter can be one of the following values: 01170 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE 01171 * @retval SWPMI clock frequency (in Hz) 01172 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) is not ready 01173 */ 01174 uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource) 01175 { 01176 uint32_t swpmi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 01177 01178 /* Check parameter */ 01179 assert_param(IS_LL_RCC_SWPMI_CLKSOURCE(SWPMIxSource)); 01180 01181 /* SWPMI1CLK clock frequency */ 01182 switch (LL_RCC_GetSWPMIClockSource(SWPMIxSource)) 01183 { 01184 case LL_RCC_SWPMI1_CLKSOURCE_HSI: /* SWPMI1 Clock is HSI Osc. */ 01185 if (LL_RCC_HSI_IsReady()) 01186 { 01187 swpmi_frequency = HSI_VALUE; 01188 } 01189 break; 01190 01191 case LL_RCC_SWPMI1_CLKSOURCE_PCLK1: /* SWPMI1 Clock is PCLK1 */ 01192 default: 01193 swpmi_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 01194 break; 01195 } 01196 01197 return swpmi_frequency; 01198 } 01199 #endif /* SWPMI1 */ 01200 01201 #if defined(DFSDM1_Channel0) 01202 /** 01203 * @brief Return DFSDMx clock frequency 01204 * @param DFSDMxSource This parameter can be one of the following values: 01205 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE 01206 * @retval DFSDM clock frequency (in Hz) 01207 */ 01208 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource) 01209 { 01210 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 01211 01212 /* Check parameter */ 01213 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource)); 01214 01215 /* DFSDM1CLK clock frequency */ 01216 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource)) 01217 { 01218 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */ 01219 dfsdm_frequency = RCC_GetSystemClockFreq(); 01220 break; 01221 01222 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */ 01223 default: 01224 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); 01225 break; 01226 } 01227 01228 return dfsdm_frequency; 01229 } 01230 01231 #if defined(RCC_CCIPR2_DFSDM1SEL) 01232 /** 01233 * @brief Return DFSDMx Audio clock frequency 01234 * @param DFSDMxSource This parameter can be one of the following values: 01235 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE 01236 * @retval DFSDM clock frequency (in Hz) 01237 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready 01238 */ 01239 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource) 01240 { 01241 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 01242 01243 /* Check parameter */ 01244 assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource)); 01245 01246 /* DFSDM1CLK clock frequency */ 01247 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource)) 01248 { 01249 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1: /* SAI1 clock used as DFSDM1 audio clock */ 01250 dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE); 01251 break; 01252 01253 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI: /* MSI clock used as DFSDM1 audio clock */ 01254 if (LL_RCC_MSI_IsReady()) 01255 { 01256 dfsdm_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01257 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01258 LL_RCC_MSI_GetRange() : 01259 LL_RCC_MSI_GetRangeAfterStandby())); 01260 } 01261 break; 01262 01263 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI: /* HSI clock used as DFSDM1 audio clock */ 01264 default: 01265 if (LL_RCC_HSI_IsReady()) 01266 { 01267 dfsdm_frequency = HSI_VALUE; 01268 } 01269 break; 01270 } 01271 01272 return dfsdm_frequency; 01273 } 01274 #endif /* RCC_CCIPR2_DFSDM1SEL */ 01275 #endif /* DFSDM1_Channel0 */ 01276 01277 #if defined(DSI) 01278 /** 01279 * @brief Return DSI clock frequency 01280 * @param DSIxSource This parameter can be one of the following values: 01281 * @arg @ref LL_RCC_DSI_CLKSOURCE 01282 * @retval DSI clock frequency (in Hz) 01283 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready 01284 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used 01285 */ 01286 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource) 01287 { 01288 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 01289 01290 /* Check parameter */ 01291 assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource)); 01292 01293 /* DSICLK clock frequency */ 01294 switch (LL_RCC_GetDSIClockSource(DSIxSource)) 01295 { 01296 case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLLSAI2 Osc. */ 01297 if (LL_RCC_PLLSAI2_IsReady()) 01298 { 01299 dsi_frequency = RCC_PLLSAI2_GetFreqDomain_DSI(); 01300 } 01301 break; 01302 01303 case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */ 01304 default: 01305 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA; 01306 break; 01307 } 01308 01309 return dsi_frequency; 01310 } 01311 #endif /* DSI */ 01312 01313 #if defined(LTDC) 01314 /** 01315 * @brief Return LTDC clock frequency 01316 * @param LTDCxSource This parameter can be one of the following values: 01317 * @arg @ref LL_RCC_LTDC_CLKSOURCE 01318 * @retval LTDC clock frequency (in Hz) 01319 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready 01320 */ 01321 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource) 01322 { 01323 uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 01324 01325 /* Check parameter */ 01326 assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource)); 01327 01328 if (LL_RCC_PLLSAI2_IsReady()) 01329 { 01330 ltdc_frequency = RCC_PLLSAI2_GetFreqDomain_LTDC(); 01331 } 01332 01333 return ltdc_frequency; 01334 } 01335 #endif /* LTDC */ 01336 01337 #if defined(OCTOSPI1) 01338 /** 01339 * @brief Return OCTOSPI clock frequency 01340 * @param OCTOSPIxSource This parameter can be one of the following values: 01341 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE 01342 * @retval OCTOSPI clock frequency (in Hz) 01343 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready 01344 */ 01345 uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource) 01346 { 01347 uint32_t octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 01348 01349 /* Check parameter */ 01350 assert_param(IS_LL_RCC_OCTOSPI_CLKSOURCE(OCTOSPIxSource)); 01351 01352 /* OCTOSPI clock frequency */ 01353 switch (LL_RCC_GetOCTOSPIClockSource(OCTOSPIxSource)) 01354 { 01355 case LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK: /* OCTOSPI clock is SYSCLK */ 01356 octospi_frequency = RCC_GetSystemClockFreq(); 01357 break; 01358 01359 case LL_RCC_OCTOSPI_CLKSOURCE_MSI: /* MSI clock used as OCTOSPI clock */ 01360 if (LL_RCC_MSI_IsReady()) 01361 { 01362 octospi_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01363 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01364 LL_RCC_MSI_GetRange() : 01365 LL_RCC_MSI_GetRangeAfterStandby())); 01366 } 01367 break; 01368 01369 case LL_RCC_OCTOSPI_CLKSOURCE_PLL: /* PLL clock used as OCTOSPI source */ 01370 if (LL_RCC_PLL_IsReady()) 01371 { 01372 octospi_frequency = RCC_PLL_GetFreqDomain_48M(); 01373 } 01374 break; 01375 01376 default: 01377 octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; 01378 break; 01379 } 01380 01381 return octospi_frequency; 01382 } 01383 #endif /* OCTOSPI1 */ 01384 01385 /** 01386 * @} 01387 */ 01388 01389 /** 01390 * @} 01391 */ 01392 01393 /** @addtogroup RCC_LL_Private_Functions 01394 * @{ 01395 */ 01396 01397 /** 01398 * @brief Return SYSTEM clock frequency 01399 * @retval SYSTEM clock frequency (in Hz) 01400 */ 01401 uint32_t RCC_GetSystemClockFreq(void) 01402 { 01403 uint32_t frequency = 0U; 01404 01405 /* Get SYSCLK source -------------------------------------------------------*/ 01406 switch (LL_RCC_GetSysClkSource()) 01407 { 01408 case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ 01409 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01410 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01411 LL_RCC_MSI_GetRange() : 01412 LL_RCC_MSI_GetRangeAfterStandby())); 01413 break; 01414 01415 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ 01416 frequency = HSI_VALUE; 01417 break; 01418 01419 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ 01420 frequency = HSE_VALUE; 01421 break; 01422 01423 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ 01424 frequency = RCC_PLL_GetFreqDomain_SYS(); 01425 break; 01426 01427 default: 01428 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01429 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01430 LL_RCC_MSI_GetRange() : 01431 LL_RCC_MSI_GetRangeAfterStandby())); 01432 break; 01433 } 01434 01435 return frequency; 01436 } 01437 01438 /** 01439 * @brief Return HCLK clock frequency 01440 * @param SYSCLK_Frequency SYSCLK clock frequency 01441 * @retval HCLK clock frequency (in Hz) 01442 */ 01443 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) 01444 { 01445 /* HCLK clock frequency */ 01446 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); 01447 } 01448 01449 /** 01450 * @brief Return PCLK1 clock frequency 01451 * @param HCLK_Frequency HCLK clock frequency 01452 * @retval PCLK1 clock frequency (in Hz) 01453 */ 01454 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) 01455 { 01456 /* PCLK1 clock frequency */ 01457 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); 01458 } 01459 01460 /** 01461 * @brief Return PCLK2 clock frequency 01462 * @param HCLK_Frequency HCLK clock frequency 01463 * @retval PCLK2 clock frequency (in Hz) 01464 */ 01465 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) 01466 { 01467 /* PCLK2 clock frequency */ 01468 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); 01469 } 01470 01471 /** 01472 * @brief Return PLL clock frequency used for system domain 01473 * @retval PLL clock frequency (in Hz) 01474 */ 01475 uint32_t RCC_PLL_GetFreqDomain_SYS(void) 01476 { 01477 uint32_t pllinputfreq = 0U, pllsource = 0U; 01478 01479 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN 01480 SYSCLK = PLL_VCO / PLLR 01481 */ 01482 pllsource = LL_RCC_PLL_GetMainSource(); 01483 01484 switch (pllsource) 01485 { 01486 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ 01487 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01488 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01489 LL_RCC_MSI_GetRange() : 01490 LL_RCC_MSI_GetRangeAfterStandby())); 01491 break; 01492 01493 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ 01494 pllinputfreq = HSI_VALUE; 01495 break; 01496 01497 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ 01498 pllinputfreq = HSE_VALUE; 01499 break; 01500 01501 default: 01502 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01503 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01504 LL_RCC_MSI_GetRange() : 01505 LL_RCC_MSI_GetRangeAfterStandby())); 01506 break; 01507 } 01508 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), 01509 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); 01510 } 01511 /** 01512 * @brief Return PLL clock frequency used for SAI domain 01513 * @retval PLL clock frequency (in Hz) 01514 */ 01515 uint32_t RCC_PLL_GetFreqDomain_SAI(void) 01516 { 01517 uint32_t pllinputfreq = 0U, pllsource = 0U; 01518 01519 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE / PLLM) * PLLN 01520 SAI Domain clock = PLL_VCO / PLLP 01521 */ 01522 pllsource = LL_RCC_PLL_GetMainSource(); 01523 01524 switch (pllsource) 01525 { 01526 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ 01527 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01528 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01529 LL_RCC_MSI_GetRange() : 01530 LL_RCC_MSI_GetRangeAfterStandby())); 01531 break; 01532 01533 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ 01534 pllinputfreq = HSI_VALUE; 01535 break; 01536 01537 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ 01538 pllinputfreq = HSE_VALUE; 01539 break; 01540 01541 default: 01542 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01543 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01544 LL_RCC_MSI_GetRange() : 01545 LL_RCC_MSI_GetRangeAfterStandby())); 01546 break; 01547 } 01548 return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), 01549 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); 01550 } 01551 01552 /** 01553 * @brief Return PLL clock frequency used for 48 MHz domain 01554 * @retval PLL clock frequency (in Hz) 01555 */ 01556 uint32_t RCC_PLL_GetFreqDomain_48M(void) 01557 { 01558 uint32_t pllinputfreq = 0U, pllsource = 0U; 01559 01560 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN 01561 48M Domain clock = PLL_VCO / PLLQ 01562 */ 01563 pllsource = LL_RCC_PLL_GetMainSource(); 01564 01565 switch (pllsource) 01566 { 01567 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ 01568 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01569 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01570 LL_RCC_MSI_GetRange() : 01571 LL_RCC_MSI_GetRangeAfterStandby())); 01572 break; 01573 01574 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ 01575 pllinputfreq = HSI_VALUE; 01576 break; 01577 01578 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ 01579 pllinputfreq = HSE_VALUE; 01580 break; 01581 01582 default: 01583 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01584 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01585 LL_RCC_MSI_GetRange() : 01586 LL_RCC_MSI_GetRangeAfterStandby())); 01587 break; 01588 } 01589 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), 01590 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); 01591 } 01592 #if defined(DSI) 01593 /** 01594 * @brief Return PLL clock frequency used for DSI clock 01595 * @retval PLL clock frequency (in Hz) 01596 */ 01597 uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void) 01598 { 01599 uint32_t pllinputfreq = 0U, pllsource = 0U; 01600 01601 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */ 01602 /* DSICLK = PLLSAI2_VCO / PLLSAI2R */ 01603 pllsource = LL_RCC_PLL_GetMainSource(); 01604 01605 switch (pllsource) 01606 { 01607 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */ 01608 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01609 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01610 LL_RCC_MSI_GetRange() : 01611 LL_RCC_MSI_GetRangeAfterStandby())); 01612 break; 01613 01614 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */ 01615 pllinputfreq = HSI_VALUE; 01616 break; 01617 01618 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */ 01619 pllinputfreq = HSE_VALUE; 01620 break; 01621 01622 default: 01623 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01624 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01625 LL_RCC_MSI_GetRange() : 01626 LL_RCC_MSI_GetRangeAfterStandby())); 01627 break; 01628 } 01629 01630 return __LL_RCC_CALC_PLLSAI2_DSI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(), 01631 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR()); 01632 } 01633 #endif /* DSI */ 01634 01635 /** 01636 * @brief Return PLLSAI1 clock frequency used for SAI domain 01637 * @retval PLLSAI1 clock frequency (in Hz) 01638 */ 01639 uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void) 01640 { 01641 uint32_t pllinputfreq = 0U, pllsource = 0U; 01642 01643 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 01644 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */ 01645 #else 01646 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */ 01647 #endif 01648 /* SAI Domain clock = PLLSAI1_VCO / PLLSAI1P */ 01649 pllsource = LL_RCC_PLL_GetMainSource(); 01650 01651 switch (pllsource) 01652 { 01653 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */ 01654 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01655 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01656 LL_RCC_MSI_GetRange() : 01657 LL_RCC_MSI_GetRangeAfterStandby())); 01658 break; 01659 01660 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */ 01661 pllinputfreq = HSI_VALUE; 01662 break; 01663 01664 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */ 01665 pllinputfreq = HSE_VALUE; 01666 break; 01667 01668 default: 01669 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01670 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01671 LL_RCC_MSI_GetRange() : 01672 LL_RCC_MSI_GetRangeAfterStandby())); 01673 break; 01674 } 01675 return __LL_RCC_CALC_PLLSAI1_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), 01676 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetP()); 01677 } 01678 01679 /** 01680 * @brief Return PLLSAI1 clock frequency used for 48Mhz domain 01681 * @retval PLLSAI1 clock frequency (in Hz) 01682 */ 01683 uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void) 01684 { 01685 uint32_t pllinputfreq = 0U, pllsource = 0U; 01686 01687 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 01688 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */ 01689 #else 01690 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */ 01691 #endif 01692 /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1Q */ 01693 pllsource = LL_RCC_PLL_GetMainSource(); 01694 01695 switch (pllsource) 01696 { 01697 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */ 01698 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01699 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01700 LL_RCC_MSI_GetRange() : 01701 LL_RCC_MSI_GetRangeAfterStandby())); 01702 break; 01703 01704 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */ 01705 pllinputfreq = HSI_VALUE; 01706 break; 01707 01708 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */ 01709 pllinputfreq = HSE_VALUE; 01710 break; 01711 01712 default: 01713 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01714 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01715 LL_RCC_MSI_GetRange() : 01716 LL_RCC_MSI_GetRangeAfterStandby())); 01717 break; 01718 } 01719 return __LL_RCC_CALC_PLLSAI1_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), 01720 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ()); 01721 } 01722 01723 /** 01724 * @brief Return PLLSAI1 clock frequency used for ADC domain 01725 * @retval PLLSAI1 clock frequency (in Hz) 01726 */ 01727 uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) 01728 { 01729 uint32_t pllinputfreq = 0U, pllsource = 0U; 01730 01731 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 01732 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */ 01733 #else 01734 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */ 01735 #endif 01736 /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1R */ 01737 pllsource = LL_RCC_PLL_GetMainSource(); 01738 01739 switch (pllsource) 01740 { 01741 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */ 01742 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01743 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01744 LL_RCC_MSI_GetRange() : 01745 LL_RCC_MSI_GetRangeAfterStandby())); 01746 break; 01747 01748 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */ 01749 pllinputfreq = HSI_VALUE; 01750 break; 01751 01752 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */ 01753 pllinputfreq = HSE_VALUE; 01754 break; 01755 01756 default: 01757 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01758 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01759 LL_RCC_MSI_GetRange() : 01760 LL_RCC_MSI_GetRangeAfterStandby())); 01761 break; 01762 } 01763 return __LL_RCC_CALC_PLLSAI1_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), 01764 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR()); 01765 } 01766 01767 #if defined(RCC_PLLSAI2_SUPPORT) 01768 /** 01769 * @brief Return PLLSAI2 clock frequency used for SAI domain 01770 * @retval PLLSAI2 clock frequency (in Hz) 01771 */ 01772 uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void) 01773 { 01774 uint32_t pllinputfreq = 0U, pllsource = 0U; 01775 01776 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 01777 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */ 01778 #else 01779 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */ 01780 #endif 01781 /* SAI Domain clock = PLLSAI2_VCO / PLLSAI2P */ 01782 pllsource = LL_RCC_PLL_GetMainSource(); 01783 01784 switch (pllsource) 01785 { 01786 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */ 01787 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01788 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01789 LL_RCC_MSI_GetRange() : 01790 LL_RCC_MSI_GetRangeAfterStandby())); 01791 break; 01792 01793 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */ 01794 pllinputfreq = HSI_VALUE; 01795 break; 01796 01797 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */ 01798 pllinputfreq = HSE_VALUE; 01799 break; 01800 01801 default: 01802 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01803 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01804 LL_RCC_MSI_GetRange() : 01805 LL_RCC_MSI_GetRangeAfterStandby())); 01806 break; 01807 } 01808 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) 01809 return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(), 01810 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP()); 01811 #else 01812 return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), 01813 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP()); 01814 #endif 01815 } 01816 01817 #if defined(LTDC) 01818 /** 01819 * @brief Return PLLSAI2 clock frequency used for LTDC domain 01820 * @retval PLLSAI2 clock frequency (in Hz) 01821 */ 01822 uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void) 01823 { 01824 uint32_t pllinputfreq = 0U, pllsource = 0U; 01825 01826 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */ 01827 /* LTDC Domain clock = (PLLSAI2_VCO / PLLSAI2R) / PLLSAI2DIVR */ 01828 pllsource = LL_RCC_PLL_GetMainSource(); 01829 01830 switch (pllsource) 01831 { 01832 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */ 01833 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01834 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01835 LL_RCC_MSI_GetRange() : 01836 LL_RCC_MSI_GetRangeAfterStandby())); 01837 break; 01838 01839 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */ 01840 pllinputfreq = HSI_VALUE; 01841 break; 01842 01843 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */ 01844 pllinputfreq = HSE_VALUE; 01845 break; 01846 01847 default: 01848 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01849 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01850 LL_RCC_MSI_GetRange() : 01851 LL_RCC_MSI_GetRangeAfterStandby())); 01852 break; 01853 } 01854 01855 return __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(), 01856 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR(), LL_RCC_PLLSAI2_GetDIVR()); 01857 } 01858 01859 #else 01860 01861 /** 01862 * @brief Return PLLSAI2 clock frequency used for ADC domain 01863 * @retval PLLSAI2 clock frequency (in Hz) 01864 */ 01865 uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void) 01866 { 01867 uint32_t pllinputfreq = 0U, pllsource = 0U; 01868 01869 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */ 01870 /* 48M Domain clock = PLLSAI2_VCO / PLLSAI2R */ 01871 pllsource = LL_RCC_PLL_GetMainSource(); 01872 01873 switch (pllsource) 01874 { 01875 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */ 01876 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01877 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01878 LL_RCC_MSI_GetRange() : 01879 LL_RCC_MSI_GetRangeAfterStandby())); 01880 break; 01881 01882 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */ 01883 pllinputfreq = HSI_VALUE; 01884 break; 01885 01886 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */ 01887 pllinputfreq = HSE_VALUE; 01888 break; 01889 01890 default: 01891 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), 01892 (LL_RCC_MSI_IsEnabledRangeSelect() ? 01893 LL_RCC_MSI_GetRange() : 01894 LL_RCC_MSI_GetRangeAfterStandby())); 01895 break; 01896 } 01897 return __LL_RCC_CALC_PLLSAI2_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), 01898 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR()); 01899 } 01900 #endif /* LTDC */ 01901 01902 #endif /*RCC_PLLSAI2_SUPPORT*/ 01903 01904 /** 01905 * @} 01906 */ 01907 01908 /** 01909 * @} 01910 */ 01911 01912 #endif /* defined(RCC) */ 01913 01914 /** 01915 * @} 01916 */ 01917 01918 #endif /* USE_FULL_LL_DRIVER */ 01919 01920 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/