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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_flash.h 00004 * @author MCD Application Team 00005 * @brief Header file of FLASH HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_HAL_FLASH_H 00038 #define __STM32L4xx_HAL_FLASH_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx_hal_def.h" 00046 00047 /** @addtogroup STM32L4xx_HAL_Driver 00048 * @{ 00049 */ 00050 00051 /** @addtogroup FLASH 00052 * @{ 00053 */ 00054 00055 /* Exported types ------------------------------------------------------------*/ 00056 /** @defgroup FLASH_Exported_Types FLASH Exported Types 00057 * @{ 00058 */ 00059 00060 /** 00061 * @brief FLASH Erase structure definition 00062 */ 00063 typedef struct 00064 { 00065 uint32_t TypeErase; /*!< Mass erase or page erase. 00066 This parameter can be a value of @ref FLASH_Type_Erase */ 00067 uint32_t Banks; /*!< Select bank to erase. 00068 This parameter must be a value of @ref FLASH_Banks 00069 (FLASH_BANK_BOTH should be used only for mass erase) */ 00070 uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled 00071 This parameter must be a value between 0 and (max number of pages in the bank - 1) 00072 (eg : 255 for 1MB dual bank) */ 00073 uint32_t NbPages; /*!< Number of pages to be erased. 00074 This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ 00075 } FLASH_EraseInitTypeDef; 00076 00077 /** 00078 * @brief FLASH Option Bytes Program structure definition 00079 */ 00080 typedef struct 00081 { 00082 uint32_t OptionType; /*!< Option byte to be configured. 00083 This parameter can be a combination of the values of @ref FLASH_OB_Type */ 00084 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). 00085 Only one WRP area could be programmed at the same time. 00086 This parameter can be value of @ref FLASH_OB_WRP_Area */ 00087 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). 00088 This parameter must be a value between 0 and (max number of pages in the bank - 1) 00089 (eg : 25 for 1MB dual bank) */ 00090 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). 00091 This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */ 00092 uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP). 00093 This parameter can be a value of @ref FLASH_OB_Read_Protection */ 00094 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). 00095 This parameter can be a combination of @ref FLASH_OB_USER_Type */ 00096 uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). 00097 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, 00098 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, 00099 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, 00100 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, 00101 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2, 00102 @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1, 00103 @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */ 00104 uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). 00105 This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) 00106 and @ref FLASH_OB_PCROP_RDP */ 00107 uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). 00108 This parameter must be a value between begin and end of bank 00109 => Be careful of the bank swapping for the address */ 00110 uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). 00111 This parameter must be a value between PCROP Start address and end of bank */ 00112 } FLASH_OBProgramInitTypeDef; 00113 00114 /** 00115 * @brief FLASH Procedure structure definition 00116 */ 00117 typedef enum 00118 { 00119 FLASH_PROC_NONE = 0, 00120 FLASH_PROC_PAGE_ERASE, 00121 FLASH_PROC_MASS_ERASE, 00122 FLASH_PROC_PROGRAM, 00123 FLASH_PROC_PROGRAM_LAST 00124 } FLASH_ProcedureTypeDef; 00125 00126 /** 00127 * @brief FLASH Cache structure definition 00128 */ 00129 typedef enum 00130 { 00131 FLASH_CACHE_DISABLED = 0, 00132 FLASH_CACHE_ICACHE_ENABLED, 00133 FLASH_CACHE_DCACHE_ENABLED, 00134 FLASH_CACHE_ICACHE_DCACHE_ENABLED 00135 } FLASH_CacheTypeDef; 00136 00137 /** 00138 * @brief FLASH handle Structure definition 00139 */ 00140 typedef struct 00141 { 00142 HAL_LockTypeDef Lock; /* FLASH locking object */ 00143 __IO uint32_t ErrorCode; /* FLASH error code */ 00144 __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ 00145 __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */ 00146 __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */ 00147 __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ 00148 __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ 00149 __IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */ 00150 }FLASH_ProcessTypeDef; 00151 00152 /** 00153 * @} 00154 */ 00155 00156 /* Exported constants --------------------------------------------------------*/ 00157 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 00158 * @{ 00159 */ 00160 00161 /** @defgroup FLASH_Error FLASH Error 00162 * @{ 00163 */ 00164 #define HAL_FLASH_ERROR_NONE 0x00000000U 00165 #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR 00166 #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR 00167 #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR 00168 #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR 00169 #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR 00170 #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR 00171 #define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR 00172 #define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR 00173 #define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR 00174 #define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR 00175 #define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD 00176 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ 00177 defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00178 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00179 #define HAL_FLASH_ERROR_PEMPTY FLASH_FLAG_PEMPTY 00180 #endif 00181 /** 00182 * @} 00183 */ 00184 00185 /** @defgroup FLASH_Type_Erase FLASH Erase Type 00186 * @{ 00187 */ 00188 #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/ 00189 #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!<Flash mass erase activation*/ 00190 /** 00191 * @} 00192 */ 00193 00194 /** @defgroup FLASH_Banks FLASH Banks 00195 * @{ 00196 */ 00197 #define FLASH_BANK_1 ((uint32_t)0x01) /*!< Bank 1 */ 00198 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00199 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00200 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00201 #define FLASH_BANK_2 ((uint32_t)0x02) /*!< Bank 2 */ 00202 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */ 00203 #else 00204 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1)) /*!< Bank 1 */ 00205 #endif 00206 /** 00207 * @} 00208 */ 00209 00210 00211 /** @defgroup FLASH_Type_Program FLASH Program Type 00212 * @{ 00213 */ 00214 #define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x00) /*!<Program a double-word (64-bit) at a specified address.*/ 00215 #define FLASH_TYPEPROGRAM_FAST ((uint32_t)0x01) /*!<Fast program a 32 row double-word (64-bit) at a specified address. 00216 And another 32 row double-word (64-bit) will be programmed */ 00217 #define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02) /*!<Fast program a 32 row double-word (64-bit) at a specified address. 00218 And this is the last 32 row double-word (64-bit) programmed */ 00219 /** 00220 * @} 00221 */ 00222 00223 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type 00224 * @{ 00225 */ 00226 #define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */ 00227 #define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */ 00228 #define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */ 00229 #define OPTIONBYTE_PCROP ((uint32_t)0x08) /*!< PCROP option byte configuration */ 00230 /** 00231 * @} 00232 */ 00233 00234 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area 00235 * @{ 00236 */ 00237 #define OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00) /*!< Flash Bank 1 Area A */ 00238 #define OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01) /*!< Flash Bank 1 Area B */ 00239 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00240 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00241 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00242 #define OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02) /*!< Flash Bank 2 Area A */ 00243 #define OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04) /*!< Flash Bank 2 Area B */ 00244 #endif 00245 /** 00246 * @} 00247 */ 00248 00249 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection 00250 * @{ 00251 */ 00252 #define OB_RDP_LEVEL_0 ((uint32_t)0xAA) 00253 #define OB_RDP_LEVEL_1 ((uint32_t)0xBB) 00254 #define OB_RDP_LEVEL_2 ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2 00255 it's no more possible to go back to level 1 or 0 */ 00256 /** 00257 * @} 00258 */ 00259 00260 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type 00261 * @{ 00262 */ 00263 #define OB_USER_BOR_LEV ((uint32_t)0x0001) /*!< BOR reset Level */ 00264 #define OB_USER_nRST_STOP ((uint32_t)0x0002) /*!< Reset generated when entering the stop mode */ 00265 #define OB_USER_nRST_STDBY ((uint32_t)0x0004) /*!< Reset generated when entering the standby mode */ 00266 #define OB_USER_IWDG_SW ((uint32_t)0x0008) /*!< Independent watchdog selection */ 00267 #define OB_USER_IWDG_STOP ((uint32_t)0x0010) /*!< Independent watchdog counter freeze in stop mode */ 00268 #define OB_USER_IWDG_STDBY ((uint32_t)0x0020) /*!< Independent watchdog counter freeze in standby mode */ 00269 #define OB_USER_WWDG_SW ((uint32_t)0x0040) /*!< Window watchdog selection */ 00270 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00271 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00272 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00273 #define OB_USER_BFB2 ((uint32_t)0x0080) /*!< Dual-bank boot */ 00274 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00275 #define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 1MB or 512kB Flash memory devices */ 00276 #else 00277 #define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 512KB or 256KB Flash memory devices */ 00278 #endif 00279 #endif 00280 #define OB_USER_nBOOT1 ((uint32_t)0x0200) /*!< Boot configuration */ 00281 #define OB_USER_SRAM2_PE ((uint32_t)0x0400) /*!< SRAM2 parity check enable */ 00282 #define OB_USER_SRAM2_RST ((uint32_t)0x0800) /*!< SRAM2 Erase when system reset */ 00283 #define OB_USER_nRST_SHDW ((uint32_t)0x1000) /*!< Reset generated when entering the shutdown mode */ 00284 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ 00285 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 00286 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00287 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00288 #define OB_USER_nSWBOOT0 ((uint32_t)0x2000) /*!< Software BOOT0 */ 00289 #define OB_USER_nBOOT0 ((uint32_t)0x4000) /*!< nBOOT0 option bit */ 00290 #endif 00291 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00292 #define OB_USER_DBANK ((uint32_t)0x8000) /*!< Single bank with 128-bits data or two banks with 64-bits data */ 00293 #endif 00294 /** 00295 * @} 00296 */ 00297 00298 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level 00299 * @{ 00300 */ 00301 #define OB_BOR_LEVEL_0 ((uint32_t)FLASH_OPTR_BOR_LEV_0) /*!< Reset level threshold is around 1.7V */ 00302 #define OB_BOR_LEVEL_1 ((uint32_t)FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.0V */ 00303 #define OB_BOR_LEVEL_2 ((uint32_t)FLASH_OPTR_BOR_LEV_2) /*!< Reset level threshold is around 2.2V */ 00304 #define OB_BOR_LEVEL_3 ((uint32_t)FLASH_OPTR_BOR_LEV_3) /*!< Reset level threshold is around 2.5V */ 00305 #define OB_BOR_LEVEL_4 ((uint32_t)FLASH_OPTR_BOR_LEV_4) /*!< Reset level threshold is around 2.8V */ 00306 /** 00307 * @} 00308 */ 00309 00310 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 00311 * @{ 00312 */ 00313 #define OB_STOP_RST ((uint32_t)0x0000) /*!< Reset generated when entering the stop mode */ 00314 #define OB_STOP_NORST ((uint32_t)FLASH_OPTR_nRST_STOP) /*!< No reset generated when entering the stop mode */ 00315 /** 00316 * @} 00317 */ 00318 00319 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby 00320 * @{ 00321 */ 00322 #define OB_STANDBY_RST ((uint32_t)0x0000) /*!< Reset generated when entering the standby mode */ 00323 #define OB_STANDBY_NORST ((uint32_t)FLASH_OPTR_nRST_STDBY) /*!< No reset generated when entering the standby mode */ 00324 /** 00325 * @} 00326 */ 00327 00328 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown 00329 * @{ 00330 */ 00331 #define OB_SHUTDOWN_RST ((uint32_t)0x0000) /*!< Reset generated when entering the shutdown mode */ 00332 #define OB_SHUTDOWN_NORST ((uint32_t)FLASH_OPTR_nRST_SHDW) /*!< No reset generated when entering the shutdown mode */ 00333 /** 00334 * @} 00335 */ 00336 00337 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type 00338 * @{ 00339 */ 00340 #define OB_IWDG_HW ((uint32_t)0x00000) /*!< Hardware independent watchdog */ 00341 #define OB_IWDG_SW ((uint32_t)FLASH_OPTR_IWDG_SW) /*!< Software independent watchdog */ 00342 /** 00343 * @} 00344 */ 00345 00346 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop 00347 * @{ 00348 */ 00349 #define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Stop mode */ 00350 #define OB_IWDG_STOP_RUN ((uint32_t)FLASH_OPTR_IWDG_STOP) /*!< Independent watchdog counter is running in Stop mode */ 00351 /** 00352 * @} 00353 */ 00354 00355 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby 00356 * @{ 00357 */ 00358 #define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Standby mode */ 00359 #define OB_IWDG_STDBY_RUN ((uint32_t)FLASH_OPTR_IWDG_STDBY) /*!< Independent watchdog counter is running in Standby mode */ 00360 /** 00361 * @} 00362 */ 00363 00364 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type 00365 * @{ 00366 */ 00367 #define OB_WWDG_HW ((uint32_t)0x00000) /*!< Hardware window watchdog */ 00368 #define OB_WWDG_SW ((uint32_t)FLASH_OPTR_WWDG_SW) /*!< Software window watchdog */ 00369 /** 00370 * @} 00371 */ 00372 00373 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00374 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00375 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00376 /** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode 00377 * @{ 00378 */ 00379 #define OB_BFB2_DISABLE ((uint32_t)0x000000) /*!< Dual-bank boot disable */ 00380 #define OB_BFB2_ENABLE ((uint32_t)FLASH_OPTR_BFB2) /*!< Dual-bank boot enable */ 00381 /** 00382 * @} 00383 */ 00384 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00385 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type 00386 * @{ 00387 */ 00388 #define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /*!< 1 MB/512 kB Single-bank Flash */ 00389 #define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DB1M) /*!< 1 MB/512 kB Dual-bank Flash */ 00390 /** 00391 * @} 00392 */ 00393 #else 00394 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type 00395 * @{ 00396 */ 00397 #define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /*!< 256 KB/512 KB Single-bank Flash */ 00398 #define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DUALBANK) /*!< 256 KB/512 KB Dual-bank Flash */ 00399 /** 00400 * @} 00401 */ 00402 #endif 00403 #endif 00404 00405 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00406 /** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type 00407 * @{ 00408 */ 00409 #define OB_DBANK_128_BITS ((uint32_t)0x000000) /*!< Single-bank with 128-bits data */ 00410 #define OB_DBANK_64_BITS ((uint32_t)FLASH_OPTR_DBANK) /*!< Dual-bank with 64-bits data */ 00411 #endif 00412 /** 00413 * @} 00414 */ 00415 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type 00416 * @{ 00417 */ 00418 #define OB_BOOT1_SRAM ((uint32_t)0x000000) /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */ 00419 #define OB_BOOT1_SYSTEM ((uint32_t)FLASH_OPTR_nBOOT1) /*!< System memory is selected as boot space (if BOOT0=1) */ 00420 /** 00421 * @} 00422 */ 00423 00424 /** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type 00425 * @{ 00426 */ 00427 #define OB_SRAM2_PARITY_ENABLE ((uint32_t)0x0000000) /*!< SRAM2 parity check enable */ 00428 #define OB_SRAM2_PARITY_DISABLE ((uint32_t)FLASH_OPTR_SRAM2_PE) /*!< SRAM2 parity check disable */ 00429 /** 00430 * @} 00431 */ 00432 00433 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type 00434 * @{ 00435 */ 00436 #define OB_SRAM2_RST_ERASE ((uint32_t)0x0000000) /*!< SRAM2 erased when a system reset occurs */ 00437 #define OB_SRAM2_RST_NOT_ERASE ((uint32_t)FLASH_OPTR_SRAM2_RST) /*!< SRAM2 is not erased when a system reset occurs */ 00438 /** 00439 * @} 00440 */ 00441 00442 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ 00443 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 00444 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00445 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00446 /** @defgroup OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 00447 * @{ 00448 */ 00449 #define OB_BOOT0_FROM_OB ((uint32_t)0x0000000) /*!< BOOT0 taken from the option bit nBOOT0 */ 00450 #define OB_BOOT0_FROM_PIN ((uint32_t)FLASH_OPTR_nSWBOOT0) /*!< BOOT0 taken from PH3/BOOT0 pin */ 00451 /** 00452 * @} 00453 */ 00454 00455 /** @defgroup OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit 00456 * @{ 00457 */ 00458 #define OB_BOOT0_RESET ((uint32_t)0x0000000) /*!< nBOOT0 = 0 */ 00459 #define OB_BOOT0_SET ((uint32_t)FLASH_OPTR_nBOOT0) /*!< nBOOT0 = 1 */ 00460 /** 00461 * @} 00462 */ 00463 #endif 00464 00465 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type 00466 * @{ 00467 */ 00468 #define OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000) /*!< PCROP area is not erased when the RDP level 00469 is decreased from Level 1 to Level 0 */ 00470 #define OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is 00471 decreased from Level 1 to Level 0 (full mass erase) */ 00472 /** 00473 * @} 00474 */ 00475 00476 /** @defgroup FLASH_Latency FLASH Latency 00477 * @{ 00478 */ 00479 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ 00480 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ 00481 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ 00482 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ 00483 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ 00484 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00485 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */ 00486 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */ 00487 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */ 00488 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */ 00489 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */ 00490 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */ 00491 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state */ 00492 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states */ 00493 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */ 00494 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */ 00495 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */ 00496 #endif 00497 /** 00498 * @} 00499 */ 00500 00501 /** @defgroup FLASH_Keys FLASH Keys 00502 * @{ 00503 */ 00504 #define FLASH_KEY1 0x45670123U /*!< Flash key1 */ 00505 #define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 00506 to unlock the FLASH registers access */ 00507 00508 #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ 00509 #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 00510 to unlock the RUN_PD bit in FLASH_ACR */ 00511 00512 #define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ 00513 #define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 00514 to allow option bytes operations */ 00515 /** 00516 * @} 00517 */ 00518 00519 /** @defgroup FLASH_Flags FLASH Flags Definition 00520 * @{ 00521 */ 00522 #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */ 00523 #define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */ 00524 #define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */ 00525 #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */ 00526 #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */ 00527 #define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ 00528 #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */ 00529 #define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */ 00530 #define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */ 00531 #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */ 00532 #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */ 00533 #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ 00534 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ 00535 defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00536 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00537 #define FLASH_FLAG_PEMPTY FLASH_SR_PEMPTY /*!< FLASH Program empty */ 00538 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 00539 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 00540 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 00541 FLASH_FLAG_OPTVERR | FLASH_FLAG_PEMPTY) 00542 #else 00543 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 00544 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 00545 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 00546 FLASH_FLAG_OPTVERR) 00547 #endif 00548 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ 00549 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ 00550 00551 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 00552 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 00553 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 00554 FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCD) 00555 /** 00556 * @} 00557 */ 00558 00559 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition 00560 * @brief FLASH Interrupt definition 00561 * @{ 00562 */ 00563 #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ 00564 #define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */ 00565 #define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source*/ 00566 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ 00567 /** 00568 * @} 00569 */ 00570 00571 /* Exported macros -----------------------------------------------------------*/ 00572 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros 00573 * @brief macros to control FLASH features 00574 * @{ 00575 */ 00576 00577 /** 00578 * @brief Set the FLASH Latency. 00579 * @param __LATENCY__: FLASH Latency 00580 * This parameter can be one of the following values : 00581 * @arg FLASH_LATENCY_0: FLASH Zero wait state 00582 * @arg FLASH_LATENCY_1: FLASH One wait state 00583 * @arg FLASH_LATENCY_2: FLASH Two wait states 00584 * @arg FLASH_LATENCY_3: FLASH Three wait states 00585 * @arg FLASH_LATENCY_4: FLASH Four wait states 00586 * @retval None 00587 */ 00588 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))) 00589 00590 /** 00591 * @brief Get the FLASH Latency. 00592 * @retval FLASH Latency 00593 * This parameter can be one of the following values : 00594 * @arg FLASH_LATENCY_0: FLASH Zero wait state 00595 * @arg FLASH_LATENCY_1: FLASH One wait state 00596 * @arg FLASH_LATENCY_2: FLASH Two wait states 00597 * @arg FLASH_LATENCY_3: FLASH Three wait states 00598 * @arg FLASH_LATENCY_4: FLASH Four wait states 00599 */ 00600 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) 00601 00602 /** 00603 * @brief Enable the FLASH prefetch buffer. 00604 * @retval None 00605 */ 00606 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 00607 00608 /** 00609 * @brief Disable the FLASH prefetch buffer. 00610 * @retval None 00611 */ 00612 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 00613 00614 /** 00615 * @brief Enable the FLASH instruction cache. 00616 * @retval none 00617 */ 00618 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) 00619 00620 /** 00621 * @brief Disable the FLASH instruction cache. 00622 * @retval none 00623 */ 00624 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) 00625 00626 /** 00627 * @brief Enable the FLASH data cache. 00628 * @retval none 00629 */ 00630 #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) 00631 00632 /** 00633 * @brief Disable the FLASH data cache. 00634 * @retval none 00635 */ 00636 #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) 00637 00638 /** 00639 * @brief Reset the FLASH instruction Cache. 00640 * @note This function must be used only when the Instruction Cache is disabled. 00641 * @retval None 00642 */ 00643 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 00644 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 00645 } while (0) 00646 00647 /** 00648 * @brief Reset the FLASH data Cache. 00649 * @note This function must be used only when the data Cache is disabled. 00650 * @retval None 00651 */ 00652 #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 00653 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 00654 } while (0) 00655 00656 /** 00657 * @brief Enable the FLASH power down during Low-power run mode. 00658 * @note Writing this bit to 0 this bit, automatically the keys are 00659 * loss and a new unlock sequence is necessary to re-write it to 1. 00660 */ 00661 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ 00662 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ 00663 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ 00664 } while (0) 00665 00666 /** 00667 * @brief Disable the FLASH power down during Low-power run mode. 00668 * @note Writing this bit to 0 this bit, automatically the keys are 00669 * loss and a new unlock sequence is necessary to re-write it to 1. 00670 */ 00671 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ 00672 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ 00673 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ 00674 } while (0) 00675 00676 /** 00677 * @brief Enable the FLASH power down during Low-Power sleep mode 00678 * @retval none 00679 */ 00680 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 00681 00682 /** 00683 * @brief Disable the FLASH power down during Low-Power sleep mode 00684 * @retval none 00685 */ 00686 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 00687 00688 /** 00689 * @} 00690 */ 00691 00692 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros 00693 * @brief macros to handle FLASH interrupts 00694 * @{ 00695 */ 00696 00697 /** 00698 * @brief Enable the specified FLASH interrupt. 00699 * @param __INTERRUPT__: FLASH interrupt 00700 * This parameter can be any combination of the following values: 00701 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 00702 * @arg FLASH_IT_OPERR: Error Interrupt 00703 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt 00704 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 00705 * @retval none 00706 */ 00707 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 00708 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 00709 } while(0) 00710 00711 /** 00712 * @brief Disable the specified FLASH interrupt. 00713 * @param __INTERRUPT__: FLASH interrupt 00714 * This parameter can be any combination of the following values: 00715 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 00716 * @arg FLASH_IT_OPERR: Error Interrupt 00717 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt 00718 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 00719 * @retval none 00720 */ 00721 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 00722 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 00723 } while(0) 00724 00725 /** 00726 * @brief Check whether the specified FLASH flag is set or not. 00727 * @param __FLAG__: specifies the FLASH flag to check. 00728 * This parameter can be one of the following values: 00729 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 00730 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 00731 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 00732 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 00733 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 00734 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 00735 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 00736 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag 00737 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag 00738 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag 00739 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag 00740 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 00741 * @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices) 00742 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 00743 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 00744 * @retval The new state of FLASH_FLAG (SET or RESET). 00745 */ 00746 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \ 00747 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 00748 (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) 00749 00750 /** 00751 * @brief Clear the FLASH's pending flags. 00752 * @param __FLAG__: specifies the FLASH flags to clear. 00753 * This parameter can be any combination of the following values: 00754 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 00755 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 00756 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 00757 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 00758 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 00759 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 00760 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 00761 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag 00762 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag 00763 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag 00764 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag 00765 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 00766 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 00767 * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags 00768 * @retval None 00769 */ 00770 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ 00771 if(((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ 00772 } while(0) 00773 /** 00774 * @} 00775 */ 00776 00777 /* Include FLASH HAL Extended module */ 00778 #include "stm32l4xx_hal_flash_ex.h" 00779 #include "stm32l4xx_hal_flash_ramfunc.h" 00780 00781 /* Exported functions --------------------------------------------------------*/ 00782 /** @addtogroup FLASH_Exported_Functions 00783 * @{ 00784 */ 00785 00786 /* Program operation functions ***********************************************/ 00787 /** @addtogroup FLASH_Exported_Functions_Group1 00788 * @{ 00789 */ 00790 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 00791 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 00792 /* FLASH IRQ handler method */ 00793 void HAL_FLASH_IRQHandler(void); 00794 /* Callbacks in non blocking modes */ 00795 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 00796 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 00797 /** 00798 * @} 00799 */ 00800 00801 /* Peripheral Control functions **********************************************/ 00802 /** @addtogroup FLASH_Exported_Functions_Group2 00803 * @{ 00804 */ 00805 HAL_StatusTypeDef HAL_FLASH_Unlock(void); 00806 HAL_StatusTypeDef HAL_FLASH_Lock(void); 00807 /* Option bytes control */ 00808 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 00809 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 00810 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 00811 /** 00812 * @} 00813 */ 00814 00815 /* Peripheral State functions ************************************************/ 00816 /** @addtogroup FLASH_Exported_Functions_Group3 00817 * @{ 00818 */ 00819 uint32_t HAL_FLASH_GetError(void); 00820 /** 00821 * @} 00822 */ 00823 00824 /** 00825 * @} 00826 */ 00827 00828 /* Private constants --------------------------------------------------------*/ 00829 /** @defgroup FLASH_Private_Constants FLASH Private Constants 00830 * @{ 00831 */ 00832 #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) 00833 00834 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00835 #define FLASH_SIZE ((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x800U << 10U) : \ 00836 (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)) 00837 #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 00838 #define FLASH_SIZE ((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x200U << 10U) : \ 00839 (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)) 00840 #else 00841 #define FLASH_SIZE ((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x400U << 10U) : \ 00842 (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)) 00843 #endif 00844 00845 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00846 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00847 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00848 #define FLASH_BANK_SIZE (FLASH_SIZE >> 1U) 00849 #else 00850 #define FLASH_BANK_SIZE (FLASH_SIZE) 00851 #endif 00852 00853 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00854 #define FLASH_PAGE_SIZE ((uint32_t)0x1000) 00855 #define FLASH_PAGE_SIZE_128_BITS ((uint32_t)0x2000) 00856 #else 00857 #define FLASH_PAGE_SIZE ((uint32_t)0x800) 00858 #endif 00859 00860 #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ 00861 /** 00862 * @} 00863 */ 00864 00865 /* Private macros ------------------------------------------------------------*/ 00866 /** @defgroup FLASH_Private_Macros FLASH Private Macros 00867 * @{ 00868 */ 00869 00870 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ 00871 ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 00872 00873 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00874 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00875 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00876 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ 00877 ((BANK) == FLASH_BANK_2) || \ 00878 ((BANK) == FLASH_BANK_BOTH)) 00879 00880 #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ 00881 ((BANK) == FLASH_BANK_2)) 00882 #else 00883 #define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) 00884 00885 #define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) 00886 #endif 00887 00888 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ 00889 ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \ 00890 ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) 00891 00892 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00893 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((ADDRESS) <= (FLASH_BASE+0x1FFFFFU))) 00894 #else 00895 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? \ 00896 ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? \ 00897 ((ADDRESS) <= (FLASH_BASE+0x7FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? \ 00898 ((ADDRESS) <= (FLASH_BASE+0x3FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? \ 00899 ((ADDRESS) <= (FLASH_BASE+0x1FFFFU)) : ((ADDRESS) <= (FLASH_BASE+0xFFFFFU))))))) 00900 #endif 00901 00902 #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU)) 00903 00904 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS))) 00905 00906 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00907 #define IS_FLASH_PAGE(PAGE) ((PAGE) < 256U) 00908 #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 00909 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? ((PAGE) < 256U) : \ 00910 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 128U) : \ 00911 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 64U) : \ 00912 ((PAGE) < 256U))))) 00913 #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 00914 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 256U) : \ 00915 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \ 00916 ((PAGE) < 256U)))) 00917 #else 00918 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \ 00919 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? ((PAGE) < 64U) : \ 00920 ((PAGE) < 128U)))) 00921 #endif 00922 00923 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP))) 00924 00925 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00926 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00927 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00928 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ 00929 ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) 00930 #else 00931 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB)) 00932 #endif 00933 00934 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ 00935 ((LEVEL) == OB_RDP_LEVEL_1)/* ||\ 00936 ((LEVEL) == OB_RDP_LEVEL_2)*/) 00937 00938 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00939 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFFU) && ((TYPE) != 0U)) 00940 #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 00941 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFFU) && ((TYPE) != 0U)) 00942 #else 00943 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7FU) && ((TYPE) != 0U) && (((TYPE)&0x0180U) == 0U)) 00944 #endif 00945 00946 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ 00947 ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ 00948 ((LEVEL) == OB_BOR_LEVEL_4)) 00949 00950 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) 00951 00952 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) 00953 00954 #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) 00955 00956 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) 00957 00958 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) 00959 00960 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) 00961 00962 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) 00963 00964 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00965 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00966 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00967 #define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE)) 00968 00969 #define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) 00970 #endif 00971 00972 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00973 #define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) 00974 #endif 00975 00976 #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) 00977 00978 #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) 00979 00980 #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) 00981 00982 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ 00983 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 00984 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00985 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00986 #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) 00987 00988 #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET)) 00989 #endif 00990 00991 #define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE)) 00992 00993 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00994 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ 00995 ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ 00996 ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ 00997 ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ 00998 ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ 00999 ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ 01000 ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ 01001 ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) 01002 #else 01003 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ 01004 ((LATENCY) == FLASH_LATENCY_1) || \ 01005 ((LATENCY) == FLASH_LATENCY_2) || \ 01006 ((LATENCY) == FLASH_LATENCY_3) || \ 01007 ((LATENCY) == FLASH_LATENCY_4)) 01008 #endif 01009 /** 01010 * @} 01011 */ 01012 01013 /** 01014 * @} 01015 */ 01016 01017 /** 01018 * @} 01019 */ 01020 01021 /** 01022 * @} 01023 */ 01024 01025 #ifdef __cplusplus 01026 } 01027 #endif 01028 01029 #endif /* __STM32L4xx_HAL_FLASH_H */ 01030 01031 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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