STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_adc.c 00004 * @author MCD Application Team 00005 * @brief ADC LL module driver 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 #if defined(USE_FULL_LL_DRIVER) 00036 00037 /* Includes ------------------------------------------------------------------*/ 00038 #include "stm32f4xx_ll_adc.h" 00039 #include "stm32f4xx_ll_bus.h" 00040 00041 #ifdef USE_FULL_ASSERT 00042 #include "stm32_assert.h" 00043 #else 00044 #define assert_param(expr) ((void)0U) 00045 #endif 00046 00047 /** @addtogroup STM32F4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined (ADC1) || defined (ADC2) || defined (ADC3) 00052 00053 /** @addtogroup ADC_LL ADC 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 /* Private constants ---------------------------------------------------------*/ 00060 /* Private macros ------------------------------------------------------------*/ 00061 00062 /** @addtogroup ADC_LL_Private_Macros 00063 * @{ 00064 */ 00065 00066 /* Check of parameters for configuration of ADC hierarchical scope: */ 00067 /* common to several ADC instances. */ 00068 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ 00069 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ 00070 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ 00071 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \ 00072 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \ 00073 ) 00074 00075 /* Check of parameters for configuration of ADC hierarchical scope: */ 00076 /* ADC instance. */ 00077 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ 00078 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ 00079 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ 00080 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ 00081 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ 00082 ) 00083 00084 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ 00085 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ 00086 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ 00087 ) 00088 00089 #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \ 00090 ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ 00091 || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ 00092 ) 00093 00094 #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \ 00095 ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ 00096 || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ 00097 ) 00098 00099 /* Check of parameters for configuration of ADC hierarchical scope: */ 00100 /* ADC group regular */ 00101 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ 00102 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ 00103 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ 00104 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ 00105 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ 00106 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ 00107 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ 00108 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \ 00109 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ 00110 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ 00111 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ 00112 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ 00113 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \ 00114 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH2) \ 00115 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \ 00116 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ 00117 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ 00118 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ 00119 ) 00120 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ 00121 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ 00122 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ 00123 ) 00124 00125 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ 00126 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ 00127 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ 00128 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ 00129 ) 00130 00131 #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \ 00132 ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \ 00133 || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \ 00134 ) 00135 00136 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ 00137 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ 00138 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ 00139 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ 00140 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ 00141 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ 00142 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ 00143 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ 00144 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ 00145 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ 00146 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ 00147 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ 00148 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ 00149 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ 00150 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ 00151 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ 00152 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ 00153 ) 00154 00155 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ 00156 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ 00157 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ 00158 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ 00159 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ 00160 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ 00161 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ 00162 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ 00163 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ 00164 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ 00165 ) 00166 00167 /* Check of parameters for configuration of ADC hierarchical scope: */ 00168 /* ADC group injected */ 00169 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ 00170 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ 00171 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ 00172 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ 00173 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ 00174 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ 00175 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH2) \ 00176 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ 00177 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \ 00178 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \ 00179 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ 00180 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ 00181 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \ 00182 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \ 00183 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ 00184 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH3) \ 00185 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ 00186 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ 00187 ) 00188 00189 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ 00190 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ 00191 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ 00192 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ 00193 ) 00194 00195 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ 00196 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ 00197 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ 00198 ) 00199 00200 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ 00201 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ 00202 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ 00203 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ 00204 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ 00205 ) 00206 00207 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ 00208 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ 00209 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ 00210 ) 00211 00212 #if defined(ADC_MULTIMODE_SUPPORT) 00213 /* Check of parameters for configuration of ADC hierarchical scope: */ 00214 /* multimode. */ 00215 #if defined(ADC3) 00216 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ 00217 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ 00218 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ 00219 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ 00220 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ 00221 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ 00222 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ 00223 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ 00224 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ 00225 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \ 00226 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \ 00227 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \ 00228 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \ 00229 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \ 00230 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \ 00231 ) 00232 #else 00233 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ 00234 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ 00235 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ 00236 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ 00237 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ 00238 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ 00239 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ 00240 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ 00241 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ 00242 ) 00243 #endif 00244 00245 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ 00246 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ 00247 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \ 00248 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \ 00249 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \ 00250 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \ 00251 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \ 00252 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \ 00253 ) 00254 00255 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ 00256 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \ 00257 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ 00258 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \ 00259 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ 00260 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ 00261 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \ 00262 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \ 00263 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \ 00264 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \ 00265 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \ 00266 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \ 00267 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \ 00268 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \ 00269 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \ 00270 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \ 00271 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \ 00272 ) 00273 00274 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ 00275 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ 00276 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ 00277 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ 00278 ) 00279 00280 #endif /* ADC_MULTIMODE_SUPPORT */ 00281 /** 00282 * @} 00283 */ 00284 00285 00286 /* Private function prototypes -----------------------------------------------*/ 00287 00288 /* Exported functions --------------------------------------------------------*/ 00289 /** @addtogroup ADC_LL_Exported_Functions 00290 * @{ 00291 */ 00292 00293 /** @addtogroup ADC_LL_EF_Init 00294 * @{ 00295 */ 00296 00297 /** 00298 * @brief De-initialize registers of all ADC instances belonging to 00299 * the same ADC common instance to their default reset values. 00300 * @param ADCxy_COMMON ADC common instance 00301 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 00302 * @retval An ErrorStatus enumeration value: 00303 * - SUCCESS: ADC common registers are de-initialized 00304 * - ERROR: not applicable 00305 */ 00306 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) 00307 { 00308 /* Check the parameters */ 00309 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); 00310 00311 00312 /* Force reset of ADC clock (core clock) */ 00313 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC); 00314 00315 /* Release reset of ADC clock (core clock) */ 00316 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC); 00317 00318 return SUCCESS; 00319 } 00320 00321 /** 00322 * @brief Initialize some features of ADC common parameters 00323 * (all ADC instances belonging to the same ADC common instance) 00324 * and multimode (for devices with several ADC instances available). 00325 * @note The setting of ADC common parameters is conditioned to 00326 * ADC instances state: 00327 * All ADC instances belonging to the same ADC common instance 00328 * must be disabled. 00329 * @param ADCxy_COMMON ADC common instance 00330 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 00331 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure 00332 * @retval An ErrorStatus enumeration value: 00333 * - SUCCESS: ADC common registers are initialized 00334 * - ERROR: ADC common registers are not initialized 00335 */ 00336 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) 00337 { 00338 ErrorStatus status = SUCCESS; 00339 00340 /* Check the parameters */ 00341 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); 00342 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); 00343 00344 #if defined(ADC_MULTIMODE_SUPPORT) 00345 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); 00346 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) 00347 { 00348 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); 00349 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); 00350 } 00351 #endif /* ADC_MULTIMODE_SUPPORT */ 00352 00353 /* Note: Hardware constraint (refer to description of functions */ 00354 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ 00355 /* On this STM32 serie, setting of these features is conditioned to */ 00356 /* ADC state: */ 00357 /* All ADC instances of the ADC common group must be disabled. */ 00358 if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) 00359 { 00360 /* Configuration of ADC hierarchical scope: */ 00361 /* - common to several ADC */ 00362 /* (all ADC instances belonging to the same ADC common instance) */ 00363 /* - Set ADC clock (conversion clock) */ 00364 /* - multimode (if several ADC instances available on the */ 00365 /* selected device) */ 00366 /* - Set ADC multimode configuration */ 00367 /* - Set ADC multimode DMA transfer */ 00368 /* - Set ADC multimode: delay between 2 sampling phases */ 00369 #if defined(ADC_MULTIMODE_SUPPORT) 00370 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) 00371 { 00372 MODIFY_REG(ADCxy_COMMON->CCR, 00373 ADC_CCR_ADCPRE 00374 | ADC_CCR_MULTI 00375 | ADC_CCR_DMA 00376 | ADC_CCR_DDS 00377 | ADC_CCR_DELAY 00378 , 00379 ADC_CommonInitStruct->CommonClock 00380 | ADC_CommonInitStruct->Multimode 00381 | ADC_CommonInitStruct->MultiDMATransfer 00382 | ADC_CommonInitStruct->MultiTwoSamplingDelay 00383 ); 00384 } 00385 else 00386 { 00387 MODIFY_REG(ADCxy_COMMON->CCR, 00388 ADC_CCR_ADCPRE 00389 | ADC_CCR_MULTI 00390 | ADC_CCR_DMA 00391 | ADC_CCR_DDS 00392 | ADC_CCR_DELAY 00393 , 00394 ADC_CommonInitStruct->CommonClock 00395 | LL_ADC_MULTI_INDEPENDENT 00396 ); 00397 } 00398 #else 00399 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); 00400 #endif 00401 } 00402 else 00403 { 00404 /* Initialization error: One or several ADC instances belonging to */ 00405 /* the same ADC common instance are not disabled. */ 00406 status = ERROR; 00407 } 00408 00409 return status; 00410 } 00411 00412 /** 00413 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. 00414 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure 00415 * whose fields will be set to default values. 00416 * @retval None 00417 */ 00418 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) 00419 { 00420 /* Set ADC_CommonInitStruct fields to default values */ 00421 /* Set fields of ADC common */ 00422 /* (all ADC instances belonging to the same ADC common instance) */ 00423 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; 00424 00425 #if defined(ADC_MULTIMODE_SUPPORT) 00426 /* Set fields of ADC multimode */ 00427 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; 00428 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; 00429 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES; 00430 #endif /* ADC_MULTIMODE_SUPPORT */ 00431 } 00432 00433 /** 00434 * @brief De-initialize registers of the selected ADC instance 00435 * to their default reset values. 00436 * @note To reset all ADC instances quickly (perform a hard reset), 00437 * use function @ref LL_ADC_CommonDeInit(). 00438 * @param ADCx ADC instance 00439 * @retval An ErrorStatus enumeration value: 00440 * - SUCCESS: ADC registers are de-initialized 00441 * - ERROR: ADC registers are not de-initialized 00442 */ 00443 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) 00444 { 00445 ErrorStatus status = SUCCESS; 00446 00447 /* Check the parameters */ 00448 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 00449 00450 /* Disable ADC instance if not already disabled. */ 00451 if(LL_ADC_IsEnabled(ADCx) == 1U) 00452 { 00453 /* Set ADC group regular trigger source to SW start to ensure to not */ 00454 /* have an external trigger event occurring during the conversion stop */ 00455 /* ADC disable process. */ 00456 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); 00457 00458 /* Set ADC group injected trigger source to SW start to ensure to not */ 00459 /* have an external trigger event occurring during the conversion stop */ 00460 /* ADC disable process. */ 00461 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); 00462 00463 /* Disable the ADC instance */ 00464 LL_ADC_Disable(ADCx); 00465 } 00466 00467 /* Check whether ADC state is compliant with expected state */ 00468 /* (hardware requirements of bits state to reset registers below) */ 00469 if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U) 00470 { 00471 /* ========== Reset ADC registers ========== */ 00472 /* Reset register SR */ 00473 CLEAR_BIT(ADCx->SR, 00474 ( LL_ADC_FLAG_STRT 00475 | LL_ADC_FLAG_JSTRT 00476 | LL_ADC_FLAG_EOCS 00477 | LL_ADC_FLAG_OVR 00478 | LL_ADC_FLAG_JEOS 00479 | LL_ADC_FLAG_AWD1 ) 00480 ); 00481 00482 /* Reset register CR1 */ 00483 CLEAR_BIT(ADCx->CR1, 00484 ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN 00485 | ADC_CR1_JAWDEN 00486 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN 00487 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN 00488 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE 00489 | ADC_CR1_AWDCH ) 00490 ); 00491 00492 /* Reset register CR2 */ 00493 CLEAR_BIT(ADCx->CR2, 00494 ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL 00495 | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL 00496 | ADC_CR2_ALIGN | ADC_CR2_EOCS 00497 | ADC_CR2_DDS | ADC_CR2_DMA 00498 | ADC_CR2_CONT | ADC_CR2_ADON ) 00499 ); 00500 00501 /* Reset register SMPR1 */ 00502 CLEAR_BIT(ADCx->SMPR1, 00503 ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 00504 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 00505 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10) 00506 ); 00507 00508 /* Reset register SMPR2 */ 00509 CLEAR_BIT(ADCx->SMPR2, 00510 ( ADC_SMPR2_SMP9 00511 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 00512 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 00513 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0) 00514 ); 00515 00516 /* Reset register JOFR1 */ 00517 CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); 00518 /* Reset register JOFR2 */ 00519 CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2); 00520 /* Reset register JOFR3 */ 00521 CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); 00522 /* Reset register JOFR4 */ 00523 CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); 00524 00525 /* Reset register HTR */ 00526 SET_BIT(ADCx->HTR, ADC_HTR_HT); 00527 /* Reset register LTR */ 00528 CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); 00529 00530 /* Reset register SQR1 */ 00531 CLEAR_BIT(ADCx->SQR1, 00532 ( ADC_SQR1_L 00533 | ADC_SQR1_SQ16 00534 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13) 00535 ); 00536 00537 /* Reset register SQR2 */ 00538 CLEAR_BIT(ADCx->SQR2, 00539 ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 00540 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7) 00541 ); 00542 00543 00544 /* Reset register JSQR */ 00545 CLEAR_BIT(ADCx->JSQR, 00546 ( ADC_JSQR_JL 00547 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 00548 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) 00549 ); 00550 00551 /* Reset register DR */ 00552 /* bits in access mode read only, no direct reset applicable */ 00553 00554 /* Reset registers JDR1, JDR2, JDR3, JDR4 */ 00555 /* bits in access mode read only, no direct reset applicable */ 00556 00557 /* Reset register CCR */ 00558 CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE); 00559 } 00560 00561 return status; 00562 } 00563 00564 /** 00565 * @brief Initialize some features of ADC instance. 00566 * @note These parameters have an impact on ADC scope: ADC instance. 00567 * Affects both group regular and group injected (availability 00568 * of ADC group injected depends on STM32 families). 00569 * Refer to corresponding unitary functions into 00570 * @ref ADC_LL_EF_Configuration_ADC_Instance . 00571 * @note The setting of these parameters by function @ref LL_ADC_Init() 00572 * is conditioned to ADC state: 00573 * ADC instance must be disabled. 00574 * This condition is applied to all ADC features, for efficiency 00575 * and compatibility over all STM32 families. However, the different 00576 * features can be set under different ADC state conditions 00577 * (setting possible with ADC enabled without conversion on going, 00578 * ADC enabled with conversion on going, ...) 00579 * Each feature can be updated afterwards with a unitary function 00580 * and potentially with ADC in a different state than disabled, 00581 * refer to description of each function for setting 00582 * conditioned to ADC state. 00583 * @note After using this function, some other features must be configured 00584 * using LL unitary functions. 00585 * The minimum configuration remaining to be done is: 00586 * - Set ADC group regular or group injected sequencer: 00587 * map channel on the selected sequencer rank. 00588 * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). 00589 * - Set ADC channel sampling time 00590 * Refer to function LL_ADC_SetChannelSamplingTime(); 00591 * @param ADCx ADC instance 00592 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure 00593 * @retval An ErrorStatus enumeration value: 00594 * - SUCCESS: ADC registers are initialized 00595 * - ERROR: ADC registers are not initialized 00596 */ 00597 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) 00598 { 00599 ErrorStatus status = SUCCESS; 00600 00601 /* Check the parameters */ 00602 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 00603 00604 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); 00605 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); 00606 assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); 00607 00608 /* Note: Hardware constraint (refer to description of this function): */ 00609 /* ADC instance must be disabled. */ 00610 if(LL_ADC_IsEnabled(ADCx) == 0U) 00611 { 00612 /* Configuration of ADC hierarchical scope: */ 00613 /* - ADC instance */ 00614 /* - Set ADC data resolution */ 00615 /* - Set ADC conversion data alignment */ 00616 MODIFY_REG(ADCx->CR1, 00617 ADC_CR1_RES 00618 | ADC_CR1_SCAN 00619 , 00620 ADC_InitStruct->Resolution 00621 | ADC_InitStruct->SequencersScanMode 00622 ); 00623 00624 MODIFY_REG(ADCx->CR2, 00625 ADC_CR2_ALIGN 00626 , 00627 ADC_InitStruct->DataAlignment 00628 ); 00629 00630 } 00631 else 00632 { 00633 /* Initialization error: ADC instance is not disabled. */ 00634 status = ERROR; 00635 } 00636 return status; 00637 } 00638 00639 /** 00640 * @brief Set each @ref LL_ADC_InitTypeDef field to default value. 00641 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure 00642 * whose fields will be set to default values. 00643 * @retval None 00644 */ 00645 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) 00646 { 00647 /* Set ADC_InitStruct fields to default values */ 00648 /* Set fields of ADC instance */ 00649 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; 00650 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; 00651 00652 /* Enable scan mode to have a generic behavior with ADC of other */ 00653 /* STM32 families, without this setting available: */ 00654 /* ADC group regular sequencer and ADC group injected sequencer depend */ 00655 /* only of their own configuration. */ 00656 ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; 00657 00658 } 00659 00660 /** 00661 * @brief Initialize some features of ADC group regular. 00662 * @note These parameters have an impact on ADC scope: ADC group regular. 00663 * Refer to corresponding unitary functions into 00664 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 00665 * (functions with prefix "REG"). 00666 * @note The setting of these parameters by function @ref LL_ADC_Init() 00667 * is conditioned to ADC state: 00668 * ADC instance must be disabled. 00669 * This condition is applied to all ADC features, for efficiency 00670 * and compatibility over all STM32 families. However, the different 00671 * features can be set under different ADC state conditions 00672 * (setting possible with ADC enabled without conversion on going, 00673 * ADC enabled with conversion on going, ...) 00674 * Each feature can be updated afterwards with a unitary function 00675 * and potentially with ADC in a different state than disabled, 00676 * refer to description of each function for setting 00677 * conditioned to ADC state. 00678 * @note After using this function, other features must be configured 00679 * using LL unitary functions. 00680 * The minimum configuration remaining to be done is: 00681 * - Set ADC group regular or group injected sequencer: 00682 * map channel on the selected sequencer rank. 00683 * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). 00684 * - Set ADC channel sampling time 00685 * Refer to function LL_ADC_SetChannelSamplingTime(); 00686 * @param ADCx ADC instance 00687 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure 00688 * @retval An ErrorStatus enumeration value: 00689 * - SUCCESS: ADC registers are initialized 00690 * - ERROR: ADC registers are not initialized 00691 */ 00692 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) 00693 { 00694 ErrorStatus status = SUCCESS; 00695 00696 /* Check the parameters */ 00697 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 00698 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); 00699 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); 00700 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) 00701 { 00702 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); 00703 } 00704 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); 00705 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); 00706 00707 /* Note: Hardware constraint (refer to description of this function): */ 00708 /* ADC instance must be disabled. */ 00709 if(LL_ADC_IsEnabled(ADCx) == 0U) 00710 { 00711 /* Configuration of ADC hierarchical scope: */ 00712 /* - ADC group regular */ 00713 /* - Set ADC group regular trigger source */ 00714 /* - Set ADC group regular sequencer length */ 00715 /* - Set ADC group regular sequencer discontinuous mode */ 00716 /* - Set ADC group regular continuous mode */ 00717 /* - Set ADC group regular conversion data transfer: no transfer or */ 00718 /* transfer by DMA, and DMA requests mode */ 00719 /* Note: On this STM32 serie, ADC trigger edge is set when starting */ 00720 /* ADC conversion. */ 00721 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ 00722 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) 00723 { 00724 MODIFY_REG(ADCx->CR1, 00725 ADC_CR1_DISCEN 00726 | ADC_CR1_DISCNUM 00727 , 00728 ADC_REG_InitStruct->SequencerLength 00729 | ADC_REG_InitStruct->SequencerDiscont 00730 ); 00731 } 00732 else 00733 { 00734 MODIFY_REG(ADCx->CR1, 00735 ADC_CR1_DISCEN 00736 | ADC_CR1_DISCNUM 00737 , 00738 ADC_REG_InitStruct->SequencerLength 00739 | LL_ADC_REG_SEQ_DISCONT_DISABLE 00740 ); 00741 } 00742 00743 MODIFY_REG(ADCx->CR2, 00744 ADC_CR2_EXTSEL 00745 | ADC_CR2_EXTEN 00746 | ADC_CR2_CONT 00747 | ADC_CR2_DMA 00748 | ADC_CR2_DDS 00749 , 00750 (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) 00751 | ADC_REG_InitStruct->ContinuousMode 00752 | ADC_REG_InitStruct->DMATransfer 00753 ); 00754 00755 /* Set ADC group regular sequencer length and scan direction */ 00756 /* Note: Hardware constraint (refer to description of this function): */ 00757 /* Note: If ADC instance feature scan mode is disabled */ 00758 /* (refer to ADC instance initialization structure */ 00759 /* parameter @ref SequencersScanMode */ 00760 /* or function @ref LL_ADC_SetSequencersScanMode() ), */ 00761 /* this parameter is discarded. */ 00762 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); 00763 } 00764 else 00765 { 00766 /* Initialization error: ADC instance is not disabled. */ 00767 status = ERROR; 00768 } 00769 return status; 00770 } 00771 00772 /** 00773 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. 00774 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure 00775 * whose fields will be set to default values. 00776 * @retval None 00777 */ 00778 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) 00779 { 00780 /* Set ADC_REG_InitStruct fields to default values */ 00781 /* Set fields of ADC group regular */ 00782 /* Note: On this STM32 serie, ADC trigger edge is set when starting */ 00783 /* ADC conversion. */ 00784 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ 00785 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; 00786 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; 00787 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; 00788 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; 00789 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; 00790 } 00791 00792 /** 00793 * @brief Initialize some features of ADC group injected. 00794 * @note These parameters have an impact on ADC scope: ADC group injected. 00795 * Refer to corresponding unitary functions into 00796 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 00797 * (functions with prefix "INJ"). 00798 * @note The setting of these parameters by function @ref LL_ADC_Init() 00799 * is conditioned to ADC state: 00800 * ADC instance must be disabled. 00801 * This condition is applied to all ADC features, for efficiency 00802 * and compatibility over all STM32 families. However, the different 00803 * features can be set under different ADC state conditions 00804 * (setting possible with ADC enabled without conversion on going, 00805 * ADC enabled with conversion on going, ...) 00806 * Each feature can be updated afterwards with a unitary function 00807 * and potentially with ADC in a different state than disabled, 00808 * refer to description of each function for setting 00809 * conditioned to ADC state. 00810 * @note After using this function, other features must be configured 00811 * using LL unitary functions. 00812 * The minimum configuration remaining to be done is: 00813 * - Set ADC group injected sequencer: 00814 * map channel on the selected sequencer rank. 00815 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). 00816 * - Set ADC channel sampling time 00817 * Refer to function LL_ADC_SetChannelSamplingTime(); 00818 * @param ADCx ADC instance 00819 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure 00820 * @retval An ErrorStatus enumeration value: 00821 * - SUCCESS: ADC registers are initialized 00822 * - ERROR: ADC registers are not initialized 00823 */ 00824 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) 00825 { 00826 ErrorStatus status = SUCCESS; 00827 00828 /* Check the parameters */ 00829 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 00830 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); 00831 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); 00832 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) 00833 { 00834 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); 00835 } 00836 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); 00837 00838 /* Note: Hardware constraint (refer to description of this function): */ 00839 /* ADC instance must be disabled. */ 00840 if(LL_ADC_IsEnabled(ADCx) == 0U) 00841 { 00842 /* Configuration of ADC hierarchical scope: */ 00843 /* - ADC group injected */ 00844 /* - Set ADC group injected trigger source */ 00845 /* - Set ADC group injected sequencer length */ 00846 /* - Set ADC group injected sequencer discontinuous mode */ 00847 /* - Set ADC group injected conversion trigger: independent or */ 00848 /* from ADC group regular */ 00849 /* Note: On this STM32 serie, ADC trigger edge is set when starting */ 00850 /* ADC conversion. */ 00851 /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ 00852 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) 00853 { 00854 MODIFY_REG(ADCx->CR1, 00855 ADC_CR1_JDISCEN 00856 | ADC_CR1_JAUTO 00857 , 00858 ADC_INJ_InitStruct->SequencerDiscont 00859 | ADC_INJ_InitStruct->TrigAuto 00860 ); 00861 } 00862 else 00863 { 00864 MODIFY_REG(ADCx->CR1, 00865 ADC_CR1_JDISCEN 00866 | ADC_CR1_JAUTO 00867 , 00868 LL_ADC_REG_SEQ_DISCONT_DISABLE 00869 | ADC_INJ_InitStruct->TrigAuto 00870 ); 00871 } 00872 00873 MODIFY_REG(ADCx->CR2, 00874 ADC_CR2_JEXTSEL 00875 | ADC_CR2_JEXTEN 00876 , 00877 (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) 00878 ); 00879 00880 /* Note: Hardware constraint (refer to description of this function): */ 00881 /* Note: If ADC instance feature scan mode is disabled */ 00882 /* (refer to ADC instance initialization structure */ 00883 /* parameter @ref SequencersScanMode */ 00884 /* or function @ref LL_ADC_SetSequencersScanMode() ), */ 00885 /* this parameter is discarded. */ 00886 LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength); 00887 } 00888 else 00889 { 00890 /* Initialization error: ADC instance is not disabled. */ 00891 status = ERROR; 00892 } 00893 return status; 00894 } 00895 00896 /** 00897 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. 00898 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure 00899 * whose fields will be set to default values. 00900 * @retval None 00901 */ 00902 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) 00903 { 00904 /* Set ADC_INJ_InitStruct fields to default values */ 00905 /* Set fields of ADC group injected */ 00906 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; 00907 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; 00908 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; 00909 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; 00910 } 00911 00912 /** 00913 * @} 00914 */ 00915 00916 /** 00917 * @} 00918 */ 00919 00920 /** 00921 * @} 00922 */ 00923 00924 #endif /* ADC1 || ADC2 || ADC3 */ 00925 00926 /** 00927 * @} 00928 */ 00929 00930 #endif /* USE_FULL_LL_DRIVER */ 00931 00932 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/