STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_tim.c 00004 * @author MCD Application Team 00005 * @brief TIM HAL module driver. 00006 * This file provides firmware functions to manage the following 00007 * functionalities of the Timer (TIM) peripheral: 00008 * + Time Base Initialization 00009 * + Time Base Start 00010 * + Time Base Start Interruption 00011 * + Time Base Start DMA 00012 * + Time Output Compare/PWM Initialization 00013 * + Time Output Compare/PWM Channel Configuration 00014 * + Time Output Compare/PWM Start 00015 * + Time Output Compare/PWM Start Interruption 00016 * + Time Output Compare/PWM Start DMA 00017 * + Time Input Capture Initialization 00018 * + Time Input Capture Channel Configuration 00019 * + Time Input Capture Start 00020 * + Time Input Capture Start Interruption 00021 * + Time Input Capture Start DMA 00022 * + Time One Pulse Initialization 00023 * + Time One Pulse Channel Configuration 00024 * + Time One Pulse Start 00025 * + Time Encoder Interface Initialization 00026 * + Time Encoder Interface Start 00027 * + Time Encoder Interface Start Interruption 00028 * + Time Encoder Interface Start DMA 00029 * + Commutation Event configuration with Interruption and DMA 00030 * + Time OCRef clear configuration 00031 * + Time External Clock configuration 00032 @verbatim 00033 ============================================================================== 00034 ##### TIMER Generic features ##### 00035 ============================================================================== 00036 [..] The Timer features include: 00037 (#) 16-bit up, down, up/down auto-reload counter. 00038 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the 00039 counter clock frequency either by any factor between 1 and 65536. 00040 (#) Up to 4 independent channels for: 00041 (++) Input Capture 00042 (++) Output Compare 00043 (++) PWM generation (Edge and Center-aligned Mode) 00044 (++) One-pulse mode output 00045 00046 ##### How to use this driver ##### 00047 ============================================================================== 00048 [..] 00049 (#) Initialize the TIM low level resources by implementing the following functions 00050 depending from feature used : 00051 (++) Time Base : HAL_TIM_Base_MspInit() 00052 (++) Input Capture : HAL_TIM_IC_MspInit() 00053 (++) Output Compare : HAL_TIM_OC_MspInit() 00054 (++) PWM generation : HAL_TIM_PWM_MspInit() 00055 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() 00056 (++) Encoder mode output : HAL_TIM_Encoder_MspInit() 00057 00058 (#) Initialize the TIM low level resources : 00059 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); 00060 (##) TIM pins configuration 00061 (+++) Enable the clock for the TIM GPIOs using the following function: 00062 __GPIOx_CLK_ENABLE(); 00063 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); 00064 00065 (#) The external Clock can be configured, if needed (the default clock is the 00066 internal clock from the APBx), using the following function: 00067 HAL_TIM_ConfigClockSource, the clock configuration should be done before 00068 any start function. 00069 00070 (#) Configure the TIM in the desired functioning mode using one of the 00071 initialization function of this driver: 00072 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base 00073 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an 00074 Output Compare signal. 00075 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a 00076 PWM signal. 00077 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an 00078 external signal. 00079 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer 00080 in One Pulse Mode. 00081 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. 00082 00083 (#) Activate the TIM peripheral using one of the start functions depending from the feature used: 00084 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() 00085 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() 00086 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() 00087 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() 00088 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() 00089 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). 00090 00091 (#) The DMA Burst is managed with the two following functions: 00092 HAL_TIM_DMABurst_WriteStart() 00093 HAL_TIM_DMABurst_ReadStart() 00094 00095 @endverbatim 00096 ****************************************************************************** 00097 * @attention 00098 * 00099 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00100 * 00101 * Redistribution and use in source and binary forms, with or without modification, 00102 * are permitted provided that the following conditions are met: 00103 * 1. Redistributions of source code must retain the above copyright notice, 00104 * this list of conditions and the following disclaimer. 00105 * 2. Redistributions in binary form must reproduce the above copyright notice, 00106 * this list of conditions and the following disclaimer in the documentation 00107 * and/or other materials provided with the distribution. 00108 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00109 * may be used to endorse or promote products derived from this software 00110 * without specific prior written permission. 00111 * 00112 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00113 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00114 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00115 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00116 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00117 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00118 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00119 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00120 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00121 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00122 * 00123 ****************************************************************************** 00124 */ 00125 00126 /* Includes ------------------------------------------------------------------*/ 00127 #include "stm32f4xx_hal.h" 00128 00129 /** @addtogroup STM32F4xx_HAL_Driver 00130 * @{ 00131 */ 00132 00133 /** @defgroup TIM TIM 00134 * @brief TIM HAL module driver 00135 * @{ 00136 */ 00137 00138 #ifdef HAL_TIM_MODULE_ENABLED 00139 00140 /* Private typedef -----------------------------------------------------------*/ 00141 /* Private define ------------------------------------------------------------*/ 00142 /* Private macro -------------------------------------------------------------*/ 00143 /* Private variables ---------------------------------------------------------*/ 00144 /** @addtogroup TIM_Private_Functions 00145 * @{ 00146 */ 00147 /* Private function prototypes -----------------------------------------------*/ 00148 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 00149 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 00150 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 00151 00152 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); 00153 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 00154 uint32_t TIM_ICFilter); 00155 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); 00156 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 00157 uint32_t TIM_ICFilter); 00158 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 00159 uint32_t TIM_ICFilter); 00160 00161 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, 00162 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 00163 00164 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx); 00165 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); 00166 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); 00167 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, 00168 TIM_SlaveConfigTypeDef * sSlaveConfig); 00169 /** 00170 * @} 00171 */ 00172 00173 /* Exported functions --------------------------------------------------------*/ 00174 /** @defgroup TIM_Exported_Functions TIM Exported Functions 00175 * @{ 00176 */ 00177 00178 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions 00179 * @brief Time Base functions 00180 * 00181 @verbatim 00182 ============================================================================== 00183 ##### Time Base functions ##### 00184 ============================================================================== 00185 [..] 00186 This section provides functions allowing to: 00187 (+) Initialize and configure the TIM base. 00188 (+) De-initialize the TIM base. 00189 (+) Start the Time Base. 00190 (+) Stop the Time Base. 00191 (+) Start the Time Base and enable interrupt. 00192 (+) Stop the Time Base and disable interrupt. 00193 (+) Start the Time Base and enable DMA transfer. 00194 (+) Stop the Time Base and disable DMA transfer. 00195 00196 @endverbatim 00197 * @{ 00198 */ 00199 /** 00200 * @brief Initializes the TIM Time base Unit according to the specified 00201 * parameters in the TIM_HandleTypeDef and create the associated handle. 00202 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00203 * the configuration information for TIM module. 00204 * @retval HAL status 00205 */ 00206 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) 00207 { 00208 /* Check the TIM handle allocation */ 00209 if(htim == NULL) 00210 { 00211 return HAL_ERROR; 00212 } 00213 00214 /* Check the parameters */ 00215 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00216 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); 00217 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 00218 00219 if(htim->State == HAL_TIM_STATE_RESET) 00220 { 00221 /* Allocate lock resource and initialize it */ 00222 htim->Lock = HAL_UNLOCKED; 00223 /* Init the low level hardware : GPIO, CLOCK, NVIC */ 00224 HAL_TIM_Base_MspInit(htim); 00225 } 00226 00227 /* Set the TIM state */ 00228 htim->State= HAL_TIM_STATE_BUSY; 00229 00230 /* Set the Time Base configuration */ 00231 TIM_Base_SetConfig(htim->Instance, &htim->Init); 00232 00233 /* Initialize the TIM state*/ 00234 htim->State= HAL_TIM_STATE_READY; 00235 00236 return HAL_OK; 00237 } 00238 00239 /** 00240 * @brief DeInitializes the TIM Base peripheral 00241 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00242 * the configuration information for TIM module. 00243 * @retval HAL status 00244 */ 00245 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) 00246 { 00247 /* Check the parameters */ 00248 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00249 00250 htim->State = HAL_TIM_STATE_BUSY; 00251 00252 /* Disable the TIM Peripheral Clock */ 00253 __HAL_TIM_DISABLE(htim); 00254 00255 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ 00256 HAL_TIM_Base_MspDeInit(htim); 00257 00258 /* Change TIM state */ 00259 htim->State = HAL_TIM_STATE_RESET; 00260 00261 /* Release Lock */ 00262 __HAL_UNLOCK(htim); 00263 00264 return HAL_OK; 00265 } 00266 00267 /** 00268 * @brief Initializes the TIM Base MSP. 00269 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00270 * the configuration information for TIM module. 00271 * @retval None 00272 */ 00273 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) 00274 { 00275 /* Prevent unused argument(s) compilation warning */ 00276 UNUSED(htim); 00277 /* NOTE : This function Should not be modified, when the callback is needed, 00278 the HAL_TIM_Base_MspInit could be implemented in the user file 00279 */ 00280 } 00281 00282 /** 00283 * @brief DeInitializes TIM Base MSP. 00284 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00285 * the configuration information for TIM module. 00286 * @retval None 00287 */ 00288 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) 00289 { 00290 /* Prevent unused argument(s) compilation warning */ 00291 UNUSED(htim); 00292 /* NOTE : This function Should not be modified, when the callback is needed, 00293 the HAL_TIM_Base_MspDeInit could be implemented in the user file 00294 */ 00295 } 00296 00297 /** 00298 * @brief Starts the TIM Base generation. 00299 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00300 * the configuration information for TIM module. 00301 * @retval HAL status 00302 */ 00303 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) 00304 { 00305 /* Check the parameters */ 00306 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00307 00308 /* Set the TIM state */ 00309 htim->State= HAL_TIM_STATE_BUSY; 00310 00311 /* Enable the Peripheral */ 00312 __HAL_TIM_ENABLE(htim); 00313 00314 /* Change the TIM state*/ 00315 htim->State= HAL_TIM_STATE_READY; 00316 00317 /* Return function status */ 00318 return HAL_OK; 00319 } 00320 00321 /** 00322 * @brief Stops the TIM Base generation. 00323 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00324 * the configuration information for TIM module. 00325 * @retval HAL status 00326 */ 00327 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) 00328 { 00329 /* Check the parameters */ 00330 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00331 00332 /* Set the TIM state */ 00333 htim->State= HAL_TIM_STATE_BUSY; 00334 00335 /* Disable the Peripheral */ 00336 __HAL_TIM_DISABLE(htim); 00337 00338 /* Change the TIM state*/ 00339 htim->State= HAL_TIM_STATE_READY; 00340 00341 /* Return function status */ 00342 return HAL_OK; 00343 } 00344 00345 /** 00346 * @brief Starts the TIM Base generation in interrupt mode. 00347 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00348 * the configuration information for TIM module. 00349 * @retval HAL status 00350 */ 00351 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) 00352 { 00353 /* Check the parameters */ 00354 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00355 00356 /* Enable the TIM Update interrupt */ 00357 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 00358 00359 /* Enable the Peripheral */ 00360 __HAL_TIM_ENABLE(htim); 00361 00362 /* Return function status */ 00363 return HAL_OK; 00364 } 00365 00366 /** 00367 * @brief Stops the TIM Base generation in interrupt mode. 00368 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00369 * the configuration information for TIM module. 00370 * @retval HAL status 00371 */ 00372 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) 00373 { 00374 /* Check the parameters */ 00375 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00376 /* Disable the TIM Update interrupt */ 00377 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); 00378 00379 /* Disable the Peripheral */ 00380 __HAL_TIM_DISABLE(htim); 00381 00382 /* Return function status */ 00383 return HAL_OK; 00384 } 00385 00386 /** 00387 * @brief Starts the TIM Base generation in DMA mode. 00388 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00389 * the configuration information for TIM module. 00390 * @param pData The source Buffer address. 00391 * @param Length The length of data to be transferred from memory to peripheral. 00392 * @retval HAL status 00393 */ 00394 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) 00395 { 00396 /* Check the parameters */ 00397 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); 00398 00399 if((htim->State == HAL_TIM_STATE_BUSY)) 00400 { 00401 return HAL_BUSY; 00402 } 00403 else if((htim->State == HAL_TIM_STATE_READY)) 00404 { 00405 if((pData == 0U) && (Length > 0)) 00406 { 00407 return HAL_ERROR; 00408 } 00409 else 00410 { 00411 htim->State = HAL_TIM_STATE_BUSY; 00412 } 00413 } 00414 /* Set the DMA Period elapsed callback */ 00415 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; 00416 00417 /* Set the DMA error callback */ 00418 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; 00419 00420 /* Enable the DMA Stream */ 00421 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); 00422 00423 /* Enable the TIM Update DMA request */ 00424 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); 00425 00426 /* Enable the Peripheral */ 00427 __HAL_TIM_ENABLE(htim); 00428 00429 /* Return function status */ 00430 return HAL_OK; 00431 } 00432 00433 /** 00434 * @brief Stops the TIM Base generation in DMA mode. 00435 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00436 * the configuration information for TIM module. 00437 * @retval HAL status 00438 */ 00439 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) 00440 { 00441 /* Check the parameters */ 00442 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); 00443 00444 /* Disable the TIM Update DMA request */ 00445 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); 00446 00447 /* Disable the Peripheral */ 00448 __HAL_TIM_DISABLE(htim); 00449 00450 /* Change the htim state */ 00451 htim->State = HAL_TIM_STATE_READY; 00452 00453 /* Return function status */ 00454 return HAL_OK; 00455 } 00456 /** 00457 * @} 00458 */ 00459 00460 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions 00461 * @brief Time Output Compare functions 00462 * 00463 @verbatim 00464 ============================================================================== 00465 ##### Time Output Compare functions ##### 00466 ============================================================================== 00467 [..] 00468 This section provides functions allowing to: 00469 (+) Initialize and configure the TIM Output Compare. 00470 (+) De-initialize the TIM Output Compare. 00471 (+) Start the Time Output Compare. 00472 (+) Stop the Time Output Compare. 00473 (+) Start the Time Output Compare and enable interrupt. 00474 (+) Stop the Time Output Compare and disable interrupt. 00475 (+) Start the Time Output Compare and enable DMA transfer. 00476 (+) Stop the Time Output Compare and disable DMA transfer. 00477 00478 @endverbatim 00479 * @{ 00480 */ 00481 /** 00482 * @brief Initializes the TIM Output Compare according to the specified 00483 * parameters in the TIM_HandleTypeDef and create the associated handle. 00484 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00485 * the configuration information for TIM module. 00486 * @retval HAL status 00487 */ 00488 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) 00489 { 00490 /* Check the TIM handle allocation */ 00491 if(htim == NULL) 00492 { 00493 return HAL_ERROR; 00494 } 00495 00496 /* Check the parameters */ 00497 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00498 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); 00499 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 00500 00501 if(htim->State == HAL_TIM_STATE_RESET) 00502 { 00503 /* Allocate lock resource and initialize it */ 00504 htim->Lock = HAL_UNLOCKED; 00505 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ 00506 HAL_TIM_OC_MspInit(htim); 00507 } 00508 00509 /* Set the TIM state */ 00510 htim->State= HAL_TIM_STATE_BUSY; 00511 00512 /* Init the base time for the Output Compare */ 00513 TIM_Base_SetConfig(htim->Instance, &htim->Init); 00514 00515 /* Initialize the TIM state*/ 00516 htim->State= HAL_TIM_STATE_READY; 00517 00518 return HAL_OK; 00519 } 00520 00521 /** 00522 * @brief DeInitializes the TIM peripheral 00523 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00524 * the configuration information for TIM module. 00525 * @retval HAL status 00526 */ 00527 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) 00528 { 00529 /* Check the parameters */ 00530 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00531 00532 htim->State = HAL_TIM_STATE_BUSY; 00533 00534 /* Disable the TIM Peripheral Clock */ 00535 __HAL_TIM_DISABLE(htim); 00536 00537 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ 00538 HAL_TIM_OC_MspDeInit(htim); 00539 00540 /* Change TIM state */ 00541 htim->State = HAL_TIM_STATE_RESET; 00542 00543 /* Release Lock */ 00544 __HAL_UNLOCK(htim); 00545 00546 return HAL_OK; 00547 } 00548 00549 /** 00550 * @brief Initializes the TIM Output Compare MSP. 00551 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00552 * the configuration information for TIM module. 00553 * @retval None 00554 */ 00555 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) 00556 { 00557 /* Prevent unused argument(s) compilation warning */ 00558 UNUSED(htim); 00559 /* NOTE : This function Should not be modified, when the callback is needed, 00560 the HAL_TIM_OC_MspInit could be implemented in the user file 00561 */ 00562 } 00563 00564 /** 00565 * @brief DeInitializes TIM Output Compare MSP. 00566 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00567 * the configuration information for TIM module. 00568 * @retval None 00569 */ 00570 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) 00571 { 00572 /* Prevent unused argument(s) compilation warning */ 00573 UNUSED(htim); 00574 /* NOTE : This function Should not be modified, when the callback is needed, 00575 the HAL_TIM_OC_MspDeInit could be implemented in the user file 00576 */ 00577 } 00578 00579 /** 00580 * @brief Starts the TIM Output Compare signal generation. 00581 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00582 * the configuration information for TIM module. 00583 * @param Channel TIM Channel to be enabled. 00584 * This parameter can be one of the following values: 00585 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00586 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00587 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00588 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 00589 * @retval HAL status 00590 */ 00591 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) 00592 { 00593 /* Check the parameters */ 00594 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 00595 00596 /* Enable the Output compare channel */ 00597 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 00598 00599 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) 00600 { 00601 /* Enable the main output */ 00602 __HAL_TIM_MOE_ENABLE(htim); 00603 } 00604 00605 /* Enable the Peripheral */ 00606 __HAL_TIM_ENABLE(htim); 00607 00608 /* Return function status */ 00609 return HAL_OK; 00610 } 00611 00612 /** 00613 * @brief Stops the TIM Output Compare signal generation. 00614 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00615 * the configuration information for TIM module. 00616 * @param Channel TIM Channel to be disabled. 00617 * This parameter can be one of the following values: 00618 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00619 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00620 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00621 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 00622 * @retval HAL status 00623 */ 00624 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) 00625 { 00626 /* Check the parameters */ 00627 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 00628 00629 /* Disable the Output compare channel */ 00630 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 00631 00632 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) 00633 { 00634 /* Disable the Main Output */ 00635 __HAL_TIM_MOE_DISABLE(htim); 00636 } 00637 00638 /* Disable the Peripheral */ 00639 __HAL_TIM_DISABLE(htim); 00640 00641 /* Return function status */ 00642 return HAL_OK; 00643 } 00644 00645 /** 00646 * @brief Starts the TIM Output Compare signal generation in interrupt mode. 00647 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00648 * the configuration information for TIM module. 00649 * @param Channel TIM Channel to be enabled. 00650 * This parameter can be one of the following values: 00651 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00652 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00653 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00654 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 00655 * @retval HAL status 00656 */ 00657 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 00658 { 00659 /* Check the parameters */ 00660 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 00661 00662 switch (Channel) 00663 { 00664 case TIM_CHANNEL_1: 00665 { 00666 /* Enable the TIM Capture/Compare 1 interrupt */ 00667 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 00668 } 00669 break; 00670 00671 case TIM_CHANNEL_2: 00672 { 00673 /* Enable the TIM Capture/Compare 2 interrupt */ 00674 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 00675 } 00676 break; 00677 00678 case TIM_CHANNEL_3: 00679 { 00680 /* Enable the TIM Capture/Compare 3 interrupt */ 00681 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 00682 } 00683 break; 00684 00685 case TIM_CHANNEL_4: 00686 { 00687 /* Enable the TIM Capture/Compare 4 interrupt */ 00688 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 00689 } 00690 break; 00691 00692 default: 00693 break; 00694 } 00695 00696 /* Enable the Output compare channel */ 00697 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 00698 00699 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) 00700 { 00701 /* Enable the main output */ 00702 __HAL_TIM_MOE_ENABLE(htim); 00703 } 00704 00705 /* Enable the Peripheral */ 00706 __HAL_TIM_ENABLE(htim); 00707 00708 /* Return function status */ 00709 return HAL_OK; 00710 } 00711 00712 /** 00713 * @brief Stops the TIM Output Compare signal generation in interrupt mode. 00714 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00715 * the configuration information for TIM module. 00716 * @param Channel TIM Channel to be disabled. 00717 * This parameter can be one of the following values: 00718 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00719 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00720 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00721 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 00722 * @retval HAL status 00723 */ 00724 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 00725 { 00726 /* Check the parameters */ 00727 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 00728 00729 switch (Channel) 00730 { 00731 case TIM_CHANNEL_1: 00732 { 00733 /* Disable the TIM Capture/Compare 1 interrupt */ 00734 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 00735 } 00736 break; 00737 00738 case TIM_CHANNEL_2: 00739 { 00740 /* Disable the TIM Capture/Compare 2 interrupt */ 00741 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 00742 } 00743 break; 00744 00745 case TIM_CHANNEL_3: 00746 { 00747 /* Disable the TIM Capture/Compare 3 interrupt */ 00748 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); 00749 } 00750 break; 00751 00752 case TIM_CHANNEL_4: 00753 { 00754 /* Disable the TIM Capture/Compare 4 interrupt */ 00755 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); 00756 } 00757 break; 00758 00759 default: 00760 break; 00761 } 00762 00763 /* Disable the Output compare channel */ 00764 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 00765 00766 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) 00767 { 00768 /* Disable the Main Output */ 00769 __HAL_TIM_MOE_DISABLE(htim); 00770 } 00771 00772 /* Disable the Peripheral */ 00773 __HAL_TIM_DISABLE(htim); 00774 00775 /* Return function status */ 00776 return HAL_OK; 00777 } 00778 00779 /** 00780 * @brief Starts the TIM Output Compare signal generation in DMA mode. 00781 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00782 * the configuration information for TIM module. 00783 * @param Channel TIM Channel to be enabled. 00784 * This parameter can be one of the following values: 00785 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00786 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00787 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00788 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 00789 * @param pData The source Buffer address. 00790 * @param Length The length of data to be transferred from memory to TIM peripheral 00791 * @retval HAL status 00792 */ 00793 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) 00794 { 00795 /* Check the parameters */ 00796 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 00797 00798 if((htim->State == HAL_TIM_STATE_BUSY)) 00799 { 00800 return HAL_BUSY; 00801 } 00802 else if((htim->State == HAL_TIM_STATE_READY)) 00803 { 00804 if(((uint32_t)pData == 0U) && (Length > 0)) 00805 { 00806 return HAL_ERROR; 00807 } 00808 else 00809 { 00810 htim->State = HAL_TIM_STATE_BUSY; 00811 } 00812 } 00813 switch (Channel) 00814 { 00815 case TIM_CHANNEL_1: 00816 { 00817 /* Set the DMA Period elapsed callback */ 00818 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; 00819 00820 /* Set the DMA error callback */ 00821 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 00822 00823 /* Enable the DMA Stream */ 00824 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); 00825 00826 /* Enable the TIM Capture/Compare 1 DMA request */ 00827 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 00828 } 00829 break; 00830 00831 case TIM_CHANNEL_2: 00832 { 00833 /* Set the DMA Period elapsed callback */ 00834 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; 00835 00836 /* Set the DMA error callback */ 00837 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 00838 00839 /* Enable the DMA Stream */ 00840 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); 00841 00842 /* Enable the TIM Capture/Compare 2 DMA request */ 00843 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 00844 } 00845 break; 00846 00847 case TIM_CHANNEL_3: 00848 { 00849 /* Set the DMA Period elapsed callback */ 00850 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; 00851 00852 /* Set the DMA error callback */ 00853 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 00854 00855 /* Enable the DMA Stream */ 00856 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); 00857 00858 /* Enable the TIM Capture/Compare 3 DMA request */ 00859 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); 00860 } 00861 break; 00862 00863 case TIM_CHANNEL_4: 00864 { 00865 /* Set the DMA Period elapsed callback */ 00866 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; 00867 00868 /* Set the DMA error callback */ 00869 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; 00870 00871 /* Enable the DMA Stream */ 00872 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); 00873 00874 /* Enable the TIM Capture/Compare 4 DMA request */ 00875 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); 00876 } 00877 break; 00878 00879 default: 00880 break; 00881 } 00882 00883 /* Enable the Output compare channel */ 00884 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 00885 00886 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) 00887 { 00888 /* Enable the main output */ 00889 __HAL_TIM_MOE_ENABLE(htim); 00890 } 00891 00892 /* Enable the Peripheral */ 00893 __HAL_TIM_ENABLE(htim); 00894 00895 /* Return function status */ 00896 return HAL_OK; 00897 } 00898 00899 /** 00900 * @brief Stops the TIM Output Compare signal generation in DMA mode. 00901 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00902 * the configuration information for TIM module. 00903 * @param Channel TIM Channel to be disabled. 00904 * This parameter can be one of the following values: 00905 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00906 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00907 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00908 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 00909 * @retval HAL status 00910 */ 00911 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) 00912 { 00913 /* Check the parameters */ 00914 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 00915 00916 switch (Channel) 00917 { 00918 case TIM_CHANNEL_1: 00919 { 00920 /* Disable the TIM Capture/Compare 1 DMA request */ 00921 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 00922 } 00923 break; 00924 00925 case TIM_CHANNEL_2: 00926 { 00927 /* Disable the TIM Capture/Compare 2 DMA request */ 00928 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 00929 } 00930 break; 00931 00932 case TIM_CHANNEL_3: 00933 { 00934 /* Disable the TIM Capture/Compare 3 DMA request */ 00935 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); 00936 } 00937 break; 00938 00939 case TIM_CHANNEL_4: 00940 { 00941 /* Disable the TIM Capture/Compare 4 interrupt */ 00942 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); 00943 } 00944 break; 00945 00946 default: 00947 break; 00948 } 00949 00950 /* Disable the Output compare channel */ 00951 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 00952 00953 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) 00954 { 00955 /* Disable the Main Output */ 00956 __HAL_TIM_MOE_DISABLE(htim); 00957 } 00958 00959 /* Disable the Peripheral */ 00960 __HAL_TIM_DISABLE(htim); 00961 00962 /* Change the htim state */ 00963 htim->State = HAL_TIM_STATE_READY; 00964 00965 /* Return function status */ 00966 return HAL_OK; 00967 } 00968 /** 00969 * @} 00970 */ 00971 00972 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions 00973 * @brief Time PWM functions 00974 * 00975 @verbatim 00976 ============================================================================== 00977 ##### Time PWM functions ##### 00978 ============================================================================== 00979 [..] 00980 This section provides functions allowing to: 00981 (+) Initialize and configure the TIM OPWM. 00982 (+) De-initialize the TIM PWM. 00983 (+) Start the Time PWM. 00984 (+) Stop the Time PWM. 00985 (+) Start the Time PWM and enable interrupt. 00986 (+) Stop the Time PWM and disable interrupt. 00987 (+) Start the Time PWM and enable DMA transfer. 00988 (+) Stop the Time PWM and disable DMA transfer. 00989 00990 @endverbatim 00991 * @{ 00992 */ 00993 /** 00994 * @brief Initializes the TIM PWM Time Base according to the specified 00995 * parameters in the TIM_HandleTypeDef and create the associated handle. 00996 * @param htim pointer to a TIM_HandleTypeDef structure that contains 00997 * the configuration information for TIM module. 00998 * @retval HAL status 00999 */ 01000 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) 01001 { 01002 /* Check the TIM handle allocation */ 01003 if(htim == NULL) 01004 { 01005 return HAL_ERROR; 01006 } 01007 01008 /* Check the parameters */ 01009 assert_param(IS_TIM_INSTANCE(htim->Instance)); 01010 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); 01011 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 01012 01013 if(htim->State == HAL_TIM_STATE_RESET) 01014 { 01015 /* Allocate lock resource and initialize it */ 01016 htim->Lock = HAL_UNLOCKED; 01017 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ 01018 HAL_TIM_PWM_MspInit(htim); 01019 } 01020 01021 /* Set the TIM state */ 01022 htim->State= HAL_TIM_STATE_BUSY; 01023 01024 /* Init the base time for the PWM */ 01025 TIM_Base_SetConfig(htim->Instance, &htim->Init); 01026 01027 /* Initialize the TIM state*/ 01028 htim->State= HAL_TIM_STATE_READY; 01029 01030 return HAL_OK; 01031 } 01032 01033 /** 01034 * @brief DeInitializes the TIM peripheral 01035 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01036 * the configuration information for TIM module. 01037 * @retval HAL status 01038 */ 01039 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) 01040 { 01041 /* Check the parameters */ 01042 assert_param(IS_TIM_INSTANCE(htim->Instance)); 01043 01044 htim->State = HAL_TIM_STATE_BUSY; 01045 01046 /* Disable the TIM Peripheral Clock */ 01047 __HAL_TIM_DISABLE(htim); 01048 01049 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ 01050 HAL_TIM_PWM_MspDeInit(htim); 01051 01052 /* Change TIM state */ 01053 htim->State = HAL_TIM_STATE_RESET; 01054 01055 /* Release Lock */ 01056 __HAL_UNLOCK(htim); 01057 01058 return HAL_OK; 01059 } 01060 01061 /** 01062 * @brief Initializes the TIM PWM MSP. 01063 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01064 * the configuration information for TIM module. 01065 * @retval None 01066 */ 01067 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) 01068 { 01069 /* Prevent unused argument(s) compilation warning */ 01070 UNUSED(htim); 01071 /* NOTE : This function Should not be modified, when the callback is needed, 01072 the HAL_TIM_PWM_MspInit could be implemented in the user file 01073 */ 01074 } 01075 01076 /** 01077 * @brief DeInitializes TIM PWM MSP. 01078 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01079 * the configuration information for TIM module. 01080 * @retval None 01081 */ 01082 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) 01083 { 01084 /* Prevent unused argument(s) compilation warning */ 01085 UNUSED(htim); 01086 /* NOTE : This function Should not be modified, when the callback is needed, 01087 the HAL_TIM_PWM_MspDeInit could be implemented in the user file 01088 */ 01089 } 01090 01091 /** 01092 * @brief Starts the PWM signal generation. 01093 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01094 * the configuration information for TIM module. 01095 * @param Channel TIM Channels to be enabled. 01096 * This parameter can be one of the following values: 01097 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01098 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01099 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01100 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01101 * @retval HAL status 01102 */ 01103 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) 01104 { 01105 /* Check the parameters */ 01106 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01107 01108 /* Enable the Capture compare channel */ 01109 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01110 01111 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) 01112 { 01113 /* Enable the main output */ 01114 __HAL_TIM_MOE_ENABLE(htim); 01115 } 01116 01117 /* Enable the Peripheral */ 01118 __HAL_TIM_ENABLE(htim); 01119 01120 /* Return function status */ 01121 return HAL_OK; 01122 } 01123 01124 /** 01125 * @brief Stops the PWM signal generation. 01126 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01127 * the configuration information for TIM module. 01128 * @param Channel TIM Channels to be disabled. 01129 * This parameter can be one of the following values: 01130 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01131 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01132 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01133 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01134 * @retval HAL status 01135 */ 01136 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) 01137 { 01138 /* Check the parameters */ 01139 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01140 01141 /* Disable the Capture compare channel */ 01142 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01143 01144 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) 01145 { 01146 /* Disable the Main Output */ 01147 __HAL_TIM_MOE_DISABLE(htim); 01148 } 01149 01150 /* Disable the Peripheral */ 01151 __HAL_TIM_DISABLE(htim); 01152 01153 /* Change the htim state */ 01154 htim->State = HAL_TIM_STATE_READY; 01155 01156 /* Return function status */ 01157 return HAL_OK; 01158 } 01159 01160 /** 01161 * @brief Starts the PWM signal generation in interrupt mode. 01162 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01163 * the configuration information for TIM module. 01164 * @param Channel TIM Channel to be enabled. 01165 * This parameter can be one of the following values: 01166 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01167 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01168 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01169 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01170 * @retval HAL status 01171 */ 01172 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 01173 { 01174 /* Check the parameters */ 01175 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01176 01177 switch (Channel) 01178 { 01179 case TIM_CHANNEL_1: 01180 { 01181 /* Enable the TIM Capture/Compare 1 interrupt */ 01182 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 01183 } 01184 break; 01185 01186 case TIM_CHANNEL_2: 01187 { 01188 /* Enable the TIM Capture/Compare 2 interrupt */ 01189 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 01190 } 01191 break; 01192 01193 case TIM_CHANNEL_3: 01194 { 01195 /* Enable the TIM Capture/Compare 3 interrupt */ 01196 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 01197 } 01198 break; 01199 01200 case TIM_CHANNEL_4: 01201 { 01202 /* Enable the TIM Capture/Compare 4 interrupt */ 01203 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 01204 } 01205 break; 01206 01207 default: 01208 break; 01209 } 01210 01211 /* Enable the Capture compare channel */ 01212 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01213 01214 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) 01215 { 01216 /* Enable the main output */ 01217 __HAL_TIM_MOE_ENABLE(htim); 01218 } 01219 01220 /* Enable the Peripheral */ 01221 __HAL_TIM_ENABLE(htim); 01222 01223 /* Return function status */ 01224 return HAL_OK; 01225 } 01226 01227 /** 01228 * @brief Stops the PWM signal generation in interrupt mode. 01229 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01230 * the configuration information for TIM module. 01231 * @param Channel TIM Channels to be disabled. 01232 * This parameter can be one of the following values: 01233 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01234 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01235 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01236 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01237 * @retval HAL status 01238 */ 01239 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) 01240 { 01241 /* Check the parameters */ 01242 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01243 01244 switch (Channel) 01245 { 01246 case TIM_CHANNEL_1: 01247 { 01248 /* Disable the TIM Capture/Compare 1 interrupt */ 01249 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 01250 } 01251 break; 01252 01253 case TIM_CHANNEL_2: 01254 { 01255 /* Disable the TIM Capture/Compare 2 interrupt */ 01256 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 01257 } 01258 break; 01259 01260 case TIM_CHANNEL_3: 01261 { 01262 /* Disable the TIM Capture/Compare 3 interrupt */ 01263 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); 01264 } 01265 break; 01266 01267 case TIM_CHANNEL_4: 01268 { 01269 /* Disable the TIM Capture/Compare 4 interrupt */ 01270 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); 01271 } 01272 break; 01273 01274 default: 01275 break; 01276 } 01277 01278 /* Disable the Capture compare channel */ 01279 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01280 01281 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) 01282 { 01283 /* Disable the Main Output */ 01284 __HAL_TIM_MOE_DISABLE(htim); 01285 } 01286 01287 /* Disable the Peripheral */ 01288 __HAL_TIM_DISABLE(htim); 01289 01290 /* Return function status */ 01291 return HAL_OK; 01292 } 01293 01294 /** 01295 * @brief Starts the TIM PWM signal generation in DMA mode. 01296 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01297 * the configuration information for TIM module. 01298 * @param Channel TIM Channels to be enabled. 01299 * This parameter can be one of the following values: 01300 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01301 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01302 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01303 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01304 * @param pData The source Buffer address. 01305 * @param Length The length of data to be transferred from memory to TIM peripheral 01306 * @retval HAL status 01307 */ 01308 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) 01309 { 01310 /* Check the parameters */ 01311 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01312 01313 if((htim->State == HAL_TIM_STATE_BUSY)) 01314 { 01315 return HAL_BUSY; 01316 } 01317 else if((htim->State == HAL_TIM_STATE_READY)) 01318 { 01319 if(((uint32_t)pData == 0U) && (Length > 0)) 01320 { 01321 return HAL_ERROR; 01322 } 01323 else 01324 { 01325 htim->State = HAL_TIM_STATE_BUSY; 01326 } 01327 } 01328 switch (Channel) 01329 { 01330 case TIM_CHANNEL_1: 01331 { 01332 /* Set the DMA Period elapsed callback */ 01333 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; 01334 01335 /* Set the DMA error callback */ 01336 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 01337 01338 /* Enable the DMA Stream */ 01339 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); 01340 01341 /* Enable the TIM Capture/Compare 1 DMA request */ 01342 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 01343 } 01344 break; 01345 01346 case TIM_CHANNEL_2: 01347 { 01348 /* Set the DMA Period elapsed callback */ 01349 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; 01350 01351 /* Set the DMA error callback */ 01352 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 01353 01354 /* Enable the DMA Stream */ 01355 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); 01356 01357 /* Enable the TIM Capture/Compare 2 DMA request */ 01358 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 01359 } 01360 break; 01361 01362 case TIM_CHANNEL_3: 01363 { 01364 /* Set the DMA Period elapsed callback */ 01365 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; 01366 01367 /* Set the DMA error callback */ 01368 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 01369 01370 /* Enable the DMA Stream */ 01371 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); 01372 01373 /* Enable the TIM Output Capture/Compare 3 request */ 01374 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); 01375 } 01376 break; 01377 01378 case TIM_CHANNEL_4: 01379 { 01380 /* Set the DMA Period elapsed callback */ 01381 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; 01382 01383 /* Set the DMA error callback */ 01384 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; 01385 01386 /* Enable the DMA Stream */ 01387 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); 01388 01389 /* Enable the TIM Capture/Compare 4 DMA request */ 01390 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); 01391 } 01392 break; 01393 01394 default: 01395 break; 01396 } 01397 01398 /* Enable the Capture compare channel */ 01399 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01400 01401 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) 01402 { 01403 /* Enable the main output */ 01404 __HAL_TIM_MOE_ENABLE(htim); 01405 } 01406 01407 /* Enable the Peripheral */ 01408 __HAL_TIM_ENABLE(htim); 01409 01410 /* Return function status */ 01411 return HAL_OK; 01412 } 01413 01414 /** 01415 * @brief Stops the TIM PWM signal generation in DMA mode. 01416 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01417 * the configuration information for TIM module. 01418 * @param Channel TIM Channels to be disabled. 01419 * This parameter can be one of the following values: 01420 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01421 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01422 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01423 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01424 * @retval HAL status 01425 */ 01426 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) 01427 { 01428 /* Check the parameters */ 01429 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01430 01431 switch (Channel) 01432 { 01433 case TIM_CHANNEL_1: 01434 { 01435 /* Disable the TIM Capture/Compare 1 DMA request */ 01436 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 01437 } 01438 break; 01439 01440 case TIM_CHANNEL_2: 01441 { 01442 /* Disable the TIM Capture/Compare 2 DMA request */ 01443 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 01444 } 01445 break; 01446 01447 case TIM_CHANNEL_3: 01448 { 01449 /* Disable the TIM Capture/Compare 3 DMA request */ 01450 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); 01451 } 01452 break; 01453 01454 case TIM_CHANNEL_4: 01455 { 01456 /* Disable the TIM Capture/Compare 4 interrupt */ 01457 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); 01458 } 01459 break; 01460 01461 default: 01462 break; 01463 } 01464 01465 /* Disable the Capture compare channel */ 01466 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01467 01468 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) 01469 { 01470 /* Disable the Main Output */ 01471 __HAL_TIM_MOE_DISABLE(htim); 01472 } 01473 01474 /* Disable the Peripheral */ 01475 __HAL_TIM_DISABLE(htim); 01476 01477 /* Change the htim state */ 01478 htim->State = HAL_TIM_STATE_READY; 01479 01480 /* Return function status */ 01481 return HAL_OK; 01482 } 01483 /** 01484 * @} 01485 */ 01486 01487 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions 01488 * @brief Time Input Capture functions 01489 * 01490 @verbatim 01491 ============================================================================== 01492 ##### Time Input Capture functions ##### 01493 ============================================================================== 01494 [..] 01495 This section provides functions allowing to: 01496 (+) Initialize and configure the TIM Input Capture. 01497 (+) De-initialize the TIM Input Capture. 01498 (+) Start the Time Input Capture. 01499 (+) Stop the Time Input Capture. 01500 (+) Start the Time Input Capture and enable interrupt. 01501 (+) Stop the Time Input Capture and disable interrupt. 01502 (+) Start the Time Input Capture and enable DMA transfer. 01503 (+) Stop the Time Input Capture and disable DMA transfer. 01504 01505 @endverbatim 01506 * @{ 01507 */ 01508 /** 01509 * @brief Initializes the TIM Input Capture Time base according to the specified 01510 * parameters in the TIM_HandleTypeDef and create the associated handle. 01511 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01512 * the configuration information for TIM module. 01513 * @retval HAL status 01514 */ 01515 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) 01516 { 01517 /* Check the TIM handle allocation */ 01518 if(htim == NULL) 01519 { 01520 return HAL_ERROR; 01521 } 01522 01523 /* Check the parameters */ 01524 assert_param(IS_TIM_INSTANCE(htim->Instance)); 01525 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); 01526 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 01527 01528 if(htim->State == HAL_TIM_STATE_RESET) 01529 { 01530 /* Allocate lock resource and initialize it */ 01531 htim->Lock = HAL_UNLOCKED; 01532 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ 01533 HAL_TIM_IC_MspInit(htim); 01534 } 01535 01536 /* Set the TIM state */ 01537 htim->State= HAL_TIM_STATE_BUSY; 01538 01539 /* Init the base time for the input capture */ 01540 TIM_Base_SetConfig(htim->Instance, &htim->Init); 01541 01542 /* Initialize the TIM state*/ 01543 htim->State= HAL_TIM_STATE_READY; 01544 01545 return HAL_OK; 01546 } 01547 01548 /** 01549 * @brief DeInitializes the TIM peripheral 01550 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01551 * the configuration information for TIM module. 01552 * @retval HAL status 01553 */ 01554 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) 01555 { 01556 /* Check the parameters */ 01557 assert_param(IS_TIM_INSTANCE(htim->Instance)); 01558 01559 htim->State = HAL_TIM_STATE_BUSY; 01560 01561 /* Disable the TIM Peripheral Clock */ 01562 __HAL_TIM_DISABLE(htim); 01563 01564 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ 01565 HAL_TIM_IC_MspDeInit(htim); 01566 01567 /* Change TIM state */ 01568 htim->State = HAL_TIM_STATE_RESET; 01569 01570 /* Release Lock */ 01571 __HAL_UNLOCK(htim); 01572 01573 return HAL_OK; 01574 } 01575 01576 /** 01577 * @brief Initializes the TIM INput Capture MSP. 01578 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01579 * the configuration information for TIM module. 01580 * @retval None 01581 */ 01582 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) 01583 { 01584 /* Prevent unused argument(s) compilation warning */ 01585 UNUSED(htim); 01586 /* NOTE : This function Should not be modified, when the callback is needed, 01587 the HAL_TIM_IC_MspInit could be implemented in the user file 01588 */ 01589 } 01590 01591 /** 01592 * @brief DeInitializes TIM Input Capture MSP. 01593 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01594 * the configuration information for TIM module. 01595 * @retval None 01596 */ 01597 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) 01598 { 01599 /* Prevent unused argument(s) compilation warning */ 01600 UNUSED(htim); 01601 /* NOTE : This function Should not be modified, when the callback is needed, 01602 the HAL_TIM_IC_MspDeInit could be implemented in the user file 01603 */ 01604 } 01605 01606 /** 01607 * @brief Starts the TIM Input Capture measurement. 01608 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01609 * the configuration information for TIM module. 01610 * @param Channel TIM Channels to be enabled. 01611 * This parameter can be one of the following values: 01612 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01613 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01614 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01615 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01616 * @retval HAL status 01617 */ 01618 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) 01619 { 01620 /* Check the parameters */ 01621 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01622 01623 /* Enable the Input Capture channel */ 01624 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01625 01626 /* Enable the Peripheral */ 01627 __HAL_TIM_ENABLE(htim); 01628 01629 /* Return function status */ 01630 return HAL_OK; 01631 } 01632 01633 /** 01634 * @brief Stops the TIM Input Capture measurement. 01635 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01636 * the configuration information for TIM module. 01637 * @param Channel TIM Channels to be disabled. 01638 * This parameter can be one of the following values: 01639 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01640 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01641 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01642 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01643 * @retval HAL status 01644 */ 01645 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) 01646 { 01647 /* Check the parameters */ 01648 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01649 01650 /* Disable the Input Capture channel */ 01651 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01652 01653 /* Disable the Peripheral */ 01654 __HAL_TIM_DISABLE(htim); 01655 01656 /* Return function status */ 01657 return HAL_OK; 01658 } 01659 01660 /** 01661 * @brief Starts the TIM Input Capture measurement in interrupt mode. 01662 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01663 * the configuration information for TIM module. 01664 * @param Channel TIM Channels to be enabled. 01665 * This parameter can be one of the following values: 01666 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01667 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01668 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01669 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01670 * @retval HAL status 01671 */ 01672 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) 01673 { 01674 /* Check the parameters */ 01675 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01676 01677 switch (Channel) 01678 { 01679 case TIM_CHANNEL_1: 01680 { 01681 /* Enable the TIM Capture/Compare 1 interrupt */ 01682 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 01683 } 01684 break; 01685 01686 case TIM_CHANNEL_2: 01687 { 01688 /* Enable the TIM Capture/Compare 2 interrupt */ 01689 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 01690 } 01691 break; 01692 01693 case TIM_CHANNEL_3: 01694 { 01695 /* Enable the TIM Capture/Compare 3 interrupt */ 01696 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 01697 } 01698 break; 01699 01700 case TIM_CHANNEL_4: 01701 { 01702 /* Enable the TIM Capture/Compare 4 interrupt */ 01703 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 01704 } 01705 break; 01706 01707 default: 01708 break; 01709 } 01710 /* Enable the Input Capture channel */ 01711 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01712 01713 /* Enable the Peripheral */ 01714 __HAL_TIM_ENABLE(htim); 01715 01716 /* Return function status */ 01717 return HAL_OK; 01718 } 01719 01720 /** 01721 * @brief Stops the TIM Input Capture measurement in interrupt mode. 01722 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01723 * the configuration information for TIM module. 01724 * @param Channel TIM Channels to be disabled. 01725 * This parameter can be one of the following values: 01726 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01727 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01728 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01729 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01730 * @retval HAL status 01731 */ 01732 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 01733 { 01734 /* Check the parameters */ 01735 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01736 01737 switch (Channel) 01738 { 01739 case TIM_CHANNEL_1: 01740 { 01741 /* Disable the TIM Capture/Compare 1 interrupt */ 01742 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 01743 } 01744 break; 01745 01746 case TIM_CHANNEL_2: 01747 { 01748 /* Disable the TIM Capture/Compare 2 interrupt */ 01749 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 01750 } 01751 break; 01752 01753 case TIM_CHANNEL_3: 01754 { 01755 /* Disable the TIM Capture/Compare 3 interrupt */ 01756 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); 01757 } 01758 break; 01759 01760 case TIM_CHANNEL_4: 01761 { 01762 /* Disable the TIM Capture/Compare 4 interrupt */ 01763 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); 01764 } 01765 break; 01766 01767 default: 01768 break; 01769 } 01770 01771 /* Disable the Input Capture channel */ 01772 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01773 01774 /* Disable the Peripheral */ 01775 __HAL_TIM_DISABLE(htim); 01776 01777 /* Return function status */ 01778 return HAL_OK; 01779 } 01780 01781 /** 01782 * @brief Starts the TIM Input Capture measurement on in DMA mode. 01783 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01784 * the configuration information for TIM module. 01785 * @param Channel TIM Channels to be enabled. 01786 * This parameter can be one of the following values: 01787 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01788 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01789 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01790 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01791 * @param pData The destination Buffer address. 01792 * @param Length The length of data to be transferred from TIM peripheral to memory. 01793 * @retval HAL status 01794 */ 01795 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) 01796 { 01797 /* Check the parameters */ 01798 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01799 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); 01800 01801 if((htim->State == HAL_TIM_STATE_BUSY)) 01802 { 01803 return HAL_BUSY; 01804 } 01805 else if((htim->State == HAL_TIM_STATE_READY)) 01806 { 01807 if((pData == 0U) && (Length > 0)) 01808 { 01809 return HAL_ERROR; 01810 } 01811 else 01812 { 01813 htim->State = HAL_TIM_STATE_BUSY; 01814 } 01815 } 01816 01817 switch (Channel) 01818 { 01819 case TIM_CHANNEL_1: 01820 { 01821 /* Set the DMA Period elapsed callback */ 01822 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; 01823 01824 /* Set the DMA error callback */ 01825 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 01826 01827 /* Enable the DMA Stream */ 01828 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); 01829 01830 /* Enable the TIM Capture/Compare 1 DMA request */ 01831 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 01832 } 01833 break; 01834 01835 case TIM_CHANNEL_2: 01836 { 01837 /* Set the DMA Period elapsed callback */ 01838 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; 01839 01840 /* Set the DMA error callback */ 01841 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 01842 01843 /* Enable the DMA Stream */ 01844 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); 01845 01846 /* Enable the TIM Capture/Compare 2 DMA request */ 01847 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 01848 } 01849 break; 01850 01851 case TIM_CHANNEL_3: 01852 { 01853 /* Set the DMA Period elapsed callback */ 01854 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; 01855 01856 /* Set the DMA error callback */ 01857 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 01858 01859 /* Enable the DMA Stream */ 01860 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); 01861 01862 /* Enable the TIM Capture/Compare 3 DMA request */ 01863 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); 01864 } 01865 break; 01866 01867 case TIM_CHANNEL_4: 01868 { 01869 /* Set the DMA Period elapsed callback */ 01870 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; 01871 01872 /* Set the DMA error callback */ 01873 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; 01874 01875 /* Enable the DMA Stream */ 01876 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); 01877 01878 /* Enable the TIM Capture/Compare 4 DMA request */ 01879 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); 01880 } 01881 break; 01882 01883 default: 01884 break; 01885 } 01886 01887 /* Enable the Input Capture channel */ 01888 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01889 01890 /* Enable the Peripheral */ 01891 __HAL_TIM_ENABLE(htim); 01892 01893 /* Return function status */ 01894 return HAL_OK; 01895 } 01896 01897 /** 01898 * @brief Stops the TIM Input Capture measurement on in DMA mode. 01899 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01900 * the configuration information for TIM module. 01901 * @param Channel TIM Channels to be disabled. 01902 * This parameter can be one of the following values: 01903 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01904 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01905 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01906 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01907 * @retval HAL status 01908 */ 01909 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) 01910 { 01911 /* Check the parameters */ 01912 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01913 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); 01914 01915 switch (Channel) 01916 { 01917 case TIM_CHANNEL_1: 01918 { 01919 /* Disable the TIM Capture/Compare 1 DMA request */ 01920 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 01921 } 01922 break; 01923 01924 case TIM_CHANNEL_2: 01925 { 01926 /* Disable the TIM Capture/Compare 2 DMA request */ 01927 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 01928 } 01929 break; 01930 01931 case TIM_CHANNEL_3: 01932 { 01933 /* Disable the TIM Capture/Compare 3 DMA request */ 01934 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); 01935 } 01936 break; 01937 01938 case TIM_CHANNEL_4: 01939 { 01940 /* Disable the TIM Capture/Compare 4 DMA request */ 01941 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); 01942 } 01943 break; 01944 01945 default: 01946 break; 01947 } 01948 01949 /* Disable the Input Capture channel */ 01950 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01951 01952 /* Disable the Peripheral */ 01953 __HAL_TIM_DISABLE(htim); 01954 01955 /* Change the htim state */ 01956 htim->State = HAL_TIM_STATE_READY; 01957 01958 /* Return function status */ 01959 return HAL_OK; 01960 } 01961 /** 01962 * @} 01963 */ 01964 01965 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions 01966 * @brief Time One Pulse functions 01967 * 01968 @verbatim 01969 ============================================================================== 01970 ##### Time One Pulse functions ##### 01971 ============================================================================== 01972 [..] 01973 This section provides functions allowing to: 01974 (+) Initialize and configure the TIM One Pulse. 01975 (+) De-initialize the TIM One Pulse. 01976 (+) Start the Time One Pulse. 01977 (+) Stop the Time One Pulse. 01978 (+) Start the Time One Pulse and enable interrupt. 01979 (+) Stop the Time One Pulse and disable interrupt. 01980 (+) Start the Time One Pulse and enable DMA transfer. 01981 (+) Stop the Time One Pulse and disable DMA transfer. 01982 01983 @endverbatim 01984 * @{ 01985 */ 01986 /** 01987 * @brief Initializes the TIM One Pulse Time Base according to the specified 01988 * parameters in the TIM_HandleTypeDef and create the associated handle. 01989 * @param htim pointer to a TIM_HandleTypeDef structure that contains 01990 * the configuration information for TIM module. 01991 * @param OnePulseMode Select the One pulse mode. 01992 * This parameter can be one of the following values: 01993 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. 01994 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. 01995 * @retval HAL status 01996 */ 01997 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) 01998 { 01999 /* Check the TIM handle allocation */ 02000 if(htim == NULL) 02001 { 02002 return HAL_ERROR; 02003 } 02004 02005 /* Check the parameters */ 02006 assert_param(IS_TIM_INSTANCE(htim->Instance)); 02007 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); 02008 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 02009 assert_param(IS_TIM_OPM_MODE(OnePulseMode)); 02010 02011 if(htim->State == HAL_TIM_STATE_RESET) 02012 { 02013 /* Allocate lock resource and initialize it */ 02014 htim->Lock = HAL_UNLOCKED; 02015 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ 02016 HAL_TIM_OnePulse_MspInit(htim); 02017 } 02018 02019 /* Set the TIM state */ 02020 htim->State= HAL_TIM_STATE_BUSY; 02021 02022 /* Configure the Time base in the One Pulse Mode */ 02023 TIM_Base_SetConfig(htim->Instance, &htim->Init); 02024 02025 /* Reset the OPM Bit */ 02026 htim->Instance->CR1 &= ~TIM_CR1_OPM; 02027 02028 /* Configure the OPM Mode */ 02029 htim->Instance->CR1 |= OnePulseMode; 02030 02031 /* Initialize the TIM state*/ 02032 htim->State= HAL_TIM_STATE_READY; 02033 02034 return HAL_OK; 02035 } 02036 02037 /** 02038 * @brief DeInitializes the TIM One Pulse 02039 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02040 * the configuration information for TIM module. 02041 * @retval HAL status 02042 */ 02043 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) 02044 { 02045 /* Check the parameters */ 02046 assert_param(IS_TIM_INSTANCE(htim->Instance)); 02047 02048 htim->State = HAL_TIM_STATE_BUSY; 02049 02050 /* Disable the TIM Peripheral Clock */ 02051 __HAL_TIM_DISABLE(htim); 02052 02053 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ 02054 HAL_TIM_OnePulse_MspDeInit(htim); 02055 02056 /* Change TIM state */ 02057 htim->State = HAL_TIM_STATE_RESET; 02058 02059 /* Release Lock */ 02060 __HAL_UNLOCK(htim); 02061 02062 return HAL_OK; 02063 } 02064 02065 /** 02066 * @brief Initializes the TIM One Pulse MSP. 02067 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02068 * the configuration information for TIM module. 02069 * @retval None 02070 */ 02071 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) 02072 { 02073 /* Prevent unused argument(s) compilation warning */ 02074 UNUSED(htim); 02075 /* NOTE : This function Should not be modified, when the callback is needed, 02076 the HAL_TIM_OnePulse_MspInit could be implemented in the user file 02077 */ 02078 } 02079 02080 /** 02081 * @brief DeInitializes TIM One Pulse MSP. 02082 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02083 * the configuration information for TIM module. 02084 * @retval None 02085 */ 02086 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) 02087 { 02088 /* Prevent unused argument(s) compilation warning */ 02089 UNUSED(htim); 02090 /* NOTE : This function Should not be modified, when the callback is needed, 02091 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file 02092 */ 02093 } 02094 02095 /** 02096 * @brief Starts the TIM One Pulse signal generation. 02097 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02098 * the configuration information for TIM module. 02099 * @param OutputChannel TIM Channels to be enabled. 02100 * This parameter can be one of the following values: 02101 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02102 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02103 * @retval HAL status 02104 */ 02105 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) 02106 { 02107 /* Prevent unused argument(s) compilation warning */ 02108 UNUSED(OutputChannel); 02109 02110 /* Enable the Capture compare and the Input Capture channels 02111 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) 02112 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and 02113 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 02114 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together 02115 02116 No need to enable the counter, it's enabled automatically by hardware 02117 (the counter starts in response to a stimulus and generate a pulse */ 02118 02119 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02120 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02121 02122 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) 02123 { 02124 /* Enable the main output */ 02125 __HAL_TIM_MOE_ENABLE(htim); 02126 } 02127 02128 /* Return function status */ 02129 return HAL_OK; 02130 } 02131 02132 /** 02133 * @brief Stops the TIM One Pulse signal generation. 02134 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02135 * the configuration information for TIM module. 02136 * @param OutputChannel TIM Channels to be disable. 02137 * This parameter can be one of the following values: 02138 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02139 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02140 * @retval HAL status 02141 */ 02142 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) 02143 { 02144 /* Prevent unused argument(s) compilation warning */ 02145 UNUSED(OutputChannel); 02146 02147 /* Disable the Capture compare and the Input Capture channels 02148 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) 02149 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and 02150 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 02151 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ 02152 02153 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02154 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02155 02156 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) 02157 { 02158 /* Disable the Main Output */ 02159 __HAL_TIM_MOE_DISABLE(htim); 02160 } 02161 02162 /* Disable the Peripheral */ 02163 __HAL_TIM_DISABLE(htim); 02164 02165 /* Return function status */ 02166 return HAL_OK; 02167 } 02168 02169 /** 02170 * @brief Starts the TIM One Pulse signal generation in interrupt mode. 02171 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02172 * the configuration information for TIM module. 02173 * @param OutputChannel TIM Channels to be enabled. 02174 * This parameter can be one of the following values: 02175 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02176 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02177 * @retval HAL status 02178 */ 02179 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) 02180 { 02181 /* Enable the Capture compare and the Input Capture channels 02182 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) 02183 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and 02184 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 02185 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together 02186 02187 No need to enable the counter, it's enabled automatically by hardware 02188 (the counter starts in response to a stimulus and generate a pulse */ 02189 02190 /* Prevent unused argument(s) compilation warning */ 02191 UNUSED(OutputChannel); 02192 02193 /* Enable the TIM Capture/Compare 1 interrupt */ 02194 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 02195 02196 /* Enable the TIM Capture/Compare 2 interrupt */ 02197 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 02198 02199 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02200 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02201 02202 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) 02203 { 02204 /* Enable the main output */ 02205 __HAL_TIM_MOE_ENABLE(htim); 02206 } 02207 02208 /* Return function status */ 02209 return HAL_OK; 02210 } 02211 02212 /** 02213 * @brief Stops the TIM One Pulse signal generation in interrupt mode. 02214 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02215 * the configuration information for TIM module. 02216 * @param OutputChannel TIM Channels to be enabled. 02217 * This parameter can be one of the following values: 02218 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02219 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02220 * @retval HAL status 02221 */ 02222 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) 02223 { 02224 /* Prevent unused argument(s) compilation warning */ 02225 UNUSED(OutputChannel); 02226 02227 /* Disable the TIM Capture/Compare 1 interrupt */ 02228 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 02229 02230 /* Disable the TIM Capture/Compare 2 interrupt */ 02231 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 02232 02233 /* Disable the Capture compare and the Input Capture channels 02234 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) 02235 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and 02236 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 02237 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ 02238 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02239 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02240 02241 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET) 02242 { 02243 /* Disable the Main Output */ 02244 __HAL_TIM_MOE_DISABLE(htim); 02245 } 02246 02247 /* Disable the Peripheral */ 02248 __HAL_TIM_DISABLE(htim); 02249 02250 /* Return function status */ 02251 return HAL_OK; 02252 } 02253 /** 02254 * @} 02255 */ 02256 02257 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions 02258 * @brief Time Encoder functions 02259 * 02260 @verbatim 02261 ============================================================================== 02262 ##### Time Encoder functions ##### 02263 ============================================================================== 02264 [..] 02265 This section provides functions allowing to: 02266 (+) Initialize and configure the TIM Encoder. 02267 (+) De-initialize the TIM Encoder. 02268 (+) Start the Time Encoder. 02269 (+) Stop the Time Encoder. 02270 (+) Start the Time Encoder and enable interrupt. 02271 (+) Stop the Time Encoder and disable interrupt. 02272 (+) Start the Time Encoder and enable DMA transfer. 02273 (+) Stop the Time Encoder and disable DMA transfer. 02274 02275 @endverbatim 02276 * @{ 02277 */ 02278 /** 02279 * @brief Initializes the TIM Encoder Interface and create the associated handle. 02280 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02281 * the configuration information for TIM module. 02282 * @param sConfig TIM Encoder Interface configuration structure 02283 * @retval HAL status 02284 */ 02285 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) 02286 { 02287 uint32_t tmpsmcr = 0U; 02288 uint32_t tmpccmr1 = 0U; 02289 uint32_t tmpccer = 0U; 02290 02291 /* Check the TIM handle allocation */ 02292 if(htim == NULL) 02293 { 02294 return HAL_ERROR; 02295 } 02296 02297 /* Check the parameters */ 02298 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 02299 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); 02300 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); 02301 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); 02302 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); 02303 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); 02304 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); 02305 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); 02306 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); 02307 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); 02308 02309 if(htim->State == HAL_TIM_STATE_RESET) 02310 { 02311 /* Allocate lock resource and initialize it */ 02312 htim->Lock = HAL_UNLOCKED; 02313 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ 02314 HAL_TIM_Encoder_MspInit(htim); 02315 } 02316 02317 /* Set the TIM state */ 02318 htim->State= HAL_TIM_STATE_BUSY; 02319 02320 /* Reset the SMS bits */ 02321 htim->Instance->SMCR &= ~TIM_SMCR_SMS; 02322 02323 /* Configure the Time base in the Encoder Mode */ 02324 TIM_Base_SetConfig(htim->Instance, &htim->Init); 02325 02326 /* Get the TIMx SMCR register value */ 02327 tmpsmcr = htim->Instance->SMCR; 02328 02329 /* Get the TIMx CCMR1 register value */ 02330 tmpccmr1 = htim->Instance->CCMR1; 02331 02332 /* Get the TIMx CCER register value */ 02333 tmpccer = htim->Instance->CCER; 02334 02335 /* Set the encoder Mode */ 02336 tmpsmcr |= sConfig->EncoderMode; 02337 02338 /* Select the Capture Compare 1 and the Capture Compare 2 as input */ 02339 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); 02340 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); 02341 02342 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ 02343 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); 02344 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); 02345 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); 02346 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); 02347 02348 /* Set the TI1 and the TI2 Polarities */ 02349 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); 02350 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); 02351 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); 02352 02353 /* Write to TIMx SMCR */ 02354 htim->Instance->SMCR = tmpsmcr; 02355 02356 /* Write to TIMx CCMR1 */ 02357 htim->Instance->CCMR1 = tmpccmr1; 02358 02359 /* Write to TIMx CCER */ 02360 htim->Instance->CCER = tmpccer; 02361 02362 /* Initialize the TIM state*/ 02363 htim->State= HAL_TIM_STATE_READY; 02364 02365 return HAL_OK; 02366 } 02367 02368 /** 02369 * @brief DeInitializes the TIM Encoder interface 02370 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02371 * the configuration information for TIM module. 02372 * @retval HAL status 02373 */ 02374 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) 02375 { 02376 /* Check the parameters */ 02377 assert_param(IS_TIM_INSTANCE(htim->Instance)); 02378 02379 htim->State = HAL_TIM_STATE_BUSY; 02380 02381 /* Disable the TIM Peripheral Clock */ 02382 __HAL_TIM_DISABLE(htim); 02383 02384 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ 02385 HAL_TIM_Encoder_MspDeInit(htim); 02386 02387 /* Change TIM state */ 02388 htim->State = HAL_TIM_STATE_RESET; 02389 02390 /* Release Lock */ 02391 __HAL_UNLOCK(htim); 02392 02393 return HAL_OK; 02394 } 02395 02396 /** 02397 * @brief Initializes the TIM Encoder Interface MSP. 02398 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02399 * the configuration information for TIM module. 02400 * @retval None 02401 */ 02402 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) 02403 { 02404 /* Prevent unused argument(s) compilation warning */ 02405 UNUSED(htim); 02406 /* NOTE : This function Should not be modified, when the callback is needed, 02407 the HAL_TIM_Encoder_MspInit could be implemented in the user file 02408 */ 02409 } 02410 02411 /** 02412 * @brief DeInitializes TIM Encoder Interface MSP. 02413 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02414 * the configuration information for TIM module. 02415 * @retval None 02416 */ 02417 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) 02418 { 02419 /* Prevent unused argument(s) compilation warning */ 02420 UNUSED(htim); 02421 /* NOTE : This function Should not be modified, when the callback is needed, 02422 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file 02423 */ 02424 } 02425 02426 /** 02427 * @brief Starts the TIM Encoder Interface. 02428 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02429 * the configuration information for TIM module. 02430 * @param Channel TIM Channels to be enabled. 02431 * This parameter can be one of the following values: 02432 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02433 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02434 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 02435 * @retval HAL status 02436 */ 02437 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) 02438 { 02439 /* Check the parameters */ 02440 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 02441 02442 /* Enable the encoder interface channels */ 02443 switch (Channel) 02444 { 02445 case TIM_CHANNEL_1: 02446 { 02447 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02448 break; 02449 } 02450 case TIM_CHANNEL_2: 02451 { 02452 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02453 break; 02454 } 02455 default : 02456 { 02457 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02458 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02459 break; 02460 } 02461 } 02462 /* Enable the Peripheral */ 02463 __HAL_TIM_ENABLE(htim); 02464 02465 /* Return function status */ 02466 return HAL_OK; 02467 } 02468 02469 /** 02470 * @brief Stops the TIM Encoder Interface. 02471 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02472 * the configuration information for TIM module. 02473 * @param Channel TIM Channels to be disabled. 02474 * This parameter can be one of the following values: 02475 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02476 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02477 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 02478 * @retval HAL status 02479 */ 02480 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) 02481 { 02482 /* Check the parameters */ 02483 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 02484 02485 /* Disable the Input Capture channels 1 and 2 02486 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 02487 switch (Channel) 02488 { 02489 case TIM_CHANNEL_1: 02490 { 02491 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02492 break; 02493 } 02494 case TIM_CHANNEL_2: 02495 { 02496 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02497 break; 02498 } 02499 default : 02500 { 02501 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02502 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02503 break; 02504 } 02505 } 02506 /* Disable the Peripheral */ 02507 __HAL_TIM_DISABLE(htim); 02508 02509 /* Return function status */ 02510 return HAL_OK; 02511 } 02512 02513 /** 02514 * @brief Starts the TIM Encoder Interface in interrupt mode. 02515 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02516 * the configuration information for TIM module. 02517 * @param Channel TIM Channels to be enabled. 02518 * This parameter can be one of the following values: 02519 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02520 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02521 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 02522 * @retval HAL status 02523 */ 02524 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 02525 { 02526 /* Check the parameters */ 02527 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 02528 02529 /* Enable the encoder interface channels */ 02530 /* Enable the capture compare Interrupts 1 and/or 2 */ 02531 switch (Channel) 02532 { 02533 case TIM_CHANNEL_1: 02534 { 02535 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02536 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 02537 break; 02538 } 02539 case TIM_CHANNEL_2: 02540 { 02541 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02542 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 02543 break; 02544 } 02545 default : 02546 { 02547 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02548 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02549 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 02550 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 02551 break; 02552 } 02553 } 02554 02555 /* Enable the Peripheral */ 02556 __HAL_TIM_ENABLE(htim); 02557 02558 /* Return function status */ 02559 return HAL_OK; 02560 } 02561 02562 /** 02563 * @brief Stops the TIM Encoder Interface in interrupt mode. 02564 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02565 * the configuration information for TIM module. 02566 * @param Channel TIM Channels to be disabled. 02567 * This parameter can be one of the following values: 02568 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02569 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02570 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 02571 * @retval HAL status 02572 */ 02573 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 02574 { 02575 /* Check the parameters */ 02576 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 02577 02578 /* Disable the Input Capture channels 1 and 2 02579 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 02580 if(Channel == TIM_CHANNEL_1) 02581 { 02582 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02583 02584 /* Disable the capture compare Interrupts 1 */ 02585 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 02586 } 02587 else if(Channel == TIM_CHANNEL_2) 02588 { 02589 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02590 02591 /* Disable the capture compare Interrupts 2 */ 02592 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 02593 } 02594 else 02595 { 02596 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02597 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02598 02599 /* Disable the capture compare Interrupts 1 and 2 */ 02600 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 02601 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 02602 } 02603 02604 /* Disable the Peripheral */ 02605 __HAL_TIM_DISABLE(htim); 02606 02607 /* Change the htim state */ 02608 htim->State = HAL_TIM_STATE_READY; 02609 02610 /* Return function status */ 02611 return HAL_OK; 02612 } 02613 02614 /** 02615 * @brief Starts the TIM Encoder Interface in DMA mode. 02616 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02617 * the configuration information for TIM module. 02618 * @param Channel TIM Channels to be enabled. 02619 * This parameter can be one of the following values: 02620 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02621 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02622 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 02623 * @param pData1 The destination Buffer address for IC1. 02624 * @param pData2 The destination Buffer address for IC2. 02625 * @param Length The length of data to be transferred from TIM peripheral to memory. 02626 * @retval HAL status 02627 */ 02628 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) 02629 { 02630 /* Check the parameters */ 02631 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); 02632 02633 if((htim->State == HAL_TIM_STATE_BUSY)) 02634 { 02635 return HAL_BUSY; 02636 } 02637 else if((htim->State == HAL_TIM_STATE_READY)) 02638 { 02639 if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0)) 02640 { 02641 return HAL_ERROR; 02642 } 02643 else 02644 { 02645 htim->State = HAL_TIM_STATE_BUSY; 02646 } 02647 } 02648 02649 switch (Channel) 02650 { 02651 case TIM_CHANNEL_1: 02652 { 02653 /* Set the DMA Period elapsed callback */ 02654 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; 02655 02656 /* Set the DMA error callback */ 02657 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 02658 02659 /* Enable the DMA Stream */ 02660 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); 02661 02662 /* Enable the TIM Input Capture DMA request */ 02663 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 02664 02665 /* Enable the Peripheral */ 02666 __HAL_TIM_ENABLE(htim); 02667 02668 /* Enable the Capture compare channel */ 02669 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02670 } 02671 break; 02672 02673 case TIM_CHANNEL_2: 02674 { 02675 /* Set the DMA Period elapsed callback */ 02676 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; 02677 02678 /* Set the DMA error callback */ 02679 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; 02680 /* Enable the DMA Stream */ 02681 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); 02682 02683 /* Enable the TIM Input Capture DMA request */ 02684 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 02685 02686 /* Enable the Peripheral */ 02687 __HAL_TIM_ENABLE(htim); 02688 02689 /* Enable the Capture compare channel */ 02690 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02691 } 02692 break; 02693 02694 case TIM_CHANNEL_ALL: 02695 { 02696 /* Set the DMA Period elapsed callback */ 02697 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; 02698 02699 /* Set the DMA error callback */ 02700 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 02701 02702 /* Enable the DMA Stream */ 02703 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); 02704 02705 /* Set the DMA Period elapsed callback */ 02706 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; 02707 02708 /* Set the DMA error callback */ 02709 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 02710 02711 /* Enable the DMA Stream */ 02712 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); 02713 02714 /* Enable the Peripheral */ 02715 __HAL_TIM_ENABLE(htim); 02716 02717 /* Enable the Capture compare channel */ 02718 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02719 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02720 02721 /* Enable the TIM Input Capture DMA request */ 02722 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 02723 /* Enable the TIM Input Capture DMA request */ 02724 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 02725 } 02726 break; 02727 02728 default: 02729 break; 02730 } 02731 /* Return function status */ 02732 return HAL_OK; 02733 } 02734 02735 /** 02736 * @brief Stops the TIM Encoder Interface in DMA mode. 02737 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02738 * the configuration information for TIM module. 02739 * @param Channel TIM Channels to be enabled. 02740 * This parameter can be one of the following values: 02741 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02742 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02743 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 02744 * @retval HAL status 02745 */ 02746 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) 02747 { 02748 /* Check the parameters */ 02749 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); 02750 02751 /* Disable the Input Capture channels 1 and 2 02752 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 02753 if(Channel == TIM_CHANNEL_1) 02754 { 02755 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02756 02757 /* Disable the capture compare DMA Request 1 */ 02758 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 02759 } 02760 else if(Channel == TIM_CHANNEL_2) 02761 { 02762 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02763 02764 /* Disable the capture compare DMA Request 2 */ 02765 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 02766 } 02767 else 02768 { 02769 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02770 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02771 02772 /* Disable the capture compare DMA Request 1 and 2 */ 02773 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 02774 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 02775 } 02776 02777 /* Disable the Peripheral */ 02778 __HAL_TIM_DISABLE(htim); 02779 02780 /* Change the htim state */ 02781 htim->State = HAL_TIM_STATE_READY; 02782 02783 /* Return function status */ 02784 return HAL_OK; 02785 } 02786 /** 02787 * @} 02788 */ 02789 02790 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management 02791 * @brief IRQ handler management 02792 * 02793 @verbatim 02794 ============================================================================== 02795 ##### IRQ handler management ##### 02796 ============================================================================== 02797 [..] 02798 This section provides Timer IRQ handler function. 02799 02800 @endverbatim 02801 * @{ 02802 */ 02803 /** 02804 * @brief This function handles TIM interrupts requests. 02805 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02806 * the configuration information for TIM module. 02807 * @retval None 02808 */ 02809 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) 02810 { 02811 /* Capture compare 1 event */ 02812 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 02813 { 02814 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) 02815 { 02816 { 02817 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); 02818 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 02819 02820 /* Input capture event */ 02821 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 02822 { 02823 HAL_TIM_IC_CaptureCallback(htim); 02824 } 02825 /* Output compare event */ 02826 else 02827 { 02828 HAL_TIM_OC_DelayElapsedCallback(htim); 02829 HAL_TIM_PWM_PulseFinishedCallback(htim); 02830 } 02831 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 02832 } 02833 } 02834 } 02835 /* Capture compare 2 event */ 02836 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) 02837 { 02838 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) 02839 { 02840 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); 02841 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 02842 /* Input capture event */ 02843 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 02844 { 02845 HAL_TIM_IC_CaptureCallback(htim); 02846 } 02847 /* Output compare event */ 02848 else 02849 { 02850 HAL_TIM_OC_DelayElapsedCallback(htim); 02851 HAL_TIM_PWM_PulseFinishedCallback(htim); 02852 } 02853 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 02854 } 02855 } 02856 /* Capture compare 3 event */ 02857 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) 02858 { 02859 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) 02860 { 02861 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); 02862 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 02863 /* Input capture event */ 02864 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 02865 { 02866 HAL_TIM_IC_CaptureCallback(htim); 02867 } 02868 /* Output compare event */ 02869 else 02870 { 02871 HAL_TIM_OC_DelayElapsedCallback(htim); 02872 HAL_TIM_PWM_PulseFinishedCallback(htim); 02873 } 02874 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 02875 } 02876 } 02877 /* Capture compare 4 event */ 02878 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) 02879 { 02880 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) 02881 { 02882 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); 02883 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 02884 /* Input capture event */ 02885 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 02886 { 02887 HAL_TIM_IC_CaptureCallback(htim); 02888 } 02889 /* Output compare event */ 02890 else 02891 { 02892 HAL_TIM_OC_DelayElapsedCallback(htim); 02893 HAL_TIM_PWM_PulseFinishedCallback(htim); 02894 } 02895 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 02896 } 02897 } 02898 /* TIM Update event */ 02899 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) 02900 { 02901 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) 02902 { 02903 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 02904 HAL_TIM_PeriodElapsedCallback(htim); 02905 } 02906 } 02907 /* TIM Break input event */ 02908 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) 02909 { 02910 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) 02911 { 02912 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 02913 HAL_TIMEx_BreakCallback(htim); 02914 } 02915 } 02916 /* TIM Trigger detection event */ 02917 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) 02918 { 02919 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) 02920 { 02921 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 02922 HAL_TIM_TriggerCallback(htim); 02923 } 02924 } 02925 /* TIM commutation event */ 02926 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) 02927 { 02928 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET) 02929 { 02930 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 02931 HAL_TIMEx_CommutationCallback(htim); 02932 } 02933 } 02934 } 02935 /** 02936 * @} 02937 */ 02938 02939 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions 02940 * @brief Peripheral Control functions 02941 * 02942 @verbatim 02943 ============================================================================== 02944 ##### Peripheral Control functions ##### 02945 ============================================================================== 02946 [..] 02947 This section provides functions allowing to: 02948 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. 02949 (+) Configure External Clock source. 02950 (+) Configure Complementary channels, break features and dead time. 02951 (+) Configure Master and the Slave synchronization. 02952 (+) Configure the DMA Burst Mode. 02953 02954 @endverbatim 02955 * @{ 02956 */ 02957 02958 /** 02959 * @brief Initializes the TIM Output Compare Channels according to the specified 02960 * parameters in the TIM_OC_InitTypeDef. 02961 * @param htim pointer to a TIM_HandleTypeDef structure that contains 02962 * the configuration information for TIM module. 02963 * @param sConfig TIM Output Compare configuration structure 02964 * @param Channel TIM Channels to be enabled. 02965 * This parameter can be one of the following values: 02966 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02967 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02968 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 02969 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 02970 * @retval HAL status 02971 */ 02972 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) 02973 { 02974 /* Check the parameters */ 02975 assert_param(IS_TIM_CHANNELS(Channel)); 02976 assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); 02977 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); 02978 02979 /* Check input state */ 02980 __HAL_LOCK(htim); 02981 02982 htim->State = HAL_TIM_STATE_BUSY; 02983 02984 switch (Channel) 02985 { 02986 case TIM_CHANNEL_1: 02987 { 02988 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 02989 /* Configure the TIM Channel 1 in Output Compare */ 02990 TIM_OC1_SetConfig(htim->Instance, sConfig); 02991 } 02992 break; 02993 02994 case TIM_CHANNEL_2: 02995 { 02996 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 02997 /* Configure the TIM Channel 2 in Output Compare */ 02998 TIM_OC2_SetConfig(htim->Instance, sConfig); 02999 } 03000 break; 03001 03002 case TIM_CHANNEL_3: 03003 { 03004 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); 03005 /* Configure the TIM Channel 3 in Output Compare */ 03006 TIM_OC3_SetConfig(htim->Instance, sConfig); 03007 } 03008 break; 03009 03010 case TIM_CHANNEL_4: 03011 { 03012 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); 03013 /* Configure the TIM Channel 4 in Output Compare */ 03014 TIM_OC4_SetConfig(htim->Instance, sConfig); 03015 } 03016 break; 03017 03018 default: 03019 break; 03020 } 03021 htim->State = HAL_TIM_STATE_READY; 03022 03023 __HAL_UNLOCK(htim); 03024 03025 return HAL_OK; 03026 } 03027 03028 /** 03029 * @brief Initializes the TIM Input Capture Channels according to the specified 03030 * parameters in the TIM_IC_InitTypeDef. 03031 * @param htim pointer to a TIM_HandleTypeDef structure that contains 03032 * the configuration information for TIM module. 03033 * @param sConfig TIM Input Capture configuration structure 03034 * @param Channel TIM Channels to be enabled. 03035 * This parameter can be one of the following values: 03036 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 03037 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 03038 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 03039 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 03040 * @retval HAL status 03041 */ 03042 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) 03043 { 03044 /* Check the parameters */ 03045 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 03046 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); 03047 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); 03048 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); 03049 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); 03050 03051 __HAL_LOCK(htim); 03052 03053 htim->State = HAL_TIM_STATE_BUSY; 03054 03055 if (Channel == TIM_CHANNEL_1) 03056 { 03057 /* TI1 Configuration */ 03058 TIM_TI1_SetConfig(htim->Instance, 03059 sConfig->ICPolarity, 03060 sConfig->ICSelection, 03061 sConfig->ICFilter); 03062 03063 /* Reset the IC1PSC Bits */ 03064 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; 03065 03066 /* Set the IC1PSC value */ 03067 htim->Instance->CCMR1 |= sConfig->ICPrescaler; 03068 } 03069 else if (Channel == TIM_CHANNEL_2) 03070 { 03071 /* TI2 Configuration */ 03072 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 03073 03074 TIM_TI2_SetConfig(htim->Instance, 03075 sConfig->ICPolarity, 03076 sConfig->ICSelection, 03077 sConfig->ICFilter); 03078 03079 /* Reset the IC2PSC Bits */ 03080 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; 03081 03082 /* Set the IC2PSC value */ 03083 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); 03084 } 03085 else if (Channel == TIM_CHANNEL_3) 03086 { 03087 /* TI3 Configuration */ 03088 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); 03089 03090 TIM_TI3_SetConfig(htim->Instance, 03091 sConfig->ICPolarity, 03092 sConfig->ICSelection, 03093 sConfig->ICFilter); 03094 03095 /* Reset the IC3PSC Bits */ 03096 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; 03097 03098 /* Set the IC3PSC value */ 03099 htim->Instance->CCMR2 |= sConfig->ICPrescaler; 03100 } 03101 else 03102 { 03103 /* TI4 Configuration */ 03104 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); 03105 03106 TIM_TI4_SetConfig(htim->Instance, 03107 sConfig->ICPolarity, 03108 sConfig->ICSelection, 03109 sConfig->ICFilter); 03110 03111 /* Reset the IC4PSC Bits */ 03112 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; 03113 03114 /* Set the IC4PSC value */ 03115 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); 03116 } 03117 03118 htim->State = HAL_TIM_STATE_READY; 03119 03120 __HAL_UNLOCK(htim); 03121 03122 return HAL_OK; 03123 } 03124 03125 /** 03126 * @brief Initializes the TIM PWM channels according to the specified 03127 * parameters in the TIM_OC_InitTypeDef. 03128 * @param htim pointer to a TIM_HandleTypeDef structure that contains 03129 * the configuration information for TIM module. 03130 * @param sConfig TIM PWM configuration structure 03131 * @param Channel TIM Channels to be enabled. 03132 * This parameter can be one of the following values: 03133 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 03134 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 03135 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 03136 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 03137 * @retval HAL status 03138 */ 03139 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) 03140 { 03141 __HAL_LOCK(htim); 03142 03143 /* Check the parameters */ 03144 assert_param(IS_TIM_CHANNELS(Channel)); 03145 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); 03146 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); 03147 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); 03148 03149 htim->State = HAL_TIM_STATE_BUSY; 03150 03151 switch (Channel) 03152 { 03153 case TIM_CHANNEL_1: 03154 { 03155 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 03156 /* Configure the Channel 1 in PWM mode */ 03157 TIM_OC1_SetConfig(htim->Instance, sConfig); 03158 03159 /* Set the Preload enable bit for channel1 */ 03160 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 03161 03162 /* Configure the Output Fast mode */ 03163 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 03164 htim->Instance->CCMR1 |= sConfig->OCFastMode; 03165 } 03166 break; 03167 03168 case TIM_CHANNEL_2: 03169 { 03170 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 03171 /* Configure the Channel 2 in PWM mode */ 03172 TIM_OC2_SetConfig(htim->Instance, sConfig); 03173 03174 /* Set the Preload enable bit for channel2 */ 03175 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 03176 03177 /* Configure the Output Fast mode */ 03178 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 03179 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 03180 } 03181 break; 03182 03183 case TIM_CHANNEL_3: 03184 { 03185 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); 03186 /* Configure the Channel 3 in PWM mode */ 03187 TIM_OC3_SetConfig(htim->Instance, sConfig); 03188 03189 /* Set the Preload enable bit for channel3 */ 03190 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 03191 03192 /* Configure the Output Fast mode */ 03193 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 03194 htim->Instance->CCMR2 |= sConfig->OCFastMode; 03195 } 03196 break; 03197 03198 case TIM_CHANNEL_4: 03199 { 03200 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); 03201 /* Configure the Channel 4 in PWM mode */ 03202 TIM_OC4_SetConfig(htim->Instance, sConfig); 03203 03204 /* Set the Preload enable bit for channel4 */ 03205 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 03206 03207 /* Configure the Output Fast mode */ 03208 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 03209 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 03210 } 03211 break; 03212 03213 default: 03214 break; 03215 } 03216 03217 htim->State = HAL_TIM_STATE_READY; 03218 03219 __HAL_UNLOCK(htim); 03220 03221 return HAL_OK; 03222 } 03223 03224 /** 03225 * @brief Initializes the TIM One Pulse Channels according to the specified 03226 * parameters in the TIM_OnePulse_InitTypeDef. 03227 * @param htim pointer to a TIM_HandleTypeDef structure that contains 03228 * the configuration information for TIM module. 03229 * @param sConfig TIM One Pulse configuration structure 03230 * @param OutputChannel TIM Channels to be enabled. 03231 * This parameter can be one of the following values: 03232 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 03233 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 03234 * @param InputChannel TIM Channels to be enabled. 03235 * This parameter can be one of the following values: 03236 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 03237 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 03238 * @retval HAL status 03239 */ 03240 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) 03241 { 03242 TIM_OC_InitTypeDef temp1; 03243 03244 /* Check the parameters */ 03245 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); 03246 assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); 03247 03248 if(OutputChannel != InputChannel) 03249 { 03250 __HAL_LOCK(htim); 03251 03252 htim->State = HAL_TIM_STATE_BUSY; 03253 03254 /* Extract the Output compare configuration from sConfig structure */ 03255 temp1.OCMode = sConfig->OCMode; 03256 temp1.Pulse = sConfig->Pulse; 03257 temp1.OCPolarity = sConfig->OCPolarity; 03258 temp1.OCNPolarity = sConfig->OCNPolarity; 03259 temp1.OCIdleState = sConfig->OCIdleState; 03260 temp1.OCNIdleState = sConfig->OCNIdleState; 03261 03262 switch (OutputChannel) 03263 { 03264 case TIM_CHANNEL_1: 03265 { 03266 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 03267 03268 TIM_OC1_SetConfig(htim->Instance, &temp1); 03269 } 03270 break; 03271 case TIM_CHANNEL_2: 03272 { 03273 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 03274 03275 TIM_OC2_SetConfig(htim->Instance, &temp1); 03276 } 03277 break; 03278 default: 03279 break; 03280 } 03281 switch (InputChannel) 03282 { 03283 case TIM_CHANNEL_1: 03284 { 03285 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 03286 03287 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, 03288 sConfig->ICSelection, sConfig->ICFilter); 03289 03290 /* Reset the IC1PSC Bits */ 03291 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; 03292 03293 /* Select the Trigger source */ 03294 htim->Instance->SMCR &= ~TIM_SMCR_TS; 03295 htim->Instance->SMCR |= TIM_TS_TI1FP1; 03296 03297 /* Select the Slave Mode */ 03298 htim->Instance->SMCR &= ~TIM_SMCR_SMS; 03299 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; 03300 } 03301 break; 03302 case TIM_CHANNEL_2: 03303 { 03304 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 03305 03306 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, 03307 sConfig->ICSelection, sConfig->ICFilter); 03308 03309 /* Reset the IC2PSC Bits */ 03310 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; 03311 03312 /* Select the Trigger source */ 03313 htim->Instance->SMCR &= ~TIM_SMCR_TS; 03314 htim->Instance->SMCR |= TIM_TS_TI2FP2; 03315 03316 /* Select the Slave Mode */ 03317 htim->Instance->SMCR &= ~TIM_SMCR_SMS; 03318 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; 03319 } 03320 break; 03321 03322 default: 03323 break; 03324 } 03325 03326 htim->State = HAL_TIM_STATE_READY; 03327 03328 __HAL_UNLOCK(htim); 03329 03330 return HAL_OK; 03331 } 03332 else 03333 { 03334 return HAL_ERROR; 03335 } 03336 } 03337 03338 /** 03339 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral 03340 * @param htim pointer to a TIM_HandleTypeDef structure that contains 03341 * the configuration information for TIM module. 03342 * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write. 03343 * This parameters can be on of the following values: 03344 * @arg TIM_DMABASE_CR1 03345 * @arg TIM_DMABASE_CR2 03346 * @arg TIM_DMABASE_SMCR 03347 * @arg TIM_DMABASE_DIER 03348 * @arg TIM_DMABASE_SR 03349 * @arg TIM_DMABASE_EGR 03350 * @arg TIM_DMABASE_CCMR1 03351 * @arg TIM_DMABASE_CCMR2 03352 * @arg TIM_DMABASE_CCER 03353 * @arg TIM_DMABASE_CNT 03354 * @arg TIM_DMABASE_PSC 03355 * @arg TIM_DMABASE_ARR 03356 * @arg TIM_DMABASE_RCR 03357 * @arg TIM_DMABASE_CCR1 03358 * @arg TIM_DMABASE_CCR2 03359 * @arg TIM_DMABASE_CCR3 03360 * @arg TIM_DMABASE_CCR4 03361 * @arg TIM_DMABASE_BDTR 03362 * @arg TIM_DMABASE_DCR 03363 * @param BurstRequestSrc TIM DMA Request sources. 03364 * This parameters can be on of the following values: 03365 * @arg TIM_DMA_UPDATE: TIM update Interrupt source 03366 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source 03367 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source 03368 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source 03369 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source 03370 * @arg TIM_DMA_COM: TIM Commutation DMA source 03371 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source 03372 * @param BurstBuffer The Buffer address. 03373 * @param BurstLength DMA Burst length. This parameter can be one value 03374 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. 03375 * @retval HAL status 03376 */ 03377 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, 03378 uint32_t* BurstBuffer, uint32_t BurstLength) 03379 { 03380 /* Check the parameters */ 03381 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); 03382 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); 03383 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); 03384 assert_param(IS_TIM_DMA_LENGTH(BurstLength)); 03385 03386 if((htim->State == HAL_TIM_STATE_BUSY)) 03387 { 03388 return HAL_BUSY; 03389 } 03390 else if((htim->State == HAL_TIM_STATE_READY)) 03391 { 03392 if((BurstBuffer == 0U) && (BurstLength > 0U)) 03393 { 03394 return HAL_ERROR; 03395 } 03396 else 03397 { 03398 htim->State = HAL_TIM_STATE_BUSY; 03399 } 03400 } 03401 switch(BurstRequestSrc) 03402 { 03403 case TIM_DMA_UPDATE: 03404 { 03405 /* Set the DMA Period elapsed callback */ 03406 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; 03407 03408 /* Set the DMA error callback */ 03409 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; 03410 03411 /* Enable the DMA Stream */ 03412 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); 03413 } 03414 break; 03415 case TIM_DMA_CC1: 03416 { 03417 /* Set the DMA Period elapsed callback */ 03418 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; 03419 03420 /* Set the DMA error callback */ 03421 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 03422 03423 /* Enable the DMA Stream */ 03424 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); 03425 } 03426 break; 03427 case TIM_DMA_CC2: 03428 { 03429 /* Set the DMA Period elapsed callback */ 03430 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; 03431 03432 /* Set the DMA error callback */ 03433 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 03434 03435 /* Enable the DMA Stream */ 03436 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); 03437 } 03438 break; 03439 case TIM_DMA_CC3: 03440 { 03441 /* Set the DMA Period elapsed callback */ 03442 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; 03443 03444 /* Set the DMA error callback */ 03445 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 03446 03447 /* Enable the DMA Stream */ 03448 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); 03449 } 03450 break; 03451 case TIM_DMA_CC4: 03452 { 03453 /* Set the DMA Period elapsed callback */ 03454 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; 03455 03456 /* Set the DMA error callback */ 03457 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; 03458 03459 /* Enable the DMA Stream */ 03460 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); 03461 } 03462 break; 03463 case TIM_DMA_COM: 03464 { 03465 /* Set the DMA Period elapsed callback */ 03466 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; 03467 03468 /* Set the DMA error callback */ 03469 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; 03470 03471 /* Enable the DMA Stream */ 03472 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); 03473 } 03474 break; 03475 case TIM_DMA_TRIGGER: 03476 { 03477 /* Set the DMA Period elapsed callback */ 03478 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; 03479 03480 /* Set the DMA error callback */ 03481 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; 03482 03483 /* Enable the DMA Stream */ 03484 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); 03485 } 03486 break; 03487 default: 03488 break; 03489 } 03490 /* configure the DMA Burst Mode */ 03491 htim->Instance->DCR = BurstBaseAddress | BurstLength; 03492 03493 /* Enable the TIM DMA Request */ 03494 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); 03495 03496 htim->State = HAL_TIM_STATE_READY; 03497 03498 /* Return function status */ 03499 return HAL_OK; 03500 } 03501 03502 /** 03503 * @brief Stops the TIM DMA Burst mode 03504 * @param htim pointer to a TIM_HandleTypeDef structure that contains 03505 * the configuration information for TIM module. 03506 * @param BurstRequestSrc TIM DMA Request sources to disable 03507 * @retval HAL status 03508 */ 03509 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) 03510 { 03511 /* Check the parameters */ 03512 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); 03513 03514 /* Abort the DMA transfer (at least disable the DMA channel) */ 03515 switch(BurstRequestSrc) 03516 { 03517 case TIM_DMA_UPDATE: 03518 { 03519 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); 03520 } 03521 break; 03522 case TIM_DMA_CC1: 03523 { 03524 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); 03525 } 03526 break; 03527 case TIM_DMA_CC2: 03528 { 03529 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); 03530 } 03531 break; 03532 case TIM_DMA_CC3: 03533 { 03534 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); 03535 } 03536 break; 03537 case TIM_DMA_CC4: 03538 { 03539 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); 03540 } 03541 break; 03542 case TIM_DMA_COM: 03543 { 03544 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); 03545 } 03546 break; 03547 case TIM_DMA_TRIGGER: 03548 { 03549 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); 03550 } 03551 break; 03552 default: 03553 break; 03554 } 03555 03556 /* Disable the TIM Update DMA request */ 03557 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); 03558 03559 /* Return function status */ 03560 return HAL_OK; 03561 } 03562 03563 /** 03564 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory 03565 * @param htim pointer to a TIM_HandleTypeDef structure that contains 03566 * the configuration information for TIM module. 03567 * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read. 03568 * This parameters can be on of the following values: 03569 * @arg TIM_DMABASE_CR1 03570 * @arg TIM_DMABASE_CR2 03571 * @arg TIM_DMABASE_SMCR 03572 * @arg TIM_DMABASE_DIER 03573 * @arg TIM_DMABASE_SR 03574 * @arg TIM_DMABASE_EGR 03575 * @arg TIM_DMABASE_CCMR1 03576 * @arg TIM_DMABASE_CCMR2 03577 * @arg TIM_DMABASE_CCER 03578 * @arg TIM_DMABASE_CNT 03579 * @arg TIM_DMABASE_PSC 03580 * @arg TIM_DMABASE_ARR 03581 * @arg TIM_DMABASE_RCR 03582 * @arg TIM_DMABASE_CCR1 03583 * @arg TIM_DMABASE_CCR2 03584 * @arg TIM_DMABASE_CCR3 03585 * @arg TIM_DMABASE_CCR4 03586 * @arg TIM_DMABASE_BDTR 03587 * @arg TIM_DMABASE_DCR 03588 * @param BurstRequestSrc TIM DMA Request sources. 03589 * This parameters can be on of the following values: 03590 * @arg TIM_DMA_UPDATE: TIM update Interrupt source 03591 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source 03592 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source 03593 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source 03594 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source 03595 * @arg TIM_DMA_COM: TIM Commutation DMA source 03596 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source 03597 * @param BurstBuffer The Buffer address. 03598 * @param BurstLength DMA Burst length. This parameter can be one value 03599 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. 03600 * @retval HAL status 03601 */ 03602 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, 03603 uint32_t *BurstBuffer, uint32_t BurstLength) 03604 { 03605 /* Check the parameters */ 03606 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); 03607 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); 03608 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); 03609 assert_param(IS_TIM_DMA_LENGTH(BurstLength)); 03610 03611 if((htim->State == HAL_TIM_STATE_BUSY)) 03612 { 03613 return HAL_BUSY; 03614 } 03615 else if((htim->State == HAL_TIM_STATE_READY)) 03616 { 03617 if((BurstBuffer == 0U) && (BurstLength > 0U)) 03618 { 03619 return HAL_ERROR; 03620 } 03621 else 03622 { 03623 htim->State = HAL_TIM_STATE_BUSY; 03624 } 03625 } 03626 switch(BurstRequestSrc) 03627 { 03628 case TIM_DMA_UPDATE: 03629 { 03630 /* Set the DMA Period elapsed callback */ 03631 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; 03632 03633 /* Set the DMA error callback */ 03634 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; 03635 03636 /* Enable the DMA Stream */ 03637 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); 03638 } 03639 break; 03640 case TIM_DMA_CC1: 03641 { 03642 /* Set the DMA Period elapsed callback */ 03643 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; 03644 03645 /* Set the DMA error callback */ 03646 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 03647 03648 /* Enable the DMA Stream */ 03649 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); 03650 } 03651 break; 03652 case TIM_DMA_CC2: 03653 { 03654 /* Set the DMA Period elapsed callback */ 03655 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; 03656 03657 /* Set the DMA error callback */ 03658 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 03659 03660 /* Enable the DMA Stream */ 03661 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); 03662 } 03663 break; 03664 case TIM_DMA_CC3: 03665 { 03666 /* Set the DMA Period elapsed callback */ 03667 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; 03668 03669 /* Set the DMA error callback */ 03670 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 03671 03672 /* Enable the DMA Stream */ 03673 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); 03674 } 03675 break; 03676 case TIM_DMA_CC4: 03677 { 03678 /* Set the DMA Period elapsed callback */ 03679 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; 03680 03681 /* Set the DMA error callback */ 03682 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; 03683 03684 /* Enable the DMA Stream */ 03685 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); 03686 } 03687 break; 03688 case TIM_DMA_COM: 03689 { 03690 /* Set the DMA Period elapsed callback */ 03691 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; 03692 03693 /* Set the DMA error callback */ 03694 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; 03695 03696 /* Enable the DMA Stream */ 03697 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); 03698 } 03699 break; 03700 case TIM_DMA_TRIGGER: 03701 { 03702 /* Set the DMA Period elapsed callback */ 03703 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; 03704 03705 /* Set the DMA error callback */ 03706 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; 03707 03708 /* Enable the DMA Stream */ 03709 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1); 03710 } 03711 break; 03712 default: 03713 break; 03714 } 03715 03716 /* configure the DMA Burst Mode */ 03717 htim->Instance->DCR = BurstBaseAddress | BurstLength; 03718 03719 /* Enable the TIM DMA Request */ 03720 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); 03721 03722 htim->State = HAL_TIM_STATE_READY; 03723 03724 /* Return function status */ 03725 return HAL_OK; 03726 } 03727 03728 /** 03729 * @brief Stop the DMA burst reading 03730 * @param htim pointer to a TIM_HandleTypeDef structure that contains 03731 * the configuration information for TIM module. 03732 * @param BurstRequestSrc TIM DMA Request sources to disable. 03733 * @retval HAL status 03734 */ 03735 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) 03736 { 03737 /* Check the parameters */ 03738 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); 03739 03740 /* Abort the DMA transfer (at least disable the DMA channel) */ 03741 switch(BurstRequestSrc) 03742 { 03743 case TIM_DMA_UPDATE: 03744 { 03745 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); 03746 } 03747 break; 03748 case TIM_DMA_CC1: 03749 { 03750 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); 03751 } 03752 break; 03753 case TIM_DMA_CC2: 03754 { 03755 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); 03756 } 03757 break; 03758 case TIM_DMA_CC3: 03759 { 03760 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); 03761 } 03762 break; 03763 case TIM_DMA_CC4: 03764 { 03765 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); 03766 } 03767 break; 03768 case TIM_DMA_COM: 03769 { 03770 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); 03771 } 03772 break; 03773 case TIM_DMA_TRIGGER: 03774 { 03775 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); 03776 } 03777 break; 03778 default: 03779 break; 03780 } 03781 03782 /* Disable the TIM Update DMA request */ 03783 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); 03784 03785 /* Return function status */ 03786 return HAL_OK; 03787 } 03788 03789 /** 03790 * @brief Generate a software event 03791 * @param htim pointer to a TIM_HandleTypeDef structure that contains 03792 * the configuration information for TIM module. 03793 * @param EventSource specifies the event source. 03794 * This parameter can be one of the following values: 03795 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source 03796 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source 03797 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source 03798 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source 03799 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source 03800 * @arg TIM_EVENTSOURCE_COM: Timer COM event source 03801 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source 03802 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source 03803 * @note TIM6 and TIM7 can only generate an update event. 03804 * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8. 03805 * @retval HAL status 03806 */ 03807 03808 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) 03809 { 03810 /* Check the parameters */ 03811 assert_param(IS_TIM_INSTANCE(htim->Instance)); 03812 assert_param(IS_TIM_EVENT_SOURCE(EventSource)); 03813 03814 /* Process Locked */ 03815 __HAL_LOCK(htim); 03816 03817 /* Change the TIM state */ 03818 htim->State = HAL_TIM_STATE_BUSY; 03819 03820 /* Set the event sources */ 03821 htim->Instance->EGR = EventSource; 03822 03823 /* Change the TIM state */ 03824 htim->State = HAL_TIM_STATE_READY; 03825 03826 __HAL_UNLOCK(htim); 03827 03828 /* Return function status */ 03829 return HAL_OK; 03830 } 03831 03832 /** 03833 * @brief Configures the OCRef clear feature 03834 * @param htim pointer to a TIM_HandleTypeDef structure that contains 03835 * the configuration information for TIM module. 03836 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that 03837 * contains the OCREF clear feature and parameters for the TIM peripheral. 03838 * @param Channel specifies the TIM Channel. 03839 * This parameter can be one of the following values: 03840 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 03841 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 03842 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 03843 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 03844 * @retval HAL status 03845 */ 03846 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) 03847 { 03848 /* Check the parameters */ 03849 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 03850 assert_param(IS_TIM_CHANNELS(Channel)); 03851 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); 03852 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); 03853 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); 03854 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); 03855 03856 /* Process Locked */ 03857 __HAL_LOCK(htim); 03858 03859 htim->State = HAL_TIM_STATE_BUSY; 03860 03861 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR) 03862 { 03863 TIM_ETR_SetConfig(htim->Instance, 03864 sClearInputConfig->ClearInputPrescaler, 03865 sClearInputConfig->ClearInputPolarity, 03866 sClearInputConfig->ClearInputFilter); 03867 } 03868 03869 switch (Channel) 03870 { 03871 case TIM_CHANNEL_1: 03872 { 03873 if(sClearInputConfig->ClearInputState != RESET) 03874 { 03875 /* Enable the Ocref clear feature for Channel 1 */ 03876 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; 03877 } 03878 else 03879 { 03880 /* Disable the Ocref clear feature for Channel 1 */ 03881 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; 03882 } 03883 } 03884 break; 03885 case TIM_CHANNEL_2: 03886 { 03887 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 03888 if(sClearInputConfig->ClearInputState != RESET) 03889 { 03890 /* Enable the Ocref clear feature for Channel 2 */ 03891 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; 03892 } 03893 else 03894 { 03895 /* Disable the Ocref clear feature for Channel 2 */ 03896 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; 03897 } 03898 } 03899 break; 03900 case TIM_CHANNEL_3: 03901 { 03902 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); 03903 if(sClearInputConfig->ClearInputState != RESET) 03904 { 03905 /* Enable the Ocref clear feature for Channel 3 */ 03906 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; 03907 } 03908 else 03909 { 03910 /* Disable the Ocref clear feature for Channel 3 */ 03911 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; 03912 } 03913 } 03914 break; 03915 case TIM_CHANNEL_4: 03916 { 03917 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); 03918 if(sClearInputConfig->ClearInputState != RESET) 03919 { 03920 /* Enable the Ocref clear feature for Channel 4 */ 03921 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; 03922 } 03923 else 03924 { 03925 /* Disable the Ocref clear feature for Channel 4 */ 03926 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; 03927 } 03928 } 03929 break; 03930 default: 03931 break; 03932 } 03933 03934 htim->State = HAL_TIM_STATE_READY; 03935 03936 __HAL_UNLOCK(htim); 03937 03938 return HAL_OK; 03939 } 03940 03941 /** 03942 * @brief Configures the clock source to be used 03943 * @param htim pointer to a TIM_HandleTypeDef structure that contains 03944 * the configuration information for TIM module. 03945 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that 03946 * contains the clock source information for the TIM peripheral. 03947 * @retval HAL status 03948 */ 03949 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) 03950 { 03951 uint32_t tmpsmcr = 0U; 03952 03953 /* Process Locked */ 03954 __HAL_LOCK(htim); 03955 03956 htim->State = HAL_TIM_STATE_BUSY; 03957 03958 /* Check the parameters */ 03959 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); 03960 03961 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ 03962 tmpsmcr = htim->Instance->SMCR; 03963 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 03964 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 03965 htim->Instance->SMCR = tmpsmcr; 03966 03967 switch (sClockSourceConfig->ClockSource) 03968 { 03969 case TIM_CLOCKSOURCE_INTERNAL: 03970 { 03971 assert_param(IS_TIM_INSTANCE(htim->Instance)); 03972 03973 /* Disable slave mode to clock the prescaler directly with the internal clock */ 03974 htim->Instance->SMCR &= ~TIM_SMCR_SMS; 03975 } 03976 break; 03977 03978 case TIM_CLOCKSOURCE_ETRMODE1: 03979 { 03980 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); 03981 03982 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); 03983 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); 03984 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); 03985 03986 /* Configure the ETR Clock source */ 03987 TIM_ETR_SetConfig(htim->Instance, 03988 sClockSourceConfig->ClockPrescaler, 03989 sClockSourceConfig->ClockPolarity, 03990 sClockSourceConfig->ClockFilter); 03991 /* Get the TIMx SMCR register value */ 03992 tmpsmcr = htim->Instance->SMCR; 03993 /* Reset the SMS and TS Bits */ 03994 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 03995 /* Select the External clock mode1 and the ETRF trigger */ 03996 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 03997 /* Write to TIMx SMCR */ 03998 htim->Instance->SMCR = tmpsmcr; 03999 } 04000 break; 04001 04002 case TIM_CLOCKSOURCE_ETRMODE2: 04003 { 04004 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); 04005 04006 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); 04007 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); 04008 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); 04009 04010 /* Configure the ETR Clock source */ 04011 TIM_ETR_SetConfig(htim->Instance, 04012 sClockSourceConfig->ClockPrescaler, 04013 sClockSourceConfig->ClockPolarity, 04014 sClockSourceConfig->ClockFilter); 04015 /* Enable the External clock mode2 */ 04016 htim->Instance->SMCR |= TIM_SMCR_ECE; 04017 } 04018 break; 04019 04020 case TIM_CLOCKSOURCE_TI1: 04021 { 04022 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 04023 04024 /* Check TI1 input conditioning related parameters */ 04025 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); 04026 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); 04027 04028 TIM_TI1_ConfigInputStage(htim->Instance, 04029 sClockSourceConfig->ClockPolarity, 04030 sClockSourceConfig->ClockFilter); 04031 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 04032 } 04033 break; 04034 case TIM_CLOCKSOURCE_TI2: 04035 { 04036 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 04037 04038 /* Check TI1 input conditioning related parameters */ 04039 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); 04040 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); 04041 04042 TIM_TI2_ConfigInputStage(htim->Instance, 04043 sClockSourceConfig->ClockPolarity, 04044 sClockSourceConfig->ClockFilter); 04045 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 04046 } 04047 break; 04048 case TIM_CLOCKSOURCE_TI1ED: 04049 { 04050 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 04051 04052 /* Check TI1 input conditioning related parameters */ 04053 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); 04054 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); 04055 04056 TIM_TI1_ConfigInputStage(htim->Instance, 04057 sClockSourceConfig->ClockPolarity, 04058 sClockSourceConfig->ClockFilter); 04059 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 04060 } 04061 break; 04062 case TIM_CLOCKSOURCE_ITR0: 04063 { 04064 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 04065 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); 04066 } 04067 break; 04068 case TIM_CLOCKSOURCE_ITR1: 04069 { 04070 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 04071 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); 04072 } 04073 break; 04074 case TIM_CLOCKSOURCE_ITR2: 04075 { 04076 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 04077 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); 04078 } 04079 break; 04080 case TIM_CLOCKSOURCE_ITR3: 04081 { 04082 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 04083 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); 04084 } 04085 break; 04086 04087 default: 04088 break; 04089 } 04090 htim->State = HAL_TIM_STATE_READY; 04091 04092 __HAL_UNLOCK(htim); 04093 04094 return HAL_OK; 04095 } 04096 04097 /** 04098 * @brief Selects the signal connected to the TI1 input: direct from CH1_input 04099 * or a XOR combination between CH1_input, CH2_input & CH3_input 04100 * @param htim pointer to a TIM_HandleTypeDef structure that contains 04101 * the configuration information for TIM module. 04102 * @param TI1_Selection Indicate whether or not channel 1 is connected to the 04103 * output of a XOR gate. 04104 * This parameter can be one of the following values: 04105 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input 04106 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 04107 * pins are connected to the TI1 input (XOR combination) 04108 * @retval HAL status 04109 */ 04110 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) 04111 { 04112 uint32_t tmpcr2 = 0U; 04113 04114 /* Check the parameters */ 04115 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); 04116 assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); 04117 04118 /* Get the TIMx CR2 register value */ 04119 tmpcr2 = htim->Instance->CR2; 04120 04121 /* Reset the TI1 selection */ 04122 tmpcr2 &= ~TIM_CR2_TI1S; 04123 04124 /* Set the TI1 selection */ 04125 tmpcr2 |= TI1_Selection; 04126 04127 /* Write to TIMxCR2 */ 04128 htim->Instance->CR2 = tmpcr2; 04129 04130 return HAL_OK; 04131 } 04132 04133 /** 04134 * @brief Configures the TIM in Slave mode 04135 * @param htim pointer to a TIM_HandleTypeDef structure that contains 04136 * the configuration information for TIM module. 04137 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that 04138 * contains the selected trigger (internal trigger input, filtered 04139 * timer input or external trigger input) and the ) and the Slave 04140 * mode (Disable, Reset, Gated, Trigger, External clock mode 1). 04141 * @retval HAL status 04142 */ 04143 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) 04144 { 04145 /* Check the parameters */ 04146 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); 04147 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); 04148 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); 04149 04150 __HAL_LOCK(htim); 04151 04152 htim->State = HAL_TIM_STATE_BUSY; 04153 04154 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); 04155 04156 /* Disable Trigger Interrupt */ 04157 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); 04158 04159 /* Disable Trigger DMA request */ 04160 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); 04161 04162 htim->State = HAL_TIM_STATE_READY; 04163 04164 __HAL_UNLOCK(htim); 04165 04166 return HAL_OK; 04167 } 04168 04169 /** 04170 * @brief Configures the TIM in Slave mode in interrupt mode 04171 * @param htim TIM handle. 04172 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that 04173 * contains the selected trigger (internal trigger input, filtered 04174 * timer input or external trigger input) and the ) and the Slave 04175 * mode (Disable, Reset, Gated, Trigger, External clock mode 1). 04176 * @retval HAL status 04177 */ 04178 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, 04179 TIM_SlaveConfigTypeDef * sSlaveConfig) 04180 { 04181 /* Check the parameters */ 04182 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); 04183 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); 04184 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); 04185 04186 __HAL_LOCK(htim); 04187 04188 htim->State = HAL_TIM_STATE_BUSY; 04189 04190 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); 04191 04192 /* Enable Trigger Interrupt */ 04193 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); 04194 04195 /* Disable Trigger DMA request */ 04196 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); 04197 04198 htim->State = HAL_TIM_STATE_READY; 04199 04200 __HAL_UNLOCK(htim); 04201 04202 return HAL_OK; 04203 } 04204 04205 /** 04206 * @brief Read the captured value from Capture Compare unit 04207 * @param htim pointer to a TIM_HandleTypeDef structure that contains 04208 * the configuration information for TIM module. 04209 * @param Channel TIM Channels to be enabled. 04210 * This parameter can be one of the following values: 04211 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 04212 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 04213 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 04214 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 04215 * @retval Captured value 04216 */ 04217 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) 04218 { 04219 uint32_t tmpreg = 0U; 04220 04221 __HAL_LOCK(htim); 04222 04223 switch (Channel) 04224 { 04225 case TIM_CHANNEL_1: 04226 { 04227 /* Check the parameters */ 04228 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 04229 04230 /* Return the capture 1 value */ 04231 tmpreg = htim->Instance->CCR1; 04232 04233 break; 04234 } 04235 case TIM_CHANNEL_2: 04236 { 04237 /* Check the parameters */ 04238 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 04239 04240 /* Return the capture 2 value */ 04241 tmpreg = htim->Instance->CCR2; 04242 04243 break; 04244 } 04245 04246 case TIM_CHANNEL_3: 04247 { 04248 /* Check the parameters */ 04249 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); 04250 04251 /* Return the capture 3 value */ 04252 tmpreg = htim->Instance->CCR3; 04253 04254 break; 04255 } 04256 04257 case TIM_CHANNEL_4: 04258 { 04259 /* Check the parameters */ 04260 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); 04261 04262 /* Return the capture 4 value */ 04263 tmpreg = htim->Instance->CCR4; 04264 04265 break; 04266 } 04267 04268 default: 04269 break; 04270 } 04271 04272 __HAL_UNLOCK(htim); 04273 return tmpreg; 04274 } 04275 /** 04276 * @} 04277 */ 04278 04279 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 04280 * @brief TIM Callbacks functions 04281 * 04282 @verbatim 04283 ============================================================================== 04284 ##### TIM Callbacks functions ##### 04285 ============================================================================== 04286 [..] 04287 This section provides TIM callback functions: 04288 (+) Timer Period elapsed callback 04289 (+) Timer Output Compare callback 04290 (+) Timer Input capture callback 04291 (+) Timer Trigger callback 04292 (+) Timer Error callback 04293 04294 @endverbatim 04295 * @{ 04296 */ 04297 04298 /** 04299 * @brief Period elapsed callback in non blocking mode 04300 * @param htim pointer to a TIM_HandleTypeDef structure that contains 04301 * the configuration information for TIM module. 04302 * @retval None 04303 */ 04304 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) 04305 { 04306 /* Prevent unused argument(s) compilation warning */ 04307 UNUSED(htim); 04308 /* NOTE : This function Should not be modified, when the callback is needed, 04309 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file 04310 */ 04311 } 04312 04313 /** 04314 * @brief Output Compare callback in non blocking mode 04315 * @param htim pointer to a TIM_HandleTypeDef structure that contains 04316 * the configuration information for TIM module. 04317 * @retval None 04318 */ 04319 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) 04320 { 04321 /* Prevent unused argument(s) compilation warning */ 04322 UNUSED(htim); 04323 /* NOTE : This function Should not be modified, when the callback is needed, 04324 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file 04325 */ 04326 } 04327 04328 /** 04329 * @brief Input Capture callback in non blocking mode 04330 * @param htim pointer to a TIM_HandleTypeDef structure that contains 04331 * the configuration information for TIM module. 04332 * @retval None 04333 */ 04334 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) 04335 { 04336 /* Prevent unused argument(s) compilation warning */ 04337 UNUSED(htim); 04338 /* NOTE : This function Should not be modified, when the callback is needed, 04339 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file 04340 */ 04341 } 04342 04343 /** 04344 * @brief PWM Pulse finished callback in non blocking mode 04345 * @param htim pointer to a TIM_HandleTypeDef structure that contains 04346 * the configuration information for TIM module. 04347 * @retval None 04348 */ 04349 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) 04350 { 04351 /* Prevent unused argument(s) compilation warning */ 04352 UNUSED(htim); 04353 /* NOTE : This function Should not be modified, when the callback is needed, 04354 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file 04355 */ 04356 } 04357 04358 /** 04359 * @brief Hall Trigger detection callback in non blocking mode 04360 * @param htim pointer to a TIM_HandleTypeDef structure that contains 04361 * the configuration information for TIM module. 04362 * @retval None 04363 */ 04364 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) 04365 { 04366 /* Prevent unused argument(s) compilation warning */ 04367 UNUSED(htim); 04368 /* NOTE : This function Should not be modified, when the callback is needed, 04369 the HAL_TIM_TriggerCallback could be implemented in the user file 04370 */ 04371 } 04372 04373 /** 04374 * @brief Timer error callback in non blocking mode 04375 * @param htim pointer to a TIM_HandleTypeDef structure that contains 04376 * the configuration information for TIM module. 04377 * @retval None 04378 */ 04379 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) 04380 { 04381 /* Prevent unused argument(s) compilation warning */ 04382 UNUSED(htim); 04383 /* NOTE : This function Should not be modified, when the callback is needed, 04384 the HAL_TIM_ErrorCallback could be implemented in the user file 04385 */ 04386 } 04387 /** 04388 * @} 04389 */ 04390 04391 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions 04392 * @brief Peripheral State functions 04393 * 04394 @verbatim 04395 ============================================================================== 04396 ##### Peripheral State functions ##### 04397 ============================================================================== 04398 [..] 04399 This subsection permits to get in run-time the status of the peripheral 04400 and the data flow. 04401 04402 @endverbatim 04403 * @{ 04404 */ 04405 04406 /** 04407 * @brief Return the TIM Base state 04408 * @param htim pointer to a TIM_HandleTypeDef structure that contains 04409 * the configuration information for TIM module. 04410 * @retval HAL state 04411 */ 04412 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) 04413 { 04414 return htim->State; 04415 } 04416 04417 /** 04418 * @brief Return the TIM OC state 04419 * @param htim pointer to a TIM_HandleTypeDef structure that contains 04420 * the configuration information for TIM module. 04421 * @retval HAL state 04422 */ 04423 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) 04424 { 04425 return htim->State; 04426 } 04427 04428 /** 04429 * @brief Return the TIM PWM state 04430 * @param htim pointer to a TIM_HandleTypeDef structure that contains 04431 * the configuration information for TIM module. 04432 * @retval HAL state 04433 */ 04434 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) 04435 { 04436 return htim->State; 04437 } 04438 04439 /** 04440 * @brief Return the TIM Input Capture state 04441 * @param htim pointer to a TIM_HandleTypeDef structure that contains 04442 * the configuration information for TIM module. 04443 * @retval HAL state 04444 */ 04445 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) 04446 { 04447 return htim->State; 04448 } 04449 04450 /** 04451 * @brief Return the TIM One Pulse Mode state 04452 * @param htim pointer to a TIM_HandleTypeDef structure that contains 04453 * the configuration information for TIM module. 04454 * @retval HAL state 04455 */ 04456 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) 04457 { 04458 return htim->State; 04459 } 04460 04461 /** 04462 * @brief Return the TIM Encoder Mode state 04463 * @param htim pointer to a TIM_HandleTypeDef structure that contains 04464 * the configuration information for TIM module. 04465 * @retval HAL state 04466 */ 04467 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) 04468 { 04469 return htim->State; 04470 } 04471 /** 04472 * @} 04473 */ 04474 04475 /** 04476 * @brief Time Base configuration 04477 * @param TIMx TIM peripheral 04478 * @param Structure pointer on TIM Time Base required parameters 04479 * @retval None 04480 */ 04481 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) 04482 { 04483 uint32_t tmpcr1 = 0U; 04484 tmpcr1 = TIMx->CR1; 04485 04486 /* Set TIM Time Base Unit parameters ---------------------------------------*/ 04487 if(IS_TIM_CC3_INSTANCE(TIMx) != RESET) 04488 { 04489 /* Select the Counter Mode */ 04490 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 04491 tmpcr1 |= Structure->CounterMode; 04492 } 04493 04494 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET) 04495 { 04496 /* Set the clock division */ 04497 tmpcr1 &= ~TIM_CR1_CKD; 04498 tmpcr1 |= (uint32_t)Structure->ClockDivision; 04499 } 04500 04501 TIMx->CR1 = tmpcr1; 04502 04503 /* Set the Auto-reload value */ 04504 TIMx->ARR = (uint32_t)Structure->Period ; 04505 04506 /* Set the Prescaler value */ 04507 TIMx->PSC = (uint32_t)Structure->Prescaler; 04508 04509 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) 04510 { 04511 /* Set the Repetition Counter value */ 04512 TIMx->RCR = Structure->RepetitionCounter; 04513 } 04514 04515 /* Generate an update event to reload the Prescaler 04516 and the repetition counter(only for TIM1 and TIM8) value immediately */ 04517 TIMx->EGR = TIM_EGR_UG; 04518 } 04519 04520 /** 04521 * @brief Configure the TI1 as Input. 04522 * @param TIMx to select the TIM peripheral. 04523 * @param TIM_ICPolarity The Input Polarity. 04524 * This parameter can be one of the following values: 04525 * @arg TIM_ICPolarity_Rising 04526 * @arg TIM_ICPolarity_Falling 04527 * @arg TIM_ICPolarity_BothEdge 04528 * @param TIM_ICSelection specifies the input to be used. 04529 * This parameter can be one of the following values: 04530 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. 04531 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. 04532 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. 04533 * @param TIM_ICFilter Specifies the Input Capture Filter. 04534 * This parameter must be a value between 0x00 and 0x0F. 04535 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 04536 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be 04537 * protected against un-initialized filter and polarity values. 04538 * @retval None 04539 */ 04540 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 04541 uint32_t TIM_ICFilter) 04542 { 04543 uint32_t tmpccmr1 = 0U; 04544 uint32_t tmpccer = 0U; 04545 04546 /* Disable the Channel 1: Reset the CC1E Bit */ 04547 TIMx->CCER &= ~TIM_CCER_CC1E; 04548 tmpccmr1 = TIMx->CCMR1; 04549 tmpccer = TIMx->CCER; 04550 04551 /* Select the Input */ 04552 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) 04553 { 04554 tmpccmr1 &= ~TIM_CCMR1_CC1S; 04555 tmpccmr1 |= TIM_ICSelection; 04556 } 04557 else 04558 { 04559 tmpccmr1 &= ~TIM_CCMR1_CC1S; 04560 tmpccmr1 |= TIM_CCMR1_CC1S_0; 04561 } 04562 04563 /* Set the filter */ 04564 tmpccmr1 &= ~TIM_CCMR1_IC1F; 04565 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); 04566 04567 /* Select the Polarity and set the CC1E Bit */ 04568 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 04569 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); 04570 04571 /* Write to TIMx CCMR1 and CCER registers */ 04572 TIMx->CCMR1 = tmpccmr1; 04573 TIMx->CCER = tmpccer; 04574 } 04575 04576 /** 04577 * @brief Time Output Compare 2 configuration 04578 * @param TIMx to select the TIM peripheral 04579 * @param OC_Config The output configuration structure 04580 * @retval None 04581 */ 04582 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) 04583 { 04584 uint32_t tmpccmrx = 0U; 04585 uint32_t tmpccer = 0U; 04586 uint32_t tmpcr2 = 0U; 04587 04588 /* Disable the Channel 2: Reset the CC2E Bit */ 04589 TIMx->CCER &= ~TIM_CCER_CC2E; 04590 04591 /* Get the TIMx CCER register value */ 04592 tmpccer = TIMx->CCER; 04593 /* Get the TIMx CR2 register value */ 04594 tmpcr2 = TIMx->CR2; 04595 04596 /* Get the TIMx CCMR1 register value */ 04597 tmpccmrx = TIMx->CCMR1; 04598 04599 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 04600 tmpccmrx &= ~TIM_CCMR1_OC2M; 04601 tmpccmrx &= ~TIM_CCMR1_CC2S; 04602 04603 /* Select the Output Compare Mode */ 04604 tmpccmrx |= (OC_Config->OCMode << 8U); 04605 04606 /* Reset the Output Polarity level */ 04607 tmpccer &= ~TIM_CCER_CC2P; 04608 /* Set the Output Compare Polarity */ 04609 tmpccer |= (OC_Config->OCPolarity << 4U); 04610 04611 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) 04612 { 04613 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); 04614 04615 /* Reset the Output N Polarity level */ 04616 tmpccer &= ~TIM_CCER_CC2NP; 04617 /* Set the Output N Polarity */ 04618 tmpccer |= (OC_Config->OCNPolarity << 4U); 04619 /* Reset the Output N State */ 04620 tmpccer &= ~TIM_CCER_CC2NE; 04621 04622 /* Reset the Output Compare and Output Compare N IDLE State */ 04623 tmpcr2 &= ~TIM_CR2_OIS2; 04624 tmpcr2 &= ~TIM_CR2_OIS2N; 04625 /* Set the Output Idle state */ 04626 tmpcr2 |= (OC_Config->OCIdleState << 2U); 04627 /* Set the Output N Idle state */ 04628 tmpcr2 |= (OC_Config->OCNIdleState << 2U); 04629 } 04630 /* Write to TIMx CR2 */ 04631 TIMx->CR2 = tmpcr2; 04632 04633 /* Write to TIMx CCMR1 */ 04634 TIMx->CCMR1 = tmpccmrx; 04635 04636 /* Set the Capture Compare Register value */ 04637 TIMx->CCR2 = OC_Config->Pulse; 04638 04639 /* Write to TIMx CCER */ 04640 TIMx->CCER = tmpccer; 04641 } 04642 04643 /** 04644 * @brief TIM DMA Delay Pulse complete callback. 04645 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 04646 * the configuration information for the specified DMA module. 04647 * @retval None 04648 */ 04649 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) 04650 { 04651 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 04652 04653 htim->State= HAL_TIM_STATE_READY; 04654 04655 if(hdma == htim->hdma[TIM_DMA_ID_CC1]) 04656 { 04657 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 04658 } 04659 else if(hdma == htim->hdma[TIM_DMA_ID_CC2]) 04660 { 04661 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 04662 } 04663 else if(hdma == htim->hdma[TIM_DMA_ID_CC3]) 04664 { 04665 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 04666 } 04667 else if(hdma == htim->hdma[TIM_DMA_ID_CC4]) 04668 { 04669 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 04670 } 04671 04672 HAL_TIM_PWM_PulseFinishedCallback(htim); 04673 04674 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 04675 } 04676 04677 /** 04678 * @brief TIM DMA error callback 04679 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 04680 * the configuration information for the specified DMA module. 04681 * @retval None 04682 */ 04683 void TIM_DMAError(DMA_HandleTypeDef *hdma) 04684 { 04685 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 04686 04687 htim->State= HAL_TIM_STATE_READY; 04688 04689 HAL_TIM_ErrorCallback(htim); 04690 } 04691 04692 /** 04693 * @brief TIM DMA Capture complete callback. 04694 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 04695 * the configuration information for the specified DMA module. 04696 * @retval None 04697 */ 04698 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) 04699 { 04700 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 04701 04702 htim->State= HAL_TIM_STATE_READY; 04703 04704 if(hdma == htim->hdma[TIM_DMA_ID_CC1]) 04705 { 04706 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 04707 } 04708 else if(hdma == htim->hdma[TIM_DMA_ID_CC2]) 04709 { 04710 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 04711 } 04712 else if(hdma == htim->hdma[TIM_DMA_ID_CC3]) 04713 { 04714 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 04715 } 04716 else if(hdma == htim->hdma[TIM_DMA_ID_CC4]) 04717 { 04718 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 04719 } 04720 04721 HAL_TIM_IC_CaptureCallback(htim); 04722 04723 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 04724 } 04725 04726 /** 04727 * @brief Enables or disables the TIM Capture Compare Channel x. 04728 * @param TIMx to select the TIM peripheral 04729 * @param Channel specifies the TIM Channel 04730 * This parameter can be one of the following values: 04731 * @arg TIM_Channel_1: TIM Channel 1 04732 * @arg TIM_Channel_2: TIM Channel 2 04733 * @arg TIM_Channel_3: TIM Channel 3 04734 * @arg TIM_Channel_4: TIM Channel 4 04735 * @param ChannelState specifies the TIM Channel CCxE bit new state. 04736 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. 04737 * @retval None 04738 */ 04739 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) 04740 { 04741 uint32_t tmp = 0U; 04742 04743 /* Check the parameters */ 04744 assert_param(IS_TIM_CC1_INSTANCE(TIMx)); 04745 assert_param(IS_TIM_CHANNELS(Channel)); 04746 04747 tmp = TIM_CCER_CC1E << Channel; 04748 04749 /* Reset the CCxE Bit */ 04750 TIMx->CCER &= ~tmp; 04751 04752 /* Set or reset the CCxE Bit */ 04753 TIMx->CCER |= (uint32_t)(ChannelState << Channel); 04754 } 04755 04756 /** 04757 * @brief TIM DMA Period Elapse complete callback. 04758 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 04759 * the configuration information for the specified DMA module. 04760 * @retval None 04761 */ 04762 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) 04763 { 04764 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 04765 04766 htim->State= HAL_TIM_STATE_READY; 04767 04768 HAL_TIM_PeriodElapsedCallback(htim); 04769 } 04770 04771 /** 04772 * @brief TIM DMA Trigger callback. 04773 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 04774 * the configuration information for the specified DMA module. 04775 * @retval None 04776 */ 04777 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) 04778 { 04779 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 04780 04781 htim->State= HAL_TIM_STATE_READY; 04782 04783 HAL_TIM_TriggerCallback(htim); 04784 } 04785 04786 /** 04787 * @brief Time Output Compare 1 configuration 04788 * @param TIMx to select the TIM peripheral 04789 * @param OC_Config The output configuration structure 04790 * @retval None 04791 */ 04792 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) 04793 { 04794 uint32_t tmpccmrx = 0U; 04795 uint32_t tmpccer = 0U; 04796 uint32_t tmpcr2 = 0U; 04797 04798 /* Disable the Channel 1: Reset the CC1E Bit */ 04799 TIMx->CCER &= ~TIM_CCER_CC1E; 04800 04801 /* Get the TIMx CCER register value */ 04802 tmpccer = TIMx->CCER; 04803 /* Get the TIMx CR2 register value */ 04804 tmpcr2 = TIMx->CR2; 04805 04806 /* Get the TIMx CCMR1 register value */ 04807 tmpccmrx = TIMx->CCMR1; 04808 04809 /* Reset the Output Compare Mode Bits */ 04810 tmpccmrx &= ~TIM_CCMR1_OC1M; 04811 tmpccmrx &= ~TIM_CCMR1_CC1S; 04812 /* Select the Output Compare Mode */ 04813 tmpccmrx |= OC_Config->OCMode; 04814 04815 /* Reset the Output Polarity level */ 04816 tmpccer &= ~TIM_CCER_CC1P; 04817 /* Set the Output Compare Polarity */ 04818 tmpccer |= OC_Config->OCPolarity; 04819 04820 04821 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) 04822 { 04823 /* Reset the Output N Polarity level */ 04824 tmpccer &= ~TIM_CCER_CC1NP; 04825 /* Set the Output N Polarity */ 04826 tmpccer |= OC_Config->OCNPolarity; 04827 /* Reset the Output N State */ 04828 tmpccer &= ~TIM_CCER_CC1NE; 04829 04830 /* Reset the Output Compare and Output Compare N IDLE State */ 04831 tmpcr2 &= ~TIM_CR2_OIS1; 04832 tmpcr2 &= ~TIM_CR2_OIS1N; 04833 /* Set the Output Idle state */ 04834 tmpcr2 |= OC_Config->OCIdleState; 04835 /* Set the Output N Idle state */ 04836 tmpcr2 |= OC_Config->OCNIdleState; 04837 } 04838 /* Write to TIMx CR2 */ 04839 TIMx->CR2 = tmpcr2; 04840 04841 /* Write to TIMx CCMR1 */ 04842 TIMx->CCMR1 = tmpccmrx; 04843 04844 /* Set the Capture Compare Register value */ 04845 TIMx->CCR1 = OC_Config->Pulse; 04846 04847 /* Write to TIMx CCER */ 04848 TIMx->CCER = tmpccer; 04849 } 04850 04851 /** 04852 * @brief Time Output Compare 3 configuration 04853 * @param TIMx to select the TIM peripheral 04854 * @param OC_Config The output configuration structure 04855 * @retval None 04856 */ 04857 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) 04858 { 04859 uint32_t tmpccmrx = 0U; 04860 uint32_t tmpccer = 0U; 04861 uint32_t tmpcr2 = 0U; 04862 04863 /* Disable the Channel 3: Reset the CC2E Bit */ 04864 TIMx->CCER &= ~TIM_CCER_CC3E; 04865 04866 /* Get the TIMx CCER register value */ 04867 tmpccer = TIMx->CCER; 04868 /* Get the TIMx CR2 register value */ 04869 tmpcr2 = TIMx->CR2; 04870 04871 /* Get the TIMx CCMR2 register value */ 04872 tmpccmrx = TIMx->CCMR2; 04873 04874 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 04875 tmpccmrx &= ~TIM_CCMR2_OC3M; 04876 tmpccmrx &= ~TIM_CCMR2_CC3S; 04877 /* Select the Output Compare Mode */ 04878 tmpccmrx |= OC_Config->OCMode; 04879 04880 /* Reset the Output Polarity level */ 04881 tmpccer &= ~TIM_CCER_CC3P; 04882 /* Set the Output Compare Polarity */ 04883 tmpccer |= (OC_Config->OCPolarity << 8U); 04884 04885 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) 04886 { 04887 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); 04888 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); 04889 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); 04890 04891 /* Reset the Output N Polarity level */ 04892 tmpccer &= ~TIM_CCER_CC3NP; 04893 /* Set the Output N Polarity */ 04894 tmpccer |= (OC_Config->OCNPolarity << 8U); 04895 /* Reset the Output N State */ 04896 tmpccer &= ~TIM_CCER_CC3NE; 04897 04898 /* Reset the Output Compare and Output Compare N IDLE State */ 04899 tmpcr2 &= ~TIM_CR2_OIS3; 04900 tmpcr2 &= ~TIM_CR2_OIS3N; 04901 /* Set the Output Idle state */ 04902 tmpcr2 |= (OC_Config->OCIdleState << 4U); 04903 /* Set the Output N Idle state */ 04904 tmpcr2 |= (OC_Config->OCNIdleState << 4U); 04905 } 04906 /* Write to TIMx CR2 */ 04907 TIMx->CR2 = tmpcr2; 04908 04909 /* Write to TIMx CCMR2 */ 04910 TIMx->CCMR2 = tmpccmrx; 04911 04912 /* Set the Capture Compare Register value */ 04913 TIMx->CCR3 = OC_Config->Pulse; 04914 04915 /* Write to TIMx CCER */ 04916 TIMx->CCER = tmpccer; 04917 } 04918 04919 /** 04920 * @brief Time Output Compare 4 configuration 04921 * @param TIMx to select the TIM peripheral 04922 * @param OC_Config The output configuration structure 04923 * @retval None 04924 */ 04925 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) 04926 { 04927 uint32_t tmpccmrx = 0U; 04928 uint32_t tmpccer = 0U; 04929 uint32_t tmpcr2 = 0U; 04930 04931 /* Disable the Channel 4: Reset the CC4E Bit */ 04932 TIMx->CCER &= ~TIM_CCER_CC4E; 04933 04934 /* Get the TIMx CCER register value */ 04935 tmpccer = TIMx->CCER; 04936 /* Get the TIMx CR2 register value */ 04937 tmpcr2 = TIMx->CR2; 04938 04939 /* Get the TIMx CCMR2 register value */ 04940 tmpccmrx = TIMx->CCMR2; 04941 04942 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 04943 tmpccmrx &= ~TIM_CCMR2_OC4M; 04944 tmpccmrx &= ~TIM_CCMR2_CC4S; 04945 04946 /* Select the Output Compare Mode */ 04947 tmpccmrx |= (OC_Config->OCMode << 8U); 04948 04949 /* Reset the Output Polarity level */ 04950 tmpccer &= ~TIM_CCER_CC4P; 04951 /* Set the Output Compare Polarity */ 04952 tmpccer |= (OC_Config->OCPolarity << 12U); 04953 04954 /*if((TIMx == TIM1) || (TIMx == TIM8))*/ 04955 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET) 04956 { 04957 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); 04958 /* Reset the Output Compare IDLE State */ 04959 tmpcr2 &= ~TIM_CR2_OIS4; 04960 /* Set the Output Idle state */ 04961 tmpcr2 |= (OC_Config->OCIdleState << 6U); 04962 } 04963 /* Write to TIMx CR2 */ 04964 TIMx->CR2 = tmpcr2; 04965 04966 /* Write to TIMx CCMR2 */ 04967 TIMx->CCMR2 = tmpccmrx; 04968 04969 /* Set the Capture Compare Register value */ 04970 TIMx->CCR4 = OC_Config->Pulse; 04971 04972 /* Write to TIMx CCER */ 04973 TIMx->CCER = tmpccer; 04974 } 04975 04976 /** 04977 * @brief Time Output Compare 4 configuration 04978 * @param htim pointer to a TIM_HandleTypeDef structure that contains 04979 * the configuration information for TIM module. 04980 * @param sSlaveConfig The slave configuration structure 04981 * @retval None 04982 */ 04983 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, 04984 TIM_SlaveConfigTypeDef * sSlaveConfig) 04985 { 04986 uint32_t tmpsmcr = 0U; 04987 uint32_t tmpccmr1 = 0U; 04988 uint32_t tmpccer = 0U; 04989 04990 /* Get the TIMx SMCR register value */ 04991 tmpsmcr = htim->Instance->SMCR; 04992 04993 /* Reset the Trigger Selection Bits */ 04994 tmpsmcr &= ~TIM_SMCR_TS; 04995 /* Set the Input Trigger source */ 04996 tmpsmcr |= sSlaveConfig->InputTrigger; 04997 04998 /* Reset the slave mode Bits */ 04999 tmpsmcr &= ~TIM_SMCR_SMS; 05000 /* Set the slave mode */ 05001 tmpsmcr |= sSlaveConfig->SlaveMode; 05002 05003 /* Write to TIMx SMCR */ 05004 htim->Instance->SMCR = tmpsmcr; 05005 05006 /* Configure the trigger prescaler, filter, and polarity */ 05007 switch (sSlaveConfig->InputTrigger) 05008 { 05009 case TIM_TS_ETRF: 05010 { 05011 /* Check the parameters */ 05012 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); 05013 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); 05014 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); 05015 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); 05016 /* Configure the ETR Trigger source */ 05017 TIM_ETR_SetConfig(htim->Instance, 05018 sSlaveConfig->TriggerPrescaler, 05019 sSlaveConfig->TriggerPolarity, 05020 sSlaveConfig->TriggerFilter); 05021 } 05022 break; 05023 05024 case TIM_TS_TI1F_ED: 05025 { 05026 /* Check the parameters */ 05027 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 05028 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); 05029 05030 /* Disable the Channel 1: Reset the CC1E Bit */ 05031 tmpccer = htim->Instance->CCER; 05032 htim->Instance->CCER &= ~TIM_CCER_CC1E; 05033 tmpccmr1 = htim->Instance->CCMR1; 05034 05035 /* Set the filter */ 05036 tmpccmr1 &= ~TIM_CCMR1_IC1F; 05037 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); 05038 05039 /* Write to TIMx CCMR1 and CCER registers */ 05040 htim->Instance->CCMR1 = tmpccmr1; 05041 htim->Instance->CCER = tmpccer; 05042 05043 } 05044 break; 05045 05046 case TIM_TS_TI1FP1: 05047 { 05048 /* Check the parameters */ 05049 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 05050 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); 05051 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); 05052 05053 /* Configure TI1 Filter and Polarity */ 05054 TIM_TI1_ConfigInputStage(htim->Instance, 05055 sSlaveConfig->TriggerPolarity, 05056 sSlaveConfig->TriggerFilter); 05057 } 05058 break; 05059 05060 case TIM_TS_TI2FP2: 05061 { 05062 /* Check the parameters */ 05063 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 05064 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); 05065 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); 05066 05067 /* Configure TI2 Filter and Polarity */ 05068 TIM_TI2_ConfigInputStage(htim->Instance, 05069 sSlaveConfig->TriggerPolarity, 05070 sSlaveConfig->TriggerFilter); 05071 } 05072 break; 05073 05074 case TIM_TS_ITR0: 05075 { 05076 /* Check the parameter */ 05077 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 05078 } 05079 break; 05080 05081 case TIM_TS_ITR1: 05082 { 05083 /* Check the parameter */ 05084 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 05085 } 05086 break; 05087 05088 case TIM_TS_ITR2: 05089 { 05090 /* Check the parameter */ 05091 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 05092 } 05093 break; 05094 05095 case TIM_TS_ITR3: 05096 { 05097 /* Check the parameter */ 05098 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 05099 } 05100 break; 05101 05102 default: 05103 break; 05104 } 05105 } 05106 05107 05108 /** 05109 * @brief Configure the Polarity and Filter for TI1. 05110 * @param TIMx to select the TIM peripheral. 05111 * @param TIM_ICPolarity The Input Polarity. 05112 * This parameter can be one of the following values: 05113 * @arg TIM_ICPolarity_Rising 05114 * @arg TIM_ICPolarity_Falling 05115 * @arg TIM_ICPolarity_BothEdge 05116 * @param TIM_ICFilter Specifies the Input Capture Filter. 05117 * This parameter must be a value between 0x00 and 0x0F. 05118 * @retval None 05119 */ 05120 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) 05121 { 05122 uint32_t tmpccmr1 = 0U; 05123 uint32_t tmpccer = 0U; 05124 05125 /* Disable the Channel 1: Reset the CC1E Bit */ 05126 tmpccer = TIMx->CCER; 05127 TIMx->CCER &= ~TIM_CCER_CC1E; 05128 tmpccmr1 = TIMx->CCMR1; 05129 05130 /* Set the filter */ 05131 tmpccmr1 &= ~TIM_CCMR1_IC1F; 05132 tmpccmr1 |= (TIM_ICFilter << 4U); 05133 05134 /* Select the Polarity and set the CC1E Bit */ 05135 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 05136 tmpccer |= TIM_ICPolarity; 05137 05138 /* Write to TIMx CCMR1 and CCER registers */ 05139 TIMx->CCMR1 = tmpccmr1; 05140 TIMx->CCER = tmpccer; 05141 } 05142 05143 /** 05144 * @brief Configure the TI2 as Input. 05145 * @param TIMx to select the TIM peripheral 05146 * @param TIM_ICPolarity The Input Polarity. 05147 * This parameter can be one of the following values: 05148 * @arg TIM_ICPolarity_Rising 05149 * @arg TIM_ICPolarity_Falling 05150 * @arg TIM_ICPolarity_BothEdge 05151 * @param TIM_ICSelection specifies the input to be used. 05152 * This parameter can be one of the following values: 05153 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. 05154 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. 05155 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. 05156 * @param TIM_ICFilter Specifies the Input Capture Filter. 05157 * This parameter must be a value between 0x00 and 0x0F. 05158 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 05159 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be 05160 * protected against un-initialized filter and polarity values. 05161 * @retval None 05162 */ 05163 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 05164 uint32_t TIM_ICFilter) 05165 { 05166 uint32_t tmpccmr1 = 0U; 05167 uint32_t tmpccer = 0U; 05168 05169 /* Disable the Channel 2: Reset the CC2E Bit */ 05170 TIMx->CCER &= ~TIM_CCER_CC2E; 05171 tmpccmr1 = TIMx->CCMR1; 05172 tmpccer = TIMx->CCER; 05173 05174 /* Select the Input */ 05175 tmpccmr1 &= ~TIM_CCMR1_CC2S; 05176 tmpccmr1 |= (TIM_ICSelection << 8U); 05177 05178 /* Set the filter */ 05179 tmpccmr1 &= ~TIM_CCMR1_IC2F; 05180 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); 05181 05182 /* Select the Polarity and set the CC2E Bit */ 05183 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 05184 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); 05185 05186 /* Write to TIMx CCMR1 and CCER registers */ 05187 TIMx->CCMR1 = tmpccmr1 ; 05188 TIMx->CCER = tmpccer; 05189 } 05190 05191 /** 05192 * @brief Configure the Polarity and Filter for TI2. 05193 * @param TIMx to select the TIM peripheral. 05194 * @param TIM_ICPolarity The Input Polarity. 05195 * This parameter can be one of the following values: 05196 * @arg TIM_ICPolarity_Rising 05197 * @arg TIM_ICPolarity_Falling 05198 * @arg TIM_ICPolarity_BothEdge 05199 * @param TIM_ICFilter Specifies the Input Capture Filter. 05200 * This parameter must be a value between 0x00 and 0x0F. 05201 * @retval None 05202 */ 05203 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) 05204 { 05205 uint32_t tmpccmr1 = 0U; 05206 uint32_t tmpccer = 0U; 05207 05208 /* Disable the Channel 2: Reset the CC2E Bit */ 05209 TIMx->CCER &= ~TIM_CCER_CC2E; 05210 tmpccmr1 = TIMx->CCMR1; 05211 tmpccer = TIMx->CCER; 05212 05213 /* Set the filter */ 05214 tmpccmr1 &= ~TIM_CCMR1_IC2F; 05215 tmpccmr1 |= (TIM_ICFilter << 12U); 05216 05217 /* Select the Polarity and set the CC2E Bit */ 05218 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 05219 tmpccer |= (TIM_ICPolarity << 4U); 05220 05221 /* Write to TIMx CCMR1 and CCER registers */ 05222 TIMx->CCMR1 = tmpccmr1 ; 05223 TIMx->CCER = tmpccer; 05224 } 05225 05226 /** 05227 * @brief Configure the TI3 as Input. 05228 * @param TIMx to select the TIM peripheral 05229 * @param TIM_ICPolarity The Input Polarity. 05230 * This parameter can be one of the following values: 05231 * @arg TIM_ICPolarity_Rising 05232 * @arg TIM_ICPolarity_Falling 05233 * @arg TIM_ICPolarity_BothEdge 05234 * @param TIM_ICSelection specifies the input to be used. 05235 * This parameter can be one of the following values: 05236 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. 05237 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. 05238 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. 05239 * @param TIM_ICFilter Specifies the Input Capture Filter. 05240 * This parameter must be a value between 0x00 and 0x0F. 05241 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 05242 * (on channel4 path) is used as the input signal. Therefore CCMR2 must be 05243 * protected against un-initialized filter and polarity values. 05244 * @retval None 05245 */ 05246 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 05247 uint32_t TIM_ICFilter) 05248 { 05249 uint32_t tmpccmr2 = 0U; 05250 uint32_t tmpccer = 0U; 05251 05252 /* Disable the Channel 3: Reset the CC3E Bit */ 05253 TIMx->CCER &= ~TIM_CCER_CC3E; 05254 tmpccmr2 = TIMx->CCMR2; 05255 tmpccer = TIMx->CCER; 05256 05257 /* Select the Input */ 05258 tmpccmr2 &= ~TIM_CCMR2_CC3S; 05259 tmpccmr2 |= TIM_ICSelection; 05260 05261 /* Set the filter */ 05262 tmpccmr2 &= ~TIM_CCMR2_IC3F; 05263 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); 05264 05265 /* Select the Polarity and set the CC3E Bit */ 05266 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); 05267 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); 05268 05269 /* Write to TIMx CCMR2 and CCER registers */ 05270 TIMx->CCMR2 = tmpccmr2; 05271 TIMx->CCER = tmpccer; 05272 } 05273 05274 /** 05275 * @brief Configure the TI4 as Input. 05276 * @param TIMx to select the TIM peripheral 05277 * @param TIM_ICPolarity The Input Polarity. 05278 * This parameter can be one of the following values: 05279 * @arg TIM_ICPolarity_Rising 05280 * @arg TIM_ICPolarity_Falling 05281 * @arg TIM_ICPolarity_BothEdge 05282 * @param TIM_ICSelection specifies the input to be used. 05283 * This parameter can be one of the following values: 05284 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. 05285 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. 05286 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. 05287 * @param TIM_ICFilter Specifies the Input Capture Filter. 05288 * This parameter must be a value between 0x00 and 0x0F. 05289 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 05290 * (on channel3 path) is used as the input signal. Therefore CCMR2 must be 05291 * protected against un-initialized filter and polarity values. 05292 * @retval None 05293 */ 05294 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 05295 uint32_t TIM_ICFilter) 05296 { 05297 uint32_t tmpccmr2 = 0U; 05298 uint32_t tmpccer = 0U; 05299 05300 /* Disable the Channel 4: Reset the CC4E Bit */ 05301 TIMx->CCER &= ~TIM_CCER_CC4E; 05302 tmpccmr2 = TIMx->CCMR2; 05303 tmpccer = TIMx->CCER; 05304 05305 /* Select the Input */ 05306 tmpccmr2 &= ~TIM_CCMR2_CC4S; 05307 tmpccmr2 |= (TIM_ICSelection << 8U); 05308 05309 /* Set the filter */ 05310 tmpccmr2 &= ~TIM_CCMR2_IC4F; 05311 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); 05312 05313 /* Select the Polarity and set the CC4E Bit */ 05314 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); 05315 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); 05316 05317 /* Write to TIMx CCMR2 and CCER registers */ 05318 TIMx->CCMR2 = tmpccmr2; 05319 TIMx->CCER = tmpccer ; 05320 } 05321 05322 /** 05323 * @brief Selects the Input Trigger source 05324 * @param TIMx to select the TIM peripheral 05325 * @param TIM_ITRx The Input Trigger source. 05326 * This parameter can be one of the following values: 05327 * @arg TIM_TS_ITR0: Internal Trigger 0 05328 * @arg TIM_TS_ITR1: Internal Trigger 1 05329 * @arg TIM_TS_ITR2: Internal Trigger 2 05330 * @arg TIM_TS_ITR3: Internal Trigger 3 05331 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector 05332 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 05333 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 05334 * @arg TIM_TS_ETRF: External Trigger input 05335 * @retval None 05336 */ 05337 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx) 05338 { 05339 uint32_t tmpsmcr = 0U; 05340 05341 /* Get the TIMx SMCR register value */ 05342 tmpsmcr = TIMx->SMCR; 05343 /* Reset the TS Bits */ 05344 tmpsmcr &= ~TIM_SMCR_TS; 05345 /* Set the Input Trigger source and the slave mode*/ 05346 tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1; 05347 /* Write to TIMx SMCR */ 05348 TIMx->SMCR = tmpsmcr; 05349 } 05350 05351 /** 05352 * @brief Configures the TIMx External Trigger (ETR). 05353 * @param TIMx to select the TIM peripheral 05354 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. 05355 * This parameter can be one of the following values: 05356 * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. 05357 * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. 05358 * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. 05359 * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. 05360 * @param TIM_ExtTRGPolarity The external Trigger Polarity. 05361 * This parameter can be one of the following values: 05362 * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. 05363 * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. 05364 * @param ExtTRGFilter External Trigger Filter. 05365 * This parameter must be a value between 0x00 and 0x0F 05366 * @retval None 05367 */ 05368 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, 05369 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) 05370 { 05371 uint32_t tmpsmcr = 0U; 05372 05373 tmpsmcr = TIMx->SMCR; 05374 05375 /* Reset the ETR Bits */ 05376 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 05377 05378 /* Set the Prescaler, the Filter value and the Polarity */ 05379 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8))); 05380 05381 /* Write to TIMx SMCR */ 05382 TIMx->SMCR = tmpsmcr; 05383 } 05384 05385 /** 05386 * @} 05387 */ 05388 05389 #endif /* HAL_TIM_MODULE_ENABLED */ 05390 /** 05391 * @} 05392 */ 05393 05394 /** 05395 * @} 05396 */ 05397 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/