STM32F439xx HAL User Manual
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Enable or disable the High Speed APB (APB2) peripheral clock. More...
Defines | |
#define | __HAL_RCC_TIM1_CLK_ENABLE() |
#define | __HAL_RCC_USART1_CLK_ENABLE() |
#define | __HAL_RCC_USART6_CLK_ENABLE() |
#define | __HAL_RCC_ADC1_CLK_ENABLE() |
#define | __HAL_RCC_SPI1_CLK_ENABLE() |
#define | __HAL_RCC_SYSCFG_CLK_ENABLE() |
#define | __HAL_RCC_TIM9_CLK_ENABLE() |
#define | __HAL_RCC_TIM11_CLK_ENABLE() |
#define | __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) |
#define | __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) |
#define | __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) |
#define | __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) |
#define | __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) |
#define | __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) |
#define | __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) |
#define | __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) |
Enable or disable the High Speed APB (APB2) peripheral clock.
#define __HAL_RCC_ADC1_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) |
Definition at line 640 of file stm32f4xx_hal_rcc.h.
#define __HAL_RCC_ADC1_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 601 of file stm32f4xx_hal_rcc.h.
#define __HAL_RCC_SPI1_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) |
Definition at line 641 of file stm32f4xx_hal_rcc.h.
#define __HAL_RCC_SPI1_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 608 of file stm32f4xx_hal_rcc.h.
#define __HAL_RCC_SYSCFG_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) |
Definition at line 642 of file stm32f4xx_hal_rcc.h.
#define __HAL_RCC_SYSCFG_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 615 of file stm32f4xx_hal_rcc.h.
Referenced by HAL_ETH_Init(), and HAL_GPIO_Init().
#define __HAL_RCC_TIM11_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) |
Definition at line 644 of file stm32f4xx_hal_rcc.h.
#define __HAL_RCC_TIM11_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 629 of file stm32f4xx_hal_rcc.h.
#define __HAL_RCC_TIM1_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) |
Definition at line 637 of file stm32f4xx_hal_rcc.h.
#define __HAL_RCC_TIM1_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 580 of file stm32f4xx_hal_rcc.h.
#define __HAL_RCC_TIM9_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) |
Definition at line 643 of file stm32f4xx_hal_rcc.h.
#define __HAL_RCC_TIM9_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 622 of file stm32f4xx_hal_rcc.h.
#define __HAL_RCC_USART1_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) |
Definition at line 638 of file stm32f4xx_hal_rcc.h.
#define __HAL_RCC_USART1_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 587 of file stm32f4xx_hal_rcc.h.
#define __HAL_RCC_USART6_CLK_DISABLE | ( | ) | (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) |
Definition at line 639 of file stm32f4xx_hal_rcc.h.
#define __HAL_RCC_USART6_CLK_ENABLE | ( | ) |
do { \ __IO uint32_t tmpreg = 0x00U; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ UNUSED(tmpreg); \ } while(0U)
Definition at line 594 of file stm32f4xx_hal_rcc.h.