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STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_rcc.h 00004 * @author MCD Application Team 00005 * @brief Header file of RCC HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32F4xx_HAL_RCC_H 00038 #define __STM32F4xx_HAL_RCC_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32f4xx_hal_def.h" 00046 00047 /* Include RCC HAL Extended module */ 00048 /* (include on top of file since RCC structures are defined in extended file) */ 00049 #include "stm32f4xx_hal_rcc_ex.h" 00050 00051 /** @addtogroup STM32F4xx_HAL_Driver 00052 * @{ 00053 */ 00054 00055 /** @addtogroup RCC 00056 * @{ 00057 */ 00058 00059 /* Exported types ------------------------------------------------------------*/ 00060 /** @defgroup RCC_Exported_Types RCC Exported Types 00061 * @{ 00062 */ 00063 00064 /** 00065 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition 00066 */ 00067 typedef struct 00068 { 00069 uint32_t OscillatorType; /*!< The oscillators to be configured. 00070 This parameter can be a value of @ref RCC_Oscillator_Type */ 00071 00072 uint32_t HSEState; /*!< The new state of the HSE. 00073 This parameter can be a value of @ref RCC_HSE_Config */ 00074 00075 uint32_t LSEState; /*!< The new state of the LSE. 00076 This parameter can be a value of @ref RCC_LSE_Config */ 00077 00078 uint32_t HSIState; /*!< The new state of the HSI. 00079 This parameter can be a value of @ref RCC_HSI_Config */ 00080 00081 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 00082 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 00083 00084 uint32_t LSIState; /*!< The new state of the LSI. 00085 This parameter can be a value of @ref RCC_LSI_Config */ 00086 00087 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ 00088 }RCC_OscInitTypeDef; 00089 00090 /** 00091 * @brief RCC System, AHB and APB busses clock configuration structure definition 00092 */ 00093 typedef struct 00094 { 00095 uint32_t ClockType; /*!< The clock to be configured. 00096 This parameter can be a value of @ref RCC_System_Clock_Type */ 00097 00098 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. 00099 This parameter can be a value of @ref RCC_System_Clock_Source */ 00100 00101 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 00102 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 00103 00104 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 00105 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 00106 00107 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 00108 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 00109 00110 }RCC_ClkInitTypeDef; 00111 00112 /** 00113 * @} 00114 */ 00115 00116 /* Exported constants --------------------------------------------------------*/ 00117 /** @defgroup RCC_Exported_Constants RCC Exported Constants 00118 * @{ 00119 */ 00120 00121 /** @defgroup RCC_Oscillator_Type Oscillator Type 00122 * @{ 00123 */ 00124 #define RCC_OSCILLATORTYPE_NONE 0x00000000U 00125 #define RCC_OSCILLATORTYPE_HSE 0x00000001U 00126 #define RCC_OSCILLATORTYPE_HSI 0x00000002U 00127 #define RCC_OSCILLATORTYPE_LSE 0x00000004U 00128 #define RCC_OSCILLATORTYPE_LSI 0x00000008U 00129 /** 00130 * @} 00131 */ 00132 00133 /** @defgroup RCC_HSE_Config HSE Config 00134 * @{ 00135 */ 00136 #define RCC_HSE_OFF 0x00000000U 00137 #define RCC_HSE_ON RCC_CR_HSEON 00138 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) 00139 /** 00140 * @} 00141 */ 00142 00143 /** @defgroup RCC_LSE_Config LSE Config 00144 * @{ 00145 */ 00146 #define RCC_LSE_OFF 0x00000000U 00147 #define RCC_LSE_ON RCC_BDCR_LSEON 00148 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) 00149 /** 00150 * @} 00151 */ 00152 00153 /** @defgroup RCC_HSI_Config HSI Config 00154 * @{ 00155 */ 00156 #define RCC_HSI_OFF ((uint8_t)0x00) 00157 #define RCC_HSI_ON ((uint8_t)0x01) 00158 00159 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ 00160 /** 00161 * @} 00162 */ 00163 00164 /** @defgroup RCC_LSI_Config LSI Config 00165 * @{ 00166 */ 00167 #define RCC_LSI_OFF ((uint8_t)0x00) 00168 #define RCC_LSI_ON ((uint8_t)0x01) 00169 /** 00170 * @} 00171 */ 00172 00173 /** @defgroup RCC_PLL_Config PLL Config 00174 * @{ 00175 */ 00176 #define RCC_PLL_NONE ((uint8_t)0x00) 00177 #define RCC_PLL_OFF ((uint8_t)0x01) 00178 #define RCC_PLL_ON ((uint8_t)0x02) 00179 /** 00180 * @} 00181 */ 00182 00183 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 00184 * @{ 00185 */ 00186 #define RCC_PLLP_DIV2 0x00000002U 00187 #define RCC_PLLP_DIV4 0x00000004U 00188 #define RCC_PLLP_DIV6 0x00000006U 00189 #define RCC_PLLP_DIV8 0x00000008U 00190 /** 00191 * @} 00192 */ 00193 00194 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 00195 * @{ 00196 */ 00197 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI 00198 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE 00199 /** 00200 * @} 00201 */ 00202 00203 /** @defgroup RCC_System_Clock_Type System Clock Type 00204 * @{ 00205 */ 00206 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U 00207 #define RCC_CLOCKTYPE_HCLK 0x00000002U 00208 #define RCC_CLOCKTYPE_PCLK1 0x00000004U 00209 #define RCC_CLOCKTYPE_PCLK2 0x00000008U 00210 /** 00211 * @} 00212 */ 00213 00214 /** @defgroup RCC_System_Clock_Source System Clock Source 00215 * @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for 00216 * STM32F446xx devices. 00217 * @{ 00218 */ 00219 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI 00220 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE 00221 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL 00222 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1)) 00223 /** 00224 * @} 00225 */ 00226 00227 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 00228 * @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for 00229 * STM32F446xx devices. 00230 * @{ 00231 */ 00232 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 00233 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 00234 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 00235 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)) /*!< PLLR used as system clock */ 00236 /** 00237 * @} 00238 */ 00239 00240 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 00241 * @{ 00242 */ 00243 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 00244 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 00245 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 00246 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 00247 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 00248 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 00249 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 00250 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 00251 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 00252 /** 00253 * @} 00254 */ 00255 00256 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source 00257 * @{ 00258 */ 00259 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 00260 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 00261 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 00262 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 00263 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 00264 /** 00265 * @} 00266 */ 00267 00268 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 00269 * @{ 00270 */ 00271 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U 00272 #define RCC_RTCCLKSOURCE_LSE 0x00000100U 00273 #define RCC_RTCCLKSOURCE_LSI 0x00000200U 00274 #define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U 00275 #define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U 00276 #define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U 00277 #define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U 00278 #define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U 00279 #define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U 00280 #define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U 00281 #define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U 00282 #define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U 00283 #define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U 00284 #define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U 00285 #define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U 00286 #define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U 00287 #define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U 00288 #define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U 00289 #define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U 00290 #define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U 00291 #define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U 00292 #define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U 00293 #define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U 00294 #define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U 00295 #define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U 00296 #define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U 00297 #define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U 00298 #define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U 00299 #define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U 00300 #define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U 00301 #define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U 00302 #define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U 00303 #define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U 00304 #define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U 00305 /** 00306 * @} 00307 */ 00308 00309 /** @defgroup RCC_MCO_Index MCO Index 00310 * @{ 00311 */ 00312 #define RCC_MCO1 0x00000000U 00313 #define RCC_MCO2 0x00000001U 00314 /** 00315 * @} 00316 */ 00317 00318 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 00319 * @{ 00320 */ 00321 #define RCC_MCO1SOURCE_HSI 0x00000000U 00322 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 00323 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 00324 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 00325 /** 00326 * @} 00327 */ 00328 00329 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler 00330 * @{ 00331 */ 00332 #define RCC_MCODIV_1 0x00000000U 00333 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 00334 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) 00335 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) 00336 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE 00337 /** 00338 * @} 00339 */ 00340 00341 /** @defgroup RCC_Interrupt Interrupts 00342 * @{ 00343 */ 00344 #define RCC_IT_LSIRDY ((uint8_t)0x01) 00345 #define RCC_IT_LSERDY ((uint8_t)0x02) 00346 #define RCC_IT_HSIRDY ((uint8_t)0x04) 00347 #define RCC_IT_HSERDY ((uint8_t)0x08) 00348 #define RCC_IT_PLLRDY ((uint8_t)0x10) 00349 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20) 00350 #define RCC_IT_CSS ((uint8_t)0x80) 00351 /** 00352 * @} 00353 */ 00354 00355 /** @defgroup RCC_Flag Flags 00356 * Elements values convention: 0XXYYYYYb 00357 * - YYYYY : Flag position in the register 00358 * - 0XX : Register index 00359 * - 01: CR register 00360 * - 10: BDCR register 00361 * - 11: CSR register 00362 * @{ 00363 */ 00364 /* Flags in the CR register */ 00365 #define RCC_FLAG_HSIRDY ((uint8_t)0x21) 00366 #define RCC_FLAG_HSERDY ((uint8_t)0x31) 00367 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 00368 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) 00369 00370 /* Flags in the BDCR register */ 00371 #define RCC_FLAG_LSERDY ((uint8_t)0x41) 00372 00373 /* Flags in the CSR register */ 00374 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 00375 #define RCC_FLAG_BORRST ((uint8_t)0x79) 00376 #define RCC_FLAG_PINRST ((uint8_t)0x7A) 00377 #define RCC_FLAG_PORRST ((uint8_t)0x7B) 00378 #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 00379 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 00380 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) 00381 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) 00382 /** 00383 * @} 00384 */ 00385 00386 /** 00387 * @} 00388 */ 00389 00390 /* Exported macro ------------------------------------------------------------*/ 00391 /** @defgroup RCC_Exported_Macros RCC Exported Macros 00392 * @{ 00393 */ 00394 00395 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 00396 * @brief Enable or disable the AHB1 peripheral clock. 00397 * @note After reset, the peripheral clock (used for registers read/write access) 00398 * is disabled and the application software has to enable this clock before 00399 * using it. 00400 * @{ 00401 */ 00402 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 00403 __IO uint32_t tmpreg = 0x00U; \ 00404 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ 00405 /* Delay after an RCC peripheral clock enabling */ \ 00406 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ 00407 UNUSED(tmpreg); \ 00408 } while(0U) 00409 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 00410 __IO uint32_t tmpreg = 0x00U; \ 00411 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ 00412 /* Delay after an RCC peripheral clock enabling */ \ 00413 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ 00414 UNUSED(tmpreg); \ 00415 } while(0U) 00416 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 00417 __IO uint32_t tmpreg = 0x00U; \ 00418 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ 00419 /* Delay after an RCC peripheral clock enabling */ \ 00420 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ 00421 UNUSED(tmpreg); \ 00422 } while(0U) 00423 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 00424 __IO uint32_t tmpreg = 0x00U; \ 00425 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ 00426 /* Delay after an RCC peripheral clock enabling */ \ 00427 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ 00428 UNUSED(tmpreg); \ 00429 } while(0U) 00430 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 00431 __IO uint32_t tmpreg = 0x00U; \ 00432 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 00433 /* Delay after an RCC peripheral clock enabling */ \ 00434 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 00435 UNUSED(tmpreg); \ 00436 } while(0U) 00437 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 00438 __IO uint32_t tmpreg = 0x00U; \ 00439 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 00440 /* Delay after an RCC peripheral clock enabling */ \ 00441 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 00442 UNUSED(tmpreg); \ 00443 } while(0U) 00444 00445 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) 00446 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) 00447 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) 00448 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) 00449 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) 00450 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) 00451 /** 00452 * @} 00453 */ 00454 00455 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 00456 * @brief Get the enable or disable status of the AHB1 peripheral clock. 00457 * @note After reset, the peripheral clock (used for registers read/write access) 00458 * is disabled and the application software has to enable this clock before 00459 * using it. 00460 * @{ 00461 */ 00462 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET) 00463 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET) 00464 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET) 00465 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET) 00466 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET) 00467 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET) 00468 00469 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET) 00470 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET) 00471 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET) 00472 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET) 00473 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET) 00474 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET) 00475 /** 00476 * @} 00477 */ 00478 00479 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 00480 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 00481 * @note After reset, the peripheral clock (used for registers read/write access) 00482 * is disabled and the application software has to enable this clock before 00483 * using it. 00484 * @{ 00485 */ 00486 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 00487 __IO uint32_t tmpreg = 0x00U; \ 00488 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 00489 /* Delay after an RCC peripheral clock enabling */ \ 00490 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 00491 UNUSED(tmpreg); \ 00492 } while(0U) 00493 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 00494 __IO uint32_t tmpreg = 0x00U; \ 00495 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 00496 /* Delay after an RCC peripheral clock enabling */ \ 00497 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 00498 UNUSED(tmpreg); \ 00499 } while(0U) 00500 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 00501 __IO uint32_t tmpreg = 0x00U; \ 00502 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 00503 /* Delay after an RCC peripheral clock enabling */ \ 00504 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 00505 UNUSED(tmpreg); \ 00506 } while(0U) 00507 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 00508 __IO uint32_t tmpreg = 0x00U; \ 00509 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 00510 /* Delay after an RCC peripheral clock enabling */ \ 00511 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 00512 UNUSED(tmpreg); \ 00513 } while(0U) 00514 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 00515 __IO uint32_t tmpreg = 0x00U; \ 00516 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 00517 /* Delay after an RCC peripheral clock enabling */ \ 00518 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 00519 UNUSED(tmpreg); \ 00520 } while(0U) 00521 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 00522 __IO uint32_t tmpreg = 0x00U; \ 00523 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 00524 /* Delay after an RCC peripheral clock enabling */ \ 00525 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 00526 UNUSED(tmpreg); \ 00527 } while(0U) 00528 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 00529 __IO uint32_t tmpreg = 0x00U; \ 00530 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 00531 /* Delay after an RCC peripheral clock enabling */ \ 00532 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 00533 UNUSED(tmpreg); \ 00534 } while(0U) 00535 00536 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) 00537 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) 00538 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) 00539 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) 00540 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) 00541 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) 00542 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) 00543 /** 00544 * @} 00545 */ 00546 00547 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 00548 * @brief Get the enable or disable status of the APB1 peripheral clock. 00549 * @note After reset, the peripheral clock (used for registers read/write access) 00550 * is disabled and the application software has to enable this clock before 00551 * using it. 00552 * @{ 00553 */ 00554 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) 00555 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) 00556 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) 00557 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) 00558 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) 00559 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) 00560 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) 00561 00562 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) 00563 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) 00564 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) 00565 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) 00566 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) 00567 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) 00568 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) 00569 /** 00570 * @} 00571 */ 00572 00573 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 00574 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 00575 * @note After reset, the peripheral clock (used for registers read/write access) 00576 * is disabled and the application software has to enable this clock before 00577 * using it. 00578 * @{ 00579 */ 00580 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 00581 __IO uint32_t tmpreg = 0x00U; \ 00582 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 00583 /* Delay after an RCC peripheral clock enabling */ \ 00584 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 00585 UNUSED(tmpreg); \ 00586 } while(0U) 00587 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 00588 __IO uint32_t tmpreg = 0x00U; \ 00589 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 00590 /* Delay after an RCC peripheral clock enabling */ \ 00591 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 00592 UNUSED(tmpreg); \ 00593 } while(0U) 00594 #define __HAL_RCC_USART6_CLK_ENABLE() do { \ 00595 __IO uint32_t tmpreg = 0x00U; \ 00596 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ 00597 /* Delay after an RCC peripheral clock enabling */ \ 00598 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ 00599 UNUSED(tmpreg); \ 00600 } while(0U) 00601 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ 00602 __IO uint32_t tmpreg = 0x00U; \ 00603 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 00604 /* Delay after an RCC peripheral clock enabling */ \ 00605 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 00606 UNUSED(tmpreg); \ 00607 } while(0U) 00608 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 00609 __IO uint32_t tmpreg = 0x00U; \ 00610 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 00611 /* Delay after an RCC peripheral clock enabling */ \ 00612 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 00613 UNUSED(tmpreg); \ 00614 } while(0U) 00615 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 00616 __IO uint32_t tmpreg = 0x00U; \ 00617 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ 00618 /* Delay after an RCC peripheral clock enabling */ \ 00619 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ 00620 UNUSED(tmpreg); \ 00621 } while(0U) 00622 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \ 00623 __IO uint32_t tmpreg = 0x00U; \ 00624 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 00625 /* Delay after an RCC peripheral clock enabling */ \ 00626 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 00627 UNUSED(tmpreg); \ 00628 } while(0U) 00629 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \ 00630 __IO uint32_t tmpreg = 0x00U; \ 00631 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 00632 /* Delay after an RCC peripheral clock enabling */ \ 00633 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 00634 UNUSED(tmpreg); \ 00635 } while(0U) 00636 00637 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) 00638 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) 00639 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) 00640 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) 00641 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) 00642 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) 00643 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) 00644 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) 00645 /** 00646 * @} 00647 */ 00648 00649 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 00650 * @brief Get the enable or disable status of the APB2 peripheral clock. 00651 * @note After reset, the peripheral clock (used for registers read/write access) 00652 * is disabled and the application software has to enable this clock before 00653 * using it. 00654 * @{ 00655 */ 00656 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) 00657 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) 00658 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) 00659 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) 00660 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) 00661 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) 00662 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) 00663 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) 00664 00665 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) 00666 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) 00667 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) 00668 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) 00669 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) 00670 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) 00671 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) 00672 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) 00673 /** 00674 * @} 00675 */ 00676 00677 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset 00678 * @brief Force or release AHB1 peripheral reset. 00679 * @{ 00680 */ 00681 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) 00682 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) 00683 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) 00684 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) 00685 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) 00686 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) 00687 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) 00688 00689 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) 00690 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) 00691 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) 00692 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) 00693 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) 00694 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) 00695 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) 00696 /** 00697 * @} 00698 */ 00699 00700 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset 00701 * @brief Force or release APB1 peripheral reset. 00702 * @{ 00703 */ 00704 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) 00705 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) 00706 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) 00707 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) 00708 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) 00709 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) 00710 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) 00711 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) 00712 00713 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) 00714 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) 00715 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) 00716 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) 00717 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) 00718 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) 00719 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) 00720 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) 00721 /** 00722 * @} 00723 */ 00724 00725 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset 00726 * @brief Force or release APB2 peripheral reset. 00727 * @{ 00728 */ 00729 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 00730 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) 00731 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) 00732 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) 00733 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) 00734 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) 00735 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) 00736 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) 00737 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) 00738 00739 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) 00740 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) 00741 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) 00742 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) 00743 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) 00744 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) 00745 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) 00746 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) 00747 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) 00748 /** 00749 * @} 00750 */ 00751 00752 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 00753 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 00754 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 00755 * power consumption. 00756 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 00757 * @note By default, all peripheral clocks are enabled during SLEEP mode. 00758 * @{ 00759 */ 00760 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) 00761 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) 00762 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) 00763 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) 00764 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) 00765 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) 00766 00767 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) 00768 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) 00769 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) 00770 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) 00771 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) 00772 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) 00773 /** 00774 * @} 00775 */ 00776 00777 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 00778 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 00779 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 00780 * power consumption. 00781 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 00782 * @note By default, all peripheral clocks are enabled during SLEEP mode. 00783 * @{ 00784 */ 00785 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) 00786 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) 00787 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) 00788 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) 00789 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) 00790 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) 00791 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) 00792 00793 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) 00794 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) 00795 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) 00796 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) 00797 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) 00798 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) 00799 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) 00800 /** 00801 * @} 00802 */ 00803 00804 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 00805 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 00806 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 00807 * power consumption. 00808 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 00809 * @note By default, all peripheral clocks are enabled during SLEEP mode. 00810 * @{ 00811 */ 00812 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) 00813 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) 00814 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) 00815 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) 00816 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) 00817 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) 00818 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) 00819 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) 00820 00821 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) 00822 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) 00823 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) 00824 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) 00825 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) 00826 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) 00827 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) 00828 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) 00829 /** 00830 * @} 00831 */ 00832 00833 /** @defgroup RCC_HSI_Configuration HSI Configuration 00834 * @{ 00835 */ 00836 00837 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 00838 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 00839 * It is used (enabled by hardware) as system clock source after startup 00840 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure 00841 * of the HSE used directly or indirectly as system clock (if the Clock 00842 * Security System CSS is enabled). 00843 * @note HSI can not be stopped if it is used as system clock source. In this case, 00844 * you have to select another source of the system clock then stop the HSI. 00845 * @note After enabling the HSI, the application software should wait on HSIRDY 00846 * flag to be set indicating that HSI clock is stable and can be used as 00847 * system clock source. 00848 * This parameter can be: ENABLE or DISABLE. 00849 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 00850 * clock cycles. 00851 */ 00852 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) 00853 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) 00854 00855 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 00856 * @note The calibration is used to compensate for the variations in voltage 00857 * and temperature that influence the frequency of the internal HSI RC. 00858 * @param __HSICalibrationValue__ specifies the calibration trimming value. 00859 * (default is RCC_HSICALIBRATION_DEFAULT). 00860 * This parameter must be a number between 0 and 0x1F. 00861 */ 00862 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\ 00863 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos)) 00864 /** 00865 * @} 00866 */ 00867 00868 /** @defgroup RCC_LSI_Configuration LSI Configuration 00869 * @{ 00870 */ 00871 00872 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 00873 * @note After enabling the LSI, the application software should wait on 00874 * LSIRDY flag to be set indicating that LSI clock is stable and can 00875 * be used to clock the IWDG and/or the RTC. 00876 * @note LSI can not be disabled if the IWDG is running. 00877 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 00878 * clock cycles. 00879 */ 00880 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) 00881 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) 00882 /** 00883 * @} 00884 */ 00885 00886 /** @defgroup RCC_HSE_Configuration HSE Configuration 00887 * @{ 00888 */ 00889 00890 /** 00891 * @brief Macro to configure the External High Speed oscillator (HSE). 00892 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. 00893 * User should request a transition to HSE Off first and then HSE On or HSE Bypass. 00894 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 00895 * software should wait on HSERDY flag to be set indicating that HSE clock 00896 * is stable and can be used to clock the PLL and/or system clock. 00897 * @note HSE state can not be changed if it is used directly or through the 00898 * PLL as system clock. In this case, you have to select another source 00899 * of the system clock then change the HSE state (ex. disable it). 00900 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 00901 * @note This function reset the CSSON bit, so if the clock security system(CSS) 00902 * was previously enabled you have to enable it again after calling this 00903 * function. 00904 * @param __STATE__ specifies the new state of the HSE. 00905 * This parameter can be one of the following values: 00906 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 00907 * 6 HSE oscillator clock cycles. 00908 * @arg RCC_HSE_ON: turn ON the HSE oscillator. 00909 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. 00910 */ 00911 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 00912 do { \ 00913 if ((__STATE__) == RCC_HSE_ON) \ 00914 { \ 00915 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 00916 } \ 00917 else if ((__STATE__) == RCC_HSE_BYPASS) \ 00918 { \ 00919 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 00920 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 00921 } \ 00922 else \ 00923 { \ 00924 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 00925 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 00926 } \ 00927 } while(0U) 00928 /** 00929 * @} 00930 */ 00931 00932 /** @defgroup RCC_LSE_Configuration LSE Configuration 00933 * @{ 00934 */ 00935 00936 /** 00937 * @brief Macro to configure the External Low Speed oscillator (LSE). 00938 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 00939 * User should request a transition to LSE Off first and then LSE On or LSE Bypass. 00940 * @note As the LSE is in the Backup domain and write access is denied to 00941 * this domain after reset, you have to enable write access using 00942 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 00943 * (to be done once after reset). 00944 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 00945 * software should wait on LSERDY flag to be set indicating that LSE clock 00946 * is stable and can be used to clock the RTC. 00947 * @param __STATE__ specifies the new state of the LSE. 00948 * This parameter can be one of the following values: 00949 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 00950 * 6 LSE oscillator clock cycles. 00951 * @arg RCC_LSE_ON: turn ON the LSE oscillator. 00952 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. 00953 */ 00954 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 00955 do { \ 00956 if((__STATE__) == RCC_LSE_ON) \ 00957 { \ 00958 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 00959 } \ 00960 else if((__STATE__) == RCC_LSE_BYPASS) \ 00961 { \ 00962 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 00963 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 00964 } \ 00965 else \ 00966 { \ 00967 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 00968 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 00969 } \ 00970 } while(0U) 00971 /** 00972 * @} 00973 */ 00974 00975 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration 00976 * @{ 00977 */ 00978 00979 /** @brief Macros to enable or disable the RTC clock. 00980 * @note These macros must be used only after the RTC clock source was selected. 00981 */ 00982 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) 00983 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) 00984 00985 /** @brief Macros to configure the RTC clock (RTCCLK). 00986 * @note As the RTC clock configuration bits are in the Backup domain and write 00987 * access is denied to this domain after reset, you have to enable write 00988 * access using the Power Backup Access macro before to configure 00989 * the RTC clock source (to be done once after reset). 00990 * @note Once the RTC clock is configured it can't be changed unless the 00991 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by 00992 * a Power On Reset (POR). 00993 * @param __RTCCLKSource__ specifies the RTC clock source. 00994 * This parameter can be one of the following values: 00995 @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock. 00996 * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. 00997 * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. 00998 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected 00999 * as RTC clock, where x:[2,31] 01000 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 01001 * work in STOP and STANDBY modes, and can be used as wake-up source. 01002 * However, when the HSE clock is used as RTC clock source, the RTC 01003 * cannot be used in STOP and STANDBY modes. 01004 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 01005 * RTC clock source). 01006 */ 01007 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ 01008 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) 01009 01010 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ 01011 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ 01012 } while(0U) 01013 01014 /** @brief Macro to get the RTC clock source. 01015 * @retval The clock source can be one of the following values: 01016 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 01017 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 01018 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 01019 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() 01020 */ 01021 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 01022 01023 /** 01024 * @brief Get the RTC and HSE clock divider (RTCPRE). 01025 * @retval Returned value can be one of the following values: 01026 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected 01027 * as RTC clock, where x:[2,31] 01028 */ 01029 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) 01030 01031 /** @brief Macros to force or release the Backup domain reset. 01032 * @note This function resets the RTC peripheral (including the backup registers) 01033 * and the RTC clock source selection in RCC_CSR register. 01034 * @note The BKPSRAM is not affected by this reset. 01035 */ 01036 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) 01037 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) 01038 /** 01039 * @} 01040 */ 01041 01042 /** @defgroup RCC_PLL_Configuration PLL Configuration 01043 * @{ 01044 */ 01045 01046 /** @brief Macros to enable or disable the main PLL. 01047 * @note After enabling the main PLL, the application software should wait on 01048 * PLLRDY flag to be set indicating that PLL clock is stable and can 01049 * be used as system clock source. 01050 * @note The main PLL can not be disabled if it is used as system clock source 01051 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 01052 */ 01053 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) 01054 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) 01055 01056 /** @brief Macro to configure the PLL clock source. 01057 * @note This function must be used only when the main PLL is disabled. 01058 * @param __PLLSOURCE__ specifies the PLL entry clock source. 01059 * This parameter can be one of the following values: 01060 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 01061 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 01062 * 01063 */ 01064 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 01065 01066 /** @brief Macro to configure the PLL multiplication factor. 01067 * @note This function must be used only when the main PLL is disabled. 01068 * @param __PLLM__ specifies the division factor for PLL VCO input clock 01069 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 01070 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 01071 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 01072 * of 2 MHz to limit PLL jitter. 01073 * 01074 */ 01075 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) 01076 /** 01077 * @} 01078 */ 01079 01080 /** @defgroup RCC_Get_Clock_source Get Clock source 01081 * @{ 01082 */ 01083 /** 01084 * @brief Macro to configure the system clock source. 01085 * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. 01086 * This parameter can be one of the following values: 01087 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 01088 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 01089 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. 01090 * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This 01091 * parameter is available only for STM32F446xx devices. 01092 */ 01093 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) 01094 01095 /** @brief Macro to get the clock source used as system clock. 01096 * @retval The clock source used as system clock. The returned value can be one 01097 * of the following: 01098 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 01099 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 01100 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. 01101 * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter 01102 * is available only for STM32F446xx devices. 01103 */ 01104 #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) 01105 01106 /** @brief Macro to get the oscillator used as PLL clock source. 01107 * @retval The oscillator used as PLL clock source. The returned value can be one 01108 * of the following: 01109 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 01110 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 01111 */ 01112 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) 01113 /** 01114 * @} 01115 */ 01116 01117 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 01118 * @{ 01119 */ 01120 01121 /** @brief Macro to configure the MCO1 clock. 01122 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 01123 * This parameter can be one of the following values: 01124 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source 01125 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source 01126 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source 01127 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source 01128 * @param __MCODIV__ specifies the MCO clock prescaler. 01129 * This parameter can be one of the following values: 01130 * @arg RCC_MCODIV_1: no division applied to MCOx clock 01131 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock 01132 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock 01133 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock 01134 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock 01135 */ 01136 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 01137 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 01138 01139 /** @brief Macro to configure the MCO2 clock. 01140 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 01141 * This parameter can be one of the following values: 01142 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source 01143 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx 01144 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices 01145 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source 01146 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source 01147 * @param __MCODIV__ specifies the MCO clock prescaler. 01148 * This parameter can be one of the following values: 01149 * @arg RCC_MCODIV_1: no division applied to MCOx clock 01150 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock 01151 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock 01152 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock 01153 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock 01154 * @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have 01155 * at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5). 01156 */ 01157 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 01158 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U))); 01159 /** 01160 * @} 01161 */ 01162 01163 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 01164 * @brief macros to manage the specified RCC Flags and interrupts. 01165 * @{ 01166 */ 01167 01168 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable 01169 * the selected interrupts). 01170 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 01171 * This parameter can be any combination of the following values: 01172 * @arg RCC_IT_LSIRDY: LSI ready interrupt. 01173 * @arg RCC_IT_LSERDY: LSE ready interrupt. 01174 * @arg RCC_IT_HSIRDY: HSI ready interrupt. 01175 * @arg RCC_IT_HSERDY: HSE ready interrupt. 01176 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. 01177 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. 01178 */ 01179 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) 01180 01181 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 01182 * the selected interrupts). 01183 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 01184 * This parameter can be any combination of the following values: 01185 * @arg RCC_IT_LSIRDY: LSI ready interrupt. 01186 * @arg RCC_IT_LSERDY: LSE ready interrupt. 01187 * @arg RCC_IT_HSIRDY: HSI ready interrupt. 01188 * @arg RCC_IT_HSERDY: HSE ready interrupt. 01189 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. 01190 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. 01191 */ 01192 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) 01193 01194 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] 01195 * bits to clear the selected interrupt pending bits. 01196 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 01197 * This parameter can be any combination of the following values: 01198 * @arg RCC_IT_LSIRDY: LSI ready interrupt. 01199 * @arg RCC_IT_LSERDY: LSE ready interrupt. 01200 * @arg RCC_IT_HSIRDY: HSI ready interrupt. 01201 * @arg RCC_IT_HSERDY: HSE ready interrupt. 01202 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. 01203 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. 01204 * @arg RCC_IT_CSS: Clock Security System interrupt 01205 */ 01206 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) 01207 01208 /** @brief Check the RCC's interrupt has occurred or not. 01209 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 01210 * This parameter can be one of the following values: 01211 * @arg RCC_IT_LSIRDY: LSI ready interrupt. 01212 * @arg RCC_IT_LSERDY: LSE ready interrupt. 01213 * @arg RCC_IT_HSIRDY: HSI ready interrupt. 01214 * @arg RCC_IT_HSERDY: HSE ready interrupt. 01215 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. 01216 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. 01217 * @arg RCC_IT_CSS: Clock Security System interrupt 01218 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 01219 */ 01220 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) 01221 01222 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, 01223 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 01224 */ 01225 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 01226 01227 /** @brief Check RCC flag is set or not. 01228 * @param __FLAG__ specifies the flag to check. 01229 * This parameter can be one of the following values: 01230 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. 01231 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. 01232 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. 01233 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. 01234 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. 01235 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. 01236 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. 01237 * @arg RCC_FLAG_PINRST: Pin reset. 01238 * @arg RCC_FLAG_PORRST: POR/PDR reset. 01239 * @arg RCC_FLAG_SFTRST: Software reset. 01240 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. 01241 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. 01242 * @arg RCC_FLAG_LPWRRST: Low Power reset. 01243 * @retval The new state of __FLAG__ (TRUE or FALSE). 01244 */ 01245 #define RCC_FLAG_MASK ((uint8_t)0x1FU) 01246 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) 01247 01248 /** 01249 * @} 01250 */ 01251 01252 /** 01253 * @} 01254 */ 01255 01256 /* Exported functions --------------------------------------------------------*/ 01257 /** @addtogroup RCC_Exported_Functions 01258 * @{ 01259 */ 01260 01261 /** @addtogroup RCC_Exported_Functions_Group1 01262 * @{ 01263 */ 01264 /* Initialization and de-initialization functions ******************************/ 01265 HAL_StatusTypeDef HAL_RCC_DeInit(void); 01266 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 01267 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 01268 /** 01269 * @} 01270 */ 01271 01272 /** @addtogroup RCC_Exported_Functions_Group2 01273 * @{ 01274 */ 01275 /* Peripheral Control functions ************************************************/ 01276 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 01277 void HAL_RCC_EnableCSS(void); 01278 void HAL_RCC_DisableCSS(void); 01279 uint32_t HAL_RCC_GetSysClockFreq(void); 01280 uint32_t HAL_RCC_GetHCLKFreq(void); 01281 uint32_t HAL_RCC_GetPCLK1Freq(void); 01282 uint32_t HAL_RCC_GetPCLK2Freq(void); 01283 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 01284 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 01285 01286 /* CSS NMI IRQ handler */ 01287 void HAL_RCC_NMI_IRQHandler(void); 01288 01289 /* User Callbacks in non blocking mode (IT mode) */ 01290 void HAL_RCC_CSSCallback(void); 01291 01292 /** 01293 * @} 01294 */ 01295 01296 /** 01297 * @} 01298 */ 01299 01300 /* Private types -------------------------------------------------------------*/ 01301 /* Private variables ---------------------------------------------------------*/ 01302 /* Private constants ---------------------------------------------------------*/ 01303 /** @defgroup RCC_Private_Constants RCC Private Constants 01304 * @{ 01305 */ 01306 01307 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion 01308 * @brief RCC registers bit address in the alias region 01309 * @{ 01310 */ 01311 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) 01312 /* --- CR Register --- */ 01313 /* Alias word address of HSION bit */ 01314 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U) 01315 #define RCC_HSION_BIT_NUMBER 0x00U 01316 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U)) 01317 /* Alias word address of CSSON bit */ 01318 #define RCC_CSSON_BIT_NUMBER 0x13U 01319 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)) 01320 /* Alias word address of PLLON bit */ 01321 #define RCC_PLLON_BIT_NUMBER 0x18U 01322 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)) 01323 01324 /* --- BDCR Register --- */ 01325 /* Alias word address of RTCEN bit */ 01326 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U) 01327 #define RCC_RTCEN_BIT_NUMBER 0x0FU 01328 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)) 01329 /* Alias word address of BDRST bit */ 01330 #define RCC_BDRST_BIT_NUMBER 0x10U 01331 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)) 01332 01333 /* --- CSR Register --- */ 01334 /* Alias word address of LSION bit */ 01335 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U) 01336 #define RCC_LSION_BIT_NUMBER 0x00U 01337 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U)) 01338 01339 /* CR register byte 3 (Bits[23:16]) base address */ 01340 #define RCC_CR_BYTE2_ADDRESS 0x40023802U 01341 01342 /* CIR register byte 2 (Bits[15:8]) base address */ 01343 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U)) 01344 01345 /* CIR register byte 3 (Bits[23:16]) base address */ 01346 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U)) 01347 01348 /* BDCR register base address */ 01349 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET) 01350 01351 #define RCC_DBP_TIMEOUT_VALUE 2U 01352 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 01353 01354 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 01355 #define HSI_TIMEOUT_VALUE 2U /* 2 ms */ 01356 #define LSI_TIMEOUT_VALUE 2U /* 2 ms */ 01357 #define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ 01358 01359 /** 01360 * @} 01361 */ 01362 01363 /** 01364 * @} 01365 */ 01366 01367 /* Private macros ------------------------------------------------------------*/ 01368 /** @defgroup RCC_Private_Macros RCC Private Macros 01369 * @{ 01370 */ 01371 01372 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters 01373 * @{ 01374 */ 01375 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U) 01376 01377 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 01378 ((HSE) == RCC_HSE_BYPASS)) 01379 01380 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 01381 ((LSE) == RCC_LSE_BYPASS)) 01382 01383 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) 01384 01385 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) 01386 01387 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) 01388 01389 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ 01390 ((SOURCE) == RCC_PLLSOURCE_HSE)) 01391 01392 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ 01393 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ 01394 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ 01395 ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK)) 01396 01397 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 01398 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 01399 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \ 01400 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ 01401 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ 01402 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ 01403 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \ 01404 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ 01405 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \ 01406 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ 01407 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \ 01408 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ 01409 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \ 01410 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ 01411 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \ 01412 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ 01413 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \ 01414 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ 01415 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \ 01416 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ 01417 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \ 01418 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ 01419 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \ 01420 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ 01421 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \ 01422 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ 01423 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \ 01424 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ 01425 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \ 01426 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ 01427 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \ 01428 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31)) 01429 01430 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U) 01431 01432 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U)) 01433 01434 #define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 01435 01436 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ 01437 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ 01438 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ 01439 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ 01440 ((HCLK) == RCC_SYSCLK_DIV512)) 01441 01442 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U)) 01443 01444 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ 01445 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ 01446 ((PCLK) == RCC_HCLK_DIV16)) 01447 01448 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) 01449 01450 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ 01451 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) 01452 01453 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ 01454 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ 01455 ((DIV) == RCC_MCODIV_5)) 01456 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU) 01457 01458 /** 01459 * @} 01460 */ 01461 01462 /** 01463 * @} 01464 */ 01465 01466 /** 01467 * @} 01468 */ 01469 01470 /** 01471 * @} 01472 */ 01473 01474 #ifdef __cplusplus 01475 } 01476 #endif 01477 01478 #endif /* __STM32F4xx_HAL_RCC_H */ 01479 01480 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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