STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_tim.c 00004 * @author MCD Application Team 00005 * @brief TIM HAL module driver. 00006 * This file provides firmware functions to manage the following 00007 * functionalities of the Timer (TIM) peripheral: 00008 * + Time Base Initialization 00009 * + Time Base Start 00010 * + Time Base Start Interruption 00011 * + Time Base Start DMA 00012 * + Time Output Compare/PWM Initialization 00013 * + Time Output Compare/PWM Channel Configuration 00014 * + Time Output Compare/PWM Start 00015 * + Time Output Compare/PWM Start Interruption 00016 * + Time Output Compare/PWM Start DMA 00017 * + Time Input Capture Initialization 00018 * + Time Input Capture Channel Configuration 00019 * + Time Input Capture Start 00020 * + Time Input Capture Start Interruption 00021 * + Time Input Capture Start DMA 00022 * + Time One Pulse Initialization 00023 * + Time One Pulse Channel Configuration 00024 * + Time One Pulse Start 00025 * + Time Encoder Interface Initialization 00026 * + Time Encoder Interface Start 00027 * + Time Encoder Interface Start Interruption 00028 * + Time Encoder Interface Start DMA 00029 * + Commutation Event configuration with Interruption and DMA 00030 * + Time OCRef clear configuration 00031 * + Time External Clock configuration 00032 @verbatim 00033 ============================================================================== 00034 ##### TIMER Generic features ##### 00035 ============================================================================== 00036 [..] The Timer features include: 00037 (#) 16-bit up, down, up/down auto-reload counter. 00038 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the 00039 counter clock frequency either by any factor between 1 and 65536. 00040 (#) Up to 4 independent channels for: 00041 (++) Input Capture 00042 (++) Output Compare 00043 (++) PWM generation (Edge and Center-aligned Mode) 00044 (++) One-pulse mode output 00045 (#) Synchronization circuit to control the timer with external signals and to interconnect 00046 several timers together. 00047 (#) Supports incremental encoder for positioning purposes 00048 00049 ##### How to use this driver ##### 00050 ============================================================================== 00051 [..] 00052 (#) Initialize the TIM low level resources by implementing the following functions 00053 depending on the selected feature: 00054 (++) Time Base : HAL_TIM_Base_MspInit() 00055 (++) Input Capture : HAL_TIM_IC_MspInit() 00056 (++) Output Compare : HAL_TIM_OC_MspInit() 00057 (++) PWM generation : HAL_TIM_PWM_MspInit() 00058 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() 00059 (++) Encoder mode output : HAL_TIM_Encoder_MspInit() 00060 00061 (#) Initialize the TIM low level resources : 00062 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); 00063 (##) TIM pins configuration 00064 (+++) Enable the clock for the TIM GPIOs using the following function: 00065 __HAL_RCC_GPIOx_CLK_ENABLE(); 00066 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); 00067 00068 (#) The external Clock can be configured, if needed (the default clock is the 00069 internal clock from the APBx), using the following function: 00070 HAL_TIM_ConfigClockSource, the clock configuration should be done before 00071 any start function. 00072 00073 (#) Configure the TIM in the desired functioning mode using one of the 00074 Initialization function of this driver: 00075 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base 00076 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an 00077 Output Compare signal. 00078 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a 00079 PWM signal. 00080 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an 00081 external signal. 00082 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer 00083 in One Pulse Mode. 00084 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. 00085 00086 (#) Activate the TIM peripheral using one of the start functions depending from the feature used: 00087 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() 00088 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() 00089 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() 00090 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() 00091 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() 00092 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). 00093 00094 (#) The DMA Burst is managed with the two following functions: 00095 HAL_TIM_DMABurst_WriteStart() 00096 HAL_TIM_DMABurst_ReadStart() 00097 00098 *** Callback registration *** 00099 ============================================= 00100 00101 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 00102 allows the user to configure dynamically the driver callbacks. 00103 00104 Use Function @ref HAL_TIM_RegisterCallback() to register a callback. 00105 @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, 00106 the Callback ID and a pointer to the user callback function. 00107 00108 Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default 00109 weak function. 00110 @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, 00111 and the Callback ID. 00112 00113 These functions allow to register/unregister following callbacks: 00114 (+) Base_MspInitCallback : TIM Base Msp Init Callback. 00115 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. 00116 (+) IC_MspInitCallback : TIM IC Msp Init Callback. 00117 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. 00118 (+) OC_MspInitCallback : TIM OC Msp Init Callback. 00119 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. 00120 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. 00121 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. 00122 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. 00123 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. 00124 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. 00125 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. 00126 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. 00127 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. 00128 (+) PeriodElapsedCallback : TIM Period Elapsed Callback. 00129 (+) TriggerCallback : TIM Trigger Callback. 00130 (+) IC_CaptureCallback : TIM Input Capture Callback. 00131 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. 00132 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. 00133 (+) ErrorCallback : TIM Error Callback. 00134 (+) CommutationCallback : TIM Commutation Callback. 00135 (+) BreakCallback : TIM Break Callback. 00136 00137 By default, after the Init and when the state is HAL_TIM_STATE_RESET 00138 all interrupt callbacks are set to the corresponding weak functions: 00139 examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). 00140 00141 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak 00142 functionalities in the Init / DeInit only when these callbacks are null 00143 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit 00144 keep and use the user MspInit / MspDeInit callbacks(registered beforehand) 00145 00146 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. 00147 Exception done MspInit / MspDeInit that can be registered / unregistered 00148 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, 00149 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. 00150 In that case first register the MspInit/MspDeInit user callbacks 00151 using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. 00152 00153 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or 00154 not defined, the callback registration feature is not available and all callbacks 00155 are set to the corresponding weak functions. 00156 00157 @endverbatim 00158 ****************************************************************************** 00159 * @attention 00160 * 00161 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00162 * 00163 * Redistribution and use in source and binary forms, with or without modification, 00164 * are permitted provided that the following conditions are met: 00165 * 1. Redistributions of source code must retain the above copyright notice, 00166 * this list of conditions and the following disclaimer. 00167 * 2. Redistributions in binary form must reproduce the above copyright notice, 00168 * this list of conditions and the following disclaimer in the documentation 00169 * and/or other materials provided with the distribution. 00170 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00171 * may be used to endorse or promote products derived from this software 00172 * without specific prior written permission. 00173 * 00174 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00175 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00176 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00177 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00178 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00179 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00180 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00181 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00182 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00183 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00184 * 00185 ****************************************************************************** 00186 */ 00187 00188 /* Includes ------------------------------------------------------------------*/ 00189 #include "stm32l4xx_hal.h" 00190 00191 /** @addtogroup STM32L4xx_HAL_Driver 00192 * @{ 00193 */ 00194 00195 /** @defgroup TIM TIM 00196 * @brief TIM HAL module driver 00197 * @{ 00198 */ 00199 00200 #ifdef HAL_TIM_MODULE_ENABLED 00201 00202 /* Private typedef -----------------------------------------------------------*/ 00203 /* Private define ------------------------------------------------------------*/ 00204 /* Private macro -------------------------------------------------------------*/ 00205 /* Private variables ---------------------------------------------------------*/ 00206 /* Private function prototypes -----------------------------------------------*/ 00207 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 00208 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 00209 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 00210 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 00211 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 00212 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); 00213 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 00214 uint32_t TIM_ICFilter); 00215 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); 00216 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 00217 uint32_t TIM_ICFilter); 00218 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 00219 uint32_t TIM_ICFilter); 00220 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); 00221 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); 00222 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); 00223 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, 00224 TIM_SlaveConfigTypeDef *sSlaveConfig); 00225 /* Exported functions --------------------------------------------------------*/ 00226 00227 /** @defgroup TIM_Exported_Functions TIM Exported Functions 00228 * @{ 00229 */ 00230 00231 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions 00232 * @brief Time Base functions 00233 * 00234 @verbatim 00235 ============================================================================== 00236 ##### Time Base functions ##### 00237 ============================================================================== 00238 [..] 00239 This section provides functions allowing to: 00240 (+) Initialize and configure the TIM base. 00241 (+) De-initialize the TIM base. 00242 (+) Start the Time Base. 00243 (+) Stop the Time Base. 00244 (+) Start the Time Base and enable interrupt. 00245 (+) Stop the Time Base and disable interrupt. 00246 (+) Start the Time Base and enable DMA transfer. 00247 (+) Stop the Time Base and disable DMA transfer. 00248 00249 @endverbatim 00250 * @{ 00251 */ 00252 /** 00253 * @brief Initializes the TIM Time base Unit according to the specified 00254 * parameters in the TIM_HandleTypeDef and initialize the associated handle. 00255 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) 00256 * requires a timer reset to avoid unexpected direction 00257 * due to DIR bit readonly in center aligned mode. 00258 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() 00259 * @param htim TIM Base handle 00260 * @retval HAL status 00261 */ 00262 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) 00263 { 00264 /* Check the TIM handle allocation */ 00265 if (htim == NULL) 00266 { 00267 return HAL_ERROR; 00268 } 00269 00270 /* Check the parameters */ 00271 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00272 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); 00273 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 00274 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); 00275 00276 if (htim->State == HAL_TIM_STATE_RESET) 00277 { 00278 /* Allocate lock resource and initialize it */ 00279 htim->Lock = HAL_UNLOCKED; 00280 00281 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 00282 /* Reset interrupt callbacks to legacy week callbacks */ 00283 TIM_ResetCallback(htim); 00284 00285 if (htim->Base_MspInitCallback == NULL) 00286 { 00287 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; 00288 } 00289 /* Init the low level hardware : GPIO, CLOCK, NVIC */ 00290 htim->Base_MspInitCallback(htim); 00291 #else 00292 /* Init the low level hardware : GPIO, CLOCK, NVIC */ 00293 HAL_TIM_Base_MspInit(htim); 00294 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 00295 } 00296 00297 /* Set the TIM state */ 00298 htim->State = HAL_TIM_STATE_BUSY; 00299 00300 /* Set the Time Base configuration */ 00301 TIM_Base_SetConfig(htim->Instance, &htim->Init); 00302 00303 /* Initialize the TIM state*/ 00304 htim->State = HAL_TIM_STATE_READY; 00305 00306 return HAL_OK; 00307 } 00308 00309 /** 00310 * @brief DeInitializes the TIM Base peripheral 00311 * @param htim TIM Base handle 00312 * @retval HAL status 00313 */ 00314 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) 00315 { 00316 /* Check the parameters */ 00317 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00318 00319 htim->State = HAL_TIM_STATE_BUSY; 00320 00321 /* Disable the TIM Peripheral Clock */ 00322 __HAL_TIM_DISABLE(htim); 00323 00324 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 00325 if (htim->Base_MspDeInitCallback == NULL) 00326 { 00327 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; 00328 } 00329 /* DeInit the low level hardware */ 00330 htim->Base_MspDeInitCallback(htim); 00331 #else 00332 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ 00333 HAL_TIM_Base_MspDeInit(htim); 00334 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 00335 00336 /* Change TIM state */ 00337 htim->State = HAL_TIM_STATE_RESET; 00338 00339 /* Release Lock */ 00340 __HAL_UNLOCK(htim); 00341 00342 return HAL_OK; 00343 } 00344 00345 /** 00346 * @brief Initializes the TIM Base MSP. 00347 * @param htim TIM Base handle 00348 * @retval None 00349 */ 00350 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) 00351 { 00352 /* Prevent unused argument(s) compilation warning */ 00353 UNUSED(htim); 00354 00355 /* NOTE : This function should not be modified, when the callback is needed, 00356 the HAL_TIM_Base_MspInit could be implemented in the user file 00357 */ 00358 } 00359 00360 /** 00361 * @brief DeInitializes TIM Base MSP. 00362 * @param htim TIM Base handle 00363 * @retval None 00364 */ 00365 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) 00366 { 00367 /* Prevent unused argument(s) compilation warning */ 00368 UNUSED(htim); 00369 00370 /* NOTE : This function should not be modified, when the callback is needed, 00371 the HAL_TIM_Base_MspDeInit could be implemented in the user file 00372 */ 00373 } 00374 00375 00376 /** 00377 * @brief Starts the TIM Base generation. 00378 * @param htim TIM Base handle 00379 * @retval HAL status 00380 */ 00381 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) 00382 { 00383 /* Check the parameters */ 00384 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00385 00386 /* Set the TIM state */ 00387 htim->State = HAL_TIM_STATE_BUSY; 00388 00389 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 00390 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 00391 { 00392 __HAL_TIM_ENABLE(htim); 00393 } 00394 00395 /* Change the TIM state*/ 00396 htim->State = HAL_TIM_STATE_READY; 00397 00398 /* Return function status */ 00399 return HAL_OK; 00400 } 00401 00402 /** 00403 * @brief Stops the TIM Base generation. 00404 * @param htim TIM Base handle 00405 * @retval HAL status 00406 */ 00407 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) 00408 { 00409 /* Check the parameters */ 00410 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00411 00412 /* Set the TIM state */ 00413 htim->State = HAL_TIM_STATE_BUSY; 00414 00415 /* Disable the Peripheral */ 00416 __HAL_TIM_DISABLE(htim); 00417 00418 /* Change the TIM state*/ 00419 htim->State = HAL_TIM_STATE_READY; 00420 00421 /* Return function status */ 00422 return HAL_OK; 00423 } 00424 00425 /** 00426 * @brief Starts the TIM Base generation in interrupt mode. 00427 * @param htim TIM Base handle 00428 * @retval HAL status 00429 */ 00430 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) 00431 { 00432 /* Check the parameters */ 00433 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00434 00435 /* Enable the TIM Update interrupt */ 00436 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 00437 00438 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 00439 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 00440 { 00441 __HAL_TIM_ENABLE(htim); 00442 } 00443 00444 /* Return function status */ 00445 return HAL_OK; 00446 } 00447 00448 /** 00449 * @brief Stops the TIM Base generation in interrupt mode. 00450 * @param htim TIM Base handle 00451 * @retval HAL status 00452 */ 00453 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) 00454 { 00455 /* Check the parameters */ 00456 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00457 /* Disable the TIM Update interrupt */ 00458 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); 00459 00460 /* Disable the Peripheral */ 00461 __HAL_TIM_DISABLE(htim); 00462 00463 /* Return function status */ 00464 return HAL_OK; 00465 } 00466 00467 /** 00468 * @brief Starts the TIM Base generation in DMA mode. 00469 * @param htim TIM Base handle 00470 * @param pData The source Buffer address. 00471 * @param Length The length of data to be transferred from memory to peripheral. 00472 * @retval HAL status 00473 */ 00474 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) 00475 { 00476 /* Check the parameters */ 00477 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); 00478 00479 if ((htim->State == HAL_TIM_STATE_BUSY)) 00480 { 00481 return HAL_BUSY; 00482 } 00483 else if ((htim->State == HAL_TIM_STATE_READY)) 00484 { 00485 if ((pData == NULL) && (Length > 0U)) 00486 { 00487 return HAL_ERROR; 00488 } 00489 else 00490 { 00491 htim->State = HAL_TIM_STATE_BUSY; 00492 } 00493 } 00494 else 00495 { 00496 /* nothing to do */ 00497 } 00498 00499 /* Set the DMA Period elapsed callback */ 00500 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; 00501 00502 /* Set the DMA error callback */ 00503 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; 00504 00505 /* Enable the DMA channel */ 00506 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) 00507 { 00508 return HAL_ERROR; 00509 } 00510 00511 /* Enable the TIM Update DMA request */ 00512 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); 00513 00514 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 00515 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 00516 { 00517 __HAL_TIM_ENABLE(htim); 00518 } 00519 00520 /* Return function status */ 00521 return HAL_OK; 00522 } 00523 00524 /** 00525 * @brief Stops the TIM Base generation in DMA mode. 00526 * @param htim TIM Base handle 00527 * @retval HAL status 00528 */ 00529 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) 00530 { 00531 /* Check the parameters */ 00532 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); 00533 00534 /* Disable the TIM Update DMA request */ 00535 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); 00536 00537 /* Disable the Peripheral */ 00538 __HAL_TIM_DISABLE(htim); 00539 00540 /* Change the htim state */ 00541 htim->State = HAL_TIM_STATE_READY; 00542 00543 /* Return function status */ 00544 return HAL_OK; 00545 } 00546 00547 /** 00548 * @} 00549 */ 00550 00551 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions 00552 * @brief Time Output Compare functions 00553 * 00554 @verbatim 00555 ============================================================================== 00556 ##### Time Output Compare functions ##### 00557 ============================================================================== 00558 [..] 00559 This section provides functions allowing to: 00560 (+) Initialize and configure the TIM Output Compare. 00561 (+) De-initialize the TIM Output Compare. 00562 (+) Start the Time Output Compare. 00563 (+) Stop the Time Output Compare. 00564 (+) Start the Time Output Compare and enable interrupt. 00565 (+) Stop the Time Output Compare and disable interrupt. 00566 (+) Start the Time Output Compare and enable DMA transfer. 00567 (+) Stop the Time Output Compare and disable DMA transfer. 00568 00569 @endverbatim 00570 * @{ 00571 */ 00572 /** 00573 * @brief Initializes the TIM Output Compare according to the specified 00574 * parameters in the TIM_HandleTypeDef and initializes the associated handle. 00575 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) 00576 * requires a timer reset to avoid unexpected direction 00577 * due to DIR bit readonly in center aligned mode. 00578 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() 00579 * @param htim TIM Output Compare handle 00580 * @retval HAL status 00581 */ 00582 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) 00583 { 00584 /* Check the TIM handle allocation */ 00585 if (htim == NULL) 00586 { 00587 return HAL_ERROR; 00588 } 00589 00590 /* Check the parameters */ 00591 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00592 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); 00593 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 00594 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); 00595 00596 if (htim->State == HAL_TIM_STATE_RESET) 00597 { 00598 /* Allocate lock resource and initialize it */ 00599 htim->Lock = HAL_UNLOCKED; 00600 00601 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 00602 /* Reset interrupt callbacks to legacy week callbacks */ 00603 TIM_ResetCallback(htim); 00604 00605 if (htim->OC_MspInitCallback == NULL) 00606 { 00607 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; 00608 } 00609 /* Init the low level hardware : GPIO, CLOCK, NVIC */ 00610 htim->OC_MspInitCallback(htim); 00611 #else 00612 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ 00613 HAL_TIM_OC_MspInit(htim); 00614 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 00615 } 00616 00617 /* Set the TIM state */ 00618 htim->State = HAL_TIM_STATE_BUSY; 00619 00620 /* Init the base time for the Output Compare */ 00621 TIM_Base_SetConfig(htim->Instance, &htim->Init); 00622 00623 /* Initialize the TIM state*/ 00624 htim->State = HAL_TIM_STATE_READY; 00625 00626 return HAL_OK; 00627 } 00628 00629 /** 00630 * @brief DeInitializes the TIM peripheral 00631 * @param htim TIM Output Compare handle 00632 * @retval HAL status 00633 */ 00634 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) 00635 { 00636 /* Check the parameters */ 00637 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00638 00639 htim->State = HAL_TIM_STATE_BUSY; 00640 00641 /* Disable the TIM Peripheral Clock */ 00642 __HAL_TIM_DISABLE(htim); 00643 00644 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 00645 if (htim->OC_MspDeInitCallback == NULL) 00646 { 00647 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; 00648 } 00649 /* DeInit the low level hardware */ 00650 htim->OC_MspDeInitCallback(htim); 00651 #else 00652 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ 00653 HAL_TIM_OC_MspDeInit(htim); 00654 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 00655 00656 /* Change TIM state */ 00657 htim->State = HAL_TIM_STATE_RESET; 00658 00659 /* Release Lock */ 00660 __HAL_UNLOCK(htim); 00661 00662 return HAL_OK; 00663 } 00664 00665 /** 00666 * @brief Initializes the TIM Output Compare MSP. 00667 * @param htim TIM Output Compare handle 00668 * @retval None 00669 */ 00670 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) 00671 { 00672 /* Prevent unused argument(s) compilation warning */ 00673 UNUSED(htim); 00674 00675 /* NOTE : This function should not be modified, when the callback is needed, 00676 the HAL_TIM_OC_MspInit could be implemented in the user file 00677 */ 00678 } 00679 00680 /** 00681 * @brief DeInitializes TIM Output Compare MSP. 00682 * @param htim TIM Output Compare handle 00683 * @retval None 00684 */ 00685 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) 00686 { 00687 /* Prevent unused argument(s) compilation warning */ 00688 UNUSED(htim); 00689 00690 /* NOTE : This function should not be modified, when the callback is needed, 00691 the HAL_TIM_OC_MspDeInit could be implemented in the user file 00692 */ 00693 } 00694 00695 /** 00696 * @brief Starts the TIM Output Compare signal generation. 00697 * @param htim TIM Output Compare handle 00698 * @param Channel TIM Channel to be enabled 00699 * This parameter can be one of the following values: 00700 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00701 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00702 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00703 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 00704 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 00705 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 00706 * @retval HAL status 00707 */ 00708 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) 00709 { 00710 /* Check the parameters */ 00711 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 00712 00713 /* Enable the Output compare channel */ 00714 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 00715 00716 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 00717 { 00718 /* Enable the main output */ 00719 __HAL_TIM_MOE_ENABLE(htim); 00720 } 00721 00722 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 00723 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 00724 { 00725 __HAL_TIM_ENABLE(htim); 00726 } 00727 00728 /* Return function status */ 00729 return HAL_OK; 00730 } 00731 00732 /** 00733 * @brief Stops the TIM Output Compare signal generation. 00734 * @param htim TIM Output Compare handle 00735 * @param Channel TIM Channel to be disabled 00736 * This parameter can be one of the following values: 00737 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00738 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00739 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00740 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 00741 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 00742 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 00743 * @retval HAL status 00744 */ 00745 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) 00746 { 00747 /* Check the parameters */ 00748 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 00749 00750 /* Disable the Output compare channel */ 00751 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 00752 00753 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 00754 { 00755 /* Disable the Main Output */ 00756 __HAL_TIM_MOE_DISABLE(htim); 00757 } 00758 00759 /* Disable the Peripheral */ 00760 __HAL_TIM_DISABLE(htim); 00761 00762 /* Return function status */ 00763 return HAL_OK; 00764 } 00765 00766 /** 00767 * @brief Starts the TIM Output Compare signal generation in interrupt mode. 00768 * @param htim TIM Output Compare handle 00769 * @param Channel TIM Channel to be enabled 00770 * This parameter can be one of the following values: 00771 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00772 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00773 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00774 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 00775 * @retval HAL status 00776 */ 00777 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 00778 { 00779 /* Check the parameters */ 00780 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 00781 00782 switch (Channel) 00783 { 00784 case TIM_CHANNEL_1: 00785 { 00786 /* Enable the TIM Capture/Compare 1 interrupt */ 00787 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 00788 break; 00789 } 00790 00791 case TIM_CHANNEL_2: 00792 { 00793 /* Enable the TIM Capture/Compare 2 interrupt */ 00794 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 00795 break; 00796 } 00797 00798 case TIM_CHANNEL_3: 00799 { 00800 /* Enable the TIM Capture/Compare 3 interrupt */ 00801 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 00802 break; 00803 } 00804 00805 case TIM_CHANNEL_4: 00806 { 00807 /* Enable the TIM Capture/Compare 4 interrupt */ 00808 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 00809 break; 00810 } 00811 00812 default: 00813 break; 00814 } 00815 00816 /* Enable the Output compare channel */ 00817 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 00818 00819 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 00820 { 00821 /* Enable the main output */ 00822 __HAL_TIM_MOE_ENABLE(htim); 00823 } 00824 00825 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 00826 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 00827 { 00828 __HAL_TIM_ENABLE(htim); 00829 } 00830 00831 /* Return function status */ 00832 return HAL_OK; 00833 } 00834 00835 /** 00836 * @brief Stops the TIM Output Compare signal generation in interrupt mode. 00837 * @param htim TIM Output Compare handle 00838 * @param Channel TIM Channel to be disabled 00839 * This parameter can be one of the following values: 00840 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00841 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00842 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00843 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 00844 * @retval HAL status 00845 */ 00846 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 00847 { 00848 /* Check the parameters */ 00849 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 00850 00851 switch (Channel) 00852 { 00853 case TIM_CHANNEL_1: 00854 { 00855 /* Disable the TIM Capture/Compare 1 interrupt */ 00856 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 00857 break; 00858 } 00859 00860 case TIM_CHANNEL_2: 00861 { 00862 /* Disable the TIM Capture/Compare 2 interrupt */ 00863 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 00864 break; 00865 } 00866 00867 case TIM_CHANNEL_3: 00868 { 00869 /* Disable the TIM Capture/Compare 3 interrupt */ 00870 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); 00871 break; 00872 } 00873 00874 case TIM_CHANNEL_4: 00875 { 00876 /* Disable the TIM Capture/Compare 4 interrupt */ 00877 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); 00878 break; 00879 } 00880 00881 default: 00882 break; 00883 } 00884 00885 /* Disable the Output compare channel */ 00886 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 00887 00888 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 00889 { 00890 /* Disable the Main Output */ 00891 __HAL_TIM_MOE_DISABLE(htim); 00892 } 00893 00894 /* Disable the Peripheral */ 00895 __HAL_TIM_DISABLE(htim); 00896 00897 /* Return function status */ 00898 return HAL_OK; 00899 } 00900 00901 /** 00902 * @brief Starts the TIM Output Compare signal generation in DMA mode. 00903 * @param htim TIM Output Compare handle 00904 * @param Channel TIM Channel to be enabled 00905 * This parameter can be one of the following values: 00906 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00907 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00908 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00909 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 00910 * @param pData The source Buffer address. 00911 * @param Length The length of data to be transferred from memory to TIM peripheral 00912 * @retval HAL status 00913 */ 00914 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) 00915 { 00916 /* Check the parameters */ 00917 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 00918 00919 if ((htim->State == HAL_TIM_STATE_BUSY)) 00920 { 00921 return HAL_BUSY; 00922 } 00923 else if ((htim->State == HAL_TIM_STATE_READY)) 00924 { 00925 if ((pData == NULL) && (Length > 0U)) 00926 { 00927 return HAL_ERROR; 00928 } 00929 else 00930 { 00931 htim->State = HAL_TIM_STATE_BUSY; 00932 } 00933 } 00934 else 00935 { 00936 /* nothing to do */ 00937 } 00938 00939 switch (Channel) 00940 { 00941 case TIM_CHANNEL_1: 00942 { 00943 /* Set the DMA Period elapsed callback */ 00944 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; 00945 00946 /* Set the DMA error callback */ 00947 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 00948 00949 /* Enable the DMA channel */ 00950 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) 00951 { 00952 return HAL_ERROR; 00953 } 00954 00955 /* Enable the TIM Capture/Compare 1 DMA request */ 00956 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 00957 break; 00958 } 00959 00960 case TIM_CHANNEL_2: 00961 { 00962 /* Set the DMA Period elapsed callback */ 00963 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; 00964 00965 /* Set the DMA error callback */ 00966 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 00967 00968 /* Enable the DMA channel */ 00969 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) 00970 { 00971 return HAL_ERROR; 00972 } 00973 00974 /* Enable the TIM Capture/Compare 2 DMA request */ 00975 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 00976 break; 00977 } 00978 00979 case TIM_CHANNEL_3: 00980 { 00981 /* Set the DMA Period elapsed callback */ 00982 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; 00983 00984 /* Set the DMA error callback */ 00985 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 00986 00987 /* Enable the DMA channel */ 00988 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) 00989 { 00990 return HAL_ERROR; 00991 } 00992 /* Enable the TIM Capture/Compare 3 DMA request */ 00993 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); 00994 break; 00995 } 00996 00997 case TIM_CHANNEL_4: 00998 { 00999 /* Set the DMA Period elapsed callback */ 01000 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; 01001 01002 /* Set the DMA error callback */ 01003 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; 01004 01005 /* Enable the DMA channel */ 01006 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) 01007 { 01008 return HAL_ERROR; 01009 } 01010 /* Enable the TIM Capture/Compare 4 DMA request */ 01011 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); 01012 break; 01013 } 01014 01015 default: 01016 break; 01017 } 01018 01019 /* Enable the Output compare channel */ 01020 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01021 01022 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 01023 { 01024 /* Enable the main output */ 01025 __HAL_TIM_MOE_ENABLE(htim); 01026 } 01027 01028 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 01029 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 01030 { 01031 __HAL_TIM_ENABLE(htim); 01032 } 01033 01034 /* Return function status */ 01035 return HAL_OK; 01036 } 01037 01038 /** 01039 * @brief Stops the TIM Output Compare signal generation in DMA mode. 01040 * @param htim TIM Output Compare handle 01041 * @param Channel TIM Channel to be disabled 01042 * This parameter can be one of the following values: 01043 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01044 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01045 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01046 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01047 * @retval HAL status 01048 */ 01049 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) 01050 { 01051 /* Check the parameters */ 01052 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01053 01054 switch (Channel) 01055 { 01056 case TIM_CHANNEL_1: 01057 { 01058 /* Disable the TIM Capture/Compare 1 DMA request */ 01059 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 01060 break; 01061 } 01062 01063 case TIM_CHANNEL_2: 01064 { 01065 /* Disable the TIM Capture/Compare 2 DMA request */ 01066 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 01067 break; 01068 } 01069 01070 case TIM_CHANNEL_3: 01071 { 01072 /* Disable the TIM Capture/Compare 3 DMA request */ 01073 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); 01074 break; 01075 } 01076 01077 case TIM_CHANNEL_4: 01078 { 01079 /* Disable the TIM Capture/Compare 4 interrupt */ 01080 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); 01081 break; 01082 } 01083 01084 default: 01085 break; 01086 } 01087 01088 /* Disable the Output compare channel */ 01089 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01090 01091 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 01092 { 01093 /* Disable the Main Output */ 01094 __HAL_TIM_MOE_DISABLE(htim); 01095 } 01096 01097 /* Disable the Peripheral */ 01098 __HAL_TIM_DISABLE(htim); 01099 01100 /* Change the htim state */ 01101 htim->State = HAL_TIM_STATE_READY; 01102 01103 /* Return function status */ 01104 return HAL_OK; 01105 } 01106 01107 /** 01108 * @} 01109 */ 01110 01111 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions 01112 * @brief Time PWM functions 01113 * 01114 @verbatim 01115 ============================================================================== 01116 ##### Time PWM functions ##### 01117 ============================================================================== 01118 [..] 01119 This section provides functions allowing to: 01120 (+) Initialize and configure the TIM PWM. 01121 (+) De-initialize the TIM PWM. 01122 (+) Start the Time PWM. 01123 (+) Stop the Time PWM. 01124 (+) Start the Time PWM and enable interrupt. 01125 (+) Stop the Time PWM and disable interrupt. 01126 (+) Start the Time PWM and enable DMA transfer. 01127 (+) Stop the Time PWM and disable DMA transfer. 01128 01129 @endverbatim 01130 * @{ 01131 */ 01132 /** 01133 * @brief Initializes the TIM PWM Time Base according to the specified 01134 * parameters in the TIM_HandleTypeDef and initializes the associated handle. 01135 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) 01136 * requires a timer reset to avoid unexpected direction 01137 * due to DIR bit readonly in center aligned mode. 01138 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() 01139 * @param htim TIM PWM handle 01140 * @retval HAL status 01141 */ 01142 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) 01143 { 01144 /* Check the TIM handle allocation */ 01145 if (htim == NULL) 01146 { 01147 return HAL_ERROR; 01148 } 01149 01150 /* Check the parameters */ 01151 assert_param(IS_TIM_INSTANCE(htim->Instance)); 01152 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); 01153 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 01154 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); 01155 01156 if (htim->State == HAL_TIM_STATE_RESET) 01157 { 01158 /* Allocate lock resource and initialize it */ 01159 htim->Lock = HAL_UNLOCKED; 01160 01161 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 01162 /* Reset interrupt callbacks to legacy week callbacks */ 01163 TIM_ResetCallback(htim); 01164 01165 if (htim->PWM_MspInitCallback == NULL) 01166 { 01167 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; 01168 } 01169 /* Init the low level hardware : GPIO, CLOCK, NVIC */ 01170 htim->PWM_MspInitCallback(htim); 01171 #else 01172 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ 01173 HAL_TIM_PWM_MspInit(htim); 01174 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 01175 } 01176 01177 /* Set the TIM state */ 01178 htim->State = HAL_TIM_STATE_BUSY; 01179 01180 /* Init the base time for the PWM */ 01181 TIM_Base_SetConfig(htim->Instance, &htim->Init); 01182 01183 /* Initialize the TIM state*/ 01184 htim->State = HAL_TIM_STATE_READY; 01185 01186 return HAL_OK; 01187 } 01188 01189 /** 01190 * @brief DeInitializes the TIM peripheral 01191 * @param htim TIM PWM handle 01192 * @retval HAL status 01193 */ 01194 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) 01195 { 01196 /* Check the parameters */ 01197 assert_param(IS_TIM_INSTANCE(htim->Instance)); 01198 01199 htim->State = HAL_TIM_STATE_BUSY; 01200 01201 /* Disable the TIM Peripheral Clock */ 01202 __HAL_TIM_DISABLE(htim); 01203 01204 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 01205 if (htim->PWM_MspDeInitCallback == NULL) 01206 { 01207 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; 01208 } 01209 /* DeInit the low level hardware */ 01210 htim->PWM_MspDeInitCallback(htim); 01211 #else 01212 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ 01213 HAL_TIM_PWM_MspDeInit(htim); 01214 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 01215 01216 /* Change TIM state */ 01217 htim->State = HAL_TIM_STATE_RESET; 01218 01219 /* Release Lock */ 01220 __HAL_UNLOCK(htim); 01221 01222 return HAL_OK; 01223 } 01224 01225 /** 01226 * @brief Initializes the TIM PWM MSP. 01227 * @param htim TIM PWM handle 01228 * @retval None 01229 */ 01230 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) 01231 { 01232 /* Prevent unused argument(s) compilation warning */ 01233 UNUSED(htim); 01234 01235 /* NOTE : This function should not be modified, when the callback is needed, 01236 the HAL_TIM_PWM_MspInit could be implemented in the user file 01237 */ 01238 } 01239 01240 /** 01241 * @brief DeInitializes TIM PWM MSP. 01242 * @param htim TIM PWM handle 01243 * @retval None 01244 */ 01245 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) 01246 { 01247 /* Prevent unused argument(s) compilation warning */ 01248 UNUSED(htim); 01249 01250 /* NOTE : This function should not be modified, when the callback is needed, 01251 the HAL_TIM_PWM_MspDeInit could be implemented in the user file 01252 */ 01253 } 01254 01255 /** 01256 * @brief Starts the PWM signal generation. 01257 * @param htim TIM handle 01258 * @param Channel TIM Channels to be enabled 01259 * This parameter can be one of the following values: 01260 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01261 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01262 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01263 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01264 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 01265 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 01266 * @retval HAL status 01267 */ 01268 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) 01269 { 01270 /* Check the parameters */ 01271 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01272 01273 /* Enable the Capture compare channel */ 01274 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01275 01276 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 01277 { 01278 /* Enable the main output */ 01279 __HAL_TIM_MOE_ENABLE(htim); 01280 } 01281 01282 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 01283 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 01284 { 01285 __HAL_TIM_ENABLE(htim); 01286 } 01287 01288 /* Return function status */ 01289 return HAL_OK; 01290 } 01291 01292 /** 01293 * @brief Stops the PWM signal generation. 01294 * @param htim TIM PWM handle 01295 * @param Channel TIM Channels to be disabled 01296 * This parameter can be one of the following values: 01297 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01298 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01299 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01300 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01301 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 01302 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 01303 * @retval HAL status 01304 */ 01305 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) 01306 { 01307 /* Check the parameters */ 01308 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01309 01310 /* Disable the Capture compare channel */ 01311 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01312 01313 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 01314 { 01315 /* Disable the Main Output */ 01316 __HAL_TIM_MOE_DISABLE(htim); 01317 } 01318 01319 /* Disable the Peripheral */ 01320 __HAL_TIM_DISABLE(htim); 01321 01322 /* Change the htim state */ 01323 htim->State = HAL_TIM_STATE_READY; 01324 01325 /* Return function status */ 01326 return HAL_OK; 01327 } 01328 01329 /** 01330 * @brief Starts the PWM signal generation in interrupt mode. 01331 * @param htim TIM PWM handle 01332 * @param Channel TIM Channel to be enabled 01333 * This parameter can be one of the following values: 01334 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01335 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01336 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01337 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01338 * @retval HAL status 01339 */ 01340 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 01341 { 01342 /* Check the parameters */ 01343 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01344 01345 switch (Channel) 01346 { 01347 case TIM_CHANNEL_1: 01348 { 01349 /* Enable the TIM Capture/Compare 1 interrupt */ 01350 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 01351 break; 01352 } 01353 01354 case TIM_CHANNEL_2: 01355 { 01356 /* Enable the TIM Capture/Compare 2 interrupt */ 01357 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 01358 break; 01359 } 01360 01361 case TIM_CHANNEL_3: 01362 { 01363 /* Enable the TIM Capture/Compare 3 interrupt */ 01364 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 01365 break; 01366 } 01367 01368 case TIM_CHANNEL_4: 01369 { 01370 /* Enable the TIM Capture/Compare 4 interrupt */ 01371 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 01372 break; 01373 } 01374 01375 default: 01376 break; 01377 } 01378 01379 /* Enable the Capture compare channel */ 01380 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01381 01382 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 01383 { 01384 /* Enable the main output */ 01385 __HAL_TIM_MOE_ENABLE(htim); 01386 } 01387 01388 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 01389 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 01390 { 01391 __HAL_TIM_ENABLE(htim); 01392 } 01393 01394 /* Return function status */ 01395 return HAL_OK; 01396 } 01397 01398 /** 01399 * @brief Stops the PWM signal generation in interrupt mode. 01400 * @param htim TIM PWM handle 01401 * @param Channel TIM Channels to be disabled 01402 * This parameter can be one of the following values: 01403 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01404 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01405 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01406 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01407 * @retval HAL status 01408 */ 01409 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 01410 { 01411 /* Check the parameters */ 01412 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01413 01414 switch (Channel) 01415 { 01416 case TIM_CHANNEL_1: 01417 { 01418 /* Disable the TIM Capture/Compare 1 interrupt */ 01419 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 01420 break; 01421 } 01422 01423 case TIM_CHANNEL_2: 01424 { 01425 /* Disable the TIM Capture/Compare 2 interrupt */ 01426 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 01427 break; 01428 } 01429 01430 case TIM_CHANNEL_3: 01431 { 01432 /* Disable the TIM Capture/Compare 3 interrupt */ 01433 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); 01434 break; 01435 } 01436 01437 case TIM_CHANNEL_4: 01438 { 01439 /* Disable the TIM Capture/Compare 4 interrupt */ 01440 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); 01441 break; 01442 } 01443 01444 default: 01445 break; 01446 } 01447 01448 /* Disable the Capture compare channel */ 01449 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01450 01451 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 01452 { 01453 /* Disable the Main Output */ 01454 __HAL_TIM_MOE_DISABLE(htim); 01455 } 01456 01457 /* Disable the Peripheral */ 01458 __HAL_TIM_DISABLE(htim); 01459 01460 /* Return function status */ 01461 return HAL_OK; 01462 } 01463 01464 /** 01465 * @brief Starts the TIM PWM signal generation in DMA mode. 01466 * @param htim TIM PWM handle 01467 * @param Channel TIM Channels to be enabled 01468 * This parameter can be one of the following values: 01469 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01470 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01471 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01472 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01473 * @param pData The source Buffer address. 01474 * @param Length The length of data to be transferred from memory to TIM peripheral 01475 * @retval HAL status 01476 */ 01477 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) 01478 { 01479 /* Check the parameters */ 01480 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01481 01482 if ((htim->State == HAL_TIM_STATE_BUSY)) 01483 { 01484 return HAL_BUSY; 01485 } 01486 else if ((htim->State == HAL_TIM_STATE_READY)) 01487 { 01488 if ((pData == NULL) && (Length > 0U)) 01489 { 01490 return HAL_ERROR; 01491 } 01492 else 01493 { 01494 htim->State = HAL_TIM_STATE_BUSY; 01495 } 01496 } 01497 else 01498 { 01499 /* nothing to do */ 01500 } 01501 01502 switch (Channel) 01503 { 01504 case TIM_CHANNEL_1: 01505 { 01506 /* Set the DMA Period elapsed callback */ 01507 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; 01508 01509 /* Set the DMA error callback */ 01510 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 01511 01512 /* Enable the DMA channel */ 01513 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) 01514 { 01515 return HAL_ERROR; 01516 } 01517 01518 /* Enable the TIM Capture/Compare 1 DMA request */ 01519 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 01520 break; 01521 } 01522 01523 case TIM_CHANNEL_2: 01524 { 01525 /* Set the DMA Period elapsed callback */ 01526 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; 01527 01528 /* Set the DMA error callback */ 01529 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 01530 01531 /* Enable the DMA channel */ 01532 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) 01533 { 01534 return HAL_ERROR; 01535 } 01536 /* Enable the TIM Capture/Compare 2 DMA request */ 01537 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 01538 break; 01539 } 01540 01541 case TIM_CHANNEL_3: 01542 { 01543 /* Set the DMA Period elapsed callback */ 01544 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; 01545 01546 /* Set the DMA error callback */ 01547 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 01548 01549 /* Enable the DMA channel */ 01550 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) 01551 { 01552 return HAL_ERROR; 01553 } 01554 /* Enable the TIM Output Capture/Compare 3 request */ 01555 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); 01556 break; 01557 } 01558 01559 case TIM_CHANNEL_4: 01560 { 01561 /* Set the DMA Period elapsed callback */ 01562 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; 01563 01564 /* Set the DMA error callback */ 01565 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; 01566 01567 /* Enable the DMA channel */ 01568 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) 01569 { 01570 return HAL_ERROR; 01571 } 01572 /* Enable the TIM Capture/Compare 4 DMA request */ 01573 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); 01574 break; 01575 } 01576 01577 default: 01578 break; 01579 } 01580 01581 /* Enable the Capture compare channel */ 01582 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01583 01584 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 01585 { 01586 /* Enable the main output */ 01587 __HAL_TIM_MOE_ENABLE(htim); 01588 } 01589 01590 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 01591 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 01592 { 01593 __HAL_TIM_ENABLE(htim); 01594 } 01595 01596 /* Return function status */ 01597 return HAL_OK; 01598 } 01599 01600 /** 01601 * @brief Stops the TIM PWM signal generation in DMA mode. 01602 * @param htim TIM PWM handle 01603 * @param Channel TIM Channels to be disabled 01604 * This parameter can be one of the following values: 01605 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01606 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01607 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01608 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01609 * @retval HAL status 01610 */ 01611 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) 01612 { 01613 /* Check the parameters */ 01614 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01615 01616 switch (Channel) 01617 { 01618 case TIM_CHANNEL_1: 01619 { 01620 /* Disable the TIM Capture/Compare 1 DMA request */ 01621 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 01622 break; 01623 } 01624 01625 case TIM_CHANNEL_2: 01626 { 01627 /* Disable the TIM Capture/Compare 2 DMA request */ 01628 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 01629 break; 01630 } 01631 01632 case TIM_CHANNEL_3: 01633 { 01634 /* Disable the TIM Capture/Compare 3 DMA request */ 01635 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); 01636 break; 01637 } 01638 01639 case TIM_CHANNEL_4: 01640 { 01641 /* Disable the TIM Capture/Compare 4 interrupt */ 01642 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); 01643 break; 01644 } 01645 01646 default: 01647 break; 01648 } 01649 01650 /* Disable the Capture compare channel */ 01651 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01652 01653 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 01654 { 01655 /* Disable the Main Output */ 01656 __HAL_TIM_MOE_DISABLE(htim); 01657 } 01658 01659 /* Disable the Peripheral */ 01660 __HAL_TIM_DISABLE(htim); 01661 01662 /* Change the htim state */ 01663 htim->State = HAL_TIM_STATE_READY; 01664 01665 /* Return function status */ 01666 return HAL_OK; 01667 } 01668 01669 /** 01670 * @} 01671 */ 01672 01673 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions 01674 * @brief Time Input Capture functions 01675 * 01676 @verbatim 01677 ============================================================================== 01678 ##### TIM Input Capture functions ##### 01679 ============================================================================== 01680 [..] 01681 This section provides functions allowing to: 01682 (+) Initialize and configure the TIM Input Capture. 01683 (+) De-initialize the TIM Input Capture. 01684 (+) Start the TIM Input Capture. 01685 (+) Stop the TIM Input Capture. 01686 (+) Start the TIM Input Capture and enable interrupt. 01687 (+) Stop the TIM Input Capture and disable interrupt. 01688 (+) Start the TIM Input Capture and enable DMA transfer. 01689 (+) Stop the TIM Input Capture and disable DMA transfer. 01690 01691 @endverbatim 01692 * @{ 01693 */ 01694 /** 01695 * @brief Initializes the TIM Input Capture Time base according to the specified 01696 * parameters in the TIM_HandleTypeDef and initializes the associated handle. 01697 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) 01698 * requires a timer reset to avoid unexpected direction 01699 * due to DIR bit readonly in center aligned mode. 01700 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() 01701 * @param htim TIM Input Capture handle 01702 * @retval HAL status 01703 */ 01704 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) 01705 { 01706 /* Check the TIM handle allocation */ 01707 if (htim == NULL) 01708 { 01709 return HAL_ERROR; 01710 } 01711 01712 /* Check the parameters */ 01713 assert_param(IS_TIM_INSTANCE(htim->Instance)); 01714 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); 01715 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 01716 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); 01717 01718 if (htim->State == HAL_TIM_STATE_RESET) 01719 { 01720 /* Allocate lock resource and initialize it */ 01721 htim->Lock = HAL_UNLOCKED; 01722 01723 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 01724 /* Reset interrupt callbacks to legacy week callbacks */ 01725 TIM_ResetCallback(htim); 01726 01727 if (htim->IC_MspInitCallback == NULL) 01728 { 01729 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; 01730 } 01731 /* Init the low level hardware : GPIO, CLOCK, NVIC */ 01732 htim->IC_MspInitCallback(htim); 01733 #else 01734 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ 01735 HAL_TIM_IC_MspInit(htim); 01736 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 01737 } 01738 01739 /* Set the TIM state */ 01740 htim->State = HAL_TIM_STATE_BUSY; 01741 01742 /* Init the base time for the input capture */ 01743 TIM_Base_SetConfig(htim->Instance, &htim->Init); 01744 01745 /* Initialize the TIM state*/ 01746 htim->State = HAL_TIM_STATE_READY; 01747 01748 return HAL_OK; 01749 } 01750 01751 /** 01752 * @brief DeInitializes the TIM peripheral 01753 * @param htim TIM Input Capture handle 01754 * @retval HAL status 01755 */ 01756 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) 01757 { 01758 /* Check the parameters */ 01759 assert_param(IS_TIM_INSTANCE(htim->Instance)); 01760 01761 htim->State = HAL_TIM_STATE_BUSY; 01762 01763 /* Disable the TIM Peripheral Clock */ 01764 __HAL_TIM_DISABLE(htim); 01765 01766 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 01767 if (htim->IC_MspDeInitCallback == NULL) 01768 { 01769 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; 01770 } 01771 /* DeInit the low level hardware */ 01772 htim->IC_MspDeInitCallback(htim); 01773 #else 01774 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ 01775 HAL_TIM_IC_MspDeInit(htim); 01776 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 01777 01778 /* Change TIM state */ 01779 htim->State = HAL_TIM_STATE_RESET; 01780 01781 /* Release Lock */ 01782 __HAL_UNLOCK(htim); 01783 01784 return HAL_OK; 01785 } 01786 01787 /** 01788 * @brief Initializes the TIM Input Capture MSP. 01789 * @param htim TIM Input Capture handle 01790 * @retval None 01791 */ 01792 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) 01793 { 01794 /* Prevent unused argument(s) compilation warning */ 01795 UNUSED(htim); 01796 01797 /* NOTE : This function should not be modified, when the callback is needed, 01798 the HAL_TIM_IC_MspInit could be implemented in the user file 01799 */ 01800 } 01801 01802 /** 01803 * @brief DeInitializes TIM Input Capture MSP. 01804 * @param htim TIM handle 01805 * @retval None 01806 */ 01807 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) 01808 { 01809 /* Prevent unused argument(s) compilation warning */ 01810 UNUSED(htim); 01811 01812 /* NOTE : This function should not be modified, when the callback is needed, 01813 the HAL_TIM_IC_MspDeInit could be implemented in the user file 01814 */ 01815 } 01816 01817 /** 01818 * @brief Starts the TIM Input Capture measurement. 01819 * @param htim TIM Input Capture handle 01820 * @param Channel TIM Channels to be enabled 01821 * This parameter can be one of the following values: 01822 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01823 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01824 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01825 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01826 * @retval HAL status 01827 */ 01828 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) 01829 { 01830 /* Check the parameters */ 01831 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01832 01833 /* Enable the Input Capture channel */ 01834 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01835 01836 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 01837 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 01838 { 01839 __HAL_TIM_ENABLE(htim); 01840 } 01841 01842 /* Return function status */ 01843 return HAL_OK; 01844 } 01845 01846 /** 01847 * @brief Stops the TIM Input Capture measurement. 01848 * @param htim TIM Input Capture handle 01849 * @param Channel TIM Channels to be disabled 01850 * This parameter can be one of the following values: 01851 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01852 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01853 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01854 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01855 * @retval HAL status 01856 */ 01857 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) 01858 { 01859 /* Check the parameters */ 01860 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01861 01862 /* Disable the Input Capture channel */ 01863 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01864 01865 /* Disable the Peripheral */ 01866 __HAL_TIM_DISABLE(htim); 01867 01868 /* Return function status */ 01869 return HAL_OK; 01870 } 01871 01872 /** 01873 * @brief Starts the TIM Input Capture measurement in interrupt mode. 01874 * @param htim TIM Input Capture handle 01875 * @param Channel TIM Channels to be enabled 01876 * This parameter can be one of the following values: 01877 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01878 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01879 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01880 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01881 * @retval HAL status 01882 */ 01883 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 01884 { 01885 /* Check the parameters */ 01886 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01887 01888 switch (Channel) 01889 { 01890 case TIM_CHANNEL_1: 01891 { 01892 /* Enable the TIM Capture/Compare 1 interrupt */ 01893 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 01894 break; 01895 } 01896 01897 case TIM_CHANNEL_2: 01898 { 01899 /* Enable the TIM Capture/Compare 2 interrupt */ 01900 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 01901 break; 01902 } 01903 01904 case TIM_CHANNEL_3: 01905 { 01906 /* Enable the TIM Capture/Compare 3 interrupt */ 01907 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 01908 break; 01909 } 01910 01911 case TIM_CHANNEL_4: 01912 { 01913 /* Enable the TIM Capture/Compare 4 interrupt */ 01914 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 01915 break; 01916 } 01917 01918 default: 01919 break; 01920 } 01921 /* Enable the Input Capture channel */ 01922 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01923 01924 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 01925 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 01926 { 01927 __HAL_TIM_ENABLE(htim); 01928 } 01929 01930 /* Return function status */ 01931 return HAL_OK; 01932 } 01933 01934 /** 01935 * @brief Stops the TIM Input Capture measurement in interrupt mode. 01936 * @param htim TIM Input Capture handle 01937 * @param Channel TIM Channels to be disabled 01938 * This parameter can be one of the following values: 01939 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01940 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01941 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01942 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01943 * @retval HAL status 01944 */ 01945 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 01946 { 01947 /* Check the parameters */ 01948 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01949 01950 switch (Channel) 01951 { 01952 case TIM_CHANNEL_1: 01953 { 01954 /* Disable the TIM Capture/Compare 1 interrupt */ 01955 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 01956 break; 01957 } 01958 01959 case TIM_CHANNEL_2: 01960 { 01961 /* Disable the TIM Capture/Compare 2 interrupt */ 01962 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 01963 break; 01964 } 01965 01966 case TIM_CHANNEL_3: 01967 { 01968 /* Disable the TIM Capture/Compare 3 interrupt */ 01969 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); 01970 break; 01971 } 01972 01973 case TIM_CHANNEL_4: 01974 { 01975 /* Disable the TIM Capture/Compare 4 interrupt */ 01976 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); 01977 break; 01978 } 01979 01980 default: 01981 break; 01982 } 01983 01984 /* Disable the Input Capture channel */ 01985 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01986 01987 /* Disable the Peripheral */ 01988 __HAL_TIM_DISABLE(htim); 01989 01990 /* Return function status */ 01991 return HAL_OK; 01992 } 01993 01994 /** 01995 * @brief Starts the TIM Input Capture measurement in DMA mode. 01996 * @param htim TIM Input Capture handle 01997 * @param Channel TIM Channels to be enabled 01998 * This parameter can be one of the following values: 01999 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02000 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02001 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 02002 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 02003 * @param pData The destination Buffer address. 02004 * @param Length The length of data to be transferred from TIM peripheral to memory. 02005 * @retval HAL status 02006 */ 02007 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) 02008 { 02009 /* Check the parameters */ 02010 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 02011 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); 02012 02013 if ((htim->State == HAL_TIM_STATE_BUSY)) 02014 { 02015 return HAL_BUSY; 02016 } 02017 else if ((htim->State == HAL_TIM_STATE_READY)) 02018 { 02019 if ((pData == NULL) && (Length > 0U)) 02020 { 02021 return HAL_ERROR; 02022 } 02023 else 02024 { 02025 htim->State = HAL_TIM_STATE_BUSY; 02026 } 02027 } 02028 else 02029 { 02030 /* nothing to do */ 02031 } 02032 02033 switch (Channel) 02034 { 02035 case TIM_CHANNEL_1: 02036 { 02037 /* Set the DMA Period elapsed callback */ 02038 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; 02039 02040 /* Set the DMA error callback */ 02041 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 02042 02043 /* Enable the DMA channel */ 02044 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) 02045 { 02046 return HAL_ERROR; 02047 } 02048 /* Enable the TIM Capture/Compare 1 DMA request */ 02049 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 02050 break; 02051 } 02052 02053 case TIM_CHANNEL_2: 02054 { 02055 /* Set the DMA Period elapsed callback */ 02056 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; 02057 02058 /* Set the DMA error callback */ 02059 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 02060 02061 /* Enable the DMA channel */ 02062 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) 02063 { 02064 return HAL_ERROR; 02065 } 02066 /* Enable the TIM Capture/Compare 2 DMA request */ 02067 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 02068 break; 02069 } 02070 02071 case TIM_CHANNEL_3: 02072 { 02073 /* Set the DMA Period elapsed callback */ 02074 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; 02075 02076 /* Set the DMA error callback */ 02077 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 02078 02079 /* Enable the DMA channel */ 02080 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) 02081 { 02082 return HAL_ERROR; 02083 } 02084 /* Enable the TIM Capture/Compare 3 DMA request */ 02085 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); 02086 break; 02087 } 02088 02089 case TIM_CHANNEL_4: 02090 { 02091 /* Set the DMA Period elapsed callback */ 02092 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; 02093 02094 /* Set the DMA error callback */ 02095 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; 02096 02097 /* Enable the DMA channel */ 02098 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) 02099 { 02100 return HAL_ERROR; 02101 } 02102 /* Enable the TIM Capture/Compare 4 DMA request */ 02103 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); 02104 break; 02105 } 02106 02107 default: 02108 break; 02109 } 02110 02111 /* Enable the Input Capture channel */ 02112 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 02113 02114 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ 02115 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(htim)) 02116 { 02117 __HAL_TIM_ENABLE(htim); 02118 } 02119 02120 /* Return function status */ 02121 return HAL_OK; 02122 } 02123 02124 /** 02125 * @brief Stops the TIM Input Capture measurement in DMA mode. 02126 * @param htim TIM Input Capture handle 02127 * @param Channel TIM Channels to be disabled 02128 * This parameter can be one of the following values: 02129 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02130 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02131 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 02132 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 02133 * @retval HAL status 02134 */ 02135 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) 02136 { 02137 /* Check the parameters */ 02138 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 02139 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); 02140 02141 switch (Channel) 02142 { 02143 case TIM_CHANNEL_1: 02144 { 02145 /* Disable the TIM Capture/Compare 1 DMA request */ 02146 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 02147 break; 02148 } 02149 02150 case TIM_CHANNEL_2: 02151 { 02152 /* Disable the TIM Capture/Compare 2 DMA request */ 02153 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 02154 break; 02155 } 02156 02157 case TIM_CHANNEL_3: 02158 { 02159 /* Disable the TIM Capture/Compare 3 DMA request */ 02160 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); 02161 break; 02162 } 02163 02164 case TIM_CHANNEL_4: 02165 { 02166 /* Disable the TIM Capture/Compare 4 DMA request */ 02167 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); 02168 break; 02169 } 02170 02171 default: 02172 break; 02173 } 02174 02175 /* Disable the Input Capture channel */ 02176 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 02177 02178 /* Disable the Peripheral */ 02179 __HAL_TIM_DISABLE(htim); 02180 02181 /* Change the htim state */ 02182 htim->State = HAL_TIM_STATE_READY; 02183 02184 /* Return function status */ 02185 return HAL_OK; 02186 } 02187 /** 02188 * @} 02189 */ 02190 02191 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions 02192 * @brief Time One Pulse functions 02193 * 02194 @verbatim 02195 ============================================================================== 02196 ##### Time One Pulse functions ##### 02197 ============================================================================== 02198 [..] 02199 This section provides functions allowing to: 02200 (+) Initialize and configure the TIM One Pulse. 02201 (+) De-initialize the TIM One Pulse. 02202 (+) Start the TIM One Pulse. 02203 (+) Stop the TIM One Pulse. 02204 (+) Start the TIM One Pulse and enable interrupt. 02205 (+) Stop the TIM One Pulse and disable interrupt. 02206 (+) Start the TIM One Pulse and enable DMA transfer. 02207 (+) Stop the TIM One Pulse and disable DMA transfer. 02208 02209 @endverbatim 02210 * @{ 02211 */ 02212 /** 02213 * @brief Initializes the TIM One Pulse Time Base according to the specified 02214 * parameters in the TIM_HandleTypeDef and initializes the associated handle. 02215 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) 02216 * requires a timer reset to avoid unexpected direction 02217 * due to DIR bit readonly in center aligned mode. 02218 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() 02219 * @param htim TIM One Pulse handle 02220 * @param OnePulseMode Select the One pulse mode. 02221 * This parameter can be one of the following values: 02222 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. 02223 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. 02224 * @retval HAL status 02225 */ 02226 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) 02227 { 02228 /* Check the TIM handle allocation */ 02229 if (htim == NULL) 02230 { 02231 return HAL_ERROR; 02232 } 02233 02234 /* Check the parameters */ 02235 assert_param(IS_TIM_INSTANCE(htim->Instance)); 02236 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); 02237 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 02238 assert_param(IS_TIM_OPM_MODE(OnePulseMode)); 02239 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); 02240 02241 if (htim->State == HAL_TIM_STATE_RESET) 02242 { 02243 /* Allocate lock resource and initialize it */ 02244 htim->Lock = HAL_UNLOCKED; 02245 02246 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 02247 /* Reset interrupt callbacks to legacy week callbacks */ 02248 TIM_ResetCallback(htim); 02249 02250 if (htim->OnePulse_MspInitCallback == NULL) 02251 { 02252 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; 02253 } 02254 /* Init the low level hardware : GPIO, CLOCK, NVIC */ 02255 htim->OnePulse_MspInitCallback(htim); 02256 #else 02257 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ 02258 HAL_TIM_OnePulse_MspInit(htim); 02259 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 02260 } 02261 02262 /* Set the TIM state */ 02263 htim->State = HAL_TIM_STATE_BUSY; 02264 02265 /* Configure the Time base in the One Pulse Mode */ 02266 TIM_Base_SetConfig(htim->Instance, &htim->Init); 02267 02268 /* Reset the OPM Bit */ 02269 htim->Instance->CR1 &= ~TIM_CR1_OPM; 02270 02271 /* Configure the OPM Mode */ 02272 htim->Instance->CR1 |= OnePulseMode; 02273 02274 /* Initialize the TIM state*/ 02275 htim->State = HAL_TIM_STATE_READY; 02276 02277 return HAL_OK; 02278 } 02279 02280 /** 02281 * @brief DeInitializes the TIM One Pulse 02282 * @param htim TIM One Pulse handle 02283 * @retval HAL status 02284 */ 02285 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) 02286 { 02287 /* Check the parameters */ 02288 assert_param(IS_TIM_INSTANCE(htim->Instance)); 02289 02290 htim->State = HAL_TIM_STATE_BUSY; 02291 02292 /* Disable the TIM Peripheral Clock */ 02293 __HAL_TIM_DISABLE(htim); 02294 02295 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 02296 if (htim->OnePulse_MspDeInitCallback == NULL) 02297 { 02298 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; 02299 } 02300 /* DeInit the low level hardware */ 02301 htim->OnePulse_MspDeInitCallback(htim); 02302 #else 02303 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ 02304 HAL_TIM_OnePulse_MspDeInit(htim); 02305 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 02306 02307 /* Change TIM state */ 02308 htim->State = HAL_TIM_STATE_RESET; 02309 02310 /* Release Lock */ 02311 __HAL_UNLOCK(htim); 02312 02313 return HAL_OK; 02314 } 02315 02316 /** 02317 * @brief Initializes the TIM One Pulse MSP. 02318 * @param htim TIM One Pulse handle 02319 * @retval None 02320 */ 02321 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) 02322 { 02323 /* Prevent unused argument(s) compilation warning */ 02324 UNUSED(htim); 02325 02326 /* NOTE : This function should not be modified, when the callback is needed, 02327 the HAL_TIM_OnePulse_MspInit could be implemented in the user file 02328 */ 02329 } 02330 02331 /** 02332 * @brief DeInitializes TIM One Pulse MSP. 02333 * @param htim TIM One Pulse handle 02334 * @retval None 02335 */ 02336 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) 02337 { 02338 /* Prevent unused argument(s) compilation warning */ 02339 UNUSED(htim); 02340 02341 /* NOTE : This function should not be modified, when the callback is needed, 02342 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file 02343 */ 02344 } 02345 02346 /** 02347 * @brief Starts the TIM One Pulse signal generation. 02348 * @param htim TIM One Pulse handle 02349 * @param OutputChannel TIM Channels to be enabled 02350 * This parameter can be one of the following values: 02351 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02352 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02353 * @retval HAL status 02354 */ 02355 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) 02356 { 02357 /* Prevent unused argument(s) compilation warning */ 02358 UNUSED(OutputChannel); 02359 02360 /* Enable the Capture compare and the Input Capture channels 02361 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) 02362 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and 02363 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 02364 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together 02365 02366 No need to enable the counter, it's enabled automatically by hardware 02367 (the counter starts in response to a stimulus and generate a pulse */ 02368 02369 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02370 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02371 02372 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 02373 { 02374 /* Enable the main output */ 02375 __HAL_TIM_MOE_ENABLE(htim); 02376 } 02377 02378 /* Return function status */ 02379 return HAL_OK; 02380 } 02381 02382 /** 02383 * @brief Stops the TIM One Pulse signal generation. 02384 * @param htim TIM One Pulse handle 02385 * @param OutputChannel TIM Channels to be disable 02386 * This parameter can be one of the following values: 02387 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02388 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02389 * @retval HAL status 02390 */ 02391 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) 02392 { 02393 /* Prevent unused argument(s) compilation warning */ 02394 UNUSED(OutputChannel); 02395 02396 /* Disable the Capture compare and the Input Capture channels 02397 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) 02398 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and 02399 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 02400 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ 02401 02402 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02403 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02404 02405 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 02406 { 02407 /* Disable the Main Output */ 02408 __HAL_TIM_MOE_DISABLE(htim); 02409 } 02410 02411 /* Disable the Peripheral */ 02412 __HAL_TIM_DISABLE(htim); 02413 02414 /* Return function status */ 02415 return HAL_OK; 02416 } 02417 02418 /** 02419 * @brief Starts the TIM One Pulse signal generation in interrupt mode. 02420 * @param htim TIM One Pulse handle 02421 * @param OutputChannel TIM Channels to be enabled 02422 * This parameter can be one of the following values: 02423 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02424 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02425 * @retval HAL status 02426 */ 02427 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) 02428 { 02429 /* Prevent unused argument(s) compilation warning */ 02430 UNUSED(OutputChannel); 02431 02432 /* Enable the Capture compare and the Input Capture channels 02433 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) 02434 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and 02435 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 02436 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together 02437 02438 No need to enable the counter, it's enabled automatically by hardware 02439 (the counter starts in response to a stimulus and generate a pulse */ 02440 02441 /* Enable the TIM Capture/Compare 1 interrupt */ 02442 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 02443 02444 /* Enable the TIM Capture/Compare 2 interrupt */ 02445 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 02446 02447 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02448 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02449 02450 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 02451 { 02452 /* Enable the main output */ 02453 __HAL_TIM_MOE_ENABLE(htim); 02454 } 02455 02456 /* Return function status */ 02457 return HAL_OK; 02458 } 02459 02460 /** 02461 * @brief Stops the TIM One Pulse signal generation in interrupt mode. 02462 * @param htim TIM One Pulse handle 02463 * @param OutputChannel TIM Channels to be enabled 02464 * This parameter can be one of the following values: 02465 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02466 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02467 * @retval HAL status 02468 */ 02469 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) 02470 { 02471 /* Prevent unused argument(s) compilation warning */ 02472 UNUSED(OutputChannel); 02473 02474 /* Disable the TIM Capture/Compare 1 interrupt */ 02475 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 02476 02477 /* Disable the TIM Capture/Compare 2 interrupt */ 02478 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 02479 02480 /* Disable the Capture compare and the Input Capture channels 02481 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) 02482 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and 02483 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 02484 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ 02485 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02486 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02487 02488 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 02489 { 02490 /* Disable the Main Output */ 02491 __HAL_TIM_MOE_DISABLE(htim); 02492 } 02493 02494 /* Disable the Peripheral */ 02495 __HAL_TIM_DISABLE(htim); 02496 02497 /* Return function status */ 02498 return HAL_OK; 02499 } 02500 02501 /** 02502 * @} 02503 */ 02504 02505 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions 02506 * @brief Time Encoder functions 02507 * 02508 @verbatim 02509 ============================================================================== 02510 ##### TIM Encoder functions ##### 02511 ============================================================================== 02512 [..] 02513 This section provides functions allowing to: 02514 (+) Initialize and configure the TIM Encoder. 02515 (+) De-initialize the TIM Encoder. 02516 (+) Start the TIM Encoder. 02517 (+) Stop the TIM Encoder. 02518 (+) Start the TIM Encoder and enable interrupt. 02519 (+) Stop the TIM Encoder and disable interrupt. 02520 (+) Start the TIM Encoder and enable DMA transfer. 02521 (+) Stop the TIM Encoder and disable DMA transfer. 02522 02523 @endverbatim 02524 * @{ 02525 */ 02526 /** 02527 * @brief Initializes the TIM Encoder Interface and initialize the associated handle. 02528 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) 02529 * requires a timer reset to avoid unexpected direction 02530 * due to DIR bit readonly in center aligned mode. 02531 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() 02532 * @param htim TIM Encoder Interface handle 02533 * @param sConfig TIM Encoder Interface configuration structure 02534 * @retval HAL status 02535 */ 02536 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) 02537 { 02538 uint32_t tmpsmcr; 02539 uint32_t tmpccmr1; 02540 uint32_t tmpccer; 02541 02542 /* Check the TIM handle allocation */ 02543 if (htim == NULL) 02544 { 02545 return HAL_ERROR; 02546 } 02547 02548 /* Check the parameters */ 02549 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); 02550 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 02551 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); 02552 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 02553 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); 02554 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); 02555 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); 02556 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); 02557 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); 02558 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); 02559 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); 02560 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); 02561 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); 02562 02563 if (htim->State == HAL_TIM_STATE_RESET) 02564 { 02565 /* Allocate lock resource and initialize it */ 02566 htim->Lock = HAL_UNLOCKED; 02567 02568 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 02569 /* Reset interrupt callbacks to legacy week callbacks */ 02570 TIM_ResetCallback(htim); 02571 02572 if (htim->Encoder_MspInitCallback == NULL) 02573 { 02574 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; 02575 } 02576 /* Init the low level hardware : GPIO, CLOCK, NVIC */ 02577 htim->Encoder_MspInitCallback(htim); 02578 #else 02579 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ 02580 HAL_TIM_Encoder_MspInit(htim); 02581 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 02582 } 02583 02584 /* Set the TIM state */ 02585 htim->State = HAL_TIM_STATE_BUSY; 02586 02587 /* Reset the SMS bits */ 02588 htim->Instance->SMCR &= ~TIM_SMCR_SMS; 02589 02590 /* Configure the Time base in the Encoder Mode */ 02591 TIM_Base_SetConfig(htim->Instance, &htim->Init); 02592 02593 /* Get the TIMx SMCR register value */ 02594 tmpsmcr = htim->Instance->SMCR; 02595 02596 /* Get the TIMx CCMR1 register value */ 02597 tmpccmr1 = htim->Instance->CCMR1; 02598 02599 /* Get the TIMx CCER register value */ 02600 tmpccer = htim->Instance->CCER; 02601 02602 /* Set the encoder Mode */ 02603 tmpsmcr |= sConfig->EncoderMode; 02604 02605 /* Select the Capture Compare 1 and the Capture Compare 2 as input */ 02606 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); 02607 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); 02608 02609 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ 02610 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); 02611 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); 02612 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); 02613 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); 02614 02615 /* Set the TI1 and the TI2 Polarities */ 02616 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); 02617 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); 02618 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); 02619 02620 /* Write to TIMx SMCR */ 02621 htim->Instance->SMCR = tmpsmcr; 02622 02623 /* Write to TIMx CCMR1 */ 02624 htim->Instance->CCMR1 = tmpccmr1; 02625 02626 /* Write to TIMx CCER */ 02627 htim->Instance->CCER = tmpccer; 02628 02629 /* Initialize the TIM state*/ 02630 htim->State = HAL_TIM_STATE_READY; 02631 02632 return HAL_OK; 02633 } 02634 02635 02636 /** 02637 * @brief DeInitializes the TIM Encoder interface 02638 * @param htim TIM Encoder Interface handle 02639 * @retval HAL status 02640 */ 02641 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) 02642 { 02643 /* Check the parameters */ 02644 assert_param(IS_TIM_INSTANCE(htim->Instance)); 02645 02646 htim->State = HAL_TIM_STATE_BUSY; 02647 02648 /* Disable the TIM Peripheral Clock */ 02649 __HAL_TIM_DISABLE(htim); 02650 02651 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 02652 if (htim->Encoder_MspDeInitCallback == NULL) 02653 { 02654 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; 02655 } 02656 /* DeInit the low level hardware */ 02657 htim->Encoder_MspDeInitCallback(htim); 02658 #else 02659 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ 02660 HAL_TIM_Encoder_MspDeInit(htim); 02661 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 02662 02663 /* Change TIM state */ 02664 htim->State = HAL_TIM_STATE_RESET; 02665 02666 /* Release Lock */ 02667 __HAL_UNLOCK(htim); 02668 02669 return HAL_OK; 02670 } 02671 02672 /** 02673 * @brief Initializes the TIM Encoder Interface MSP. 02674 * @param htim TIM Encoder Interface handle 02675 * @retval None 02676 */ 02677 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) 02678 { 02679 /* Prevent unused argument(s) compilation warning */ 02680 UNUSED(htim); 02681 02682 /* NOTE : This function should not be modified, when the callback is needed, 02683 the HAL_TIM_Encoder_MspInit could be implemented in the user file 02684 */ 02685 } 02686 02687 /** 02688 * @brief DeInitializes TIM Encoder Interface MSP. 02689 * @param htim TIM Encoder Interface handle 02690 * @retval None 02691 */ 02692 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) 02693 { 02694 /* Prevent unused argument(s) compilation warning */ 02695 UNUSED(htim); 02696 02697 /* NOTE : This function should not be modified, when the callback is needed, 02698 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file 02699 */ 02700 } 02701 02702 /** 02703 * @brief Starts the TIM Encoder Interface. 02704 * @param htim TIM Encoder Interface handle 02705 * @param Channel TIM Channels to be enabled 02706 * This parameter can be one of the following values: 02707 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02708 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02709 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 02710 * @retval HAL status 02711 */ 02712 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) 02713 { 02714 /* Check the parameters */ 02715 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 02716 02717 /* Enable the encoder interface channels */ 02718 switch (Channel) 02719 { 02720 case TIM_CHANNEL_1: 02721 { 02722 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02723 break; 02724 } 02725 02726 case TIM_CHANNEL_2: 02727 { 02728 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02729 break; 02730 } 02731 02732 default : 02733 { 02734 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02735 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02736 break; 02737 } 02738 } 02739 /* Enable the Peripheral */ 02740 __HAL_TIM_ENABLE(htim); 02741 02742 /* Return function status */ 02743 return HAL_OK; 02744 } 02745 02746 /** 02747 * @brief Stops the TIM Encoder Interface. 02748 * @param htim TIM Encoder Interface handle 02749 * @param Channel TIM Channels to be disabled 02750 * This parameter can be one of the following values: 02751 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02752 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02753 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 02754 * @retval HAL status 02755 */ 02756 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) 02757 { 02758 /* Check the parameters */ 02759 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 02760 02761 /* Disable the Input Capture channels 1 and 2 02762 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 02763 switch (Channel) 02764 { 02765 case TIM_CHANNEL_1: 02766 { 02767 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02768 break; 02769 } 02770 02771 case TIM_CHANNEL_2: 02772 { 02773 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02774 break; 02775 } 02776 02777 default : 02778 { 02779 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02780 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02781 break; 02782 } 02783 } 02784 02785 /* Disable the Peripheral */ 02786 __HAL_TIM_DISABLE(htim); 02787 02788 /* Return function status */ 02789 return HAL_OK; 02790 } 02791 02792 /** 02793 * @brief Starts the TIM Encoder Interface in interrupt mode. 02794 * @param htim TIM Encoder Interface handle 02795 * @param Channel TIM Channels to be enabled 02796 * This parameter can be one of the following values: 02797 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02798 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02799 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 02800 * @retval HAL status 02801 */ 02802 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 02803 { 02804 /* Check the parameters */ 02805 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 02806 02807 /* Enable the encoder interface channels */ 02808 /* Enable the capture compare Interrupts 1 and/or 2 */ 02809 switch (Channel) 02810 { 02811 case TIM_CHANNEL_1: 02812 { 02813 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02814 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 02815 break; 02816 } 02817 02818 case TIM_CHANNEL_2: 02819 { 02820 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02821 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 02822 break; 02823 } 02824 02825 default : 02826 { 02827 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02828 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02829 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 02830 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 02831 break; 02832 } 02833 } 02834 02835 /* Enable the Peripheral */ 02836 __HAL_TIM_ENABLE(htim); 02837 02838 /* Return function status */ 02839 return HAL_OK; 02840 } 02841 02842 /** 02843 * @brief Stops the TIM Encoder Interface in interrupt mode. 02844 * @param htim TIM Encoder Interface handle 02845 * @param Channel TIM Channels to be disabled 02846 * This parameter can be one of the following values: 02847 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02848 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02849 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 02850 * @retval HAL status 02851 */ 02852 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 02853 { 02854 /* Check the parameters */ 02855 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 02856 02857 /* Disable the Input Capture channels 1 and 2 02858 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 02859 if (Channel == TIM_CHANNEL_1) 02860 { 02861 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02862 02863 /* Disable the capture compare Interrupts 1 */ 02864 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 02865 } 02866 else if (Channel == TIM_CHANNEL_2) 02867 { 02868 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02869 02870 /* Disable the capture compare Interrupts 2 */ 02871 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 02872 } 02873 else 02874 { 02875 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02876 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02877 02878 /* Disable the capture compare Interrupts 1 and 2 */ 02879 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 02880 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 02881 } 02882 02883 /* Disable the Peripheral */ 02884 __HAL_TIM_DISABLE(htim); 02885 02886 /* Change the htim state */ 02887 htim->State = HAL_TIM_STATE_READY; 02888 02889 /* Return function status */ 02890 return HAL_OK; 02891 } 02892 02893 /** 02894 * @brief Starts the TIM Encoder Interface in DMA mode. 02895 * @param htim TIM Encoder Interface handle 02896 * @param Channel TIM Channels to be enabled 02897 * This parameter can be one of the following values: 02898 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02899 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02900 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 02901 * @param pData1 The destination Buffer address for IC1. 02902 * @param pData2 The destination Buffer address for IC2. 02903 * @param Length The length of data to be transferred from TIM peripheral to memory. 02904 * @retval HAL status 02905 */ 02906 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) 02907 { 02908 /* Check the parameters */ 02909 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); 02910 02911 if ((htim->State == HAL_TIM_STATE_BUSY)) 02912 { 02913 return HAL_BUSY; 02914 } 02915 else if ((htim->State == HAL_TIM_STATE_READY)) 02916 { 02917 if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) 02918 { 02919 return HAL_ERROR; 02920 } 02921 else 02922 { 02923 htim->State = HAL_TIM_STATE_BUSY; 02924 } 02925 } 02926 else 02927 { 02928 /* nothing to do */ 02929 } 02930 02931 switch (Channel) 02932 { 02933 case TIM_CHANNEL_1: 02934 { 02935 /* Set the DMA Period elapsed callback */ 02936 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; 02937 02938 /* Set the DMA error callback */ 02939 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 02940 02941 /* Enable the DMA channel */ 02942 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) 02943 { 02944 return HAL_ERROR; 02945 } 02946 /* Enable the TIM Input Capture DMA request */ 02947 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 02948 02949 /* Enable the Peripheral */ 02950 __HAL_TIM_ENABLE(htim); 02951 02952 /* Enable the Capture compare channel */ 02953 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02954 break; 02955 } 02956 02957 case TIM_CHANNEL_2: 02958 { 02959 /* Set the DMA Period elapsed callback */ 02960 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; 02961 02962 /* Set the DMA error callback */ 02963 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; 02964 /* Enable the DMA channel */ 02965 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) 02966 { 02967 return HAL_ERROR; 02968 } 02969 /* Enable the TIM Input Capture DMA request */ 02970 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 02971 02972 /* Enable the Peripheral */ 02973 __HAL_TIM_ENABLE(htim); 02974 02975 /* Enable the Capture compare channel */ 02976 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02977 break; 02978 } 02979 02980 case TIM_CHANNEL_ALL: 02981 { 02982 /* Set the DMA Period elapsed callback */ 02983 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; 02984 02985 /* Set the DMA error callback */ 02986 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 02987 02988 /* Enable the DMA channel */ 02989 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) 02990 { 02991 return HAL_ERROR; 02992 } 02993 02994 /* Set the DMA Period elapsed callback */ 02995 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; 02996 02997 /* Set the DMA error callback */ 02998 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 02999 03000 /* Enable the DMA channel */ 03001 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) 03002 { 03003 return HAL_ERROR; 03004 } 03005 /* Enable the Peripheral */ 03006 __HAL_TIM_ENABLE(htim); 03007 03008 /* Enable the Capture compare channel */ 03009 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 03010 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 03011 03012 /* Enable the TIM Input Capture DMA request */ 03013 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 03014 /* Enable the TIM Input Capture DMA request */ 03015 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 03016 break; 03017 } 03018 03019 default: 03020 break; 03021 } 03022 /* Return function status */ 03023 return HAL_OK; 03024 } 03025 03026 /** 03027 * @brief Stops the TIM Encoder Interface in DMA mode. 03028 * @param htim TIM Encoder Interface handle 03029 * @param Channel TIM Channels to be enabled 03030 * This parameter can be one of the following values: 03031 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 03032 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 03033 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 03034 * @retval HAL status 03035 */ 03036 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) 03037 { 03038 /* Check the parameters */ 03039 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); 03040 03041 /* Disable the Input Capture channels 1 and 2 03042 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 03043 if (Channel == TIM_CHANNEL_1) 03044 { 03045 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 03046 03047 /* Disable the capture compare DMA Request 1 */ 03048 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 03049 } 03050 else if (Channel == TIM_CHANNEL_2) 03051 { 03052 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 03053 03054 /* Disable the capture compare DMA Request 2 */ 03055 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 03056 } 03057 else 03058 { 03059 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 03060 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 03061 03062 /* Disable the capture compare DMA Request 1 and 2 */ 03063 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 03064 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 03065 } 03066 03067 /* Disable the Peripheral */ 03068 __HAL_TIM_DISABLE(htim); 03069 03070 /* Change the htim state */ 03071 htim->State = HAL_TIM_STATE_READY; 03072 03073 /* Return function status */ 03074 return HAL_OK; 03075 } 03076 03077 /** 03078 * @} 03079 */ 03080 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management 03081 * @brief IRQ handler management 03082 * 03083 @verbatim 03084 ============================================================================== 03085 ##### IRQ handler management ##### 03086 ============================================================================== 03087 [..] 03088 This section provides Timer IRQ handler function. 03089 03090 @endverbatim 03091 * @{ 03092 */ 03093 /** 03094 * @brief This function handles TIM interrupts requests. 03095 * @param htim TIM handle 03096 * @retval None 03097 */ 03098 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) 03099 { 03100 /* Capture compare 1 event */ 03101 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 03102 { 03103 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) 03104 { 03105 { 03106 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); 03107 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 03108 03109 /* Input capture event */ 03110 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 03111 { 03112 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 03113 htim->IC_CaptureCallback(htim); 03114 #else 03115 HAL_TIM_IC_CaptureCallback(htim); 03116 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 03117 } 03118 /* Output compare event */ 03119 else 03120 { 03121 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 03122 htim->OC_DelayElapsedCallback(htim); 03123 htim->PWM_PulseFinishedCallback(htim); 03124 #else 03125 HAL_TIM_OC_DelayElapsedCallback(htim); 03126 HAL_TIM_PWM_PulseFinishedCallback(htim); 03127 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 03128 } 03129 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 03130 } 03131 } 03132 } 03133 /* Capture compare 2 event */ 03134 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) 03135 { 03136 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) 03137 { 03138 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); 03139 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 03140 /* Input capture event */ 03141 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 03142 { 03143 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 03144 htim->IC_CaptureCallback(htim); 03145 #else 03146 HAL_TIM_IC_CaptureCallback(htim); 03147 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 03148 } 03149 /* Output compare event */ 03150 else 03151 { 03152 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 03153 htim->OC_DelayElapsedCallback(htim); 03154 htim->PWM_PulseFinishedCallback(htim); 03155 #else 03156 HAL_TIM_OC_DelayElapsedCallback(htim); 03157 HAL_TIM_PWM_PulseFinishedCallback(htim); 03158 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 03159 } 03160 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 03161 } 03162 } 03163 /* Capture compare 3 event */ 03164 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) 03165 { 03166 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) 03167 { 03168 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); 03169 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 03170 /* Input capture event */ 03171 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 03172 { 03173 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 03174 htim->IC_CaptureCallback(htim); 03175 #else 03176 HAL_TIM_IC_CaptureCallback(htim); 03177 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 03178 } 03179 /* Output compare event */ 03180 else 03181 { 03182 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 03183 htim->OC_DelayElapsedCallback(htim); 03184 htim->PWM_PulseFinishedCallback(htim); 03185 #else 03186 HAL_TIM_OC_DelayElapsedCallback(htim); 03187 HAL_TIM_PWM_PulseFinishedCallback(htim); 03188 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 03189 } 03190 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 03191 } 03192 } 03193 /* Capture compare 4 event */ 03194 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) 03195 { 03196 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) 03197 { 03198 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); 03199 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 03200 /* Input capture event */ 03201 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 03202 { 03203 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 03204 htim->IC_CaptureCallback(htim); 03205 #else 03206 HAL_TIM_IC_CaptureCallback(htim); 03207 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 03208 } 03209 /* Output compare event */ 03210 else 03211 { 03212 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 03213 htim->OC_DelayElapsedCallback(htim); 03214 htim->PWM_PulseFinishedCallback(htim); 03215 #else 03216 HAL_TIM_OC_DelayElapsedCallback(htim); 03217 HAL_TIM_PWM_PulseFinishedCallback(htim); 03218 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 03219 } 03220 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 03221 } 03222 } 03223 /* TIM Update event */ 03224 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) 03225 { 03226 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) 03227 { 03228 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 03229 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 03230 htim->PeriodElapsedCallback(htim); 03231 #else 03232 HAL_TIM_PeriodElapsedCallback(htim); 03233 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 03234 } 03235 } 03236 /* TIM Break input event */ 03237 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) 03238 { 03239 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) 03240 { 03241 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 03242 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 03243 htim->BreakCallback(htim); 03244 #else 03245 HAL_TIMEx_BreakCallback(htim); 03246 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 03247 } 03248 } 03249 /* TIM Break2 input event */ 03250 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) 03251 { 03252 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) 03253 { 03254 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 03255 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 03256 htim->Break2Callback(htim); 03257 #else 03258 HAL_TIMEx_Break2Callback(htim); 03259 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 03260 } 03261 } 03262 /* TIM Trigger detection event */ 03263 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) 03264 { 03265 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) 03266 { 03267 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 03268 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 03269 htim->TriggerCallback(htim); 03270 #else 03271 HAL_TIM_TriggerCallback(htim); 03272 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 03273 } 03274 } 03275 /* TIM commutation event */ 03276 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) 03277 { 03278 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) 03279 { 03280 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 03281 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 03282 htim->CommutationCallback(htim); 03283 #else 03284 HAL_TIMEx_CommutationCallback(htim); 03285 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 03286 } 03287 } 03288 } 03289 03290 /** 03291 * @} 03292 */ 03293 03294 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions 03295 * @brief Peripheral Control functions 03296 * 03297 @verbatim 03298 ============================================================================== 03299 ##### Peripheral Control functions ##### 03300 ============================================================================== 03301 [..] 03302 This section provides functions allowing to: 03303 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. 03304 (+) Configure External Clock source. 03305 (+) Configure Complementary channels, break features and dead time. 03306 (+) Configure Master and the Slave synchronization. 03307 (+) Configure the DMA Burst Mode. 03308 03309 @endverbatim 03310 * @{ 03311 */ 03312 03313 /** 03314 * @brief Initializes the TIM Output Compare Channels according to the specified 03315 * parameters in the TIM_OC_InitTypeDef. 03316 * @param htim TIM Output Compare handle 03317 * @param sConfig TIM Output Compare configuration structure 03318 * @param Channel TIM Channels to configure 03319 * This parameter can be one of the following values: 03320 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 03321 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 03322 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 03323 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 03324 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 03325 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 03326 * @retval HAL status 03327 */ 03328 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, 03329 TIM_OC_InitTypeDef *sConfig, 03330 uint32_t Channel) 03331 { 03332 /* Check the parameters */ 03333 assert_param(IS_TIM_CHANNELS(Channel)); 03334 assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); 03335 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); 03336 03337 /* Process Locked */ 03338 __HAL_LOCK(htim); 03339 03340 htim->State = HAL_TIM_STATE_BUSY; 03341 03342 switch (Channel) 03343 { 03344 case TIM_CHANNEL_1: 03345 { 03346 /* Check the parameters */ 03347 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 03348 03349 /* Configure the TIM Channel 1 in Output Compare */ 03350 TIM_OC1_SetConfig(htim->Instance, sConfig); 03351 break; 03352 } 03353 03354 case TIM_CHANNEL_2: 03355 { 03356 /* Check the parameters */ 03357 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 03358 03359 /* Configure the TIM Channel 2 in Output Compare */ 03360 TIM_OC2_SetConfig(htim->Instance, sConfig); 03361 break; 03362 } 03363 03364 case TIM_CHANNEL_3: 03365 { 03366 /* Check the parameters */ 03367 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); 03368 03369 /* Configure the TIM Channel 3 in Output Compare */ 03370 TIM_OC3_SetConfig(htim->Instance, sConfig); 03371 break; 03372 } 03373 03374 case TIM_CHANNEL_4: 03375 { 03376 /* Check the parameters */ 03377 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); 03378 03379 /* Configure the TIM Channel 4 in Output Compare */ 03380 TIM_OC4_SetConfig(htim->Instance, sConfig); 03381 break; 03382 } 03383 03384 case TIM_CHANNEL_5: 03385 { 03386 /* Check the parameters */ 03387 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); 03388 03389 /* Configure the TIM Channel 5 in Output Compare */ 03390 TIM_OC5_SetConfig(htim->Instance, sConfig); 03391 break; 03392 } 03393 03394 case TIM_CHANNEL_6: 03395 { 03396 /* Check the parameters */ 03397 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); 03398 03399 /* Configure the TIM Channel 6 in Output Compare */ 03400 TIM_OC6_SetConfig(htim->Instance, sConfig); 03401 break; 03402 } 03403 03404 default: 03405 break; 03406 } 03407 03408 htim->State = HAL_TIM_STATE_READY; 03409 03410 __HAL_UNLOCK(htim); 03411 03412 return HAL_OK; 03413 } 03414 03415 /** 03416 * @brief Initializes the TIM Input Capture Channels according to the specified 03417 * parameters in the TIM_IC_InitTypeDef. 03418 * @param htim TIM IC handle 03419 * @param sConfig TIM Input Capture configuration structure 03420 * @param Channel TIM Channel to configure 03421 * This parameter can be one of the following values: 03422 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 03423 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 03424 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 03425 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 03426 * @retval HAL status 03427 */ 03428 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) 03429 { 03430 /* Check the parameters */ 03431 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 03432 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); 03433 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); 03434 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); 03435 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); 03436 03437 /* Process Locked */ 03438 __HAL_LOCK(htim); 03439 03440 htim->State = HAL_TIM_STATE_BUSY; 03441 03442 if (Channel == TIM_CHANNEL_1) 03443 { 03444 /* TI1 Configuration */ 03445 TIM_TI1_SetConfig(htim->Instance, 03446 sConfig->ICPolarity, 03447 sConfig->ICSelection, 03448 sConfig->ICFilter); 03449 03450 /* Reset the IC1PSC Bits */ 03451 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; 03452 03453 /* Set the IC1PSC value */ 03454 htim->Instance->CCMR1 |= sConfig->ICPrescaler; 03455 } 03456 else if (Channel == TIM_CHANNEL_2) 03457 { 03458 /* TI2 Configuration */ 03459 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 03460 03461 TIM_TI2_SetConfig(htim->Instance, 03462 sConfig->ICPolarity, 03463 sConfig->ICSelection, 03464 sConfig->ICFilter); 03465 03466 /* Reset the IC2PSC Bits */ 03467 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; 03468 03469 /* Set the IC2PSC value */ 03470 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); 03471 } 03472 else if (Channel == TIM_CHANNEL_3) 03473 { 03474 /* TI3 Configuration */ 03475 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); 03476 03477 TIM_TI3_SetConfig(htim->Instance, 03478 sConfig->ICPolarity, 03479 sConfig->ICSelection, 03480 sConfig->ICFilter); 03481 03482 /* Reset the IC3PSC Bits */ 03483 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; 03484 03485 /* Set the IC3PSC value */ 03486 htim->Instance->CCMR2 |= sConfig->ICPrescaler; 03487 } 03488 else 03489 { 03490 /* TI4 Configuration */ 03491 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); 03492 03493 TIM_TI4_SetConfig(htim->Instance, 03494 sConfig->ICPolarity, 03495 sConfig->ICSelection, 03496 sConfig->ICFilter); 03497 03498 /* Reset the IC4PSC Bits */ 03499 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; 03500 03501 /* Set the IC4PSC value */ 03502 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); 03503 } 03504 03505 htim->State = HAL_TIM_STATE_READY; 03506 03507 __HAL_UNLOCK(htim); 03508 03509 return HAL_OK; 03510 } 03511 03512 /** 03513 * @brief Initializes the TIM PWM channels according to the specified 03514 * parameters in the TIM_OC_InitTypeDef. 03515 * @param htim TIM PWM handle 03516 * @param sConfig TIM PWM configuration structure 03517 * @param Channel TIM Channels to be configured 03518 * This parameter can be one of the following values: 03519 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 03520 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 03521 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 03522 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 03523 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 03524 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 03525 * @retval HAL status 03526 */ 03527 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, 03528 TIM_OC_InitTypeDef *sConfig, 03529 uint32_t Channel) 03530 { 03531 /* Check the parameters */ 03532 assert_param(IS_TIM_CHANNELS(Channel)); 03533 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); 03534 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); 03535 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); 03536 03537 /* Process Locked */ 03538 __HAL_LOCK(htim); 03539 03540 htim->State = HAL_TIM_STATE_BUSY; 03541 03542 switch (Channel) 03543 { 03544 case TIM_CHANNEL_1: 03545 { 03546 /* Check the parameters */ 03547 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 03548 03549 /* Configure the Channel 1 in PWM mode */ 03550 TIM_OC1_SetConfig(htim->Instance, sConfig); 03551 03552 /* Set the Preload enable bit for channel1 */ 03553 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 03554 03555 /* Configure the Output Fast mode */ 03556 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 03557 htim->Instance->CCMR1 |= sConfig->OCFastMode; 03558 break; 03559 } 03560 03561 case TIM_CHANNEL_2: 03562 { 03563 /* Check the parameters */ 03564 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 03565 03566 /* Configure the Channel 2 in PWM mode */ 03567 TIM_OC2_SetConfig(htim->Instance, sConfig); 03568 03569 /* Set the Preload enable bit for channel2 */ 03570 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 03571 03572 /* Configure the Output Fast mode */ 03573 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 03574 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 03575 break; 03576 } 03577 03578 case TIM_CHANNEL_3: 03579 { 03580 /* Check the parameters */ 03581 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); 03582 03583 /* Configure the Channel 3 in PWM mode */ 03584 TIM_OC3_SetConfig(htim->Instance, sConfig); 03585 03586 /* Set the Preload enable bit for channel3 */ 03587 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 03588 03589 /* Configure the Output Fast mode */ 03590 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 03591 htim->Instance->CCMR2 |= sConfig->OCFastMode; 03592 break; 03593 } 03594 03595 case TIM_CHANNEL_4: 03596 { 03597 /* Check the parameters */ 03598 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); 03599 03600 /* Configure the Channel 4 in PWM mode */ 03601 TIM_OC4_SetConfig(htim->Instance, sConfig); 03602 03603 /* Set the Preload enable bit for channel4 */ 03604 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 03605 03606 /* Configure the Output Fast mode */ 03607 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 03608 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 03609 break; 03610 } 03611 03612 case TIM_CHANNEL_5: 03613 { 03614 /* Check the parameters */ 03615 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); 03616 03617 /* Configure the Channel 5 in PWM mode */ 03618 TIM_OC5_SetConfig(htim->Instance, sConfig); 03619 03620 /* Set the Preload enable bit for channel5*/ 03621 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 03622 03623 /* Configure the Output Fast mode */ 03624 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 03625 htim->Instance->CCMR3 |= sConfig->OCFastMode; 03626 break; 03627 } 03628 03629 case TIM_CHANNEL_6: 03630 { 03631 /* Check the parameters */ 03632 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); 03633 03634 /* Configure the Channel 6 in PWM mode */ 03635 TIM_OC6_SetConfig(htim->Instance, sConfig); 03636 03637 /* Set the Preload enable bit for channel6 */ 03638 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 03639 03640 /* Configure the Output Fast mode */ 03641 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 03642 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 03643 break; 03644 } 03645 03646 default: 03647 break; 03648 } 03649 03650 htim->State = HAL_TIM_STATE_READY; 03651 03652 __HAL_UNLOCK(htim); 03653 03654 return HAL_OK; 03655 } 03656 03657 /** 03658 * @brief Initializes the TIM One Pulse Channels according to the specified 03659 * parameters in the TIM_OnePulse_InitTypeDef. 03660 * @param htim TIM One Pulse handle 03661 * @param sConfig TIM One Pulse configuration structure 03662 * @param OutputChannel TIM output channel to configure 03663 * This parameter can be one of the following values: 03664 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 03665 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 03666 * @param InputChannel TIM input Channel to configure 03667 * This parameter can be one of the following values: 03668 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 03669 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 03670 * @retval HAL status 03671 */ 03672 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel) 03673 { 03674 TIM_OC_InitTypeDef temp1; 03675 03676 /* Check the parameters */ 03677 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); 03678 assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); 03679 03680 if (OutputChannel != InputChannel) 03681 { 03682 /* Process Locked */ 03683 __HAL_LOCK(htim); 03684 03685 htim->State = HAL_TIM_STATE_BUSY; 03686 03687 /* Extract the Output compare configuration from sConfig structure */ 03688 temp1.OCMode = sConfig->OCMode; 03689 temp1.Pulse = sConfig->Pulse; 03690 temp1.OCPolarity = sConfig->OCPolarity; 03691 temp1.OCNPolarity = sConfig->OCNPolarity; 03692 temp1.OCIdleState = sConfig->OCIdleState; 03693 temp1.OCNIdleState = sConfig->OCNIdleState; 03694 03695 switch (OutputChannel) 03696 { 03697 case TIM_CHANNEL_1: 03698 { 03699 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 03700 03701 TIM_OC1_SetConfig(htim->Instance, &temp1); 03702 break; 03703 } 03704 case TIM_CHANNEL_2: 03705 { 03706 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 03707 03708 TIM_OC2_SetConfig(htim->Instance, &temp1); 03709 break; 03710 } 03711 default: 03712 break; 03713 } 03714 03715 switch (InputChannel) 03716 { 03717 case TIM_CHANNEL_1: 03718 { 03719 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 03720 03721 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, 03722 sConfig->ICSelection, sConfig->ICFilter); 03723 03724 /* Reset the IC1PSC Bits */ 03725 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; 03726 03727 /* Select the Trigger source */ 03728 htim->Instance->SMCR &= ~TIM_SMCR_TS; 03729 htim->Instance->SMCR |= TIM_TS_TI1FP1; 03730 03731 /* Select the Slave Mode */ 03732 htim->Instance->SMCR &= ~TIM_SMCR_SMS; 03733 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; 03734 break; 03735 } 03736 case TIM_CHANNEL_2: 03737 { 03738 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 03739 03740 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, 03741 sConfig->ICSelection, sConfig->ICFilter); 03742 03743 /* Reset the IC2PSC Bits */ 03744 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; 03745 03746 /* Select the Trigger source */ 03747 htim->Instance->SMCR &= ~TIM_SMCR_TS; 03748 htim->Instance->SMCR |= TIM_TS_TI2FP2; 03749 03750 /* Select the Slave Mode */ 03751 htim->Instance->SMCR &= ~TIM_SMCR_SMS; 03752 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; 03753 break; 03754 } 03755 03756 default: 03757 break; 03758 } 03759 03760 htim->State = HAL_TIM_STATE_READY; 03761 03762 __HAL_UNLOCK(htim); 03763 03764 return HAL_OK; 03765 } 03766 else 03767 { 03768 return HAL_ERROR; 03769 } 03770 } 03771 03772 /** 03773 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral 03774 * @param htim TIM handle 03775 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write 03776 * This parameter can be one of the following values: 03777 * @arg TIM_DMABASE_CR1 03778 * @arg TIM_DMABASE_CR2 03779 * @arg TIM_DMABASE_SMCR 03780 * @arg TIM_DMABASE_DIER 03781 * @arg TIM_DMABASE_SR 03782 * @arg TIM_DMABASE_EGR 03783 * @arg TIM_DMABASE_CCMR1 03784 * @arg TIM_DMABASE_CCMR2 03785 * @arg TIM_DMABASE_CCER 03786 * @arg TIM_DMABASE_CNT 03787 * @arg TIM_DMABASE_PSC 03788 * @arg TIM_DMABASE_ARR 03789 * @arg TIM_DMABASE_RCR 03790 * @arg TIM_DMABASE_CCR1 03791 * @arg TIM_DMABASE_CCR2 03792 * @arg TIM_DMABASE_CCR3 03793 * @arg TIM_DMABASE_CCR4 03794 * @arg TIM_DMABASE_BDTR 03795 * @arg TIM_DMABASE_DCR 03796 * @param BurstRequestSrc TIM DMA Request sources 03797 * This parameter can be one of the following values: 03798 * @arg TIM_DMA_UPDATE: TIM update Interrupt source 03799 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source 03800 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source 03801 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source 03802 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source 03803 * @arg TIM_DMA_COM: TIM Commutation DMA source 03804 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source 03805 * @param BurstBuffer The Buffer address. 03806 * @param BurstLength DMA Burst length. This parameter can be one value 03807 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. 03808 * @retval HAL status 03809 */ 03810 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, 03811 uint32_t *BurstBuffer, uint32_t BurstLength) 03812 { 03813 /* Check the parameters */ 03814 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); 03815 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); 03816 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); 03817 assert_param(IS_TIM_DMA_LENGTH(BurstLength)); 03818 03819 if ((htim->State == HAL_TIM_STATE_BUSY)) 03820 { 03821 return HAL_BUSY; 03822 } 03823 else if ((htim->State == HAL_TIM_STATE_READY)) 03824 { 03825 if ((BurstBuffer == NULL) && (BurstLength > 0U)) 03826 { 03827 return HAL_ERROR; 03828 } 03829 else 03830 { 03831 htim->State = HAL_TIM_STATE_BUSY; 03832 } 03833 } 03834 else 03835 { 03836 /* nothing to do */ 03837 } 03838 switch (BurstRequestSrc) 03839 { 03840 case TIM_DMA_UPDATE: 03841 { 03842 /* Set the DMA Period elapsed callback */ 03843 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; 03844 03845 /* Set the DMA error callback */ 03846 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; 03847 03848 /* Enable the DMA channel */ 03849 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) 03850 { 03851 return HAL_ERROR; 03852 } 03853 break; 03854 } 03855 case TIM_DMA_CC1: 03856 { 03857 /* Set the DMA Period elapsed callback */ 03858 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; 03859 03860 /* Set the DMA error callback */ 03861 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 03862 03863 /* Enable the DMA channel */ 03864 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) 03865 { 03866 return HAL_ERROR; 03867 } 03868 break; 03869 } 03870 case TIM_DMA_CC2: 03871 { 03872 /* Set the DMA Period elapsed callback */ 03873 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; 03874 03875 /* Set the DMA error callback */ 03876 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 03877 03878 /* Enable the DMA channel */ 03879 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) 03880 { 03881 return HAL_ERROR; 03882 } 03883 break; 03884 } 03885 case TIM_DMA_CC3: 03886 { 03887 /* Set the DMA Period elapsed callback */ 03888 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; 03889 03890 /* Set the DMA error callback */ 03891 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 03892 03893 /* Enable the DMA channel */ 03894 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) 03895 { 03896 return HAL_ERROR; 03897 } 03898 break; 03899 } 03900 case TIM_DMA_CC4: 03901 { 03902 /* Set the DMA Period elapsed callback */ 03903 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; 03904 03905 /* Set the DMA error callback */ 03906 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; 03907 03908 /* Enable the DMA channel */ 03909 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) 03910 { 03911 return HAL_ERROR; 03912 } 03913 break; 03914 } 03915 case TIM_DMA_COM: 03916 { 03917 /* Set the DMA Period elapsed callback */ 03918 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; 03919 03920 /* Set the DMA error callback */ 03921 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; 03922 03923 /* Enable the DMA channel */ 03924 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) 03925 { 03926 return HAL_ERROR; 03927 } 03928 break; 03929 } 03930 case TIM_DMA_TRIGGER: 03931 { 03932 /* Set the DMA Period elapsed callback */ 03933 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; 03934 03935 /* Set the DMA error callback */ 03936 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; 03937 03938 /* Enable the DMA channel */ 03939 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) 03940 { 03941 return HAL_ERROR; 03942 } 03943 break; 03944 } 03945 default: 03946 break; 03947 } 03948 /* configure the DMA Burst Mode */ 03949 htim->Instance->DCR = (BurstBaseAddress | BurstLength); 03950 03951 /* Enable the TIM DMA Request */ 03952 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); 03953 03954 htim->State = HAL_TIM_STATE_READY; 03955 03956 /* Return function status */ 03957 return HAL_OK; 03958 } 03959 03960 /** 03961 * @brief Stops the TIM DMA Burst mode 03962 * @param htim TIM handle 03963 * @param BurstRequestSrc TIM DMA Request sources to disable 03964 * @retval HAL status 03965 */ 03966 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) 03967 { 03968 HAL_StatusTypeDef status = HAL_OK; 03969 /* Check the parameters */ 03970 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); 03971 03972 /* Abort the DMA transfer (at least disable the DMA channel) */ 03973 switch (BurstRequestSrc) 03974 { 03975 case TIM_DMA_UPDATE: 03976 { 03977 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); 03978 break; 03979 } 03980 case TIM_DMA_CC1: 03981 { 03982 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); 03983 break; 03984 } 03985 case TIM_DMA_CC2: 03986 { 03987 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); 03988 break; 03989 } 03990 case TIM_DMA_CC3: 03991 { 03992 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); 03993 break; 03994 } 03995 case TIM_DMA_CC4: 03996 { 03997 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); 03998 break; 03999 } 04000 case TIM_DMA_COM: 04001 { 04002 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); 04003 break; 04004 } 04005 case TIM_DMA_TRIGGER: 04006 { 04007 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); 04008 break; 04009 } 04010 default: 04011 break; 04012 } 04013 04014 if (HAL_OK == status) 04015 { 04016 /* Disable the TIM Update DMA request */ 04017 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); 04018 } 04019 04020 /* Return function status */ 04021 return status; 04022 } 04023 04024 /** 04025 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory 04026 * @param htim TIM handle 04027 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read 04028 * This parameter can be one of the following values: 04029 * @arg TIM_DMABASE_CR1 04030 * @arg TIM_DMABASE_CR2 04031 * @arg TIM_DMABASE_SMCR 04032 * @arg TIM_DMABASE_DIER 04033 * @arg TIM_DMABASE_SR 04034 * @arg TIM_DMABASE_EGR 04035 * @arg TIM_DMABASE_CCMR1 04036 * @arg TIM_DMABASE_CCMR2 04037 * @arg TIM_DMABASE_CCER 04038 * @arg TIM_DMABASE_CNT 04039 * @arg TIM_DMABASE_PSC 04040 * @arg TIM_DMABASE_ARR 04041 * @arg TIM_DMABASE_RCR 04042 * @arg TIM_DMABASE_CCR1 04043 * @arg TIM_DMABASE_CCR2 04044 * @arg TIM_DMABASE_CCR3 04045 * @arg TIM_DMABASE_CCR4 04046 * @arg TIM_DMABASE_BDTR 04047 * @arg TIM_DMABASE_DCR 04048 * @param BurstRequestSrc TIM DMA Request sources 04049 * This parameter can be one of the following values: 04050 * @arg TIM_DMA_UPDATE: TIM update Interrupt source 04051 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source 04052 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source 04053 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source 04054 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source 04055 * @arg TIM_DMA_COM: TIM Commutation DMA source 04056 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source 04057 * @param BurstBuffer The Buffer address. 04058 * @param BurstLength DMA Burst length. This parameter can be one value 04059 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. 04060 * @retval HAL status 04061 */ 04062 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, 04063 uint32_t *BurstBuffer, uint32_t BurstLength) 04064 { 04065 /* Check the parameters */ 04066 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); 04067 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); 04068 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); 04069 assert_param(IS_TIM_DMA_LENGTH(BurstLength)); 04070 04071 if ((htim->State == HAL_TIM_STATE_BUSY)) 04072 { 04073 return HAL_BUSY; 04074 } 04075 else if ((htim->State == HAL_TIM_STATE_READY)) 04076 { 04077 if ((BurstBuffer == NULL) && (BurstLength > 0U)) 04078 { 04079 return HAL_ERROR; 04080 } 04081 else 04082 { 04083 htim->State = HAL_TIM_STATE_BUSY; 04084 } 04085 } 04086 else 04087 { 04088 /* nothing to do */ 04089 } 04090 switch (BurstRequestSrc) 04091 { 04092 case TIM_DMA_UPDATE: 04093 { 04094 /* Set the DMA Period elapsed callback */ 04095 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; 04096 04097 /* Set the DMA error callback */ 04098 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; 04099 04100 /* Enable the DMA channel */ 04101 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) 04102 { 04103 return HAL_ERROR; 04104 } 04105 break; 04106 } 04107 case TIM_DMA_CC1: 04108 { 04109 /* Set the DMA Period elapsed callback */ 04110 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; 04111 04112 /* Set the DMA error callback */ 04113 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 04114 04115 /* Enable the DMA channel */ 04116 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) 04117 { 04118 return HAL_ERROR; 04119 } 04120 break; 04121 } 04122 case TIM_DMA_CC2: 04123 { 04124 /* Set the DMA Period elapsed callback */ 04125 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; 04126 04127 /* Set the DMA error callback */ 04128 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 04129 04130 /* Enable the DMA channel */ 04131 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) 04132 { 04133 return HAL_ERROR; 04134 } 04135 break; 04136 } 04137 case TIM_DMA_CC3: 04138 { 04139 /* Set the DMA Period elapsed callback */ 04140 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; 04141 04142 /* Set the DMA error callback */ 04143 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 04144 04145 /* Enable the DMA channel */ 04146 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) 04147 { 04148 return HAL_ERROR; 04149 } 04150 break; 04151 } 04152 case TIM_DMA_CC4: 04153 { 04154 /* Set the DMA Period elapsed callback */ 04155 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; 04156 04157 /* Set the DMA error callback */ 04158 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; 04159 04160 /* Enable the DMA channel */ 04161 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) 04162 { 04163 return HAL_ERROR; 04164 } 04165 break; 04166 } 04167 case TIM_DMA_COM: 04168 { 04169 /* Set the DMA Period elapsed callback */ 04170 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; 04171 04172 /* Set the DMA error callback */ 04173 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; 04174 04175 /* Enable the DMA channel */ 04176 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) 04177 { 04178 return HAL_ERROR; 04179 } 04180 break; 04181 } 04182 case TIM_DMA_TRIGGER: 04183 { 04184 /* Set the DMA Period elapsed callback */ 04185 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; 04186 04187 /* Set the DMA error callback */ 04188 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; 04189 04190 /* Enable the DMA channel */ 04191 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) 04192 { 04193 return HAL_ERROR; 04194 } 04195 break; 04196 } 04197 default: 04198 break; 04199 } 04200 04201 /* configure the DMA Burst Mode */ 04202 htim->Instance->DCR = (BurstBaseAddress | BurstLength); 04203 04204 /* Enable the TIM DMA Request */ 04205 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); 04206 04207 htim->State = HAL_TIM_STATE_READY; 04208 04209 /* Return function status */ 04210 return HAL_OK; 04211 } 04212 04213 /** 04214 * @brief Stop the DMA burst reading 04215 * @param htim TIM handle 04216 * @param BurstRequestSrc TIM DMA Request sources to disable. 04217 * @retval HAL status 04218 */ 04219 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) 04220 { 04221 HAL_StatusTypeDef status = HAL_OK; 04222 /* Check the parameters */ 04223 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); 04224 04225 /* Abort the DMA transfer (at least disable the DMA channel) */ 04226 switch (BurstRequestSrc) 04227 { 04228 case TIM_DMA_UPDATE: 04229 { 04230 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); 04231 break; 04232 } 04233 case TIM_DMA_CC1: 04234 { 04235 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); 04236 break; 04237 } 04238 case TIM_DMA_CC2: 04239 { 04240 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); 04241 break; 04242 } 04243 case TIM_DMA_CC3: 04244 { 04245 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); 04246 break; 04247 } 04248 case TIM_DMA_CC4: 04249 { 04250 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); 04251 break; 04252 } 04253 case TIM_DMA_COM: 04254 { 04255 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); 04256 break; 04257 } 04258 case TIM_DMA_TRIGGER: 04259 { 04260 status = HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); 04261 break; 04262 } 04263 default: 04264 break; 04265 } 04266 04267 if (HAL_OK == status) 04268 { 04269 /* Disable the TIM Update DMA request */ 04270 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); 04271 } 04272 04273 /* Return function status */ 04274 return status; 04275 } 04276 04277 /** 04278 * @brief Generate a software event 04279 * @param htim TIM handle 04280 * @param EventSource specifies the event source. 04281 * This parameter can be one of the following values: 04282 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source 04283 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source 04284 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source 04285 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source 04286 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source 04287 * @arg TIM_EVENTSOURCE_COM: Timer COM event source 04288 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source 04289 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source 04290 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source 04291 * @note Basic timers can only generate an update event. 04292 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. 04293 * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant 04294 * only for timer instances supporting break input(s). 04295 * @retval HAL status 04296 */ 04297 04298 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) 04299 { 04300 /* Check the parameters */ 04301 assert_param(IS_TIM_INSTANCE(htim->Instance)); 04302 assert_param(IS_TIM_EVENT_SOURCE(EventSource)); 04303 04304 /* Process Locked */ 04305 __HAL_LOCK(htim); 04306 04307 /* Change the TIM state */ 04308 htim->State = HAL_TIM_STATE_BUSY; 04309 04310 /* Set the event sources */ 04311 htim->Instance->EGR = EventSource; 04312 04313 /* Change the TIM state */ 04314 htim->State = HAL_TIM_STATE_READY; 04315 04316 __HAL_UNLOCK(htim); 04317 04318 /* Return function status */ 04319 return HAL_OK; 04320 } 04321 04322 /** 04323 * @brief Configures the OCRef clear feature 04324 * @param htim TIM handle 04325 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that 04326 * contains the OCREF clear feature and parameters for the TIM peripheral. 04327 * @param Channel specifies the TIM Channel 04328 * This parameter can be one of the following values: 04329 * @arg TIM_CHANNEL_1: TIM Channel 1 04330 * @arg TIM_CHANNEL_2: TIM Channel 2 04331 * @arg TIM_CHANNEL_3: TIM Channel 3 04332 * @arg TIM_CHANNEL_4: TIM Channel 4 04333 * @arg TIM_CHANNEL_5: TIM Channel 5 04334 * @arg TIM_CHANNEL_6: TIM Channel 6 04335 * @retval HAL status 04336 */ 04337 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, 04338 TIM_ClearInputConfigTypeDef *sClearInputConfig, 04339 uint32_t Channel) 04340 { 04341 /* Check the parameters */ 04342 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); 04343 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); 04344 04345 /* Process Locked */ 04346 __HAL_LOCK(htim); 04347 04348 htim->State = HAL_TIM_STATE_BUSY; 04349 04350 switch (sClearInputConfig->ClearInputSource) 04351 { 04352 case TIM_CLEARINPUTSOURCE_NONE: 04353 { 04354 /* Clear the OCREF clear selection bit and the the ETR Bits */ 04355 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); 04356 break; 04357 } 04358 case TIM_CLEARINPUTSOURCE_OCREFCLR: 04359 { 04360 /* Clear the OCREF clear selection bit */ 04361 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); 04362 } 04363 break; 04364 04365 case TIM_CLEARINPUTSOURCE_ETR: 04366 { 04367 /* Check the parameters */ 04368 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); 04369 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); 04370 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); 04371 04372 TIM_ETR_SetConfig(htim->Instance, 04373 sClearInputConfig->ClearInputPrescaler, 04374 sClearInputConfig->ClearInputPolarity, 04375 sClearInputConfig->ClearInputFilter); 04376 04377 /* Set the OCREF clear selection bit */ 04378 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); 04379 break; 04380 } 04381 04382 default: 04383 break; 04384 } 04385 04386 switch (Channel) 04387 { 04388 case TIM_CHANNEL_1: 04389 { 04390 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) 04391 { 04392 /* Enable the OCREF clear feature for Channel 1 */ 04393 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); 04394 } 04395 else 04396 { 04397 /* Disable the OCREF clear feature for Channel 1 */ 04398 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); 04399 } 04400 break; 04401 } 04402 case TIM_CHANNEL_2: 04403 { 04404 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) 04405 { 04406 /* Enable the OCREF clear feature for Channel 2 */ 04407 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); 04408 } 04409 else 04410 { 04411 /* Disable the OCREF clear feature for Channel 2 */ 04412 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); 04413 } 04414 break; 04415 } 04416 case TIM_CHANNEL_3: 04417 { 04418 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) 04419 { 04420 /* Enable the OCREF clear feature for Channel 3 */ 04421 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); 04422 } 04423 else 04424 { 04425 /* Disable the OCREF clear feature for Channel 3 */ 04426 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); 04427 } 04428 break; 04429 } 04430 case TIM_CHANNEL_4: 04431 { 04432 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) 04433 { 04434 /* Enable the OCREF clear feature for Channel 4 */ 04435 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); 04436 } 04437 else 04438 { 04439 /* Disable the OCREF clear feature for Channel 4 */ 04440 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); 04441 } 04442 break; 04443 } 04444 case TIM_CHANNEL_5: 04445 { 04446 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) 04447 { 04448 /* Enable the OCREF clear feature for Channel 5 */ 04449 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); 04450 } 04451 else 04452 { 04453 /* Disable the OCREF clear feature for Channel 5 */ 04454 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); 04455 } 04456 break; 04457 } 04458 case TIM_CHANNEL_6: 04459 { 04460 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) 04461 { 04462 /* Enable the OCREF clear feature for Channel 6 */ 04463 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); 04464 } 04465 else 04466 { 04467 /* Disable the OCREF clear feature for Channel 6 */ 04468 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); 04469 } 04470 break; 04471 } 04472 default: 04473 break; 04474 } 04475 04476 htim->State = HAL_TIM_STATE_READY; 04477 04478 __HAL_UNLOCK(htim); 04479 04480 return HAL_OK; 04481 } 04482 04483 /** 04484 * @brief Configures the clock source to be used 04485 * @param htim TIM handle 04486 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that 04487 * contains the clock source information for the TIM peripheral. 04488 * @retval HAL status 04489 */ 04490 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) 04491 { 04492 uint32_t tmpsmcr; 04493 04494 /* Process Locked */ 04495 __HAL_LOCK(htim); 04496 04497 htim->State = HAL_TIM_STATE_BUSY; 04498 04499 /* Check the parameters */ 04500 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); 04501 04502 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ 04503 tmpsmcr = htim->Instance->SMCR; 04504 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 04505 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 04506 htim->Instance->SMCR = tmpsmcr; 04507 04508 switch (sClockSourceConfig->ClockSource) 04509 { 04510 case TIM_CLOCKSOURCE_INTERNAL: 04511 { 04512 assert_param(IS_TIM_INSTANCE(htim->Instance)); 04513 /* Disable slave mode to clock the prescaler directly with the internal clock */ 04514 htim->Instance->SMCR &= ~TIM_SMCR_SMS; 04515 break; 04516 } 04517 04518 case TIM_CLOCKSOURCE_ETRMODE1: 04519 { 04520 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ 04521 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); 04522 04523 /* Check ETR input conditioning related parameters */ 04524 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); 04525 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); 04526 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); 04527 04528 /* Configure the ETR Clock source */ 04529 TIM_ETR_SetConfig(htim->Instance, 04530 sClockSourceConfig->ClockPrescaler, 04531 sClockSourceConfig->ClockPolarity, 04532 sClockSourceConfig->ClockFilter); 04533 /* Get the TIMx SMCR register value */ 04534 tmpsmcr = htim->Instance->SMCR; 04535 /* Reset the SMS and TS Bits */ 04536 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 04537 /* Select the External clock mode1 and the ETRF trigger */ 04538 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 04539 /* Write to TIMx SMCR */ 04540 htim->Instance->SMCR = tmpsmcr; 04541 break; 04542 } 04543 04544 case TIM_CLOCKSOURCE_ETRMODE2: 04545 { 04546 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ 04547 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); 04548 04549 /* Check ETR input conditioning related parameters */ 04550 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); 04551 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); 04552 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); 04553 04554 /* Configure the ETR Clock source */ 04555 TIM_ETR_SetConfig(htim->Instance, 04556 sClockSourceConfig->ClockPrescaler, 04557 sClockSourceConfig->ClockPolarity, 04558 sClockSourceConfig->ClockFilter); 04559 /* Enable the External clock mode2 */ 04560 htim->Instance->SMCR |= TIM_SMCR_ECE; 04561 break; 04562 } 04563 04564 case TIM_CLOCKSOURCE_TI1: 04565 { 04566 /* Check whether or not the timer instance supports external clock mode 1 */ 04567 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); 04568 04569 /* Check TI1 input conditioning related parameters */ 04570 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); 04571 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); 04572 04573 TIM_TI1_ConfigInputStage(htim->Instance, 04574 sClockSourceConfig->ClockPolarity, 04575 sClockSourceConfig->ClockFilter); 04576 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 04577 break; 04578 } 04579 04580 case TIM_CLOCKSOURCE_TI2: 04581 { 04582 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ 04583 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); 04584 04585 /* Check TI2 input conditioning related parameters */ 04586 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); 04587 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); 04588 04589 TIM_TI2_ConfigInputStage(htim->Instance, 04590 sClockSourceConfig->ClockPolarity, 04591 sClockSourceConfig->ClockFilter); 04592 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 04593 break; 04594 } 04595 04596 case TIM_CLOCKSOURCE_TI1ED: 04597 { 04598 /* Check whether or not the timer instance supports external clock mode 1 */ 04599 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); 04600 04601 /* Check TI1 input conditioning related parameters */ 04602 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); 04603 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); 04604 04605 TIM_TI1_ConfigInputStage(htim->Instance, 04606 sClockSourceConfig->ClockPolarity, 04607 sClockSourceConfig->ClockFilter); 04608 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 04609 break; 04610 } 04611 04612 case TIM_CLOCKSOURCE_ITR0: 04613 case TIM_CLOCKSOURCE_ITR1: 04614 case TIM_CLOCKSOURCE_ITR2: 04615 case TIM_CLOCKSOURCE_ITR3: 04616 { 04617 /* Check whether or not the timer instance supports internal trigger input */ 04618 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); 04619 04620 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 04621 break; 04622 } 04623 04624 default: 04625 break; 04626 } 04627 htim->State = HAL_TIM_STATE_READY; 04628 04629 __HAL_UNLOCK(htim); 04630 04631 return HAL_OK; 04632 } 04633 04634 /** 04635 * @brief Selects the signal connected to the TI1 input: direct from CH1_input 04636 * or a XOR combination between CH1_input, CH2_input & CH3_input 04637 * @param htim TIM handle. 04638 * @param TI1_Selection Indicate whether or not channel 1 is connected to the 04639 * output of a XOR gate. 04640 * This parameter can be one of the following values: 04641 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input 04642 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 04643 * pins are connected to the TI1 input (XOR combination) 04644 * @retval HAL status 04645 */ 04646 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) 04647 { 04648 uint32_t tmpcr2; 04649 04650 /* Check the parameters */ 04651 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); 04652 assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); 04653 04654 /* Get the TIMx CR2 register value */ 04655 tmpcr2 = htim->Instance->CR2; 04656 04657 /* Reset the TI1 selection */ 04658 tmpcr2 &= ~TIM_CR2_TI1S; 04659 04660 /* Set the TI1 selection */ 04661 tmpcr2 |= TI1_Selection; 04662 04663 /* Write to TIMxCR2 */ 04664 htim->Instance->CR2 = tmpcr2; 04665 04666 return HAL_OK; 04667 } 04668 04669 /** 04670 * @brief Configures the TIM in Slave mode 04671 * @param htim TIM handle. 04672 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that 04673 * contains the selected trigger (internal trigger input, filtered 04674 * timer input or external trigger input) and the Slave mode 04675 * (Disable, Reset, Gated, Trigger, External clock mode 1). 04676 * @retval HAL status 04677 */ 04678 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) 04679 { 04680 /* Check the parameters */ 04681 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); 04682 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); 04683 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); 04684 04685 __HAL_LOCK(htim); 04686 04687 htim->State = HAL_TIM_STATE_BUSY; 04688 04689 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); 04690 04691 /* Disable Trigger Interrupt */ 04692 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); 04693 04694 /* Disable Trigger DMA request */ 04695 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); 04696 04697 htim->State = HAL_TIM_STATE_READY; 04698 04699 __HAL_UNLOCK(htim); 04700 04701 return HAL_OK; 04702 } 04703 04704 /** 04705 * @brief Configures the TIM in Slave mode in interrupt mode 04706 * @param htim TIM handle. 04707 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that 04708 * contains the selected trigger (internal trigger input, filtered 04709 * timer input or external trigger input) and the Slave mode 04710 * (Disable, Reset, Gated, Trigger, External clock mode 1). 04711 * @retval HAL status 04712 */ 04713 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, 04714 TIM_SlaveConfigTypeDef *sSlaveConfig) 04715 { 04716 /* Check the parameters */ 04717 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); 04718 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); 04719 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); 04720 04721 __HAL_LOCK(htim); 04722 04723 htim->State = HAL_TIM_STATE_BUSY; 04724 04725 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); 04726 04727 /* Enable Trigger Interrupt */ 04728 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); 04729 04730 /* Disable Trigger DMA request */ 04731 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); 04732 04733 htim->State = HAL_TIM_STATE_READY; 04734 04735 __HAL_UNLOCK(htim); 04736 04737 return HAL_OK; 04738 } 04739 04740 /** 04741 * @brief Read the captured value from Capture Compare unit 04742 * @param htim TIM handle. 04743 * @param Channel TIM Channels to be enabled 04744 * This parameter can be one of the following values: 04745 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 04746 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 04747 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 04748 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 04749 * @retval Captured value 04750 */ 04751 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) 04752 { 04753 uint32_t tmpreg = 0U; 04754 04755 __HAL_LOCK(htim); 04756 04757 switch (Channel) 04758 { 04759 case TIM_CHANNEL_1: 04760 { 04761 /* Check the parameters */ 04762 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 04763 04764 /* Return the capture 1 value */ 04765 tmpreg = htim->Instance->CCR1; 04766 04767 break; 04768 } 04769 case TIM_CHANNEL_2: 04770 { 04771 /* Check the parameters */ 04772 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 04773 04774 /* Return the capture 2 value */ 04775 tmpreg = htim->Instance->CCR2; 04776 04777 break; 04778 } 04779 04780 case TIM_CHANNEL_3: 04781 { 04782 /* Check the parameters */ 04783 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); 04784 04785 /* Return the capture 3 value */ 04786 tmpreg = htim->Instance->CCR3; 04787 04788 break; 04789 } 04790 04791 case TIM_CHANNEL_4: 04792 { 04793 /* Check the parameters */ 04794 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); 04795 04796 /* Return the capture 4 value */ 04797 tmpreg = htim->Instance->CCR4; 04798 04799 break; 04800 } 04801 04802 default: 04803 break; 04804 } 04805 04806 __HAL_UNLOCK(htim); 04807 return tmpreg; 04808 } 04809 04810 /** 04811 * @} 04812 */ 04813 04814 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 04815 * @brief TIM Callbacks functions 04816 * 04817 @verbatim 04818 ============================================================================== 04819 ##### TIM Callbacks functions ##### 04820 ============================================================================== 04821 [..] 04822 This section provides TIM callback functions: 04823 (+) Timer Period elapsed callback 04824 (+) Timer Output Compare callback 04825 (+) Timer Input capture callback 04826 (+) Timer Trigger callback 04827 (+) Timer Error callback 04828 04829 @endverbatim 04830 * @{ 04831 */ 04832 04833 /** 04834 * @brief Period elapsed callback in non-blocking mode 04835 * @param htim TIM handle 04836 * @retval None 04837 */ 04838 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) 04839 { 04840 /* Prevent unused argument(s) compilation warning */ 04841 UNUSED(htim); 04842 04843 /* NOTE : This function should not be modified, when the callback is needed, 04844 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file 04845 */ 04846 04847 } 04848 /** 04849 * @brief Output Compare callback in non-blocking mode 04850 * @param htim TIM OC handle 04851 * @retval None 04852 */ 04853 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) 04854 { 04855 /* Prevent unused argument(s) compilation warning */ 04856 UNUSED(htim); 04857 04858 /* NOTE : This function should not be modified, when the callback is needed, 04859 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file 04860 */ 04861 } 04862 /** 04863 * @brief Input Capture callback in non-blocking mode 04864 * @param htim TIM IC handle 04865 * @retval None 04866 */ 04867 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) 04868 { 04869 /* Prevent unused argument(s) compilation warning */ 04870 UNUSED(htim); 04871 04872 /* NOTE : This function should not be modified, when the callback is needed, 04873 the HAL_TIM_IC_CaptureCallback could be implemented in the user file 04874 */ 04875 } 04876 04877 /** 04878 * @brief PWM Pulse finished callback in non-blocking mode 04879 * @param htim TIM handle 04880 * @retval None 04881 */ 04882 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) 04883 { 04884 /* Prevent unused argument(s) compilation warning */ 04885 UNUSED(htim); 04886 04887 /* NOTE : This function should not be modified, when the callback is needed, 04888 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file 04889 */ 04890 } 04891 04892 /** 04893 * @brief Hall Trigger detection callback in non-blocking mode 04894 * @param htim TIM handle 04895 * @retval None 04896 */ 04897 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) 04898 { 04899 /* Prevent unused argument(s) compilation warning */ 04900 UNUSED(htim); 04901 04902 /* NOTE : This function should not be modified, when the callback is needed, 04903 the HAL_TIM_TriggerCallback could be implemented in the user file 04904 */ 04905 } 04906 04907 /** 04908 * @brief Timer error callback in non-blocking mode 04909 * @param htim TIM handle 04910 * @retval None 04911 */ 04912 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) 04913 { 04914 /* Prevent unused argument(s) compilation warning */ 04915 UNUSED(htim); 04916 04917 /* NOTE : This function should not be modified, when the callback is needed, 04918 the HAL_TIM_ErrorCallback could be implemented in the user file 04919 */ 04920 } 04921 04922 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 04923 /** 04924 * @brief Register a User TIM callback to be used instead of the weak predefined callback 04925 * @param htim tim handle 04926 * @param CallbackID ID of the callback to be registered 04927 * This parameter can be one of the following values: 04928 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID 04929 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID 04930 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID 04931 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID 04932 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID 04933 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID 04934 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID 04935 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID 04936 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID 04937 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID 04938 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID 04939 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID 04940 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID 04941 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID 04942 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID 04943 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID 04944 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID 04945 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID 04946 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID 04947 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID 04948 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID 04949 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID 04950 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID 04951 * @param pCallback pointer to the callback function 04952 * @retval status 04953 */ 04954 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback) 04955 { 04956 HAL_StatusTypeDef status = HAL_OK; 04957 04958 if (pCallback == NULL) 04959 { 04960 return HAL_ERROR; 04961 } 04962 /* Process locked */ 04963 __HAL_LOCK(htim); 04964 04965 if (htim->State == HAL_TIM_STATE_READY) 04966 { 04967 switch (CallbackID) 04968 { 04969 case HAL_TIM_BASE_MSPINIT_CB_ID : 04970 htim->Base_MspInitCallback = pCallback; 04971 break; 04972 04973 case HAL_TIM_BASE_MSPDEINIT_CB_ID : 04974 htim->Base_MspDeInitCallback = pCallback; 04975 break; 04976 04977 case HAL_TIM_IC_MSPINIT_CB_ID : 04978 htim->IC_MspInitCallback = pCallback; 04979 break; 04980 04981 case HAL_TIM_IC_MSPDEINIT_CB_ID : 04982 htim->IC_MspDeInitCallback = pCallback; 04983 break; 04984 04985 case HAL_TIM_OC_MSPINIT_CB_ID : 04986 htim->OC_MspInitCallback = pCallback; 04987 break; 04988 04989 case HAL_TIM_OC_MSPDEINIT_CB_ID : 04990 htim->OC_MspDeInitCallback = pCallback; 04991 break; 04992 04993 case HAL_TIM_PWM_MSPINIT_CB_ID : 04994 htim->PWM_MspInitCallback = pCallback; 04995 break; 04996 04997 case HAL_TIM_PWM_MSPDEINIT_CB_ID : 04998 htim->PWM_MspDeInitCallback = pCallback; 04999 break; 05000 05001 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : 05002 htim->OnePulse_MspInitCallback = pCallback; 05003 break; 05004 05005 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : 05006 htim->OnePulse_MspDeInitCallback = pCallback; 05007 break; 05008 05009 case HAL_TIM_ENCODER_MSPINIT_CB_ID : 05010 htim->Encoder_MspInitCallback = pCallback; 05011 break; 05012 05013 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : 05014 htim->Encoder_MspDeInitCallback = pCallback; 05015 break; 05016 05017 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : 05018 htim->HallSensor_MspInitCallback = pCallback; 05019 break; 05020 05021 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : 05022 htim->HallSensor_MspDeInitCallback = pCallback; 05023 break; 05024 05025 case HAL_TIM_PERIOD_ELAPSED_CB_ID : 05026 htim->PeriodElapsedCallback = pCallback; 05027 break; 05028 05029 case HAL_TIM_TRIGGER_CB_ID : 05030 htim->TriggerCallback = pCallback; 05031 break; 05032 05033 case HAL_TIM_IC_CAPTURE_CB_ID : 05034 htim->IC_CaptureCallback = pCallback; 05035 break; 05036 05037 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : 05038 htim->OC_DelayElapsedCallback = pCallback; 05039 break; 05040 05041 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : 05042 htim->PWM_PulseFinishedCallback = pCallback; 05043 break; 05044 05045 case HAL_TIM_ERROR_CB_ID : 05046 htim->ErrorCallback = pCallback; 05047 break; 05048 05049 case HAL_TIM_COMMUTATION_CB_ID : 05050 htim->CommutationCallback = pCallback; 05051 break; 05052 05053 case HAL_TIM_BREAK_CB_ID : 05054 htim->BreakCallback = pCallback; 05055 break; 05056 05057 case HAL_TIM_BREAK2_CB_ID : 05058 htim->Break2Callback = pCallback; 05059 break; 05060 05061 default : 05062 /* Return error status */ 05063 status = HAL_ERROR; 05064 break; 05065 } 05066 } 05067 else if (htim->State == HAL_TIM_STATE_RESET) 05068 { 05069 switch (CallbackID) 05070 { 05071 case HAL_TIM_BASE_MSPINIT_CB_ID : 05072 htim->Base_MspInitCallback = pCallback; 05073 break; 05074 05075 case HAL_TIM_BASE_MSPDEINIT_CB_ID : 05076 htim->Base_MspDeInitCallback = pCallback; 05077 break; 05078 05079 case HAL_TIM_IC_MSPINIT_CB_ID : 05080 htim->IC_MspInitCallback = pCallback; 05081 break; 05082 05083 case HAL_TIM_IC_MSPDEINIT_CB_ID : 05084 htim->IC_MspDeInitCallback = pCallback; 05085 break; 05086 05087 case HAL_TIM_OC_MSPINIT_CB_ID : 05088 htim->OC_MspInitCallback = pCallback; 05089 break; 05090 05091 case HAL_TIM_OC_MSPDEINIT_CB_ID : 05092 htim->OC_MspDeInitCallback = pCallback; 05093 break; 05094 05095 case HAL_TIM_PWM_MSPINIT_CB_ID : 05096 htim->PWM_MspInitCallback = pCallback; 05097 break; 05098 05099 case HAL_TIM_PWM_MSPDEINIT_CB_ID : 05100 htim->PWM_MspDeInitCallback = pCallback; 05101 break; 05102 05103 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : 05104 htim->OnePulse_MspInitCallback = pCallback; 05105 break; 05106 05107 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : 05108 htim->OnePulse_MspDeInitCallback = pCallback; 05109 break; 05110 05111 case HAL_TIM_ENCODER_MSPINIT_CB_ID : 05112 htim->Encoder_MspInitCallback = pCallback; 05113 break; 05114 05115 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : 05116 htim->Encoder_MspDeInitCallback = pCallback; 05117 break; 05118 05119 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : 05120 htim->HallSensor_MspInitCallback = pCallback; 05121 break; 05122 05123 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : 05124 htim->HallSensor_MspDeInitCallback = pCallback; 05125 break; 05126 05127 default : 05128 /* Return error status */ 05129 status = HAL_ERROR; 05130 break; 05131 } 05132 } 05133 else 05134 { 05135 /* Return error status */ 05136 status = HAL_ERROR; 05137 } 05138 05139 /* Release Lock */ 05140 __HAL_UNLOCK(htim); 05141 05142 return status; 05143 } 05144 05145 /** 05146 * @brief Unregister a TIM callback 05147 * TIM callback is redirected to the weak predefined callback 05148 * @param htim tim handle 05149 * @param CallbackID ID of the callback to be unregistered 05150 * This parameter can be one of the following values: 05151 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID 05152 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID 05153 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID 05154 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID 05155 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID 05156 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID 05157 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID 05158 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID 05159 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID 05160 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID 05161 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID 05162 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID 05163 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID 05164 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID 05165 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID 05166 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID 05167 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID 05168 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID 05169 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID 05170 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID 05171 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID 05172 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID 05173 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID 05174 */ 05175 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) 05176 { 05177 HAL_StatusTypeDef status = HAL_OK; 05178 05179 /* Process locked */ 05180 __HAL_LOCK(htim); 05181 05182 if (htim->State == HAL_TIM_STATE_READY) 05183 { 05184 switch (CallbackID) 05185 { 05186 case HAL_TIM_BASE_MSPINIT_CB_ID : 05187 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ 05188 break; 05189 05190 case HAL_TIM_BASE_MSPDEINIT_CB_ID : 05191 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ 05192 break; 05193 05194 case HAL_TIM_IC_MSPINIT_CB_ID : 05195 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ 05196 break; 05197 05198 case HAL_TIM_IC_MSPDEINIT_CB_ID : 05199 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ 05200 break; 05201 05202 case HAL_TIM_OC_MSPINIT_CB_ID : 05203 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ 05204 break; 05205 05206 case HAL_TIM_OC_MSPDEINIT_CB_ID : 05207 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ 05208 break; 05209 05210 case HAL_TIM_PWM_MSPINIT_CB_ID : 05211 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ 05212 break; 05213 05214 case HAL_TIM_PWM_MSPDEINIT_CB_ID : 05215 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ 05216 break; 05217 05218 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : 05219 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ 05220 break; 05221 05222 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : 05223 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ 05224 break; 05225 05226 case HAL_TIM_ENCODER_MSPINIT_CB_ID : 05227 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ 05228 break; 05229 05230 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : 05231 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ 05232 break; 05233 05234 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : 05235 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ 05236 break; 05237 05238 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : 05239 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ 05240 break; 05241 05242 case HAL_TIM_PERIOD_ELAPSED_CB_ID : 05243 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ 05244 break; 05245 05246 case HAL_TIM_TRIGGER_CB_ID : 05247 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ 05248 break; 05249 05250 case HAL_TIM_IC_CAPTURE_CB_ID : 05251 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ 05252 break; 05253 05254 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : 05255 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ 05256 break; 05257 05258 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : 05259 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ 05260 break; 05261 05262 case HAL_TIM_ERROR_CB_ID : 05263 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ 05264 break; 05265 05266 case HAL_TIM_COMMUTATION_CB_ID : 05267 htim->CommutationCallback = HAL_TIMEx_CommutationCallback; /* Legacy weak Commutation Callback */ 05268 break; 05269 05270 case HAL_TIM_BREAK_CB_ID : 05271 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ 05272 break; 05273 05274 case HAL_TIM_BREAK2_CB_ID : 05275 htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */ 05276 break; 05277 05278 default : 05279 /* Return error status */ 05280 status = HAL_ERROR; 05281 break; 05282 } 05283 } 05284 else if (htim->State == HAL_TIM_STATE_RESET) 05285 { 05286 switch (CallbackID) 05287 { 05288 case HAL_TIM_BASE_MSPINIT_CB_ID : 05289 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ 05290 break; 05291 05292 case HAL_TIM_BASE_MSPDEINIT_CB_ID : 05293 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ 05294 break; 05295 05296 case HAL_TIM_IC_MSPINIT_CB_ID : 05297 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ 05298 break; 05299 05300 case HAL_TIM_IC_MSPDEINIT_CB_ID : 05301 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ 05302 break; 05303 05304 case HAL_TIM_OC_MSPINIT_CB_ID : 05305 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ 05306 break; 05307 05308 case HAL_TIM_OC_MSPDEINIT_CB_ID : 05309 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ 05310 break; 05311 05312 case HAL_TIM_PWM_MSPINIT_CB_ID : 05313 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ 05314 break; 05315 05316 case HAL_TIM_PWM_MSPDEINIT_CB_ID : 05317 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ 05318 break; 05319 05320 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : 05321 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ 05322 break; 05323 05324 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : 05325 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ 05326 break; 05327 05328 case HAL_TIM_ENCODER_MSPINIT_CB_ID : 05329 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ 05330 break; 05331 05332 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : 05333 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ 05334 break; 05335 05336 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : 05337 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ 05338 break; 05339 05340 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : 05341 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ 05342 break; 05343 05344 default : 05345 /* Return error status */ 05346 status = HAL_ERROR; 05347 break; 05348 } 05349 } 05350 else 05351 { 05352 /* Return error status */ 05353 status = HAL_ERROR; 05354 } 05355 05356 /* Release Lock */ 05357 __HAL_UNLOCK(htim); 05358 05359 return status; 05360 } 05361 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 05362 05363 /** 05364 * @} 05365 */ 05366 05367 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions 05368 * @brief Peripheral State functions 05369 * 05370 @verbatim 05371 ============================================================================== 05372 ##### Peripheral State functions ##### 05373 ============================================================================== 05374 [..] 05375 This subsection permits to get in run-time the status of the peripheral 05376 and the data flow. 05377 05378 @endverbatim 05379 * @{ 05380 */ 05381 05382 /** 05383 * @brief Return the TIM Base handle state. 05384 * @param htim TIM Base handle 05385 * @retval HAL state 05386 */ 05387 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) 05388 { 05389 return htim->State; 05390 } 05391 05392 /** 05393 * @brief Return the TIM OC handle state. 05394 * @param htim TIM Output Compare handle 05395 * @retval HAL state 05396 */ 05397 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) 05398 { 05399 return htim->State; 05400 } 05401 05402 /** 05403 * @brief Return the TIM PWM handle state. 05404 * @param htim TIM handle 05405 * @retval HAL state 05406 */ 05407 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) 05408 { 05409 return htim->State; 05410 } 05411 05412 /** 05413 * @brief Return the TIM Input Capture handle state. 05414 * @param htim TIM IC handle 05415 * @retval HAL state 05416 */ 05417 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) 05418 { 05419 return htim->State; 05420 } 05421 05422 /** 05423 * @brief Return the TIM One Pulse Mode handle state. 05424 * @param htim TIM OPM handle 05425 * @retval HAL state 05426 */ 05427 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) 05428 { 05429 return htim->State; 05430 } 05431 05432 /** 05433 * @brief Return the TIM Encoder Mode handle state. 05434 * @param htim TIM Encoder Interface handle 05435 * @retval HAL state 05436 */ 05437 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) 05438 { 05439 return htim->State; 05440 } 05441 05442 /** 05443 * @} 05444 */ 05445 05446 /** 05447 * @} 05448 */ 05449 05450 /** @defgroup TIM_Private_Functions TIM Private Functions 05451 * @{ 05452 */ 05453 05454 /** 05455 * @brief TIM DMA error callback 05456 * @param hdma pointer to DMA handle. 05457 * @retval None 05458 */ 05459 void TIM_DMAError(DMA_HandleTypeDef *hdma) 05460 { 05461 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 05462 05463 htim->State = HAL_TIM_STATE_READY; 05464 05465 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 05466 htim->ErrorCallback(htim); 05467 #else 05468 HAL_TIM_ErrorCallback(htim); 05469 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 05470 } 05471 05472 /** 05473 * @brief TIM DMA Delay Pulse complete callback. 05474 * @param hdma pointer to DMA handle. 05475 * @retval None 05476 */ 05477 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) 05478 { 05479 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 05480 05481 htim->State = HAL_TIM_STATE_READY; 05482 05483 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) 05484 { 05485 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 05486 } 05487 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) 05488 { 05489 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 05490 } 05491 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) 05492 { 05493 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 05494 } 05495 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) 05496 { 05497 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 05498 } 05499 else 05500 { 05501 /* nothing to do */ 05502 } 05503 05504 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 05505 htim->PWM_PulseFinishedCallback(htim); 05506 #else 05507 HAL_TIM_PWM_PulseFinishedCallback(htim); 05508 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 05509 05510 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 05511 } 05512 /** 05513 * @brief TIM DMA Capture complete callback. 05514 * @param hdma pointer to DMA handle. 05515 * @retval None 05516 */ 05517 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) 05518 { 05519 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 05520 05521 htim->State = HAL_TIM_STATE_READY; 05522 05523 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) 05524 { 05525 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 05526 } 05527 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) 05528 { 05529 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 05530 } 05531 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) 05532 { 05533 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 05534 } 05535 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) 05536 { 05537 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 05538 } 05539 else 05540 { 05541 /* nothing to do */ 05542 } 05543 05544 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 05545 htim->IC_CaptureCallback(htim); 05546 #else 05547 HAL_TIM_IC_CaptureCallback(htim); 05548 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 05549 05550 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 05551 } 05552 05553 /** 05554 * @brief TIM DMA Period Elapse complete callback. 05555 * @param hdma pointer to DMA handle. 05556 * @retval None 05557 */ 05558 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) 05559 { 05560 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 05561 05562 htim->State = HAL_TIM_STATE_READY; 05563 05564 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 05565 htim->PeriodElapsedCallback(htim); 05566 #else 05567 HAL_TIM_PeriodElapsedCallback(htim); 05568 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 05569 } 05570 05571 /** 05572 * @brief TIM DMA Trigger callback. 05573 * @param hdma pointer to DMA handle. 05574 * @retval None 05575 */ 05576 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) 05577 { 05578 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 05579 05580 htim->State = HAL_TIM_STATE_READY; 05581 05582 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 05583 htim->TriggerCallback(htim); 05584 #else 05585 HAL_TIM_TriggerCallback(htim); 05586 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 05587 } 05588 05589 /** 05590 * @brief Time Base configuration 05591 * @param TIMx TIM peripheral 05592 * @param Structure TIM Base configuration structure 05593 * @retval None 05594 */ 05595 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) 05596 { 05597 uint32_t tmpcr1; 05598 tmpcr1 = TIMx->CR1; 05599 05600 /* Set TIM Time Base Unit parameters ---------------------------------------*/ 05601 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 05602 { 05603 /* Select the Counter Mode */ 05604 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 05605 tmpcr1 |= Structure->CounterMode; 05606 } 05607 05608 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 05609 { 05610 /* Set the clock division */ 05611 tmpcr1 &= ~TIM_CR1_CKD; 05612 tmpcr1 |= (uint32_t)Structure->ClockDivision; 05613 } 05614 05615 /* Set the auto-reload preload */ 05616 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 05617 05618 TIMx->CR1 = tmpcr1; 05619 05620 /* Set the Autoreload value */ 05621 TIMx->ARR = (uint32_t)Structure->Period ; 05622 05623 /* Set the Prescaler value */ 05624 TIMx->PSC = Structure->Prescaler; 05625 05626 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 05627 { 05628 /* Set the Repetition Counter value */ 05629 TIMx->RCR = Structure->RepetitionCounter; 05630 } 05631 05632 /* Generate an update event to reload the Prescaler 05633 and the repetition counter (only for advanced timer) value immediately */ 05634 TIMx->EGR = TIM_EGR_UG; 05635 } 05636 05637 /** 05638 * @brief Timer Output Compare 1 configuration 05639 * @param TIMx to select the TIM peripheral 05640 * @param OC_Config The ouput configuration structure 05641 * @retval None 05642 */ 05643 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) 05644 { 05645 uint32_t tmpccmrx; 05646 uint32_t tmpccer; 05647 uint32_t tmpcr2; 05648 05649 /* Disable the Channel 1: Reset the CC1E Bit */ 05650 TIMx->CCER &= ~TIM_CCER_CC1E; 05651 05652 /* Get the TIMx CCER register value */ 05653 tmpccer = TIMx->CCER; 05654 /* Get the TIMx CR2 register value */ 05655 tmpcr2 = TIMx->CR2; 05656 05657 /* Get the TIMx CCMR1 register value */ 05658 tmpccmrx = TIMx->CCMR1; 05659 05660 /* Reset the Output Compare Mode Bits */ 05661 tmpccmrx &= ~TIM_CCMR1_OC1M; 05662 tmpccmrx &= ~TIM_CCMR1_CC1S; 05663 /* Select the Output Compare Mode */ 05664 tmpccmrx |= OC_Config->OCMode; 05665 05666 /* Reset the Output Polarity level */ 05667 tmpccer &= ~TIM_CCER_CC1P; 05668 /* Set the Output Compare Polarity */ 05669 tmpccer |= OC_Config->OCPolarity; 05670 05671 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 05672 { 05673 /* Check parameters */ 05674 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); 05675 05676 /* Reset the Output N Polarity level */ 05677 tmpccer &= ~TIM_CCER_CC1NP; 05678 /* Set the Output N Polarity */ 05679 tmpccer |= OC_Config->OCNPolarity; 05680 /* Reset the Output N State */ 05681 tmpccer &= ~TIM_CCER_CC1NE; 05682 } 05683 05684 if (IS_TIM_BREAK_INSTANCE(TIMx)) 05685 { 05686 /* Check parameters */ 05687 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); 05688 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); 05689 05690 /* Reset the Output Compare and Output Compare N IDLE State */ 05691 tmpcr2 &= ~TIM_CR2_OIS1; 05692 tmpcr2 &= ~TIM_CR2_OIS1N; 05693 /* Set the Output Idle state */ 05694 tmpcr2 |= OC_Config->OCIdleState; 05695 /* Set the Output N Idle state */ 05696 tmpcr2 |= OC_Config->OCNIdleState; 05697 } 05698 05699 /* Write to TIMx CR2 */ 05700 TIMx->CR2 = tmpcr2; 05701 05702 /* Write to TIMx CCMR1 */ 05703 TIMx->CCMR1 = tmpccmrx; 05704 05705 /* Set the Capture Compare Register value */ 05706 TIMx->CCR1 = OC_Config->Pulse; 05707 05708 /* Write to TIMx CCER */ 05709 TIMx->CCER = tmpccer; 05710 } 05711 05712 /** 05713 * @brief Timer Output Compare 2 configuration 05714 * @param TIMx to select the TIM peripheral 05715 * @param OC_Config The ouput configuration structure 05716 * @retval None 05717 */ 05718 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) 05719 { 05720 uint32_t tmpccmrx; 05721 uint32_t tmpccer; 05722 uint32_t tmpcr2; 05723 05724 /* Disable the Channel 2: Reset the CC2E Bit */ 05725 TIMx->CCER &= ~TIM_CCER_CC2E; 05726 05727 /* Get the TIMx CCER register value */ 05728 tmpccer = TIMx->CCER; 05729 /* Get the TIMx CR2 register value */ 05730 tmpcr2 = TIMx->CR2; 05731 05732 /* Get the TIMx CCMR1 register value */ 05733 tmpccmrx = TIMx->CCMR1; 05734 05735 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 05736 tmpccmrx &= ~TIM_CCMR1_OC2M; 05737 tmpccmrx &= ~TIM_CCMR1_CC2S; 05738 05739 /* Select the Output Compare Mode */ 05740 tmpccmrx |= (OC_Config->OCMode << 8U); 05741 05742 /* Reset the Output Polarity level */ 05743 tmpccer &= ~TIM_CCER_CC2P; 05744 /* Set the Output Compare Polarity */ 05745 tmpccer |= (OC_Config->OCPolarity << 4U); 05746 05747 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 05748 { 05749 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); 05750 05751 /* Reset the Output N Polarity level */ 05752 tmpccer &= ~TIM_CCER_CC2NP; 05753 /* Set the Output N Polarity */ 05754 tmpccer |= (OC_Config->OCNPolarity << 4U); 05755 /* Reset the Output N State */ 05756 tmpccer &= ~TIM_CCER_CC2NE; 05757 05758 } 05759 05760 if (IS_TIM_BREAK_INSTANCE(TIMx)) 05761 { 05762 /* Check parameters */ 05763 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); 05764 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); 05765 05766 /* Reset the Output Compare and Output Compare N IDLE State */ 05767 tmpcr2 &= ~TIM_CR2_OIS2; 05768 tmpcr2 &= ~TIM_CR2_OIS2N; 05769 /* Set the Output Idle state */ 05770 tmpcr2 |= (OC_Config->OCIdleState << 2U); 05771 /* Set the Output N Idle state */ 05772 tmpcr2 |= (OC_Config->OCNIdleState << 2U); 05773 } 05774 05775 /* Write to TIMx CR2 */ 05776 TIMx->CR2 = tmpcr2; 05777 05778 /* Write to TIMx CCMR1 */ 05779 TIMx->CCMR1 = tmpccmrx; 05780 05781 /* Set the Capture Compare Register value */ 05782 TIMx->CCR2 = OC_Config->Pulse; 05783 05784 /* Write to TIMx CCER */ 05785 TIMx->CCER = tmpccer; 05786 } 05787 05788 /** 05789 * @brief Timer Output Compare 3 configuration 05790 * @param TIMx to select the TIM peripheral 05791 * @param OC_Config The ouput configuration structure 05792 * @retval None 05793 */ 05794 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) 05795 { 05796 uint32_t tmpccmrx; 05797 uint32_t tmpccer; 05798 uint32_t tmpcr2; 05799 05800 /* Disable the Channel 3: Reset the CC2E Bit */ 05801 TIMx->CCER &= ~TIM_CCER_CC3E; 05802 05803 /* Get the TIMx CCER register value */ 05804 tmpccer = TIMx->CCER; 05805 /* Get the TIMx CR2 register value */ 05806 tmpcr2 = TIMx->CR2; 05807 05808 /* Get the TIMx CCMR2 register value */ 05809 tmpccmrx = TIMx->CCMR2; 05810 05811 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 05812 tmpccmrx &= ~TIM_CCMR2_OC3M; 05813 tmpccmrx &= ~TIM_CCMR2_CC3S; 05814 /* Select the Output Compare Mode */ 05815 tmpccmrx |= OC_Config->OCMode; 05816 05817 /* Reset the Output Polarity level */ 05818 tmpccer &= ~TIM_CCER_CC3P; 05819 /* Set the Output Compare Polarity */ 05820 tmpccer |= (OC_Config->OCPolarity << 8U); 05821 05822 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 05823 { 05824 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); 05825 05826 /* Reset the Output N Polarity level */ 05827 tmpccer &= ~TIM_CCER_CC3NP; 05828 /* Set the Output N Polarity */ 05829 tmpccer |= (OC_Config->OCNPolarity << 8U); 05830 /* Reset the Output N State */ 05831 tmpccer &= ~TIM_CCER_CC3NE; 05832 } 05833 05834 if (IS_TIM_BREAK_INSTANCE(TIMx)) 05835 { 05836 /* Check parameters */ 05837 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); 05838 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); 05839 05840 /* Reset the Output Compare and Output Compare N IDLE State */ 05841 tmpcr2 &= ~TIM_CR2_OIS3; 05842 tmpcr2 &= ~TIM_CR2_OIS3N; 05843 /* Set the Output Idle state */ 05844 tmpcr2 |= (OC_Config->OCIdleState << 4U); 05845 /* Set the Output N Idle state */ 05846 tmpcr2 |= (OC_Config->OCNIdleState << 4U); 05847 } 05848 05849 /* Write to TIMx CR2 */ 05850 TIMx->CR2 = tmpcr2; 05851 05852 /* Write to TIMx CCMR2 */ 05853 TIMx->CCMR2 = tmpccmrx; 05854 05855 /* Set the Capture Compare Register value */ 05856 TIMx->CCR3 = OC_Config->Pulse; 05857 05858 /* Write to TIMx CCER */ 05859 TIMx->CCER = tmpccer; 05860 } 05861 05862 /** 05863 * @brief Timer Output Compare 4 configuration 05864 * @param TIMx to select the TIM peripheral 05865 * @param OC_Config The ouput configuration structure 05866 * @retval None 05867 */ 05868 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) 05869 { 05870 uint32_t tmpccmrx; 05871 uint32_t tmpccer; 05872 uint32_t tmpcr2; 05873 05874 /* Disable the Channel 4: Reset the CC4E Bit */ 05875 TIMx->CCER &= ~TIM_CCER_CC4E; 05876 05877 /* Get the TIMx CCER register value */ 05878 tmpccer = TIMx->CCER; 05879 /* Get the TIMx CR2 register value */ 05880 tmpcr2 = TIMx->CR2; 05881 05882 /* Get the TIMx CCMR2 register value */ 05883 tmpccmrx = TIMx->CCMR2; 05884 05885 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 05886 tmpccmrx &= ~TIM_CCMR2_OC4M; 05887 tmpccmrx &= ~TIM_CCMR2_CC4S; 05888 05889 /* Select the Output Compare Mode */ 05890 tmpccmrx |= (OC_Config->OCMode << 8U); 05891 05892 /* Reset the Output Polarity level */ 05893 tmpccer &= ~TIM_CCER_CC4P; 05894 /* Set the Output Compare Polarity */ 05895 tmpccer |= (OC_Config->OCPolarity << 12U); 05896 05897 if (IS_TIM_BREAK_INSTANCE(TIMx)) 05898 { 05899 /* Check parameters */ 05900 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); 05901 05902 /* Reset the Output Compare IDLE State */ 05903 tmpcr2 &= ~TIM_CR2_OIS4; 05904 05905 /* Set the Output Idle state */ 05906 tmpcr2 |= (OC_Config->OCIdleState << 6U); 05907 } 05908 05909 /* Write to TIMx CR2 */ 05910 TIMx->CR2 = tmpcr2; 05911 05912 /* Write to TIMx CCMR2 */ 05913 TIMx->CCMR2 = tmpccmrx; 05914 05915 /* Set the Capture Compare Register value */ 05916 TIMx->CCR4 = OC_Config->Pulse; 05917 05918 /* Write to TIMx CCER */ 05919 TIMx->CCER = tmpccer; 05920 } 05921 05922 /** 05923 * @brief Timer Output Compare 5 configuration 05924 * @param TIMx to select the TIM peripheral 05925 * @param OC_Config The ouput configuration structure 05926 * @retval None 05927 */ 05928 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, 05929 TIM_OC_InitTypeDef *OC_Config) 05930 { 05931 uint32_t tmpccmrx; 05932 uint32_t tmpccer; 05933 uint32_t tmpcr2; 05934 05935 /* Disable the output: Reset the CCxE Bit */ 05936 TIMx->CCER &= ~TIM_CCER_CC5E; 05937 05938 /* Get the TIMx CCER register value */ 05939 tmpccer = TIMx->CCER; 05940 /* Get the TIMx CR2 register value */ 05941 tmpcr2 = TIMx->CR2; 05942 /* Get the TIMx CCMR1 register value */ 05943 tmpccmrx = TIMx->CCMR3; 05944 05945 /* Reset the Output Compare Mode Bits */ 05946 tmpccmrx &= ~(TIM_CCMR3_OC5M); 05947 /* Select the Output Compare Mode */ 05948 tmpccmrx |= OC_Config->OCMode; 05949 05950 /* Reset the Output Polarity level */ 05951 tmpccer &= ~TIM_CCER_CC5P; 05952 /* Set the Output Compare Polarity */ 05953 tmpccer |= (OC_Config->OCPolarity << 16U); 05954 05955 if (IS_TIM_BREAK_INSTANCE(TIMx)) 05956 { 05957 /* Reset the Output Compare IDLE State */ 05958 tmpcr2 &= ~TIM_CR2_OIS5; 05959 /* Set the Output Idle state */ 05960 tmpcr2 |= (OC_Config->OCIdleState << 8U); 05961 } 05962 /* Write to TIMx CR2 */ 05963 TIMx->CR2 = tmpcr2; 05964 05965 /* Write to TIMx CCMR3 */ 05966 TIMx->CCMR3 = tmpccmrx; 05967 05968 /* Set the Capture Compare Register value */ 05969 TIMx->CCR5 = OC_Config->Pulse; 05970 05971 /* Write to TIMx CCER */ 05972 TIMx->CCER = tmpccer; 05973 } 05974 05975 /** 05976 * @brief Timer Output Compare 6 configuration 05977 * @param TIMx to select the TIM peripheral 05978 * @param OC_Config The ouput configuration structure 05979 * @retval None 05980 */ 05981 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, 05982 TIM_OC_InitTypeDef *OC_Config) 05983 { 05984 uint32_t tmpccmrx; 05985 uint32_t tmpccer; 05986 uint32_t tmpcr2; 05987 05988 /* Disable the output: Reset the CCxE Bit */ 05989 TIMx->CCER &= ~TIM_CCER_CC6E; 05990 05991 /* Get the TIMx CCER register value */ 05992 tmpccer = TIMx->CCER; 05993 /* Get the TIMx CR2 register value */ 05994 tmpcr2 = TIMx->CR2; 05995 /* Get the TIMx CCMR1 register value */ 05996 tmpccmrx = TIMx->CCMR3; 05997 05998 /* Reset the Output Compare Mode Bits */ 05999 tmpccmrx &= ~(TIM_CCMR3_OC6M); 06000 /* Select the Output Compare Mode */ 06001 tmpccmrx |= (OC_Config->OCMode << 8U); 06002 06003 /* Reset the Output Polarity level */ 06004 tmpccer &= (uint32_t)~TIM_CCER_CC6P; 06005 /* Set the Output Compare Polarity */ 06006 tmpccer |= (OC_Config->OCPolarity << 20U); 06007 06008 if (IS_TIM_BREAK_INSTANCE(TIMx)) 06009 { 06010 /* Reset the Output Compare IDLE State */ 06011 tmpcr2 &= ~TIM_CR2_OIS6; 06012 /* Set the Output Idle state */ 06013 tmpcr2 |= (OC_Config->OCIdleState << 10U); 06014 } 06015 06016 /* Write to TIMx CR2 */ 06017 TIMx->CR2 = tmpcr2; 06018 06019 /* Write to TIMx CCMR3 */ 06020 TIMx->CCMR3 = tmpccmrx; 06021 06022 /* Set the Capture Compare Register value */ 06023 TIMx->CCR6 = OC_Config->Pulse; 06024 06025 /* Write to TIMx CCER */ 06026 TIMx->CCER = tmpccer; 06027 } 06028 06029 /** 06030 * @brief Slave Timer configuration function 06031 * @param htim TIM handle 06032 * @param sSlaveConfig Slave timer configuration 06033 * @retval None 06034 */ 06035 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, 06036 TIM_SlaveConfigTypeDef *sSlaveConfig) 06037 { 06038 uint32_t tmpsmcr; 06039 uint32_t tmpccmr1; 06040 uint32_t tmpccer; 06041 06042 /* Get the TIMx SMCR register value */ 06043 tmpsmcr = htim->Instance->SMCR; 06044 06045 /* Reset the Trigger Selection Bits */ 06046 tmpsmcr &= ~TIM_SMCR_TS; 06047 /* Set the Input Trigger source */ 06048 tmpsmcr |= sSlaveConfig->InputTrigger; 06049 06050 /* Reset the slave mode Bits */ 06051 tmpsmcr &= ~TIM_SMCR_SMS; 06052 /* Set the slave mode */ 06053 tmpsmcr |= sSlaveConfig->SlaveMode; 06054 06055 /* Write to TIMx SMCR */ 06056 htim->Instance->SMCR = tmpsmcr; 06057 06058 /* Configure the trigger prescaler, filter, and polarity */ 06059 switch (sSlaveConfig->InputTrigger) 06060 { 06061 case TIM_TS_ETRF: 06062 { 06063 /* Check the parameters */ 06064 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); 06065 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); 06066 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); 06067 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); 06068 /* Configure the ETR Trigger source */ 06069 TIM_ETR_SetConfig(htim->Instance, 06070 sSlaveConfig->TriggerPrescaler, 06071 sSlaveConfig->TriggerPolarity, 06072 sSlaveConfig->TriggerFilter); 06073 break; 06074 } 06075 06076 case TIM_TS_TI1F_ED: 06077 { 06078 /* Check the parameters */ 06079 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 06080 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); 06081 06082 /* Disable the Channel 1: Reset the CC1E Bit */ 06083 tmpccer = htim->Instance->CCER; 06084 htim->Instance->CCER &= ~TIM_CCER_CC1E; 06085 tmpccmr1 = htim->Instance->CCMR1; 06086 06087 /* Set the filter */ 06088 tmpccmr1 &= ~TIM_CCMR1_IC1F; 06089 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); 06090 06091 /* Write to TIMx CCMR1 and CCER registers */ 06092 htim->Instance->CCMR1 = tmpccmr1; 06093 htim->Instance->CCER = tmpccer; 06094 break; 06095 } 06096 06097 case TIM_TS_TI1FP1: 06098 { 06099 /* Check the parameters */ 06100 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 06101 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); 06102 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); 06103 06104 /* Configure TI1 Filter and Polarity */ 06105 TIM_TI1_ConfigInputStage(htim->Instance, 06106 sSlaveConfig->TriggerPolarity, 06107 sSlaveConfig->TriggerFilter); 06108 break; 06109 } 06110 06111 case TIM_TS_TI2FP2: 06112 { 06113 /* Check the parameters */ 06114 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 06115 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); 06116 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); 06117 06118 /* Configure TI2 Filter and Polarity */ 06119 TIM_TI2_ConfigInputStage(htim->Instance, 06120 sSlaveConfig->TriggerPolarity, 06121 sSlaveConfig->TriggerFilter); 06122 break; 06123 } 06124 06125 case TIM_TS_ITR0: 06126 case TIM_TS_ITR1: 06127 case TIM_TS_ITR2: 06128 case TIM_TS_ITR3: 06129 { 06130 /* Check the parameter */ 06131 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 06132 break; 06133 } 06134 06135 default: 06136 break; 06137 } 06138 } 06139 06140 /** 06141 * @brief Configure the TI1 as Input. 06142 * @param TIMx to select the TIM peripheral. 06143 * @param TIM_ICPolarity The Input Polarity. 06144 * This parameter can be one of the following values: 06145 * @arg TIM_ICPOLARITY_RISING 06146 * @arg TIM_ICPOLARITY_FALLING 06147 * @arg TIM_ICPOLARITY_BOTHEDGE 06148 * @param TIM_ICSelection specifies the input to be used. 06149 * This parameter can be one of the following values: 06150 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. 06151 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. 06152 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. 06153 * @param TIM_ICFilter Specifies the Input Capture Filter. 06154 * This parameter must be a value between 0x00 and 0x0F. 06155 * @retval None 06156 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 06157 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be 06158 * protected against un-initialized filter and polarity values. 06159 */ 06160 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 06161 uint32_t TIM_ICFilter) 06162 { 06163 uint32_t tmpccmr1; 06164 uint32_t tmpccer; 06165 06166 /* Disable the Channel 1: Reset the CC1E Bit */ 06167 TIMx->CCER &= ~TIM_CCER_CC1E; 06168 tmpccmr1 = TIMx->CCMR1; 06169 tmpccer = TIMx->CCER; 06170 06171 /* Select the Input */ 06172 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) 06173 { 06174 tmpccmr1 &= ~TIM_CCMR1_CC1S; 06175 tmpccmr1 |= TIM_ICSelection; 06176 } 06177 else 06178 { 06179 tmpccmr1 |= TIM_CCMR1_CC1S_0; 06180 } 06181 06182 /* Set the filter */ 06183 tmpccmr1 &= ~TIM_CCMR1_IC1F; 06184 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); 06185 06186 /* Select the Polarity and set the CC1E Bit */ 06187 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 06188 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); 06189 06190 /* Write to TIMx CCMR1 and CCER registers */ 06191 TIMx->CCMR1 = tmpccmr1; 06192 TIMx->CCER = tmpccer; 06193 } 06194 06195 /** 06196 * @brief Configure the Polarity and Filter for TI1. 06197 * @param TIMx to select the TIM peripheral. 06198 * @param TIM_ICPolarity The Input Polarity. 06199 * This parameter can be one of the following values: 06200 * @arg TIM_ICPOLARITY_RISING 06201 * @arg TIM_ICPOLARITY_FALLING 06202 * @arg TIM_ICPOLARITY_BOTHEDGE 06203 * @param TIM_ICFilter Specifies the Input Capture Filter. 06204 * This parameter must be a value between 0x00 and 0x0F. 06205 * @retval None 06206 */ 06207 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) 06208 { 06209 uint32_t tmpccmr1; 06210 uint32_t tmpccer; 06211 06212 /* Disable the Channel 1: Reset the CC1E Bit */ 06213 tmpccer = TIMx->CCER; 06214 TIMx->CCER &= ~TIM_CCER_CC1E; 06215 tmpccmr1 = TIMx->CCMR1; 06216 06217 /* Set the filter */ 06218 tmpccmr1 &= ~TIM_CCMR1_IC1F; 06219 tmpccmr1 |= (TIM_ICFilter << 4U); 06220 06221 /* Select the Polarity and set the CC1E Bit */ 06222 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 06223 tmpccer |= TIM_ICPolarity; 06224 06225 /* Write to TIMx CCMR1 and CCER registers */ 06226 TIMx->CCMR1 = tmpccmr1; 06227 TIMx->CCER = tmpccer; 06228 } 06229 06230 /** 06231 * @brief Configure the TI2 as Input. 06232 * @param TIMx to select the TIM peripheral 06233 * @param TIM_ICPolarity The Input Polarity. 06234 * This parameter can be one of the following values: 06235 * @arg TIM_ICPOLARITY_RISING 06236 * @arg TIM_ICPOLARITY_FALLING 06237 * @arg TIM_ICPOLARITY_BOTHEDGE 06238 * @param TIM_ICSelection specifies the input to be used. 06239 * This parameter can be one of the following values: 06240 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. 06241 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. 06242 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. 06243 * @param TIM_ICFilter Specifies the Input Capture Filter. 06244 * This parameter must be a value between 0x00 and 0x0F. 06245 * @retval None 06246 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 06247 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be 06248 * protected against un-initialized filter and polarity values. 06249 */ 06250 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 06251 uint32_t TIM_ICFilter) 06252 { 06253 uint32_t tmpccmr1; 06254 uint32_t tmpccer; 06255 06256 /* Disable the Channel 2: Reset the CC2E Bit */ 06257 TIMx->CCER &= ~TIM_CCER_CC2E; 06258 tmpccmr1 = TIMx->CCMR1; 06259 tmpccer = TIMx->CCER; 06260 06261 /* Select the Input */ 06262 tmpccmr1 &= ~TIM_CCMR1_CC2S; 06263 tmpccmr1 |= (TIM_ICSelection << 8U); 06264 06265 /* Set the filter */ 06266 tmpccmr1 &= ~TIM_CCMR1_IC2F; 06267 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); 06268 06269 /* Select the Polarity and set the CC2E Bit */ 06270 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 06271 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); 06272 06273 /* Write to TIMx CCMR1 and CCER registers */ 06274 TIMx->CCMR1 = tmpccmr1 ; 06275 TIMx->CCER = tmpccer; 06276 } 06277 06278 /** 06279 * @brief Configure the Polarity and Filter for TI2. 06280 * @param TIMx to select the TIM peripheral. 06281 * @param TIM_ICPolarity The Input Polarity. 06282 * This parameter can be one of the following values: 06283 * @arg TIM_ICPOLARITY_RISING 06284 * @arg TIM_ICPOLARITY_FALLING 06285 * @arg TIM_ICPOLARITY_BOTHEDGE 06286 * @param TIM_ICFilter Specifies the Input Capture Filter. 06287 * This parameter must be a value between 0x00 and 0x0F. 06288 * @retval None 06289 */ 06290 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) 06291 { 06292 uint32_t tmpccmr1; 06293 uint32_t tmpccer; 06294 06295 /* Disable the Channel 2: Reset the CC2E Bit */ 06296 TIMx->CCER &= ~TIM_CCER_CC2E; 06297 tmpccmr1 = TIMx->CCMR1; 06298 tmpccer = TIMx->CCER; 06299 06300 /* Set the filter */ 06301 tmpccmr1 &= ~TIM_CCMR1_IC2F; 06302 tmpccmr1 |= (TIM_ICFilter << 12U); 06303 06304 /* Select the Polarity and set the CC2E Bit */ 06305 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 06306 tmpccer |= (TIM_ICPolarity << 4U); 06307 06308 /* Write to TIMx CCMR1 and CCER registers */ 06309 TIMx->CCMR1 = tmpccmr1 ; 06310 TIMx->CCER = tmpccer; 06311 } 06312 06313 /** 06314 * @brief Configure the TI3 as Input. 06315 * @param TIMx to select the TIM peripheral 06316 * @param TIM_ICPolarity The Input Polarity. 06317 * This parameter can be one of the following values: 06318 * @arg TIM_ICPOLARITY_RISING 06319 * @arg TIM_ICPOLARITY_FALLING 06320 * @arg TIM_ICPOLARITY_BOTHEDGE 06321 * @param TIM_ICSelection specifies the input to be used. 06322 * This parameter can be one of the following values: 06323 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. 06324 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. 06325 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. 06326 * @param TIM_ICFilter Specifies the Input Capture Filter. 06327 * This parameter must be a value between 0x00 and 0x0F. 06328 * @retval None 06329 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 06330 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be 06331 * protected against un-initialized filter and polarity values. 06332 */ 06333 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 06334 uint32_t TIM_ICFilter) 06335 { 06336 uint32_t tmpccmr2; 06337 uint32_t tmpccer; 06338 06339 /* Disable the Channel 3: Reset the CC3E Bit */ 06340 TIMx->CCER &= ~TIM_CCER_CC3E; 06341 tmpccmr2 = TIMx->CCMR2; 06342 tmpccer = TIMx->CCER; 06343 06344 /* Select the Input */ 06345 tmpccmr2 &= ~TIM_CCMR2_CC3S; 06346 tmpccmr2 |= TIM_ICSelection; 06347 06348 /* Set the filter */ 06349 tmpccmr2 &= ~TIM_CCMR2_IC3F; 06350 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); 06351 06352 /* Select the Polarity and set the CC3E Bit */ 06353 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); 06354 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); 06355 06356 /* Write to TIMx CCMR2 and CCER registers */ 06357 TIMx->CCMR2 = tmpccmr2; 06358 TIMx->CCER = tmpccer; 06359 } 06360 06361 /** 06362 * @brief Configure the TI4 as Input. 06363 * @param TIMx to select the TIM peripheral 06364 * @param TIM_ICPolarity The Input Polarity. 06365 * This parameter can be one of the following values: 06366 * @arg TIM_ICPOLARITY_RISING 06367 * @arg TIM_ICPOLARITY_FALLING 06368 * @arg TIM_ICPOLARITY_BOTHEDGE 06369 * @param TIM_ICSelection specifies the input to be used. 06370 * This parameter can be one of the following values: 06371 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. 06372 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. 06373 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. 06374 * @param TIM_ICFilter Specifies the Input Capture Filter. 06375 * This parameter must be a value between 0x00 and 0x0F. 06376 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 06377 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be 06378 * protected against un-initialized filter and polarity values. 06379 * @retval None 06380 */ 06381 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 06382 uint32_t TIM_ICFilter) 06383 { 06384 uint32_t tmpccmr2; 06385 uint32_t tmpccer; 06386 06387 /* Disable the Channel 4: Reset the CC4E Bit */ 06388 TIMx->CCER &= ~TIM_CCER_CC4E; 06389 tmpccmr2 = TIMx->CCMR2; 06390 tmpccer = TIMx->CCER; 06391 06392 /* Select the Input */ 06393 tmpccmr2 &= ~TIM_CCMR2_CC4S; 06394 tmpccmr2 |= (TIM_ICSelection << 8U); 06395 06396 /* Set the filter */ 06397 tmpccmr2 &= ~TIM_CCMR2_IC4F; 06398 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); 06399 06400 /* Select the Polarity and set the CC4E Bit */ 06401 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); 06402 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); 06403 06404 /* Write to TIMx CCMR2 and CCER registers */ 06405 TIMx->CCMR2 = tmpccmr2; 06406 TIMx->CCER = tmpccer ; 06407 } 06408 06409 /** 06410 * @brief Selects the Input Trigger source 06411 * @param TIMx to select the TIM peripheral 06412 * @param InputTriggerSource The Input Trigger source. 06413 * This parameter can be one of the following values: 06414 * @arg TIM_TS_ITR0: Internal Trigger 0 06415 * @arg TIM_TS_ITR1: Internal Trigger 1 06416 * @arg TIM_TS_ITR2: Internal Trigger 2 06417 * @arg TIM_TS_ITR3: Internal Trigger 3 06418 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector 06419 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 06420 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 06421 * @arg TIM_TS_ETRF: External Trigger input 06422 * @retval None 06423 */ 06424 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) 06425 { 06426 uint32_t tmpsmcr; 06427 06428 /* Get the TIMx SMCR register value */ 06429 tmpsmcr = TIMx->SMCR; 06430 /* Reset the TS Bits */ 06431 tmpsmcr &= ~TIM_SMCR_TS; 06432 /* Set the Input Trigger source and the slave mode*/ 06433 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 06434 /* Write to TIMx SMCR */ 06435 TIMx->SMCR = tmpsmcr; 06436 } 06437 /** 06438 * @brief Configures the TIMx External Trigger (ETR). 06439 * @param TIMx to select the TIM peripheral 06440 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. 06441 * This parameter can be one of the following values: 06442 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. 06443 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. 06444 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. 06445 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. 06446 * @param TIM_ExtTRGPolarity The external Trigger Polarity. 06447 * This parameter can be one of the following values: 06448 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. 06449 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. 06450 * @param ExtTRGFilter External Trigger Filter. 06451 * This parameter must be a value between 0x00 and 0x0F 06452 * @retval None 06453 */ 06454 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 06455 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) 06456 { 06457 uint32_t tmpsmcr; 06458 06459 tmpsmcr = TIMx->SMCR; 06460 06461 /* Reset the ETR Bits */ 06462 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 06463 06464 /* Set the Prescaler, the Filter value and the Polarity */ 06465 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 06466 06467 /* Write to TIMx SMCR */ 06468 TIMx->SMCR = tmpsmcr; 06469 } 06470 06471 /** 06472 * @brief Enables or disables the TIM Capture Compare Channel x. 06473 * @param TIMx to select the TIM peripheral 06474 * @param Channel specifies the TIM Channel 06475 * This parameter can be one of the following values: 06476 * @arg TIM_CHANNEL_1: TIM Channel 1 06477 * @arg TIM_CHANNEL_2: TIM Channel 2 06478 * @arg TIM_CHANNEL_3: TIM Channel 3 06479 * @arg TIM_CHANNEL_4: TIM Channel 4 06480 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 06481 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 06482 * @param ChannelState specifies the TIM Channel CCxE bit new state. 06483 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. 06484 * @retval None 06485 */ 06486 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) 06487 { 06488 uint32_t tmp; 06489 06490 /* Check the parameters */ 06491 assert_param(IS_TIM_CC1_INSTANCE(TIMx)); 06492 assert_param(IS_TIM_CHANNELS(Channel)); 06493 06494 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 06495 06496 /* Reset the CCxE Bit */ 06497 TIMx->CCER &= ~tmp; 06498 06499 /* Set or reset the CCxE Bit */ 06500 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 06501 } 06502 06503 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 06504 /** 06505 * @brief Reset interrupt callbacks to the legacy week callbacks. 06506 * @param htim pointer to a TIM_HandleTypeDef structure that contains 06507 * the configuration information for TIM module. 06508 * @retval None 06509 */ 06510 void TIM_ResetCallback(TIM_HandleTypeDef *htim) 06511 { 06512 /* Reset the TIM callback to the legacy weak callbacks */ 06513 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ 06514 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ 06515 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ 06516 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ 06517 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ 06518 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ 06519 htim->CommutationCallback = HAL_TIMEx_CommutationCallback; /* Legacy weak CommutationCallback */ 06520 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ 06521 } 06522 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 06523 06524 /** 06525 * @} 06526 */ 06527 06528 #endif /* HAL_TIM_MODULE_ENABLED */ 06529 /** 06530 * @} 06531 */ 06532 06533 /** 06534 * @} 06535 */ 06536 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/