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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_adc_ex.h 00004 * @author MCD Application Team 00005 * @brief Header file of ADC HAL extended module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_HAL_ADC_EX_H 00038 #define __STM32L4xx_HAL_ADC_EX_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx_hal_def.h" 00046 00047 /** @addtogroup STM32L4xx_HAL_Driver 00048 * @{ 00049 */ 00050 00051 /** @addtogroup ADCEx 00052 * @{ 00053 */ 00054 00055 /* Exported types ------------------------------------------------------------*/ 00056 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 00057 * @{ 00058 */ 00059 00060 /** 00061 * @brief ADC Injected Conversion Oversampling structure definition 00062 */ 00063 typedef struct 00064 { 00065 uint32_t Ratio; /*!< Configures the oversampling ratio. 00066 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 00067 00068 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 00069 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 00070 }ADC_InjOversamplingTypeDef; 00071 00072 /** 00073 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected 00074 * @note Parameters of this structure are shared within 2 scopes: 00075 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset 00076 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 00077 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. 00078 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 00079 * ADC state can be either: 00080 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') 00081 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. 00082 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. 00083 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going 00084 * on ADC groups regular and injected. 00085 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 00086 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 00087 */ 00088 typedef struct 00089 { 00090 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. 00091 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 00092 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 00093 00094 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. 00095 This parameter must be a value of @ref ADC_LL_EC_INJ_SEQ_RANKS. 00096 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 00097 the new channel setting (or parameter number of conversions adjusted) */ 00098 00099 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 00100 Unit: ADC clock cycles. 00101 Conversion time is the addition of sampling time and processing time 00102 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 00103 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. 00104 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 00105 It overwrites the last setting. 00106 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 00107 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 00108 Refer to device datasheet for timings values. */ 00109 00110 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 00111 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 00112 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 00113 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. 00114 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 00115 It overwrites the last setting. 00116 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 00117 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 00118 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 00119 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 00120 of another parameter update on the fly) */ 00121 00122 uint32_t InjectedOffsetNumber; /*!< Selects the offset number. 00123 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. 00124 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 00125 00126 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. 00127 Offset value must be a positive number. 00128 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 00129 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 00130 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 00131 without continuous mode or external trigger that could launch a conversion). */ 00132 00133 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. 00134 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 00135 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 00136 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00137 configure a channel on injected group can impact the configuration of other channels previously set. */ 00138 00139 uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence 00140 (main sequence subdivided in successive parts). 00141 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 00142 Discontinuous mode can be enabled only if continuous mode is disabled. 00143 This parameter can be set to ENABLE or DISABLE. 00144 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 00145 Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). 00146 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00147 configure a channel on injected group can impact the configuration of other channels previously set. */ 00148 00149 uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one 00150 This parameter can be set to ENABLE or DISABLE. 00151 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 00152 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) 00153 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 00154 To maintain JAUTO always enabled, DMA must be configured in circular mode. 00155 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00156 configure a channel on injected group can impact the configuration of other channels previously set. */ 00157 00158 uint32_t QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. 00159 This parameter can be set to ENABLE or DISABLE. 00160 If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a 00161 new injected context is set when queue is full, error is triggered by interruption and through function 00162 'HAL_ADCEx_InjectedQueueOverflowCallback'. 00163 Caution: This feature request that the sequence is fully configured before injected conversion start. 00164 Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. 00165 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00166 configure a channel on injected group can impact the configuration of other channels previously set. 00167 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ 00168 00169 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 00170 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 00171 This parameter can be a value of @ref ADC_injected_external_trigger_source. 00172 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00173 configure a channel on injected group can impact the configuration of other channels previously set. */ 00174 00175 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 00176 This parameter can be a value of @ref ADC_injected_external_trigger_edge. 00177 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. 00178 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00179 configure a channel on injected group can impact the configuration of other channels previously set. */ 00180 00181 uint32_t InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 00182 This parameter can be set to ENABLE or DISABLE. 00183 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 00184 00185 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. 00186 Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. 00187 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 00188 }ADC_InjectionConfTypeDef; 00189 00190 #if defined(ADC_MULTIMODE_SUPPORT) 00191 /** 00192 * @brief Structure definition of ADC multimode 00193 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). 00194 * Both Master and Slave ADCs must be disabled. 00195 */ 00196 typedef struct 00197 { 00198 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. 00199 This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ 00200 00201 uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: 00202 selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master) 00203 This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */ 00204 00205 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 00206 This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. 00207 Delay range depends on selected resolution: 00208 from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, 00209 from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */ 00210 }ADC_MultiModeTypeDef; 00211 #endif /* ADC_MULTIMODE_SUPPORT */ 00212 00213 /** 00214 * @} 00215 */ 00216 00217 /* Exported constants --------------------------------------------------------*/ 00218 00219 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 00220 * @{ 00221 */ 00222 00223 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source 00224 * @{ 00225 */ 00226 /* ADC group regular trigger sources for all ADC instances */ 00227 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ 00228 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 00229 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ 00230 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00231 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 00232 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00233 #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 00234 #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00235 #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00236 #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00237 #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 00238 #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ 00239 #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00240 #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 00241 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ 00242 #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ 00243 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 00244 /** 00245 * @} 00246 */ 00247 00248 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) 00249 * @{ 00250 */ 00251 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U) /*!< Injected conversions hardware trigger detection disabled */ 00252 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ 00253 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ 00254 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ 00255 /** 00256 * @} 00257 */ 00258 00259 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 00260 * @{ 00261 */ 00262 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ 00263 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ 00264 /** 00265 * @} 00266 */ 00267 00268 /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number 00269 * @{ 00270 */ 00271 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ 00272 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00273 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00274 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00275 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00276 /** 00277 * @} 00278 */ 00279 00280 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 00281 * @{ 00282 */ 00283 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ 00284 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ 00285 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ 00286 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ 00287 /** 00288 * @} 00289 */ 00290 00291 #if defined(ADC_MULTIMODE_SUPPORT) 00292 /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode 00293 * @{ 00294 */ 00295 #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ 00296 #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ 00297 #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ 00298 #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ 00299 #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 00300 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 00301 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 00302 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ 00303 00304 /** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution 00305 * @{ 00306 */ 00307 #define ADC_DMAACCESSMODE_DISABLED (0x00000000U) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ 00308 #define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ 00309 #define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ 00310 /** 00311 * @} 00312 */ 00313 00314 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 00315 * @{ 00316 */ 00317 #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ 00318 #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ 00319 #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ 00320 #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ 00321 #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ 00322 #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ 00323 #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ 00324 #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ 00325 #define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ 00326 #define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ 00327 #define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ 00328 #define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ 00329 /** 00330 * @} 00331 */ 00332 00333 /** 00334 * @} 00335 */ 00336 #endif /* ADC_MULTIMODE_SUPPORT */ 00337 00338 /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups 00339 * @{ 00340 */ 00341 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ 00342 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ 00343 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ 00344 /** 00345 * @} 00346 */ 00347 00348 /** @defgroup ADC_CFGR_fields ADCx CFGR fields 00349 * @{ 00350 */ 00351 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 00352 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 00353 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 00354 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 00355 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 00356 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 00357 ADC_CFGR_RES | ADC_CFGR_DFSDMCFG | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) 00358 #else 00359 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 00360 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 00361 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 00362 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 00363 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 00364 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) 00365 #endif 00366 /** 00367 * @} 00368 */ 00369 00370 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields 00371 * @{ 00372 */ 00373 #if defined(ADC_SMPR1_SMPPLUS) 00374 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 00375 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 00376 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 00377 ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS) 00378 #else 00379 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 00380 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 00381 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 00382 ADC_SMPR1_SMP0) 00383 #endif 00384 /** 00385 * @} 00386 */ 00387 00388 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 00389 * @{ 00390 */ 00391 /* ADC_CFGR fields of parameters that can be updated when no conversion 00392 (neither regular nor injected) is on-going */ 00393 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 00394 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY | ADC_CFGR_DFSDMCFG)) 00395 #else 00396 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY)) 00397 #endif 00398 /** 00399 * @} 00400 */ 00401 00402 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 00403 /** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data 00404 * @{ 00405 */ 00406 #define ADC_DFSDM_MODE_DISABLE (0x00000000U) /*!< ADC conversions are not transferred by DFSDM. */ 00407 #define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ 00408 /** 00409 * @} 00410 */ 00411 #endif 00412 00413 /** 00414 * @} 00415 */ 00416 00417 /* Exported macros -----------------------------------------------------------*/ 00418 00419 #if defined(ADC_MULTIMODE_SUPPORT) 00420 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros 00421 * @{ 00422 */ 00423 00424 /** @brief Force ADC instance in multimode mode independant (multimode disable). 00425 * @note This macro must be used only in case of transition from multimode 00426 * to mode independent and in case of unknown previous state, 00427 * to ensure ADC configuration is in mode independent. 00428 * @note Standard way of multimode configuration change is done from 00429 * HAL ADC handle of ADC master using function 00430 * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". 00431 * Usage of this macro is not the Standard way of multimode 00432 * configuration and can lead to have HAL ADC handles status 00433 * misaligned. Usage of this macro must be limited to cases 00434 * mentionned above. 00435 * @param __HANDLE__ ADC handle. 00436 * @retval None 00437 */ 00438 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ 00439 LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) 00440 00441 /** 00442 * @} 00443 */ 00444 #endif /* ADC_MULTIMODE_SUPPORT */ 00445 00446 /* Private macros ------------------------------------------------------------*/ 00447 00448 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 00449 * @{ 00450 */ 00451 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 00452 /* code of final user. */ 00453 00454 /** 00455 * @brief Test if conversion trigger of injected group is software start 00456 * or external trigger. 00457 * @param __HANDLE__ ADC handle. 00458 * @retval SET (software start) or RESET (external trigger). 00459 */ 00460 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 00461 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET) 00462 00463 /** 00464 * @brief Check if conversion is on going on regular or injected groups. 00465 * @param __HANDLE__ ADC handle. 00466 * @retval SET (conversion is on going) or RESET (no conversion is on going). 00467 */ 00468 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ 00469 (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET \ 00470 ) ? RESET : SET) 00471 00472 /** 00473 * @brief Check if conversion is on going on injected group. 00474 * @param __HANDLE__ ADC handle. 00475 * @retval SET (conversion is on going) or RESET (no conversion is on going). 00476 */ 00477 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ 00478 (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance)) 00479 00480 /** 00481 * @brief Check whether or not ADC is independent. 00482 * @param __HANDLE__ ADC handle. 00483 * @note When multimode feature is not available, the macro always returns SET. 00484 * @retval SET (ADC is independent) or RESET (ADC is not). 00485 */ 00486 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 00487 #define ADC_IS_INDEPENDENT(__HANDLE__) \ 00488 ( ( ( ((__HANDLE__)->Instance) == ADC3) \ 00489 )? \ 00490 SET \ 00491 : \ 00492 RESET \ 00493 ) 00494 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00495 #define ADC_IS_INDEPENDENT(__HANDLE__) (SET) 00496 #endif 00497 00498 /** 00499 * @brief Set the selected injected Channel rank. 00500 * @param __CHANNELNB__ Channel number. 00501 * @param __RANKNB__ Rank number. 00502 * @retval None 00503 */ 00504 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) 00505 00506 /** 00507 * @brief Configure ADC injected context queue 00508 * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. 00509 * @retval None 00510 */ 00511 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) 00512 00513 /** 00514 * @brief Configure ADC discontinuous conversion mode for injected group 00515 * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. 00516 * @retval None 00517 */ 00518 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) 00519 00520 /** 00521 * @brief Configure ADC discontinuous conversion mode for regular group 00522 * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. 00523 * @retval None 00524 */ 00525 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) 00526 00527 /** 00528 * @brief Configure the number of discontinuous conversions for regular group. 00529 * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. 00530 * @retval None 00531 */ 00532 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << ADC_CFGR_DISCNUM_Pos) 00533 00534 /** 00535 * @brief Configure the ADC auto delay mode. 00536 * @param __AUTOWAIT__ Auto delay bit enable or disable. 00537 * @retval None 00538 */ 00539 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) 00540 00541 /** 00542 * @brief Configure ADC continuous conversion mode. 00543 * @param __CONTINUOUS_MODE__ Continuous mode. 00544 * @retval None 00545 */ 00546 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) 00547 00548 /** 00549 * @brief Configure the ADC DMA continuous request. 00550 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 00551 * @retval None 00552 */ 00553 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos) 00554 00555 /** 00556 * @brief Configure the channel number into offset OFRx register. 00557 * @param __CHANNEL__ ADC Channel. 00558 * @retval None 00559 */ 00560 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos) 00561 00562 /** 00563 * @brief Configure the channel number into differential mode selection register. 00564 * @param __CHANNEL__ ADC Channel. 00565 * @retval None 00566 */ 00567 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__)) 00568 00569 /** 00570 * @brief Configure calibration factor in differential mode to be set into calibration register. 00571 * @param __CALIBRATION_FACTOR__ Calibration factor value. 00572 * @retval None 00573 */ 00574 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos) 00575 00576 /** 00577 * @brief Calibration factor in differential mode to be retrieved from calibration register. 00578 * @param __CALIBRATION_FACTOR__ Calibration factor value. 00579 * @retval None 00580 */ 00581 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos) 00582 00583 /** 00584 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. 00585 * @param __THRESHOLD__ Threshold value. 00586 * @retval None 00587 */ 00588 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16) 00589 00590 #if defined(ADC_MULTIMODE_SUPPORT) 00591 /** 00592 * @brief Configure the ADC DMA continuous request for ADC multimode. 00593 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 00594 * @retval None 00595 */ 00596 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) 00597 #endif /* ADC_MULTIMODE_SUPPORT */ 00598 /** 00599 * @brief Enable the ADC peripheral. 00600 * @param __HANDLE__ ADC handle. 00601 * @retval None 00602 */ 00603 #define ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) 00604 00605 /** 00606 * @brief Verification of hardware constraints before ADC can be enabled. 00607 * @param __HANDLE__ ADC handle. 00608 * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) 00609 */ 00610 #define ADC_ENABLING_CONDITIONS(__HANDLE__) \ 00611 (( ( ((__HANDLE__)->Instance->CR) & \ 00612 (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | \ 00613 ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) \ 00614 ) == RESET \ 00615 ) ? SET : RESET) 00616 00617 /** 00618 * @brief Disable the ADC peripheral. 00619 * @param __HANDLE__ ADC handle. 00620 * @retval None 00621 */ 00622 #define ADC_DISABLE(__HANDLE__) \ 00623 do{ \ 00624 (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ 00625 __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ 00626 } while(0) 00627 00628 /** 00629 * @brief Verification of hardware constraints before ADC can be disabled. 00630 * @param __HANDLE__ ADC handle. 00631 * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) 00632 */ 00633 #define ADC_DISABLING_CONDITIONS(__HANDLE__) \ 00634 (( ( ((__HANDLE__)->Instance->CR) & \ 00635 (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ 00636 ) ? SET : RESET) 00637 00638 /** 00639 * @brief Shift the offset with respect to the selected ADC resolution. 00640 * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. 00641 * If resolution 12 bits, no shift. 00642 * If resolution 10 bits, shift of 2 ranks on the left. 00643 * If resolution 8 bits, shift of 4 ranks on the left. 00644 * If resolution 6 bits, shift of 6 ranks on the left. 00645 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 00646 * @param __HANDLE__ ADC handle 00647 * @param __OFFSET__ Value to be shifted 00648 * @retval None 00649 */ 00650 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 00651 ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2)) 00652 00653 00654 /** 00655 * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. 00656 * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. 00657 * If resolution 12 bits, no shift. 00658 * If resolution 10 bits, shift of 2 ranks on the left. 00659 * If resolution 8 bits, shift of 4 ranks on the left. 00660 * If resolution 6 bits, shift of 6 ranks on the left. 00661 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 00662 * @param __HANDLE__ ADC handle 00663 * @param __THRESHOLD__ Value to be shifted 00664 * @retval None 00665 */ 00666 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 00667 ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2)) 00668 00669 /** 00670 * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. 00671 * @note Thresholds have to be left-aligned on bit 7. 00672 * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded). 00673 * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). 00674 * If resolution 8 bits, no shift. 00675 * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0). 00676 * @param __HANDLE__ ADC handle 00677 * @param __THRESHOLD__ Value to be shifted 00678 * @retval None 00679 */ 00680 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 00681 ( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \ 00682 ((__THRESHOLD__) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \ 00683 (__THRESHOLD__) << 2 ) 00684 00685 /** 00686 * @brief Report Master Instance. 00687 * @param __HANDLE__ ADC handle. 00688 * @note Return same instance if ADC of input handle is independent ADC or if 00689 * multimode feature is not available. 00690 * @retval Master Instance 00691 */ 00692 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 00693 #define ADC_MASTER_REGISTER(__HANDLE__) \ 00694 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \ 00695 )? \ 00696 ((__HANDLE__)->Instance) \ 00697 : \ 00698 (ADC1) \ 00699 ) 00700 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00701 #define ADC_MASTER_REGISTER(__HANDLE__) ((__HANDLE__)->Instance) 00702 #endif 00703 00704 /** 00705 * @brief Clear Common Control Register. 00706 * @param __HANDLE__ ADC handle. 00707 * @retval None 00708 */ 00709 #if defined(ADC_MULTIMODE_SUPPORT) 00710 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ 00711 ADC_CCR_PRESC | \ 00712 ADC_CCR_VBATEN | \ 00713 ADC_CCR_TSEN | \ 00714 ADC_CCR_VREFEN | \ 00715 ADC_CCR_MDMA | \ 00716 ADC_CCR_DMACFG | \ 00717 ADC_CCR_DELAY | \ 00718 ADC_CCR_DUAL ) 00719 #else 00720 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ 00721 ADC_CCR_PRESC | \ 00722 ADC_CCR_VBATEN | \ 00723 ADC_CCR_TSEN | \ 00724 ADC_CCR_VREFEN ) 00725 00726 #endif /* ADC_MULTIMODE_SUPPORT */ 00727 00728 /** 00729 * @brief Check whether or not dual conversions are enabled. 00730 * @param __HANDLE__ ADC handle. 00731 * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available. 00732 * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled) 00733 */ 00734 #if defined(ADC_MULTIMODE_SUPPORT) 00735 #define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) \ 00736 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ 00737 )? \ 00738 ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) ) \ 00739 : \ 00740 RESET \ 00741 ) 00742 #else 00743 #define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) (RESET) 00744 #endif 00745 00746 /** 00747 * @brief Check whether or not dual regular conversions are enabled. 00748 * @param __HANDLE__ ADC handle. 00749 * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available. 00750 * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled) 00751 */ 00752 #if defined(ADC_MULTIMODE_SUPPORT) 00753 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \ 00754 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ 00755 )? \ 00756 ( (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \ 00757 (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \ 00758 (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \ 00759 : \ 00760 RESET \ 00761 ) 00762 #else 00763 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) (RESET) 00764 #endif 00765 00766 /** 00767 * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with handle of ADC master. 00768 * @param __HANDLE__ ADC handle. 00769 * @note Return SET if multimode feature is not available. 00770 * @retval SET (non-multimode or Master handle) or RESET (handle of Slave ADC in multimode) 00771 */ 00772 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 00773 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ 00774 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ 00775 )? \ 00776 SET \ 00777 : \ 00778 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == RESET) \ 00779 ) 00780 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00781 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (SET) 00782 #endif 00783 00784 /** 00785 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled. 00786 * @param __HANDLE__ ADC handle. 00787 * @note Return SET if multimode feature is not available. 00788 * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled) 00789 */ 00790 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 00791 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \ 00792 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ 00793 )? \ 00794 SET \ 00795 : \ 00796 ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 00797 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \ 00798 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) 00799 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined( STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00800 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) (SET) 00801 #endif 00802 00803 /** 00804 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled. 00805 * @param __HANDLE__ ADC handle. 00806 * @note Return SET if multimode feature is not available. 00807 * @retval SET (non-multimode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled) 00808 */ 00809 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 00810 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \ 00811 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ 00812 )? \ 00813 SET \ 00814 : \ 00815 ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 00816 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \ 00817 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) )) 00818 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00819 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) (SET) 00820 #endif 00821 00822 /** 00823 * @brief Verification of ADC state: enabled or disabled, directly checked on instance as input parameter. 00824 * @param __INSTANCE__ ADC instance. 00825 * @retval SET (ADC enabled) or RESET (ADC disabled) 00826 */ 00827 #define ADC_INSTANCE_IS_ENABLED(__INSTANCE__) \ 00828 (( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 00829 ((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ 00830 ) ? SET : RESET) 00831 00832 /** 00833 * @brief Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle. 00834 * @param __HANDLE__ ADC handle. 00835 * @retval SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled) 00836 */ 00837 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 00838 #define ADC_ANY_OTHER_ENABLED(__HANDLE__) \ 00839 ( ( ((__HANDLE__)->Instance == ADC1) \ 00840 )? \ 00841 (ADC_INSTANCE_IS_ENABLED(ADC2)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \ 00842 : \ 00843 ( ( ((__HANDLE__)->Instance == ADC2) \ 00844 )? \ 00845 (ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \ 00846 : \ 00847 ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC2)) \ 00848 ) 00849 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00850 #define ADC_ANY_OTHER_ENABLED(__HANDLE__) (RESET) 00851 #endif 00852 00853 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 00854 /** 00855 * @brief Set handle instance of the ADC slave associated to the ADC master. 00856 * @param __HANDLE_MASTER__ ADC master handle. 00857 * @param __HANDLE_SLAVE__ ADC slave handle. 00858 * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. 00859 * @retval None 00860 */ 00861 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 00862 ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) 00863 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00864 00865 /** 00866 * @brief Check whether or not multimode is configured in DMA mode. 00867 * @param __HANDLE__ ADC handle. 00868 * @note Return RESET if multimode feature is not available. 00869 * @retval SET (multimode is configured in DMA mode) or RESET (DMA multimode is disabled) 00870 */ 00871 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 00872 #define ADC_MULTIMODE_DMA_ENABLED(__HANDLE__) \ 00873 ((READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_12_10_BITS) \ 00874 || (READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_8_6_BITS)) 00875 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00876 #define ADC_MULTIMODE_DMA_ENABLED(__HANDLE__) (RESET) 00877 #endif 00878 00879 /** 00880 * @brief Verify the ADC instance connected to the temperature sensor. 00881 * @param __HANDLE__ ADC handle. 00882 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 00883 */ 00884 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00885 /* The temperature sensor measurement path (channel 17) is available on ADC1 */ 00886 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 00887 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 00888 /* The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */ 00889 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) 00890 #endif 00891 00892 /** 00893 * @brief Verify the ADC instance connected to the battery voltage VBAT. 00894 * @param __HANDLE__ ADC handle. 00895 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 00896 */ 00897 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00898 /* The battery voltage measurement path (channel 18) is available on ADC1 */ 00899 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 00900 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 00901 /* The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */ 00902 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) 00903 #endif 00904 00905 /** 00906 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. 00907 * @param __HANDLE__ ADC handle. 00908 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 00909 */ 00910 /* The internal voltage reference VREFINT measurement path (channel 0) is available on ADC1 */ 00911 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 00912 00913 /** 00914 * @brief Verify the length of scheduled injected conversions group. 00915 * @param __LENGTH__ number of programmed conversions. 00916 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) 00917 */ 00918 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) 00919 00920 /** 00921 * @brief Calibration factor size verification (7 bits maximum). 00922 * @param __CALIBRATION_FACTOR__ Calibration factor value. 00923 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 00924 */ 00925 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) 00926 00927 00928 /** 00929 * @brief Verify the ADC channel setting. 00930 * @param __HANDLE__ ADC handle. 00931 * @param __CHANNEL__ programmed ADC channel. 00932 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 00933 */ 00934 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00935 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \ 00936 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 00937 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 00938 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 00939 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 00940 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 00941 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 00942 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 00943 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 00944 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 00945 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 00946 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 00947 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 00948 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 00949 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 00950 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 00951 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 00952 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 00953 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 00954 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 00955 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 00956 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 00957 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1) || \ 00958 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2))) 00959 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 00960 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ 00961 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 00962 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 00963 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 00964 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 00965 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 00966 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 00967 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 00968 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 00969 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 00970 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 00971 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 00972 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 00973 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 00974 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 00975 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 00976 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 00977 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 00978 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 00979 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ 00980 ((((__HANDLE__)->Instance) == ADC2) && \ 00981 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 00982 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 00983 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 00984 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 00985 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 00986 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 00987 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 00988 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 00989 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 00990 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 00991 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 00992 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 00993 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 00994 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 00995 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 00996 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 00997 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 00998 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 00999 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2) || \ 01000 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2))) || \ 01001 ((((__HANDLE__)->Instance) == ADC3) && \ 01002 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 01003 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 01004 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 01005 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 01006 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 01007 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 01008 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 01009 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 01010 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 01011 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 01012 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 01013 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 01014 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 01015 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 01016 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 01017 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 01018 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC3) || \ 01019 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC3) ))) 01020 #endif 01021 01022 /** 01023 * @brief Verify the ADC channel setting in differential mode. 01024 * @param __HANDLE__ ADC handle. 01025 * @param __CHANNEL__ programmed ADC channel. 01026 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 01027 */ 01028 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 01029 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 01030 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 01031 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 01032 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 01033 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 01034 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 01035 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 01036 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 01037 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 01038 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 01039 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 01040 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 01041 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 01042 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 01043 ((__CHANNEL__) == ADC_CHANNEL_15) ) 01044 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 01045 /* For ADC1 and ADC2, channels 1 to 15 are available in differential mode, 01046 channels 0, 16 to 18 can be only used in single-ended mode. 01047 For ADC3, channels 1 to 3 and 6 to 12 are available in differential mode, 01048 channels 4, 5 and 13 to 18 can only be used in single-ended mode. */ 01049 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ((((((__HANDLE__)->Instance) == ADC1) || \ 01050 (((__HANDLE__)->Instance) == ADC2)) && \ 01051 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 01052 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 01053 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 01054 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 01055 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 01056 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 01057 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 01058 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 01059 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 01060 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 01061 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 01062 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 01063 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 01064 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 01065 ((__CHANNEL__) == ADC_CHANNEL_15))) || \ 01066 ((((__HANDLE__)->Instance) == ADC3) && \ 01067 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 01068 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 01069 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 01070 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 01071 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 01072 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 01073 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 01074 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 01075 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 01076 ((__CHANNEL__) == ADC_CHANNEL_12) ))) 01077 #endif 01078 01079 /** 01080 * @brief Verify the ADC single-ended input or differential mode setting. 01081 * @param __SING_DIFF__ programmed channel setting. 01082 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) 01083 */ 01084 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ 01085 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) 01086 01087 /** 01088 * @brief Verify the ADC offset management setting. 01089 * @param __OFFSET_NUMBER__ ADC offset management. 01090 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) 01091 */ 01092 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ 01093 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ 01094 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ 01095 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ 01096 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) 01097 01098 /** 01099 * @brief Verify the ADC injected channel setting. 01100 * @param __CHANNEL__ programmed ADC injected channel. 01101 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 01102 */ 01103 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ 01104 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ 01105 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ 01106 ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) 01107 01108 /** 01109 * @brief Verify the ADC injected conversions external trigger. 01110 * @param __HANDLE__ ADC handle. 01111 * @param __INJTRIG__ programmed ADC injected conversions external trigger. 01112 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) 01113 */ 01114 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 01115 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 01116 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 01117 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 01118 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 01119 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 01120 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 01121 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 01122 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 01123 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 01124 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 01125 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 01126 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 01127 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 01128 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 01129 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 01130 ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) 01131 01132 /** 01133 * @brief Verify the ADC edge trigger setting for injected group. 01134 * @param __EDGE__ programmed ADC edge trigger setting. 01135 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 01136 */ 01137 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 01138 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 01139 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 01140 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 01141 01142 #if defined(ADC_MULTIMODE_SUPPORT) 01143 /** 01144 * @brief Verify the ADC multimode setting. 01145 * @param __MODE__ programmed ADC multimode setting. 01146 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 01147 */ 01148 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ 01149 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ 01150 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ 01151 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ 01152 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ 01153 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ 01154 ((__MODE__) == ADC_DUALMODE_INTERL) || \ 01155 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) 01156 01157 /** 01158 * @brief Verify the ADC multimode DMA access setting. 01159 * @param __MODE__ programmed ADC multimode DMA access setting. 01160 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 01161 */ 01162 #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ 01163 ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \ 01164 ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) ) 01165 01166 /** 01167 * @brief Verify the ADC multimode delay setting. 01168 * @param __DELAY__ programmed ADC multimode delay setting. 01169 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) 01170 */ 01171 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ 01172 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ 01173 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ 01174 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ 01175 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 01176 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 01177 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 01178 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 01179 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ 01180 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ 01181 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ 01182 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) 01183 #endif /* ADC_MULTIMODE_SUPPORT */ 01184 01185 /** 01186 * @brief Verify the ADC analog watchdog setting. 01187 * @param __WATCHDOG__ programmed ADC analog watchdog setting. 01188 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) 01189 */ 01190 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ 01191 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ 01192 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) 01193 01194 /** 01195 * @brief Verify the ADC analog watchdog mode setting. 01196 * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. 01197 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) 01198 */ 01199 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 01200 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 01201 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 01202 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 01203 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 01204 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 01205 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 01206 01207 /** 01208 * @brief Verify the ADC conversion (regular or injected or both). 01209 * @param __CONVERSION__ ADC conversion group. 01210 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) 01211 */ 01212 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ 01213 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ 01214 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) 01215 01216 /** 01217 * @brief Verify the ADC event type. 01218 * @param __EVENT__ ADC event. 01219 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) 01220 */ 01221 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 01222 ((__EVENT__) == ADC_AWD_EVENT) || \ 01223 ((__EVENT__) == ADC_AWD2_EVENT) || \ 01224 ((__EVENT__) == ADC_AWD3_EVENT) || \ 01225 ((__EVENT__) == ADC_OVR_EVENT) || \ 01226 ((__EVENT__) == ADC_JQOVF_EVENT) ) 01227 01228 /** 01229 * @brief Verify the ADC oversampling ratio. 01230 * @param __RATIO__ programmed ADC oversampling ratio. 01231 * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) 01232 */ 01233 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ 01234 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ 01235 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ 01236 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ 01237 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ 01238 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ 01239 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ 01240 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) 01241 01242 /** 01243 * @brief Verify the ADC oversampling shift. 01244 * @param __SHIFT__ programmed ADC oversampling shift. 01245 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 01246 */ 01247 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 01248 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 01249 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 01250 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 01251 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 01252 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 01253 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 01254 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 01255 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) 01256 01257 /** 01258 * @brief Verify the ADC oversampling triggered mode. 01259 * @param __MODE__ programmed ADC oversampling triggered mode. 01260 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 01261 */ 01262 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 01263 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 01264 01265 /** 01266 * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 01267 * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. 01268 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 01269 */ 01270 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ 01271 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) 01272 01273 /** 01274 * @brief Verify the DFSDM mode configuration. 01275 * @param __HANDLE__ ADC handle. 01276 * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For 01277 * this reason, the input parameter is the ADC handle and not the configuration parameter 01278 * directly. 01279 * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) 01280 */ 01281 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 01282 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \ 01283 ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) ) 01284 #else 01285 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) 01286 #endif 01287 01288 /** 01289 * @brief Return the DFSDM configuration mode. 01290 * @param __HANDLE__ ADC handle. 01291 * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). 01292 * For this reason, the input parameter is the ADC handle and not the configuration parameter 01293 * directly. 01294 * @retval DFSDM configuration mode 01295 */ 01296 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 01297 #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig) 01298 #else 01299 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0) 01300 #endif 01301 01302 /** 01303 * @} 01304 */ 01305 01306 01307 /* Exported functions --------------------------------------------------------*/ 01308 /** @addtogroup ADCEx_Exported_Functions 01309 * @{ 01310 */ 01311 01312 /** @addtogroup ADCEx_Exported_Functions_Group1 01313 * @{ 01314 */ 01315 /* IO operation functions *****************************************************/ 01316 01317 /* ADC calibration */ 01318 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff); 01319 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 01320 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); 01321 01322 /* Blocking mode: Polling */ 01323 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); 01324 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); 01325 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 01326 01327 /* Non-blocking mode: Interruption */ 01328 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); 01329 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); 01330 01331 #if defined(ADC_MULTIMODE_SUPPORT) 01332 /* ADC multimode */ 01333 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 01334 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 01335 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); 01336 #endif /* ADC_MULTIMODE_SUPPORT */ 01337 01338 /* ADC retrieve conversion value intended to be used with polling or interruption */ 01339 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); 01340 01341 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 01342 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); 01343 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc); 01344 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc); 01345 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc); 01346 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc); 01347 01348 /* ADC group regular conversions stop */ 01349 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc); 01350 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc); 01351 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc); 01352 #if defined(ADC_MULTIMODE_SUPPORT) 01353 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc); 01354 #endif /* ADC_MULTIMODE_SUPPORT */ 01355 01356 /** 01357 * @} 01358 */ 01359 01360 /** @addtogroup ADCEx_Exported_Functions_Group2 01361 * @{ 01362 */ 01363 /* Peripheral Control functions ***********************************************/ 01364 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); 01365 #if defined(ADC_MULTIMODE_SUPPORT) 01366 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); 01367 #endif /* ADC_MULTIMODE_SUPPORT */ 01368 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc); 01369 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc); 01370 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc); 01371 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc); 01372 01373 /** 01374 * @} 01375 */ 01376 01377 /** 01378 * @} 01379 */ 01380 01381 /** 01382 * @} 01383 */ 01384 01385 /** 01386 * @} 01387 */ 01388 01389 #ifdef __cplusplus 01390 } 01391 #endif 01392 01393 #endif /* __STM32L4xx_HAL_ADC_EX_H */ 01394 01395 01396 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1