STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_adc_ex.c 00004 * @author MCD Application Team 00005 * @brief This file provides firmware functions to manage the following 00006 * functionalities of the Analog to Digital Convertor (ADC) 00007 * peripheral: 00008 * + Operation functions 00009 * ++ Start, stop, get result of conversions of ADC group injected, 00010 * using 2 possible modes: polling, interruption. 00011 * ++ Calibration 00012 * +++ ADC automatic self-calibration 00013 * +++ Calibration factors get or set 00014 * ++ Multimode feature when available 00015 * + Control functions 00016 * ++ Channels configuration on ADC group injected 00017 * + State functions 00018 * ++ ADC group injected contexts queue management 00019 * Other functions (generic functions) are available in file 00020 * "stm32l4xx_hal_adc.c". 00021 * 00022 @verbatim 00023 [..] 00024 (@) Sections "ADC peripheral features" and "How to use this driver" are 00025 available in file of generic functions "stm32l4xx_hal_adc.c". 00026 [..] 00027 @endverbatim 00028 ****************************************************************************** 00029 * @attention 00030 * 00031 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00032 * 00033 * Redistribution and use in source and binary forms, with or without modification, 00034 * are permitted provided that the following conditions are met: 00035 * 1. Redistributions of source code must retain the above copyright notice, 00036 * this list of conditions and the following disclaimer. 00037 * 2. Redistributions in binary form must reproduce the above copyright notice, 00038 * this list of conditions and the following disclaimer in the documentation 00039 * and/or other materials provided with the distribution. 00040 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00041 * may be used to endorse or promote products derived from this software 00042 * without specific prior written permission. 00043 * 00044 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00045 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00046 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00047 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00048 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00049 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00050 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00051 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00052 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00053 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00054 * 00055 ****************************************************************************** 00056 */ 00057 00058 /* Includes ------------------------------------------------------------------*/ 00059 #include "stm32l4xx_hal.h" 00060 00061 /** @addtogroup STM32L4xx_HAL_Driver 00062 * @{ 00063 */ 00064 00065 /** @defgroup ADCEx ADCEx 00066 * @brief ADC Extended HAL module driver 00067 * @{ 00068 */ 00069 00070 #ifdef HAL_ADC_MODULE_ENABLED 00071 00072 /* Private typedef -----------------------------------------------------------*/ 00073 /* Private define ------------------------------------------------------------*/ 00074 00075 /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants 00076 * @{ 00077 */ 00078 00079 #define ADC_JSQR_FIELDS ((uint32_t)(ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\ 00080 ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\ 00081 ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime 00082 once the ADC is enabled */ 00083 00084 /* Fixed timeout value for ADC calibration. */ 00085 /* Values defined to be higher than worst cases: maximum ratio between ADC */ 00086 /* and CPU clock frequencies. */ 00087 /* Example of profile low frequency : ADC frequency at 31.25kHz (ADC clock */ 00088 /* source PLL SAI 8MHz, ADC clock prescaler 256), CPU frequency 80MHz. */ 00089 /* Calibration time max = 116 / fADC (refer to datasheet) */ 00090 /* = 296 960 CPU cycles */ 00091 #define ADC_CALIBRATION_TIMEOUT (296960U) /*!< ADC calibration time-out value (unit: CPU cycles) */ 00092 00093 /** 00094 * @} 00095 */ 00096 00097 /* Private macro -------------------------------------------------------------*/ 00098 /* Private variables ---------------------------------------------------------*/ 00099 /* Private function prototypes -----------------------------------------------*/ 00100 /* Exported functions --------------------------------------------------------*/ 00101 00102 /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions 00103 * @{ 00104 */ 00105 00106 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions 00107 * @brief Extended IO operation functions 00108 * 00109 @verbatim 00110 =============================================================================== 00111 ##### IO operation functions ##### 00112 =============================================================================== 00113 [..] This section provides functions allowing to: 00114 00115 (+) Perform the ADC self-calibration for single or differential ending. 00116 (+) Get calibration factors for single or differential ending. 00117 (+) Set calibration factors for single or differential ending. 00118 00119 (+) Start conversion of ADC group injected. 00120 (+) Stop conversion of ADC group injected. 00121 (+) Poll for conversion complete on ADC group injected. 00122 (+) Get result of ADC group injected channel conversion. 00123 (+) Start conversion of ADC group injected and enable interruptions. 00124 (+) Stop conversion of ADC group injected and disable interruptions. 00125 00126 (+) When multimode feature is available, start multimode and enable DMA transfer. 00127 (+) Stop multimode and disable ADC DMA transfer. 00128 (+) Get result of multimode conversion. 00129 00130 @endverbatim 00131 * @{ 00132 */ 00133 00134 /** 00135 * @brief Perform an ADC automatic self-calibration 00136 * Calibration prerequisite: ADC must be disabled (execute this 00137 * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). 00138 * @param hadc ADC handle 00139 * @param SingleDiff Selection of single-ended or differential input 00140 * This parameter can be one of the following values: 00141 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended 00142 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended 00143 * @retval HAL status 00144 */ 00145 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) 00146 { 00147 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 00148 uint32_t WaitLoopIndex = 0; 00149 00150 /* Check the parameters */ 00151 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00152 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); 00153 00154 /* Process locked */ 00155 __HAL_LOCK(hadc); 00156 00157 /* Calibration prerequisite: ADC must be disabled. */ 00158 00159 /* Disable the ADC (if not already disabled) */ 00160 tmp_hal_status = ADC_Disable(hadc); 00161 00162 /* Check if ADC is effectively disabled */ 00163 if (tmp_hal_status == HAL_OK) 00164 { 00165 /* Set ADC state */ 00166 ADC_STATE_CLR_SET(hadc->State, 00167 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 00168 HAL_ADC_STATE_BUSY_INTERNAL); 00169 00170 00171 00172 /* Select calibration mode single ended or differential ended */ 00173 MODIFY_REG(hadc->Instance->CR, ADC_CR_ADCALDIF, SingleDiff); 00174 00175 /* Start ADC calibration */ 00176 SET_BIT(hadc->Instance->CR, ADC_CR_ADCAL); 00177 00178 /* Wait for calibration completion */ 00179 while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL)) 00180 { 00181 WaitLoopIndex++; 00182 if (WaitLoopIndex >= ADC_CALIBRATION_TIMEOUT) 00183 { 00184 /* Update ADC state machine to error */ 00185 ADC_STATE_CLR_SET(hadc->State, 00186 HAL_ADC_STATE_BUSY_INTERNAL, 00187 HAL_ADC_STATE_ERROR_INTERNAL); 00188 00189 /* Process unlocked */ 00190 __HAL_UNLOCK(hadc); 00191 00192 return HAL_ERROR; 00193 } 00194 } 00195 00196 /* Set ADC state */ 00197 ADC_STATE_CLR_SET(hadc->State, 00198 HAL_ADC_STATE_BUSY_INTERNAL, 00199 HAL_ADC_STATE_READY); 00200 } 00201 else 00202 { 00203 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 00204 00205 /* Note: No need to update variable "tmp_hal_status" here: already set */ 00206 /* to state "HAL_ERROR" by function disabling the ADC. */ 00207 } 00208 00209 /* Process unlocked */ 00210 __HAL_UNLOCK(hadc); 00211 00212 /* Return function status */ 00213 return tmp_hal_status; 00214 } 00215 00216 /** 00217 * @brief Get the calibration factor. 00218 * @param hadc ADC handle. 00219 * @param SingleDiff This parameter can be only: 00220 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended 00221 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended 00222 * @retval Calibration value. 00223 */ 00224 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) 00225 { 00226 /* Check the parameters */ 00227 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00228 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); 00229 00230 /* Return the selected ADC calibration value */ 00231 if (SingleDiff == ADC_DIFFERENTIAL_ENDED) 00232 { 00233 return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT); 00234 } 00235 else 00236 { 00237 return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S); 00238 } 00239 } 00240 00241 /** 00242 * @brief Set the calibration factor to overwrite automatic conversion result. 00243 * ADC must be enabled and no conversion is ongoing. 00244 * @param hadc ADC handle 00245 * @param SingleDiff This parameter can be only: 00246 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended 00247 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended 00248 * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) 00249 * @retval HAL state 00250 */ 00251 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) 00252 { 00253 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 00254 00255 /* Check the parameters */ 00256 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00257 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); 00258 assert_param(IS_ADC_CALFACT(CalibrationFactor)); 00259 00260 /* Process locked */ 00261 __HAL_LOCK(hadc); 00262 00263 /* Verification of hardware constraints before modifying the calibration */ 00264 /* factors register: ADC must be enabled, no conversion on going. */ 00265 if ( (ADC_IS_ENABLE(hadc) != RESET) && 00266 (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) ) 00267 { 00268 /* Set the selected ADC calibration value */ 00269 if (SingleDiff == ADC_DIFFERENTIAL_ENDED) 00270 { 00271 MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D, ADC_CALFACT_DIFF_SET(CalibrationFactor)); 00272 } 00273 else 00274 { 00275 MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_S, CalibrationFactor); 00276 } 00277 } 00278 else 00279 { 00280 /* Update ADC state machine */ 00281 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 00282 /* Update ADC error code */ 00283 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 00284 00285 /* Update ADC state machine to error */ 00286 tmp_hal_status = HAL_ERROR; 00287 } 00288 00289 /* Process unlocked */ 00290 __HAL_UNLOCK(hadc); 00291 00292 /* Return function status */ 00293 return tmp_hal_status; 00294 } 00295 00296 /** 00297 * @brief Enable ADC, start conversion of injected group. 00298 * @note Interruptions enabled in this function: None. 00299 * @note Case of multimode enabled when multimode feature is available: 00300 * HAL_ADCEx_InjectedStart() API must be called for ADC slave first, 00301 * then for ADC master. 00302 * For ADC slave, ADC is enabled only (conversion is not started). 00303 * For ADC master, ADC is enabled and multimode conversion is started. 00304 * @param hadc ADC handle. 00305 * @retval HAL status 00306 */ 00307 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) 00308 { 00309 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 00310 00311 /* Check the parameters */ 00312 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00313 00314 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc)) 00315 { 00316 return HAL_BUSY; 00317 } 00318 else 00319 { 00320 00321 /* In case of software trigger detection enabled, JQDIS must be set 00322 (which can be done only if ADSTART and JADSTART are both cleared). 00323 If JQDIS is not set at that point, returns an error 00324 - since software trigger detection is disabled. User needs to 00325 resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. 00326 - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means 00327 the queue is empty */ 00328 if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET) 00329 && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET)) 00330 { 00331 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 00332 return HAL_ERROR; 00333 } 00334 00335 00336 /* Process locked */ 00337 __HAL_LOCK(hadc); 00338 00339 /* Enable the ADC peripheral */ 00340 tmp_hal_status = ADC_Enable(hadc); 00341 00342 /* Start conversion if ADC is effectively enabled */ 00343 if (tmp_hal_status == HAL_OK) 00344 { 00345 /* Check if a regular conversion is ongoing */ 00346 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY)) 00347 { 00348 /* Reset ADC error code field related to injected conversions only */ 00349 CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); 00350 } 00351 else 00352 { 00353 /* Set ADC error code to none */ 00354 ADC_CLEAR_ERRORCODE(hadc); 00355 } 00356 00357 /* Set ADC state */ 00358 /* - Clear state bitfield related to injected group conversion results */ 00359 /* - Set state bitfield related to injected operation */ 00360 ADC_STATE_CLR_SET(hadc->State, 00361 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, 00362 HAL_ADC_STATE_INJ_BUSY); 00363 00364 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit 00365 - by default if ADC is Master or Independent or if multimode feature is not available 00366 - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ 00367 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 00368 { 00369 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 00370 } 00371 00372 /* Clear ADC group injected group conversion flag */ 00373 /* (To ensure of no unknown state from potential previous ADC operations) */ 00374 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); 00375 00376 /* Process unlocked */ 00377 /* Unlock before starting ADC conversions: in case of potential */ 00378 /* interruption, to let the process to ADC IRQ Handler. */ 00379 __HAL_UNLOCK(hadc); 00380 00381 /* Enable conversion of injected group, if automatic injected conversion */ 00382 /* is disabled. */ 00383 /* If software start has been selected, conversion starts immediately. */ 00384 /* If external trigger has been selected, conversion will start at next */ 00385 /* trigger event. */ 00386 /* Case of multimode enabled (when multimode feature is available): */ 00387 /* if ADC is slave, */ 00388 /* - ADC is enabled only (conversion is not started). */ 00389 /* - if multimode only concerns regular conversion, ADC is enabled */ 00390 /* and conversion is started. */ 00391 /* If ADC is master or independent, */ 00392 /* - ADC is enabled and conversion is started. */ 00393 00394 /* Are injected conversions that of a dual Slave ? */ 00395 if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc)) 00396 { 00397 /* hadc is not the handle of a Slave ADC with dual injected conversions enabled: 00398 set ADSTART only if JAUTO is cleared */ 00399 if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) 00400 { 00401 SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ; 00402 } 00403 } 00404 else 00405 { 00406 /* hadc is the handle of a Slave ADC with dual injected conversions enabled: 00407 ADSTART is not set */ 00408 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 00409 } 00410 } 00411 else 00412 { 00413 /* Process unlocked */ 00414 __HAL_UNLOCK(hadc); 00415 } 00416 00417 /* Return function status */ 00418 return tmp_hal_status; 00419 } 00420 } 00421 00422 /** 00423 * @brief Stop conversion of injected channels. Disable ADC peripheral if 00424 * no regular conversion is on going. 00425 * @note If ADC must be disabled and if conversion is on going on 00426 * regular group, function HAL_ADC_Stop must be used to stop both 00427 * injected and regular groups, and disable the ADC. 00428 * @note If injected group mode auto-injection is enabled, 00429 * function HAL_ADC_Stop must be used. 00430 * @note In case of multimode enabled (when multimode feature is available), 00431 * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave. 00432 * For ADC master, conversion is stopped and ADC is disabled. 00433 * For ADC slave, ADC is disabled only (conversion stop of ADC master 00434 * has already stopped conversion of ADC slave). 00435 * @param hadc ADC handle. 00436 * @retval HAL status 00437 */ 00438 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) 00439 { 00440 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 00441 00442 /* Check the parameters */ 00443 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00444 00445 /* Process locked */ 00446 __HAL_LOCK(hadc); 00447 00448 /* 1. Stop potential conversion on going on injected group only. */ 00449 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); 00450 00451 /* Disable ADC peripheral if injected conversions are effectively stopped */ 00452 /* and if no conversion on regular group is on-going */ 00453 if (tmp_hal_status == HAL_OK) 00454 { 00455 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 00456 { 00457 /* 2. Disable the ADC peripheral */ 00458 tmp_hal_status = ADC_Disable(hadc); 00459 00460 /* Check if ADC is effectively disabled */ 00461 if (tmp_hal_status == HAL_OK) 00462 { 00463 /* Set ADC state */ 00464 ADC_STATE_CLR_SET(hadc->State, 00465 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 00466 HAL_ADC_STATE_READY); 00467 } 00468 } 00469 /* Conversion on injected group is stopped, but ADC not disabled since */ 00470 /* conversion on regular group is still running. */ 00471 else 00472 { 00473 /* Set ADC state */ 00474 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 00475 } 00476 } 00477 00478 /* Process unlocked */ 00479 __HAL_UNLOCK(hadc); 00480 00481 /* Return function status */ 00482 return tmp_hal_status; 00483 } 00484 00485 /** 00486 * @brief Wait for injected group conversion to be completed. 00487 * @param hadc ADC handle 00488 * @param Timeout Timeout value in millisecond. 00489 * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is 00490 * checked and cleared depending on AUTDLY bit status. 00491 * @retval HAL status 00492 */ 00493 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) 00494 { 00495 uint32_t tickstart = 0U; 00496 uint32_t tmp_Flag_End = 0U; 00497 uint32_t tmp_cfgr = 0U; 00498 ADC_TypeDef *tmpADC_Master; 00499 00500 /* Check the parameters */ 00501 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00502 00503 /* If end of sequence selected */ 00504 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) 00505 { 00506 tmp_Flag_End = ADC_FLAG_JEOS; 00507 } 00508 else /* end of conversion selected */ 00509 { 00510 tmp_Flag_End = ADC_FLAG_JEOC; 00511 } 00512 00513 /* Get timeout */ 00514 tickstart = HAL_GetTick(); 00515 00516 /* Wait until End of Conversion or Sequence flag is raised */ 00517 while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End)) 00518 { 00519 /* Check if timeout is disabled (set to infinite wait) */ 00520 if(Timeout != HAL_MAX_DELAY) 00521 { 00522 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) 00523 { 00524 /* Update ADC state machine to timeout */ 00525 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 00526 00527 /* Process unlocked */ 00528 __HAL_UNLOCK(hadc); 00529 00530 return HAL_TIMEOUT; 00531 } 00532 } 00533 } 00534 00535 /* Get relevant register CFGR in ADC instance of ADC master or slave */ 00536 /* in function of multimode state (for devices with multimode */ 00537 /* available). */ 00538 if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc) == SET) 00539 { 00540 tmp_cfgr = READ_REG(hadc->Instance->CFGR); 00541 } 00542 else 00543 { 00544 tmpADC_Master = ADC_MASTER_REGISTER(hadc); 00545 tmp_cfgr = READ_REG(tmpADC_Master->CFGR); 00546 } 00547 00548 /* Update ADC state machine */ 00549 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 00550 00551 /* Determine whether any further conversion upcoming on group injected */ 00552 /* by external trigger or by automatic injected conversion */ 00553 /* from group regular. */ 00554 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 00555 ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) && 00556 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 00557 (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) ) 00558 { 00559 /* Check whether end of sequence is reached */ 00560 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) ) 00561 { 00562 /* Particular case if injected contexts queue is enabled: */ 00563 /* when the last context has been fully processed, JSQR is reset */ 00564 /* by the hardware. Even if no injected conversion is planned to come */ 00565 /* (queue empty, triggers are ignored), it can start again */ 00566 /* immediately after setting a new context (JADSTART is still set). */ 00567 /* Therefore, state of HAL ADC injected group is kept to busy. */ 00568 if(READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == RESET) 00569 { 00570 /* Set ADC state */ 00571 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 00572 00573 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 00574 { 00575 SET_BIT(hadc->State, HAL_ADC_STATE_READY); 00576 } 00577 } 00578 } 00579 } 00580 00581 /* Clear polled flag */ 00582 if (tmp_Flag_End == ADC_FLAG_JEOS) 00583 { 00584 /* Clear end of sequence JEOS flag of injected group if low power feature */ 00585 /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */ 00586 /* For injected groups, no new conversion will start before JEOS is */ 00587 /* cleared. */ 00588 if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET) 00589 { 00590 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); 00591 } 00592 } 00593 else 00594 { 00595 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); 00596 } 00597 00598 /* Return API HAL status */ 00599 return HAL_OK; 00600 } 00601 00602 /** 00603 * @brief Enable ADC, start conversion of injected group with interruption. 00604 * @note Interruptions enabled in this function according to initialization 00605 * setting : JEOC (end of conversion) or JEOS (end of sequence) 00606 * @note Case of multimode enabled (when multimode feature is enabled): 00607 * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first, 00608 * then for ADC master. 00609 * For ADC slave, ADC is enabled only (conversion is not started). 00610 * For ADC master, ADC is enabled and multimode conversion is started. 00611 * @param hadc ADC handle. 00612 * @retval HAL status. 00613 */ 00614 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) 00615 { 00616 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 00617 00618 /* Check the parameters */ 00619 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00620 00621 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc)) 00622 { 00623 return HAL_BUSY; 00624 } 00625 else 00626 { 00627 /* In case of software trigger detection enabled, JQDIS must be set 00628 (which can be done only if ADSTART and JADSTART are both cleared). 00629 If JQDIS is not set at that point, returns an error 00630 - since software trigger detection is disabled. User needs to 00631 resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. 00632 - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means 00633 the queue is empty */ 00634 if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET) 00635 && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET)) 00636 { 00637 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 00638 return HAL_ERROR; 00639 } 00640 00641 /* Process locked */ 00642 __HAL_LOCK(hadc); 00643 00644 /* Enable the ADC peripheral */ 00645 tmp_hal_status = ADC_Enable(hadc); 00646 00647 /* Start conversion if ADC is effectively enabled */ 00648 if (tmp_hal_status == HAL_OK) 00649 { 00650 /* Check if a regular conversion is ongoing */ 00651 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY)) 00652 { 00653 /* Reset ADC error code field related to injected conversions only */ 00654 CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); 00655 } 00656 else 00657 { 00658 /* Set ADC error code to none */ 00659 ADC_CLEAR_ERRORCODE(hadc); 00660 } 00661 00662 /* Set ADC state */ 00663 /* - Clear state bitfield related to injected group conversion results */ 00664 /* - Set state bitfield related to injected operation */ 00665 ADC_STATE_CLR_SET(hadc->State, 00666 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, 00667 HAL_ADC_STATE_INJ_BUSY); 00668 00669 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit 00670 - by default if ADC is Master or Independent or if multimode feature is not available 00671 - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ 00672 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 00673 { 00674 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 00675 } 00676 00677 /* Clear ADC group injected group conversion flag */ 00678 /* (To ensure of no unknown state from potential previous ADC operations) */ 00679 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); 00680 00681 /* Process unlocked */ 00682 /* Unlock before starting ADC conversions: in case of potential */ 00683 /* interruption, to let the process to ADC IRQ Handler. */ 00684 __HAL_UNLOCK(hadc); 00685 00686 /* Enable ADC Injected context queue overflow interrupt if this feature */ 00687 /* is enabled. */ 00688 if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET) 00689 { 00690 __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF); 00691 } 00692 00693 /* Enable ADC end of conversion interrupt */ 00694 switch(hadc->Init.EOCSelection) 00695 { 00696 case ADC_EOC_SEQ_CONV: 00697 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 00698 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); 00699 break; 00700 /* case ADC_EOC_SINGLE_CONV */ 00701 default: 00702 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); 00703 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); 00704 break; 00705 } 00706 00707 /* Enable conversion of injected group, if automatic injected conversion */ 00708 /* is disabled. */ 00709 /* If software start has been selected, conversion starts immediately. */ 00710 /* If external trigger has been selected, conversion will start at next */ 00711 /* trigger event. */ 00712 /* Case of multimode enabled (when multimode feature is available): */ 00713 /* if ADC is slave, */ 00714 /* - ADC is enabled only (conversion is not started), */ 00715 /* - if multimode only concerns regular conversion, ADC is enabled */ 00716 /* and conversion is started. */ 00717 /* If ADC is master or independent, */ 00718 /* - ADC is enabled and conversion is started. */ 00719 00720 /* Are injected conversions that of a dual Slave ? */ 00721 if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc)) 00722 { 00723 /* hadc is not the handle of a Slave ADC with dual injected conversions enabled: 00724 set ADSTART only if JAUTO is cleared */ 00725 if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) 00726 { 00727 SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ; 00728 } 00729 } 00730 else 00731 { 00732 /* hadc is the handle of a Slave ADC with dual injected conversions enabled: 00733 ADSTART is not set */ 00734 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 00735 } 00736 } 00737 else 00738 { 00739 /* Process unlocked */ 00740 __HAL_UNLOCK(hadc); 00741 } 00742 00743 /* Return function status */ 00744 return tmp_hal_status; 00745 } 00746 } 00747 00748 /** 00749 * @brief Stop conversion of injected channels, disable interruption of 00750 * end-of-conversion. Disable ADC peripheral if no regular conversion 00751 * is on going. 00752 * @note If ADC must be disabled and if conversion is on going on 00753 * regular group, function HAL_ADC_Stop must be used to stop both 00754 * injected and regular groups, and disable the ADC. 00755 * @note If injected group mode auto-injection is enabled, 00756 * function HAL_ADC_Stop must be used. 00757 * @note Case of multimode enabled (when multimode feature is available): 00758 * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first, 00759 * then for ADC slave. 00760 * For ADC master, conversion is stopped and ADC is disabled. 00761 * For ADC slave, ADC is disabled only (conversion stop of ADC master 00762 * has already stopped conversion of ADC slave). 00763 * @note In case of auto-injection mode, HAL_ADC_Stop() must be used. 00764 * @param hadc ADC handle 00765 * @retval HAL status 00766 */ 00767 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) 00768 { 00769 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 00770 00771 /* Check the parameters */ 00772 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00773 00774 /* Process locked */ 00775 __HAL_LOCK(hadc); 00776 00777 /* 1. Stop potential conversion on going on injected group only. */ 00778 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); 00779 00780 /* Disable ADC peripheral if injected conversions are effectively stopped */ 00781 /* and if no conversion on the other group (regular group) is intended to */ 00782 /* continue. */ 00783 if (tmp_hal_status == HAL_OK) 00784 { 00785 /* Disable ADC end of conversion interrupt for injected channels */ 00786 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF)); 00787 00788 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 00789 { 00790 /* 2. Disable the ADC peripheral */ 00791 tmp_hal_status = ADC_Disable(hadc); 00792 00793 /* Check if ADC is effectively disabled */ 00794 if (tmp_hal_status == HAL_OK) 00795 { 00796 /* Set ADC state */ 00797 ADC_STATE_CLR_SET(hadc->State, 00798 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 00799 HAL_ADC_STATE_READY); 00800 } 00801 } 00802 /* Conversion on injected group is stopped, but ADC not disabled since */ 00803 /* conversion on regular group is still running. */ 00804 else 00805 { 00806 /* Set ADC state */ 00807 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 00808 } 00809 } 00810 00811 /* Process unlocked */ 00812 __HAL_UNLOCK(hadc); 00813 00814 /* Return function status */ 00815 return tmp_hal_status; 00816 } 00817 00818 #if defined(ADC_MULTIMODE_SUPPORT) 00819 /** 00820 * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA. 00821 * @note Multimode must have been previously configured using 00822 * HAL_ADCEx_MultiModeConfigChannel() function. 00823 * Interruptions enabled in this function: 00824 * overrun, DMA half transfer, DMA transfer complete. 00825 * Each of these interruptions has its dedicated callback function. 00826 * @note State field of Slave ADC handle is not updated in this configuration: 00827 * user should not rely on it for information related to Slave regular 00828 * conversions. 00829 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) 00830 * @param pData Destination Buffer address. 00831 * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes). 00832 * @retval HAL status 00833 */ 00834 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) 00835 { 00836 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 00837 ADC_HandleTypeDef tmphadcSlave; 00838 ADC_Common_TypeDef *tmpADC_Common; 00839 00840 /* Check the parameters */ 00841 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); 00842 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); 00843 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 00844 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); 00845 00846 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) 00847 { 00848 return HAL_BUSY; 00849 } 00850 else 00851 { 00852 /* Process locked */ 00853 __HAL_LOCK(hadc); 00854 00855 /* Set a temporary handle of the ADC slave associated to the ADC master */ 00856 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 00857 00858 if (tmphadcSlave.Instance == NULL) 00859 { 00860 /* Set ADC state */ 00861 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 00862 00863 /* Process unlocked */ 00864 __HAL_UNLOCK(hadc); 00865 00866 return HAL_ERROR; 00867 } 00868 00869 /* Enable the ADC peripherals: master and slave (in case if not already */ 00870 /* enabled previously) */ 00871 tmp_hal_status = ADC_Enable(hadc); 00872 if (tmp_hal_status == HAL_OK) 00873 { 00874 tmp_hal_status = ADC_Enable(&tmphadcSlave); 00875 } 00876 00877 /* Start multimode conversion of ADCs pair */ 00878 if (tmp_hal_status == HAL_OK) 00879 { 00880 /* Set ADC state */ 00881 ADC_STATE_CLR_SET(hadc->State, 00882 (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP), 00883 HAL_ADC_STATE_REG_BUSY); 00884 00885 /* Set ADC error code to none */ 00886 ADC_CLEAR_ERRORCODE(hadc); 00887 00888 /* Set the DMA transfer complete callback */ 00889 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 00890 00891 /* Set the DMA half transfer complete callback */ 00892 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 00893 00894 /* Set the DMA error callback */ 00895 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ; 00896 00897 /* Pointer to the common control register */ 00898 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); 00899 00900 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ 00901 /* start (in case of SW start): */ 00902 00903 /* Clear regular group conversion flag and overrun flag */ 00904 /* (To ensure of no unknown state from potential previous ADC operations) */ 00905 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 00906 00907 /* Process unlocked */ 00908 /* Unlock before starting ADC conversions: in case of potential */ 00909 /* interruption, to let the process to ADC IRQ Handler. */ 00910 __HAL_UNLOCK(hadc); 00911 00912 /* Enable ADC overrun interrupt */ 00913 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 00914 00915 /* Start the DMA channel */ 00916 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); 00917 00918 /* Enable conversion of regular group. */ 00919 /* If software start has been selected, conversion starts immediately. */ 00920 /* If external trigger has been selected, conversion will start at next */ 00921 /* trigger event. */ 00922 /* Start ADC group regular conversion */ 00923 LL_ADC_REG_StartConversion(hadc->Instance); 00924 } 00925 else 00926 { 00927 /* Process unlocked */ 00928 __HAL_UNLOCK(hadc); 00929 } 00930 00931 /* Return function status */ 00932 return tmp_hal_status; 00933 } 00934 } 00935 00936 /** 00937 * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral. 00938 * @note Multimode is kept enabled after this function. MultiMode DMA bits 00939 * (MDMA and DMACFG bits of common CCR register) are maintained. To disable 00940 * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be 00941 * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can 00942 * resort to HAL_ADCEx_DisableMultiMode() API. 00943 * @note In case of DMA configured in circular mode, function 00944 * HAL_ADC_Stop_DMA() must be called after this function with handle of 00945 * ADC slave, to properly disable the DMA channel. 00946 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) 00947 * @retval HAL status 00948 */ 00949 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) 00950 { 00951 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 00952 uint32_t tickstart; 00953 ADC_HandleTypeDef tmphadcSlave; 00954 00955 /* Check the parameters */ 00956 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); 00957 00958 /* Process locked */ 00959 __HAL_LOCK(hadc); 00960 00961 00962 /* 1. Stop potential multimode conversion on going, on regular and injected groups */ 00963 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); 00964 00965 /* Disable ADC peripheral if conversions are effectively stopped */ 00966 if (tmp_hal_status == HAL_OK) 00967 { 00968 /* Set a temporary handle of the ADC slave associated to the ADC master */ 00969 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 00970 00971 if (tmphadcSlave.Instance == NULL) 00972 { 00973 /* Update ADC state machine to error */ 00974 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 00975 00976 /* Process unlocked */ 00977 __HAL_UNLOCK(hadc); 00978 00979 return HAL_ERROR; 00980 } 00981 00982 /* Procedure to disable the ADC peripheral: wait for conversions */ 00983 /* effectively stopped (ADC master and ADC slave), then disable ADC */ 00984 00985 /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/ 00986 tickstart = HAL_GetTick(); 00987 00988 while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) || 00989 ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) ) 00990 { 00991 if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT) 00992 { 00993 /* Update ADC state machine to error */ 00994 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 00995 00996 /* Process unlocked */ 00997 __HAL_UNLOCK(hadc); 00998 00999 return HAL_ERROR; 01000 } 01001 } 01002 01003 /* Disable the DMA channel (in case of DMA in circular mode or stop */ 01004 /* while DMA transfer is on going) */ 01005 /* Note: DMA channel of ADC slave should be stopped after this function */ 01006 /* with HAL_ADC_Stop_DMA() API. */ 01007 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); 01008 01009 /* Check if DMA channel effectively disabled */ 01010 if (tmp_hal_status == HAL_ERROR) 01011 { 01012 /* Update ADC state machine to error */ 01013 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 01014 } 01015 01016 /* Disable ADC overrun interrupt */ 01017 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); 01018 01019 /* 2. Disable the ADC peripherals: master and slave */ 01020 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */ 01021 /* memory a potential failing status. */ 01022 if (tmp_hal_status == HAL_OK) 01023 { 01024 /* Check if ADC are effectively disabled */ 01025 if ((ADC_Disable(hadc) == HAL_OK) && 01026 (ADC_Disable(&tmphadcSlave) == HAL_OK) ) 01027 { 01028 tmp_hal_status = HAL_OK; 01029 } 01030 } 01031 else 01032 { 01033 ADC_Disable(hadc); 01034 ADC_Disable(&tmphadcSlave); 01035 } 01036 01037 /* Set ADC state (ADC master) */ 01038 ADC_STATE_CLR_SET(hadc->State, 01039 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 01040 HAL_ADC_STATE_READY); 01041 } 01042 01043 /* Process unlocked */ 01044 __HAL_UNLOCK(hadc); 01045 01046 /* Return function status */ 01047 return tmp_hal_status; 01048 } 01049 01050 /** 01051 * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration. 01052 * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used) 01053 * @retval The converted data values. 01054 */ 01055 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) 01056 { 01057 ADC_Common_TypeDef *tmpADC_Common; 01058 01059 /* Check the parameters */ 01060 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); 01061 01062 /* Prevent unused argument(s) compilation warning if no assert_param check */ 01063 /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */ 01064 UNUSED(hadc); 01065 01066 /* Pointer to the common control register */ 01067 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); 01068 01069 /* Return the multi mode conversion value */ 01070 return tmpADC_Common->CDR; 01071 } 01072 #endif /* ADC_MULTIMODE_SUPPORT */ 01073 01074 /** 01075 * @brief Get ADC injected group conversion result. 01076 * @note Reading register JDRx automatically clears ADC flag JEOC 01077 * (ADC group injected end of unitary conversion). 01078 * @note This function does not clear ADC flag JEOS 01079 * (ADC group injected end of sequence conversion) 01080 * Occurrence of flag JEOS rising: 01081 * - If sequencer is composed of 1 rank, flag JEOS is equivalent 01082 * to flag JEOC. 01083 * - If sequencer is composed of several ranks, during the scan 01084 * sequence flag JEOC only is raised, at the end of the scan sequence 01085 * both flags JEOC and EOS are raised. 01086 * Flag JEOS must not be cleared by this function because 01087 * it would not be compliant with low power features 01088 * (feature low power auto-wait, not available on all STM32 families). 01089 * To clear this flag, either use function: 01090 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming 01091 * model polling: @ref HAL_ADCEx_InjectedPollForConversion() 01092 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). 01093 * @param hadc ADC handle 01094 * @param InjectedRank the converted ADC injected rank. 01095 * This parameter can be one of the following values: 01096 * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1 01097 * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2 01098 * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3 01099 * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4 01100 * @retval ADC group injected conversion data 01101 */ 01102 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) 01103 { 01104 uint32_t tmp_jdr = 0; 01105 01106 /* Check the parameters */ 01107 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 01108 assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); 01109 01110 /* Get ADC converted value */ 01111 switch(InjectedRank) 01112 { 01113 case ADC_INJECTED_RANK_4: 01114 tmp_jdr = hadc->Instance->JDR4; 01115 break; 01116 case ADC_INJECTED_RANK_3: 01117 tmp_jdr = hadc->Instance->JDR3; 01118 break; 01119 case ADC_INJECTED_RANK_2: 01120 tmp_jdr = hadc->Instance->JDR2; 01121 break; 01122 case ADC_INJECTED_RANK_1: 01123 default: 01124 tmp_jdr = hadc->Instance->JDR1; 01125 break; 01126 } 01127 01128 /* Return ADC converted value */ 01129 return tmp_jdr; 01130 } 01131 01132 /** 01133 * @brief Injected conversion complete callback in non-blocking mode. 01134 * @param hadc ADC handle 01135 * @retval None 01136 */ 01137 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) 01138 { 01139 /* Prevent unused argument(s) compilation warning */ 01140 UNUSED(hadc); 01141 01142 /* NOTE : This function should not be modified. When the callback is needed, 01143 function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file. 01144 */ 01145 } 01146 01147 /** 01148 * @brief Injected context queue overflow callback. 01149 * @note This callback is called if injected context queue is enabled 01150 (parameter "QueueInjectedContext" in injected channel configuration) 01151 and if a new injected context is set when queue is full (maximum 2 01152 contexts). 01153 * @param hadc ADC handle 01154 * @retval None 01155 */ 01156 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc) 01157 { 01158 /* Prevent unused argument(s) compilation warning */ 01159 UNUSED(hadc); 01160 01161 /* NOTE : This function should not be modified. When the callback is needed, 01162 function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file. 01163 */ 01164 } 01165 01166 /** 01167 * @brief Analog watchdog 2 callback in non-blocking mode. 01168 * @param hadc ADC handle 01169 * @retval None 01170 */ 01171 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc) 01172 { 01173 /* Prevent unused argument(s) compilation warning */ 01174 UNUSED(hadc); 01175 01176 /* NOTE : This function should not be modified. When the callback is needed, 01177 function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file. 01178 */ 01179 } 01180 01181 /** 01182 * @brief Analog watchdog 3 callback in non-blocking mode. 01183 * @param hadc ADC handle 01184 * @retval None 01185 */ 01186 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc) 01187 { 01188 /* Prevent unused argument(s) compilation warning */ 01189 UNUSED(hadc); 01190 01191 /* NOTE : This function should not be modified. When the callback is needed, 01192 function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file. 01193 */ 01194 } 01195 01196 01197 /** 01198 * @brief End Of Sampling callback in non-blocking mode. 01199 * @param hadc ADC handle 01200 * @retval None 01201 */ 01202 __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc) 01203 { 01204 /* Prevent unused argument(s) compilation warning */ 01205 UNUSED(hadc); 01206 01207 /* NOTE : This function should not be modified. When the callback is needed, 01208 function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file. 01209 */ 01210 } 01211 01212 /** 01213 * @brief Stop ADC conversion of regular group (and injected channels in 01214 * case of auto_injection mode), disable ADC peripheral if no 01215 * conversion is on going on injected group. 01216 * @param hadc ADC handle 01217 * @retval HAL status. 01218 */ 01219 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) 01220 { 01221 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 01222 01223 /* Check the parameters */ 01224 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 01225 01226 /* Process locked */ 01227 __HAL_LOCK(hadc); 01228 01229 /* 1. Stop potential regular conversion on going */ 01230 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); 01231 01232 /* Disable ADC peripheral if regular conversions are effectively stopped 01233 and if no injected conversions are on-going */ 01234 if (tmp_hal_status == HAL_OK) 01235 { 01236 /* Clear HAL_ADC_STATE_REG_BUSY bit */ 01237 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 01238 01239 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) 01240 { 01241 /* 2. Disable the ADC peripheral */ 01242 tmp_hal_status = ADC_Disable(hadc); 01243 01244 /* Check if ADC is effectively disabled */ 01245 if (tmp_hal_status == HAL_OK) 01246 { 01247 /* Set ADC state */ 01248 ADC_STATE_CLR_SET(hadc->State, 01249 HAL_ADC_STATE_INJ_BUSY, 01250 HAL_ADC_STATE_READY); 01251 } 01252 } 01253 /* Conversion on injected group is stopped, but ADC not disabled since */ 01254 /* conversion on regular group is still running. */ 01255 else 01256 { 01257 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 01258 } 01259 } 01260 01261 /* Process unlocked */ 01262 __HAL_UNLOCK(hadc); 01263 01264 /* Return function status */ 01265 return tmp_hal_status; 01266 } 01267 01268 01269 /** 01270 * @brief Stop ADC conversion of ADC groups regular and injected, 01271 * disable interrution of end-of-conversion, 01272 * disable ADC peripheral if no conversion is on going 01273 * on injected group. 01274 * @param hadc ADC handle 01275 * @retval HAL status. 01276 */ 01277 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc) 01278 { 01279 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 01280 01281 /* Check the parameters */ 01282 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 01283 01284 /* Process locked */ 01285 __HAL_LOCK(hadc); 01286 01287 /* 1. Stop potential regular conversion on going */ 01288 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); 01289 01290 /* Disable ADC peripheral if conversions are effectively stopped 01291 and if no injected conversion is on-going */ 01292 if (tmp_hal_status == HAL_OK) 01293 { 01294 /* Clear HAL_ADC_STATE_REG_BUSY bit */ 01295 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 01296 01297 /* Disable all regular-related interrupts */ 01298 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); 01299 01300 /* 2. Disable ADC peripheral if no injected conversions are on-going */ 01301 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) 01302 { 01303 tmp_hal_status = ADC_Disable(hadc); 01304 /* if no issue reported */ 01305 if (tmp_hal_status == HAL_OK) 01306 { 01307 /* Set ADC state */ 01308 ADC_STATE_CLR_SET(hadc->State, 01309 HAL_ADC_STATE_INJ_BUSY, 01310 HAL_ADC_STATE_READY); 01311 } 01312 } 01313 else 01314 { 01315 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 01316 } 01317 } 01318 01319 /* Process unlocked */ 01320 __HAL_UNLOCK(hadc); 01321 01322 /* Return function status */ 01323 return tmp_hal_status; 01324 } 01325 01326 /** 01327 * @brief Stop ADC conversion of regular group (and injected group in 01328 * case of auto_injection mode), disable ADC DMA transfer, disable 01329 * ADC peripheral if no conversion is on going 01330 * on injected group. 01331 * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. 01332 * For multimode (when multimode feature is available), 01333 * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used. 01334 * @param hadc ADC handle 01335 * @retval HAL status. 01336 */ 01337 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) 01338 { 01339 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 01340 01341 /* Check the parameters */ 01342 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 01343 01344 /* Process locked */ 01345 __HAL_LOCK(hadc); 01346 01347 /* 1. Stop potential regular conversion on going */ 01348 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); 01349 01350 /* Disable ADC peripheral if conversions are effectively stopped 01351 and if no injected conversion is on-going */ 01352 if (tmp_hal_status == HAL_OK) 01353 { 01354 /* Clear HAL_ADC_STATE_REG_BUSY bit */ 01355 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 01356 01357 /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ 01358 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); 01359 01360 /* Disable the DMA channel (in case of DMA in circular mode or stop while */ 01361 /* while DMA transfer is on going) */ 01362 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); 01363 01364 /* Check if DMA channel effectively disabled */ 01365 if (tmp_hal_status != HAL_OK) 01366 { 01367 /* Update ADC state machine to error */ 01368 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 01369 } 01370 01371 /* Disable ADC overrun interrupt */ 01372 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); 01373 01374 /* 2. Disable the ADC peripheral */ 01375 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */ 01376 /* memory a potential failing status. */ 01377 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) 01378 { 01379 if (tmp_hal_status == HAL_OK) 01380 { 01381 tmp_hal_status = ADC_Disable(hadc); 01382 } 01383 else 01384 { 01385 ADC_Disable(hadc); 01386 } 01387 01388 /* Check if ADC is effectively disabled */ 01389 if (tmp_hal_status == HAL_OK) 01390 { 01391 /* Set ADC state */ 01392 ADC_STATE_CLR_SET(hadc->State, 01393 HAL_ADC_STATE_INJ_BUSY, 01394 HAL_ADC_STATE_READY); 01395 } 01396 } 01397 else 01398 { 01399 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 01400 } 01401 } 01402 01403 /* Process unlocked */ 01404 __HAL_UNLOCK(hadc); 01405 01406 /* Return function status */ 01407 return tmp_hal_status; 01408 } 01409 01410 #if defined(ADC_MULTIMODE_SUPPORT) 01411 /** 01412 * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going. 01413 * @note Multimode is kept enabled after this function. Multimode DMA bits 01414 * (MDMA and DMACFG bits of common CCR register) are maintained. To disable 01415 * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be 01416 * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can 01417 * resort to HAL_ADCEx_DisableMultiMode() API. 01418 * @note In case of DMA configured in circular mode, function 01419 * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of 01420 * ADC slave, to properly disable the DMA channel. 01421 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) 01422 * @retval HAL status 01423 */ 01424 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) 01425 { 01426 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 01427 uint32_t tickstart; 01428 ADC_HandleTypeDef tmphadcSlave; 01429 01430 /* Check the parameters */ 01431 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); 01432 01433 /* Process locked */ 01434 __HAL_LOCK(hadc); 01435 01436 01437 /* 1. Stop potential multimode conversion on going, on regular groups */ 01438 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); 01439 01440 /* Disable ADC peripheral if conversions are effectively stopped */ 01441 if (tmp_hal_status == HAL_OK) 01442 { 01443 /* Clear HAL_ADC_STATE_REG_BUSY bit */ 01444 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 01445 01446 /* Set a temporary handle of the ADC slave associated to the ADC master */ 01447 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 01448 01449 if (tmphadcSlave.Instance == NULL) 01450 { 01451 /* Update ADC state machine to error */ 01452 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 01453 01454 /* Process unlocked */ 01455 __HAL_UNLOCK(hadc); 01456 01457 return HAL_ERROR; 01458 } 01459 01460 /* Procedure to disable the ADC peripheral: wait for conversions */ 01461 /* effectively stopped (ADC master and ADC slave), then disable ADC */ 01462 01463 /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/ 01464 tickstart = HAL_GetTick(); 01465 01466 while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) || 01467 ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) ) 01468 { 01469 if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT) 01470 { 01471 /* Update ADC state machine to error */ 01472 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 01473 01474 /* Process unlocked */ 01475 __HAL_UNLOCK(hadc); 01476 01477 return HAL_ERROR; 01478 } 01479 } 01480 01481 /* Disable the DMA channel (in case of DMA in circular mode or stop */ 01482 /* while DMA transfer is on going) */ 01483 /* Note: DMA channel of ADC slave should be stopped after this function */ 01484 /* with HAL_ADCEx_RegularStop_DMA() API. */ 01485 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); 01486 01487 /* Check if DMA channel effectively disabled */ 01488 if (tmp_hal_status != HAL_OK) 01489 { 01490 /* Update ADC state machine to error */ 01491 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 01492 } 01493 01494 /* Disable ADC overrun interrupt */ 01495 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); 01496 01497 /* 2. Disable the ADC peripherals: master and slave if no injected */ 01498 /* conversion is on-going. */ 01499 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */ 01500 /* memory a potential failing status. */ 01501 if (tmp_hal_status == HAL_OK) 01502 { 01503 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) 01504 { 01505 tmp_hal_status = ADC_Disable(hadc); 01506 if (tmp_hal_status == HAL_OK) 01507 { 01508 if (ADC_IS_CONVERSION_ONGOING_INJECTED(&tmphadcSlave) == RESET) 01509 { 01510 tmp_hal_status = ADC_Disable(&tmphadcSlave); 01511 } 01512 } 01513 } 01514 01515 if (tmp_hal_status == HAL_OK) 01516 { 01517 /* Both Master and Slave ADC's could be disabled. Update Master State */ 01518 /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */ 01519 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); 01520 } 01521 else 01522 { 01523 /* injected (Master or Slave) conversions are still on-going, 01524 no Master State change */ 01525 } 01526 } 01527 } 01528 01529 /* Process unlocked */ 01530 __HAL_UNLOCK(hadc); 01531 01532 /* Return function status */ 01533 return tmp_hal_status; 01534 } 01535 #endif /* ADC_MULTIMODE_SUPPORT */ 01536 01537 /** 01538 * @} 01539 */ 01540 01541 /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions 01542 * @brief ADC Extended Peripheral Control functions 01543 * 01544 @verbatim 01545 =============================================================================== 01546 ##### Peripheral Control functions ##### 01547 =============================================================================== 01548 [..] This section provides functions allowing to: 01549 (+) Configure channels on injected group 01550 (+) Configure multimode when multimode feature is available 01551 (+) Enable or Disable Injected Queue 01552 (+) Disable ADC voltage regulator 01553 (+) Enter ADC deep-power-down mode 01554 01555 @endverbatim 01556 * @{ 01557 */ 01558 01559 /** 01560 * @brief Configure a channel to be assigned to ADC group injected. 01561 * @note Possibility to update parameters on the fly: 01562 * This function initializes injected group, following calls to this 01563 * function can be used to reconfigure some parameters of structure 01564 * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC. 01565 * The setting of these parameters is conditioned to ADC state: 01566 * Refer to comments of structure "ADC_InjectionConfTypeDef". 01567 * @note In case of usage of internal measurement channels: 01568 * Vbat/VrefInt/TempSensor. 01569 * These internal paths can be disabled using function 01570 * HAL_ADC_DeInit(). 01571 * @note Caution: For Injected Context Queue use, a context must be fully 01572 * defined before start of injected conversion. All channels are configured 01573 * consecutively for the same ADC instance. Therefore, the number of calls to 01574 * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter 01575 * InjectedNbrOfConversion for each context. 01576 * - Example 1: If 1 context is intended to be used (or if there is no use of the 01577 * Injected Queue Context feature) and if the context contains 3 injected ranks 01578 * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be 01579 * called once for each channel (i.e. 3 times) before starting a conversion. 01580 * This function must not be called to configure a 4th injected channel: 01581 * it would start a new context into context queue. 01582 * - Example 2: If 2 contexts are intended to be used and each of them contains 01583 * 3 injected ranks (InjectedNbrOfConversion = 3), 01584 * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and 01585 * for each context (3 channels x 2 contexts = 6 calls). Conversion can 01586 * start once the 1st context is set, that is after the first three 01587 * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly. 01588 * @param hadc ADC handle 01589 * @param sConfigInjected Structure of ADC injected group and ADC channel for 01590 * injected group. 01591 * @retval HAL status 01592 */ 01593 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) 01594 { 01595 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 01596 uint32_t tmpOffsetShifted; 01597 uint32_t wait_loop_index = 0U; 01598 01599 uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U; 01600 01601 /* Check the parameters */ 01602 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 01603 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); 01604 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff)); 01605 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); 01606 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext)); 01607 assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); 01608 assert_param(IS_ADC_EXTTRIGINJEC(hadc, sConfigInjected->ExternalTrigInjecConv)); 01609 assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber)); 01610 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset)); 01611 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode)); 01612 01613 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 01614 { 01615 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); 01616 assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); 01617 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); 01618 } 01619 01620 01621 /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is 01622 ignored (considered as reset) */ 01623 assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE))); 01624 01625 /* JDISCEN and JAUTO bits can't be set at the same time */ 01626 assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); 01627 01628 /* DISCEN and JAUTO bits can't be set at the same time */ 01629 assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); 01630 01631 /* Verification of channel number */ 01632 if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) 01633 { 01634 assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel)); 01635 } 01636 else 01637 { 01638 assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel)); 01639 } 01640 01641 /* Process locked */ 01642 __HAL_LOCK(hadc); 01643 01644 /* Configuration of injected group sequencer: */ 01645 /* Hardware constraint: Must fully define injected context register JSQR */ 01646 /* before make it entering into injected sequencer queue. */ 01647 /* */ 01648 /* - if scan mode is disabled: */ 01649 /* * Injected channels sequence length is set to 0x00: 1 channel */ 01650 /* converted (channel on injected rank 1) */ 01651 /* Parameter "InjectedNbrOfConversion" is discarded. */ 01652 /* * Injected context register JSQR setting is simple: register is fully */ 01653 /* defined on one call of this function (for injected rank 1) and can */ 01654 /* be entered into queue directly. */ 01655 /* - if scan mode is enabled: */ 01656 /* * Injected channels sequence length is set to parameter */ 01657 /* "InjectedNbrOfConversion". */ 01658 /* * Injected context register JSQR setting more complex: register is */ 01659 /* fully defined over successive calls of this function, for each */ 01660 /* injected channel rank. It is entered into queue only when all */ 01661 /* injected ranks have been set. */ 01662 /* Note: Scan mode is not present by hardware on this device, but used */ 01663 /* by software for alignment over all STM32 devices. */ 01664 01665 if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) || 01666 (sConfigInjected->InjectedNbrOfConversion == 1U) ) 01667 { 01668 /* Configuration of context register JSQR: */ 01669 /* - number of ranks in injected group sequencer: fixed to 1st rank */ 01670 /* (scan mode disabled, only rank 1 used) */ 01671 /* - external trigger to start conversion */ 01672 /* - external trigger polarity */ 01673 /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */ 01674 01675 if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) 01676 { 01677 /* Enable external trigger if trigger selection is different of */ 01678 /* software start. */ 01679 /* Note: This configuration keeps the hardware feature of parameter */ 01680 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ 01681 /* software start. */ 01682 if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) 01683 { 01684 tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) 01685 | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) 01686 | sConfigInjected->ExternalTrigInjecConvEdge 01687 ); 01688 } 01689 else 01690 { 01691 tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) ); 01692 } 01693 01694 MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt); 01695 /* For debug and informative reasons, hadc handle saves JSQR setting */ 01696 hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt; 01697 01698 } 01699 } 01700 else 01701 { 01702 /* Case of scan mode enabled, several channels to set into injected group */ 01703 /* sequencer. */ 01704 /* */ 01705 /* Procedure to define injected context register JSQR over successive */ 01706 /* calls of this function, for each injected channel rank: */ 01707 /* 1. Start new context and set parameters related to all injected */ 01708 /* channels: injected sequence length and trigger. */ 01709 01710 /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */ 01711 /* call of the context under setting */ 01712 if (hadc->InjectionConfig.ChannelCount == 0U) 01713 { 01714 /* Initialize number of channels that will be configured on the context */ 01715 /* being built */ 01716 hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion; 01717 /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel() 01718 call, this context will be written in JSQR register at the last call. 01719 At this point, the context is merely reset */ 01720 hadc->InjectionConfig.ContextQueue = 0x00000000U; 01721 01722 /* Configuration of context register JSQR: */ 01723 /* - number of ranks in injected group sequencer */ 01724 /* - external trigger to start conversion */ 01725 /* - external trigger polarity */ 01726 01727 /* Enable external trigger if trigger selection is different of */ 01728 /* software start. */ 01729 /* Note: This configuration keeps the hardware feature of parameter */ 01730 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ 01731 /* software start. */ 01732 if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) 01733 { 01734 tmp_JSQR_ContextQueueBeingBuilt = ( (sConfigInjected->InjectedNbrOfConversion - 1U) 01735 | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) 01736 | sConfigInjected->ExternalTrigInjecConvEdge 01737 ); 01738 } 01739 else 01740 { 01741 tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U) ); 01742 } 01743 01744 } 01745 01746 /* 2. Continue setting of context under definition with parameter */ 01747 /* related to each channel: channel rank sequence */ 01748 /* Clear the old JSQx bits for the selected rank */ 01749 tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank); 01750 01751 /* Set the JSQx bits for the selected rank */ 01752 tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank); 01753 01754 /* Decrease channel count */ 01755 hadc->InjectionConfig.ChannelCount--; 01756 01757 /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel() 01758 call, aggregate the setting to those already built during the previous 01759 HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */ 01760 hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt; 01761 01762 /* 4. End of context setting: if this is the last channel set, then write context 01763 into register JSQR and make it enter into queue */ 01764 if (hadc->InjectionConfig.ChannelCount == 0U) 01765 { 01766 MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue); 01767 } 01768 } 01769 01770 /* Parameters update conditioned to ADC state: */ 01771 /* Parameters that can be updated when ADC is disabled or enabled without */ 01772 /* conversion on going on injected group: */ 01773 /* - Injected context queue: Queue disable (active context is kept) or */ 01774 /* enable (context decremented, up to 2 contexts queued) */ 01775 /* - Injected discontinuous mode: can be enabled only if auto-injected */ 01776 /* mode is disabled. */ 01777 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) 01778 { 01779 /* If auto-injected mode is disabled: no constraint */ 01780 if (sConfigInjected->AutoInjectedConv == DISABLE) 01781 { 01782 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, 01783 ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) | 01784 ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) ); 01785 } 01786 /* If auto-injected mode is enabled: Injected discontinuous setting is */ 01787 /* discarded. */ 01788 else 01789 { 01790 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, 01791 ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) ); 01792 } 01793 01794 } 01795 01796 /* Parameters update conditioned to ADC state: */ 01797 /* Parameters that can be updated when ADC is disabled or enabled without */ 01798 /* conversion on going on regular and injected groups: */ 01799 /* - Automatic injected conversion: can be enabled if injected group */ 01800 /* external triggers are disabled. */ 01801 /* - Channel sampling time */ 01802 /* - Channel offset */ 01803 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) 01804 { 01805 /* If injected group external triggers are disabled (set to injected */ 01806 /* software start): no constraint */ 01807 if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) 01808 || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) 01809 { 01810 if (sConfigInjected->AutoInjectedConv == ENABLE) 01811 { 01812 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); 01813 } 01814 else 01815 { 01816 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); 01817 } 01818 } 01819 /* If Automatic injected conversion was intended to be set and could not */ 01820 /* due to injected group external triggers enabled, error is reported. */ 01821 else 01822 { 01823 if (sConfigInjected->AutoInjectedConv == ENABLE) 01824 { 01825 /* Update ADC state machine to error */ 01826 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 01827 01828 tmp_hal_status = HAL_ERROR; 01829 } 01830 else 01831 { 01832 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); 01833 } 01834 } 01835 01836 if (sConfigInjected->InjecOversamplingMode == ENABLE) 01837 { 01838 assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio)); 01839 assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift)); 01840 01841 /* JOVSE must be reset in case of triggered regular mode */ 01842 assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS))); 01843 01844 /* Configuration of Injected Oversampler: */ 01845 /* - Oversampling Ratio */ 01846 /* - Right bit shift */ 01847 01848 /* Enable OverSampling mode */ 01849 MODIFY_REG(hadc->Instance->CFGR2, 01850 ADC_CFGR2_JOVSE | 01851 ADC_CFGR2_OVSR | 01852 ADC_CFGR2_OVSS, 01853 ADC_CFGR2_JOVSE | 01854 sConfigInjected->InjecOversampling.Ratio | 01855 sConfigInjected->InjecOversampling.RightBitShift 01856 ); 01857 } 01858 else 01859 { 01860 /* Disable Regular OverSampling */ 01861 CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_JOVSE); 01862 } 01863 01864 #if defined(ADC_SMPR1_SMPPLUS) 01865 /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ 01866 if(sConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5) 01867 { 01868 /* Set sampling time of the selected ADC channel */ 01869 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5); 01870 01871 /* Set ADC sampling time common configuration */ 01872 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); 01873 } 01874 else 01875 { 01876 /* Set sampling time of the selected ADC channel */ 01877 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime); 01878 01879 /* Set ADC sampling time common configuration */ 01880 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); 01881 } 01882 #else 01883 /* Set sampling time of the selected ADC channel */ 01884 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime); 01885 #endif 01886 01887 /* Configure the offset: offset enable/disable, channel, offset value */ 01888 01889 /* Shift the offset with respect to the selected ADC resolution. */ 01890 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ 01891 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset); 01892 01893 if(sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) 01894 { 01895 /* Set ADC selected offset number */ 01896 LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, tmpOffsetShifted); 01897 01898 } 01899 else 01900 { 01901 /* Scan each offset register to check if the selected channel is targeted. */ 01902 /* If this is the case, the corresponding offset number is disabled. */ 01903 if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) 01904 { 01905 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); 01906 } 01907 if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) 01908 { 01909 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); 01910 } 01911 if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) 01912 { 01913 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); 01914 } 01915 if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) 01916 { 01917 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); 01918 } 01919 } 01920 01921 } 01922 01923 /* Parameters update conditioned to ADC state: */ 01924 /* Parameters that can be updated only when ADC is disabled: */ 01925 /* - Single or differential mode */ 01926 if (ADC_IS_ENABLE(hadc) == RESET) 01927 { 01928 /* Set mode single-ended or differential input of the selected ADC channel */ 01929 LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff); 01930 01931 /* Configuration of differential mode */ 01932 if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) 01933 { 01934 /* Set sampling time of the selected ADC channel */ 01935 LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) + 1), sConfigInjected->InjectedSamplingTime); 01936 } 01937 01938 } 01939 01940 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ 01941 /* internal measurement paths enable: If internal channel selected, */ 01942 /* enable dedicated internal buffers and path. */ 01943 /* Note: these internal measurement paths can be disabled using */ 01944 /* HAL_ADC_DeInit(). */ 01945 01946 /* Configuration of common ADC parameters */ 01947 /* If the requested internal measurement path has already been enabled, */ 01948 /* bypass the configuration processing. */ 01949 if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && 01950 ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) || 01951 ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && 01952 ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) || 01953 ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && 01954 ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U)) 01955 ) 01956 { 01957 if (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) 01958 { 01959 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 01960 { 01961 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); 01962 01963 /* Delay for temperature sensor stabilization time */ 01964 /* Compute number of CPU cycles to wait for */ 01965 wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / 1000000)); 01966 while(wait_loop_index != 0) 01967 { 01968 wait_loop_index--; 01969 } 01970 } 01971 } 01972 else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) 01973 { 01974 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 01975 { 01976 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); 01977 } 01978 } 01979 else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) 01980 { 01981 if (ADC_VREFINT_INSTANCE(hadc)) 01982 { 01983 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); 01984 } 01985 } 01986 } 01987 01988 /* Process unlocked */ 01989 __HAL_UNLOCK(hadc); 01990 01991 /* Return function status */ 01992 return tmp_hal_status; 01993 } 01994 01995 #if defined(ADC_MULTIMODE_SUPPORT) 01996 /** 01997 * @brief Enable ADC multimode and configure multimode parameters 01998 * @note Possibility to update parameters on the fly: 01999 * This function initializes multimode parameters, following 02000 * calls to this function can be used to reconfigure some parameters 02001 * of structure "ADC_MultiModeTypeDef" on the fly, without resetting 02002 * the ADCs. 02003 * The setting of these parameters is conditioned to ADC state. 02004 * For parameters constraints, see comments of structure 02005 * "ADC_MultiModeTypeDef". 02006 * @note To move back configuration from multimode to single mode, ADC must 02007 * be reset (using function HAL_ADC_Init() ). 02008 * @param hadc Master ADC handle 02009 * @param multimode Structure of ADC multimode configuration 02010 * @retval HAL status 02011 */ 02012 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) 02013 { 02014 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 02015 ADC_Common_TypeDef *tmpADC_Common; 02016 ADC_HandleTypeDef tmphadcSlave; 02017 02018 /* Check the parameters */ 02019 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); 02020 assert_param(IS_ADC_MULTIMODE(multimode->Mode)); 02021 if(multimode->Mode != ADC_MODE_INDEPENDENT) 02022 { 02023 assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode)); 02024 assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); 02025 } 02026 02027 /* Process locked */ 02028 __HAL_LOCK(hadc); 02029 02030 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 02031 02032 if (tmphadcSlave.Instance == NULL) 02033 { 02034 /* Update ADC state machine to error */ 02035 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 02036 02037 /* Process unlocked */ 02038 __HAL_UNLOCK(hadc); 02039 02040 return HAL_ERROR; 02041 } 02042 02043 /* Parameters update conditioned to ADC state: */ 02044 /* Parameters that can be updated when ADC is disabled or enabled without */ 02045 /* conversion on going on regular group: */ 02046 /* - Multimode DMA configuration */ 02047 /* - Multimode DMA mode */ 02048 if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 02049 && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) == RESET) ) 02050 { 02051 /* Pointer to the common control register */ 02052 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); 02053 02054 /* If multimode is selected, configure all multimode paramaters. */ 02055 /* Otherwise, reset multimode parameters (can be used in case of */ 02056 /* transition from multimode to independent mode). */ 02057 if(multimode->Mode != ADC_MODE_INDEPENDENT) 02058 { 02059 MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, 02060 multimode->DMAAccessMode | 02061 ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests)); 02062 02063 /* Parameters that can be updated only when ADC is disabled: */ 02064 /* - Multimode mode selection */ 02065 /* - Multimode delay */ 02066 /* Note: Delay range depends on selected resolution: */ 02067 /* from 1 to 12 clock cycles for 12 bits */ 02068 /* from 1 to 10 clock cycles for 10 bits, */ 02069 /* from 1 to 8 clock cycles for 8 bits */ 02070 /* from 1 to 6 clock cycles for 6 bits */ 02071 /* If a higher delay is selected, it will be clipped to maximum delay */ 02072 /* range */ 02073 if ((ADC_IS_ENABLE(hadc) == RESET) && 02074 (ADC_IS_ENABLE(&tmphadcSlave) == RESET) ) 02075 { 02076 MODIFY_REG(tmpADC_Common->CCR, 02077 ADC_CCR_DUAL | 02078 ADC_CCR_DELAY, 02079 multimode->Mode | 02080 multimode->TwoSamplingDelay 02081 ); 02082 } 02083 } 02084 else /* ADC_MODE_INDEPENDENT */ 02085 { 02086 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG); 02087 02088 /* Parameters that can be updated only when ADC is disabled: */ 02089 /* - Multimode mode selection */ 02090 /* - Multimode delay */ 02091 if ((ADC_IS_ENABLE(hadc) == RESET) && 02092 (ADC_IS_ENABLE(&tmphadcSlave) == RESET) ) 02093 { 02094 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); 02095 } 02096 } 02097 } 02098 /* If one of the ADC sharing the same common group is enabled, no update */ 02099 /* could be done on neither of the multimode structure parameters. */ 02100 else 02101 { 02102 /* Update ADC state machine to error */ 02103 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 02104 02105 tmp_hal_status = HAL_ERROR; 02106 } 02107 02108 /* Process unlocked */ 02109 __HAL_UNLOCK(hadc); 02110 02111 /* Return function status */ 02112 return tmp_hal_status; 02113 } 02114 #endif /* ADC_MULTIMODE_SUPPORT */ 02115 02116 /** 02117 * @brief Enable Injected Queue 02118 * @note This function resets CFGR register JQDIS bit in order to enable the 02119 * Injected Queue. JQDIS can be written only when ADSTART and JDSTART 02120 * are both equal to 0 to ensure that no regular nor injected 02121 * conversion is ongoing. 02122 * @param hadc ADC handle 02123 * @retval HAL status 02124 */ 02125 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc) 02126 { 02127 /* Parameter can be set only if no conversion is on-going */ 02128 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) 02129 { 02130 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); 02131 02132 /* Update state, clear previous result related to injected queue overflow */ 02133 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); 02134 02135 return HAL_OK; 02136 } 02137 else 02138 { 02139 return HAL_ERROR; 02140 } 02141 } 02142 02143 /** 02144 * @brief Disable Injected Queue 02145 * @note This function sets CFGR register JQDIS bit in order to disable the 02146 * Injected Queue. JQDIS can be written only when ADSTART and JDSTART 02147 * are both equal to 0 to ensure that no regular nor injected 02148 * conversion is ongoing. 02149 * @param hadc ADC handle 02150 * @retval HAL status 02151 */ 02152 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc) 02153 { 02154 /* Parameter can be set only if no conversion is on-going */ 02155 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) 02156 { 02157 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); 02158 return HAL_OK; 02159 } 02160 else 02161 { 02162 return HAL_ERROR; 02163 } 02164 } 02165 02166 /** 02167 * @brief Disable ADC voltage regulator. 02168 * @note Disabling voltage regulator allows to save power. This operation can 02169 * be carried out only when ADC is disabled. 02170 * @note To enable again the voltage regulator, the user is expected to 02171 * resort to HAL_ADC_Init() API. 02172 * @param hadc ADC handle 02173 * @retval HAL status 02174 */ 02175 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc) 02176 { 02177 /* ADVREGEN can be written only when the ADC is disabled */ 02178 if (ADC_IS_ENABLE(hadc) == RESET) 02179 { 02180 CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN); 02181 return HAL_OK; 02182 } 02183 else 02184 { 02185 return HAL_ERROR; 02186 } 02187 } 02188 02189 /** 02190 * @brief Enter ADC deep-power-down mode 02191 * @note This mode is achieved in setting DEEPPWD bit and allows to save power 02192 * in reducing leakage currents. It is particularly interesting before 02193 * entering stop modes. 02194 * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the 02195 * ADC voltage regulator. This means that this API encompasses 02196 * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal 02197 * calibration is lost. 02198 * @note To exit the ADC deep-power-down mode, the user is expected to 02199 * resort to HAL_ADC_Init() API as well as to relaunch a calibration 02200 * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously 02201 * saved calibration factor. 02202 * @param hadc ADC handle 02203 * @retval HAL status 02204 */ 02205 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc) 02206 { 02207 /* DEEPPWD can be written only when the ADC is disabled */ 02208 if (ADC_IS_ENABLE(hadc) == RESET) 02209 { 02210 SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); 02211 return HAL_OK; 02212 } 02213 else 02214 { 02215 return HAL_ERROR; 02216 } 02217 } 02218 02219 /** 02220 * @} 02221 */ 02222 02223 /** 02224 * @} 02225 */ 02226 02227 #endif /* HAL_ADC_MODULE_ENABLED */ 02228 /** 02229 * @} 02230 */ 02231 02232 /** 02233 * @} 02234 */ 02235 02236 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/