System Configuration functions. More...

Functions
void	LL_SetSystemCoreClock (uint32_t HCLKFrequency)
	This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus	LL_PLL_ConfigSystemClock_MSI (LL_UTILS_PLLInitTypeDef UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct)
	This function configures system clock with MSI as clock source of the PLL.
ErrorStatus	LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct)
	This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus	LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct)
	This function configures system clock with HSE as clock source of the PLL.

Detailed Description

System Configuration functions.

 ===============================================================================
           ##### System Configuration functions #####
 ===============================================================================
    [..]
         System, AHB and APB buses clocks configuration

         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 
             120000000 Hz for STM32L4Rx/STM32L4Sx devices and 80000000 Hz for others.

Function Documentation

ErrorStatus LL_PLL_ConfigSystemClock_HSE	(	uint32_t	HSEFrequency,
		uint32_t	HSEBypass,
		LL_UTILS_PLLInitTypeDef *	UTILS_PLLInitStruct,
		LL_UTILS_ClkInitTypeDef *	UTILS_ClkInitStruct
	)

This function configures system clock with HSE as clock source of the PLL.

Note:

The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.

Function is based on the following formula:

PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)
PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
PLLR: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLR)

Parameters:

HSEFrequency	Value between Min_Data = 4000000 and Max_Data = 48000000
HSEBypass	This parameter can be one of the following values: LL_UTILS_HSEBYPASS_ON LL_UTILS_HSEBYPASS_OFF
UTILS_PLLInitStruct	pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct	pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.

Return values:

An	ErrorStatus enumeration value: SUCCESS: Max frequency configuration done ERROR: Max frequency configuration not done

Definition at line 521 of file stm32l4xx_ll_utils.c.

References LL_UTILS_ClkInitTypeDef::AHBCLKDivider, assert_param, IS_LL_UTILS_HSE_BYPASS, IS_LL_UTILS_HSE_FREQUENCY, LL_RCC_HSE_DisableBypass(), LL_RCC_HSE_Enable(), LL_RCC_HSE_EnableBypass(), LL_RCC_HSE_IsReady(), LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_HSE, LL_RCC_SetAHBPrescaler(), LL_RCC_SYSCLK_DIV_1, LL_RCC_SYSCLK_DIV_2, LL_UTILS_HSEBYPASS_ON, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLR, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

ErrorStatus LL_PLL_ConfigSystemClock_HSI	(	LL_UTILS_PLLInitTypeDef *	UTILS_PLLInitStruct,
		LL_UTILS_ClkInitTypeDef *	UTILS_ClkInitStruct
	)

This function configures system clock at maximum frequency with HSI as clock source of the PLL.

Note:

The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.

Function is based on the following formula:

PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
PLLR: ensure that max frequency at 120000000 Hz is reach (PLLVCO_output / PLLR)

Parameters:

UTILS_PLLInitStruct	pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct	pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.

Return values:

An	ErrorStatus enumeration value: SUCCESS: Max frequency configuration done ERROR: Max frequency configuration not done

Definition at line 440 of file stm32l4xx_ll_utils.c.

References LL_UTILS_ClkInitTypeDef::AHBCLKDivider, HSI_VALUE, LL_RCC_HSI_Enable(), LL_RCC_HSI_IsReady(), LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_HSI, LL_RCC_SetAHBPrescaler(), LL_RCC_SYSCLK_DIV_1, LL_RCC_SYSCLK_DIV_2, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLR, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

ErrorStatus LL_PLL_ConfigSystemClock_MSI	(	LL_UTILS_PLLInitTypeDef *	UTILS_PLLInitStruct,
		LL_UTILS_ClkInitTypeDef *	UTILS_ClkInitStruct
	)

This function configures system clock with MSI as clock source of the PLL.

Note:

The application needs to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.

Function is based on the following formula:

PLL output frequency = (((MSI frequency / PLLM) * PLLN) / PLLR)
PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = MSI frequency / PLLM)
PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
PLLR: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLR)

Parameters:

UTILS_PLLInitStruct	pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct	pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.

Return values:

An	ErrorStatus enumeration value: SUCCESS: Max frequency configuration done ERROR: Max frequency configuration not done

Definition at line 314 of file stm32l4xx_ll_utils.c.

References __LL_RCC_CALC_MSI_FREQ, LL_UTILS_ClkInitTypeDef::AHBCLKDivider, LL_RCC_MSI_Enable(), LL_RCC_MSI_GetRange(), LL_RCC_MSI_GetRangeAfterStandby(), LL_RCC_MSI_IsEnabledRangeSelect(), LL_RCC_MSI_IsReady(), LL_RCC_MSIRANGE_0, LL_RCC_MSIRANGE_1, LL_RCC_MSIRANGE_10, LL_RCC_MSIRANGE_11, LL_RCC_MSIRANGE_2, LL_RCC_MSIRANGE_3, LL_RCC_MSIRANGE_4, LL_RCC_MSIRANGE_5, LL_RCC_MSIRANGE_6, LL_RCC_MSIRANGE_7, LL_RCC_MSIRANGE_8, LL_RCC_MSIRANGE_9, LL_RCC_MSISRANGE_4, LL_RCC_MSISRANGE_5, LL_RCC_MSISRANGE_6, LL_RCC_MSISRANGE_7, LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_MSI, LL_RCC_SetAHBPrescaler(), LL_RCC_SYSCLK_DIV_1, LL_RCC_SYSCLK_DIV_2, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLR, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

void LL_SetSystemCoreClock ( uint32_t HCLKFrequency )

This function sets directly SystemCoreClock CMSIS variable.

Note:: Variable can be calculated also through SystemCoreClockUpdate function.

Parameters:

HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)

Return values:

None

Definition at line 292 of file stm32l4xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Functions

Detailed Description

Function Documentation