HAL state structure definition

HAL State structure definition. More...

Enumerations
enum	HAL_I2C_StateTypeDef {   HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,   HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,   HAL_I2C_STATE_ABORT = 0x60U, HAL_I2C_STATE_TIMEOUT = 0xA0U, HAL_I2C_STATE_ERROR = 0xE0U }

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Detailed Description

HAL State structure definition.

Note:

HAL I2C State value coding follow below described bitmap :
b7-b6 Error information
00 : No Error
01 : Abort (Abort user request on going)
10 : Timeout
11 : Error
b5 IP initilisation status
0 : Reset (IP not initialized)
1 : Init done (IP initialized and ready to use. HAL I2C Init function called)
b4 (not used)
x : Should be set to 0
b3
0 : Ready or Busy (No Listen mode ongoing)
1 : Listen (IP in Address Listen Mode)
b2 Intrinsic process state
0 : Ready
1 : Busy (IP busy with some configuration or internal operations)
b1 Rx state
0 : Ready (no Rx operation ongoing)
1 : Busy (Rx operation ongoing)
b0 Tx state
0 : Ready (no Tx operation ongoing)
1 : Busy (Tx operation ongoing)

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Enumeration Type Documentation

enum HAL_I2C_StateTypeDef

Enumerator:

HAL_I2C_STATE_RESET	Peripheral is not yet Initialized
HAL_I2C_STATE_READY	Peripheral Initialized and ready for use
HAL_I2C_STATE_BUSY	An internal process is ongoing
HAL_I2C_STATE_BUSY_TX	Data Transmission process is ongoing
HAL_I2C_STATE_BUSY_RX	Data Reception process is ongoing
HAL_I2C_STATE_LISTEN	Address Listen Mode is ongoing
HAL_I2C_STATE_BUSY_TX_LISTEN	Address Listen Mode and Data Transmission process is ongoing
HAL_I2C_STATE_BUSY_RX_LISTEN	Address Listen Mode and Data Reception process is ongoing
HAL_I2C_STATE_ABORT	Abort user request ongoing
HAL_I2C_STATE_TIMEOUT	Timeout state
HAL_I2C_STATE_ERROR	Error

Definition at line 124 of file stm32l4xx_hal_i2c.h.