STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_adc.c 00004 * @author MCD Application Team 00005 * @brief This file provides firmware functions to manage the following 00006 * functionalities of the Analog to Digital Convertor (ADC) peripheral: 00007 * + Initialization and de-initialization functions 00008 * + IO operation functions 00009 * + State and errors functions 00010 * 00011 @verbatim 00012 ============================================================================== 00013 ##### ADC Peripheral features ##### 00014 ============================================================================== 00015 [..] 00016 (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. 00017 (#) Interrupt generation at the end of conversion, end of injected conversion, 00018 and in case of analog watchdog or overrun events 00019 (#) Single and continuous conversion modes. 00020 (#) Scan mode for automatic conversion of channel 0 to channel x. 00021 (#) Data alignment with in-built data coherency. 00022 (#) Channel-wise programmable sampling time. 00023 (#) External trigger option with configurable polarity for both regular and 00024 injected conversion. 00025 (#) Dual/Triple mode (on devices with 2 ADCs or more). 00026 (#) Configurable DMA data storage in Dual/Triple ADC mode. 00027 (#) Configurable delay between conversions in Dual/Triple interleaved mode. 00028 (#) ADC conversion type (refer to the datasheets). 00029 (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at 00030 slower speed. 00031 (#) ADC input range: VREF(minus) = VIN = VREF(plus). 00032 (#) DMA request generation during regular channel conversion. 00033 00034 00035 ##### How to use this driver ##### 00036 ============================================================================== 00037 [..] 00038 (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit(): 00039 (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() 00040 (##) ADC pins configuration 00041 (+++) Enable the clock for the ADC GPIOs using the following function: 00042 __HAL_RCC_GPIOx_CLK_ENABLE() 00043 (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() 00044 (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) 00045 (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() 00046 (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() 00047 (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler() 00048 (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA()) 00049 (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE() 00050 (+++) Configure and enable two DMA streams stream for managing data 00051 transfer from peripheral to memory (output stream) 00052 (+++) Associate the initialized DMA handle to the CRYP DMA handle 00053 using __HAL_LINKDMA() 00054 (+++) Configure the priority and enable the NVIC for the transfer complete 00055 interrupt on the two DMA Streams. The output stream should have higher 00056 priority than the input stream. 00057 00058 *** Configuration of ADC, groups regular/injected, channels parameters *** 00059 ============================================================================== 00060 [..] 00061 (#) Configure the ADC parameters (resolution, data alignment, ...) 00062 and regular group parameters (conversion trigger, sequencer, ...) 00063 using function HAL_ADC_Init(). 00064 00065 (#) Configure the channels for regular group parameters (channel number, 00066 channel rank into sequencer, ..., into regular group) 00067 using function HAL_ADC_ConfigChannel(). 00068 00069 (#) Optionally, configure the injected group parameters (conversion trigger, 00070 sequencer, ..., of injected group) 00071 and the channels for injected group parameters (channel number, 00072 channel rank into sequencer, ..., into injected group) 00073 using function HAL_ADCEx_InjectedConfigChannel(). 00074 00075 (#) Optionally, configure the analog watchdog parameters (channels 00076 monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig(). 00077 00078 (#) Optionally, for devices with several ADC instances: configure the 00079 multimode parameters using function HAL_ADCEx_MultiModeConfigChannel(). 00080 00081 *** Execution of ADC conversions *** 00082 ============================================================================== 00083 [..] 00084 (#) ADC driver can be used among three modes: polling, interruption, 00085 transfer by DMA. 00086 00087 *** Polling mode IO operation *** 00088 ================================= 00089 [..] 00090 (+) Start the ADC peripheral using HAL_ADC_Start() 00091 (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage 00092 user can specify the value of timeout according to his end application 00093 (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. 00094 (+) Stop the ADC peripheral using HAL_ADC_Stop() 00095 00096 *** Interrupt mode IO operation *** 00097 =================================== 00098 [..] 00099 (+) Start the ADC peripheral using HAL_ADC_Start_IT() 00100 (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine 00101 (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can 00102 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback 00103 (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can 00104 add his own code by customization of function pointer HAL_ADC_ErrorCallback 00105 (+) Stop the ADC peripheral using HAL_ADC_Stop_IT() 00106 00107 *** DMA mode IO operation *** 00108 ============================== 00109 [..] 00110 (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length 00111 of data to be transferred at each end of conversion 00112 (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can 00113 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback 00114 (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can 00115 add his own code by customization of function pointer HAL_ADC_ErrorCallback 00116 (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA() 00117 00118 *** ADC HAL driver macros list *** 00119 ============================================= 00120 [..] 00121 Below the list of most used macros in ADC HAL driver. 00122 00123 (+) __HAL_ADC_ENABLE : Enable the ADC peripheral 00124 (+) __HAL_ADC_DISABLE : Disable the ADC peripheral 00125 (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt 00126 (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt 00127 (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled 00128 (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags 00129 (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status 00130 (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register 00131 00132 [..] 00133 (@) You can refer to the ADC HAL driver header file for more useful macros 00134 00135 *** Deinitialization of ADC *** 00136 ============================================================================== 00137 [..] 00138 (#) Disable the ADC interface 00139 (++) ADC clock can be hard reset and disabled at RCC top level. 00140 (++) Hard reset of ADC peripherals 00141 using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET(). 00142 (++) ADC clock disable using the equivalent macro/functions as configuration step. 00143 (+++) Example: 00144 Into HAL_ADC_MspDeInit() (recommended code location) or with 00145 other device clock parameters configuration: 00146 (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); 00147 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; 00148 (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock) 00149 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); 00150 00151 (#) ADC pins configuration 00152 (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE() 00153 00154 (#) Optionally, in case of usage of ADC with interruptions: 00155 (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn) 00156 00157 (#) Optionally, in case of usage of DMA: 00158 (++) Deinitialize the DMA using function HAL_DMA_DeInit(). 00159 (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn) 00160 00161 @endverbatim 00162 ****************************************************************************** 00163 * @attention 00164 * 00165 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00166 * 00167 * Redistribution and use in source and binary forms, with or without modification, 00168 * are permitted provided that the following conditions are met: 00169 * 1. Redistributions of source code must retain the above copyright notice, 00170 * this list of conditions and the following disclaimer. 00171 * 2. Redistributions in binary form must reproduce the above copyright notice, 00172 * this list of conditions and the following disclaimer in the documentation 00173 * and/or other materials provided with the distribution. 00174 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00175 * may be used to endorse or promote products derived from this software 00176 * without specific prior written permission. 00177 * 00178 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00179 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00180 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00181 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00182 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00183 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00184 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00185 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00186 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00187 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00188 * 00189 ****************************************************************************** 00190 */ 00191 00192 /* Includes ------------------------------------------------------------------*/ 00193 #include "stm32f4xx_hal.h" 00194 00195 /** @addtogroup STM32F4xx_HAL_Driver 00196 * @{ 00197 */ 00198 00199 /** @defgroup ADC ADC 00200 * @brief ADC driver modules 00201 * @{ 00202 */ 00203 00204 #ifdef HAL_ADC_MODULE_ENABLED 00205 00206 /* Private typedef -----------------------------------------------------------*/ 00207 /* Private define ------------------------------------------------------------*/ 00208 /* Private macro -------------------------------------------------------------*/ 00209 /* Private variables ---------------------------------------------------------*/ 00210 /** @addtogroup ADC_Private_Functions 00211 * @{ 00212 */ 00213 /* Private function prototypes -----------------------------------------------*/ 00214 static void ADC_Init(ADC_HandleTypeDef* hadc); 00215 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 00216 static void ADC_DMAError(DMA_HandleTypeDef *hdma); 00217 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 00218 /** 00219 * @} 00220 */ 00221 /* Exported functions --------------------------------------------------------*/ 00222 /** @defgroup ADC_Exported_Functions ADC Exported Functions 00223 * @{ 00224 */ 00225 00226 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions 00227 * @brief Initialization and Configuration functions 00228 * 00229 @verbatim 00230 =============================================================================== 00231 ##### Initialization and de-initialization functions ##### 00232 =============================================================================== 00233 [..] This section provides functions allowing to: 00234 (+) Initialize and configure the ADC. 00235 (+) De-initialize the ADC. 00236 00237 @endverbatim 00238 * @{ 00239 */ 00240 00241 /** 00242 * @brief Initializes the ADCx peripheral according to the specified parameters 00243 * in the ADC_InitStruct and initializes the ADC MSP. 00244 * 00245 * @note This function is used to configure the global features of the ADC ( 00246 * ClockPrescaler, Resolution, Data Alignment and number of conversion), however, 00247 * the rest of the configuration parameters are specific to the regular 00248 * channels group (scan mode activation, continuous mode activation, 00249 * External trigger source and edge, DMA continuous request after the 00250 * last transfer and End of conversion selection). 00251 * 00252 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00253 * the configuration information for the specified ADC. 00254 * @retval HAL status 00255 */ 00256 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) 00257 { 00258 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 00259 00260 /* Check ADC handle */ 00261 if(hadc == NULL) 00262 { 00263 return HAL_ERROR; 00264 } 00265 00266 /* Check the parameters */ 00267 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00268 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); 00269 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); 00270 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode)); 00271 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); 00272 assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv)); 00273 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); 00274 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); 00275 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); 00276 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); 00277 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); 00278 00279 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 00280 { 00281 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 00282 } 00283 00284 if(hadc->State == HAL_ADC_STATE_RESET) 00285 { 00286 /* Initialize ADC error code */ 00287 ADC_CLEAR_ERRORCODE(hadc); 00288 00289 /* Allocate lock resource and initialize it */ 00290 hadc->Lock = HAL_UNLOCKED; 00291 00292 /* Init the low level hardware */ 00293 HAL_ADC_MspInit(hadc); 00294 } 00295 00296 /* Configuration of ADC parameters if previous preliminary actions are */ 00297 /* correctly completed. */ 00298 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 00299 { 00300 /* Set ADC state */ 00301 ADC_STATE_CLR_SET(hadc->State, 00302 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 00303 HAL_ADC_STATE_BUSY_INTERNAL); 00304 00305 /* Set ADC parameters */ 00306 ADC_Init(hadc); 00307 00308 /* Set ADC error code to none */ 00309 ADC_CLEAR_ERRORCODE(hadc); 00310 00311 /* Set the ADC state */ 00312 ADC_STATE_CLR_SET(hadc->State, 00313 HAL_ADC_STATE_BUSY_INTERNAL, 00314 HAL_ADC_STATE_READY); 00315 } 00316 else 00317 { 00318 tmp_hal_status = HAL_ERROR; 00319 } 00320 00321 /* Release Lock */ 00322 __HAL_UNLOCK(hadc); 00323 00324 /* Return function status */ 00325 return tmp_hal_status; 00326 } 00327 00328 /** 00329 * @brief Deinitializes the ADCx peripheral registers to their default reset values. 00330 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00331 * the configuration information for the specified ADC. 00332 * @retval HAL status 00333 */ 00334 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) 00335 { 00336 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 00337 00338 /* Check ADC handle */ 00339 if(hadc == NULL) 00340 { 00341 return HAL_ERROR; 00342 } 00343 00344 /* Check the parameters */ 00345 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00346 00347 /* Set ADC state */ 00348 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); 00349 00350 /* Stop potential conversion on going, on regular and injected groups */ 00351 /* Disable ADC peripheral */ 00352 __HAL_ADC_DISABLE(hadc); 00353 00354 /* Configuration of ADC parameters if previous preliminary actions are */ 00355 /* correctly completed. */ 00356 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) 00357 { 00358 /* DeInit the low level hardware */ 00359 HAL_ADC_MspDeInit(hadc); 00360 00361 /* Set ADC error code to none */ 00362 ADC_CLEAR_ERRORCODE(hadc); 00363 00364 /* Set ADC state */ 00365 hadc->State = HAL_ADC_STATE_RESET; 00366 } 00367 00368 /* Process unlocked */ 00369 __HAL_UNLOCK(hadc); 00370 00371 /* Return function status */ 00372 return tmp_hal_status; 00373 } 00374 00375 /** 00376 * @brief Initializes the ADC MSP. 00377 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00378 * the configuration information for the specified ADC. 00379 * @retval None 00380 */ 00381 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) 00382 { 00383 /* Prevent unused argument(s) compilation warning */ 00384 UNUSED(hadc); 00385 /* NOTE : This function Should not be modified, when the callback is needed, 00386 the HAL_ADC_MspInit could be implemented in the user file 00387 */ 00388 } 00389 00390 /** 00391 * @brief DeInitializes the ADC MSP. 00392 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00393 * the configuration information for the specified ADC. 00394 * @retval None 00395 */ 00396 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) 00397 { 00398 /* Prevent unused argument(s) compilation warning */ 00399 UNUSED(hadc); 00400 /* NOTE : This function Should not be modified, when the callback is needed, 00401 the HAL_ADC_MspDeInit could be implemented in the user file 00402 */ 00403 } 00404 00405 /** 00406 * @} 00407 */ 00408 00409 /** @defgroup ADC_Exported_Functions_Group2 IO operation functions 00410 * @brief IO operation functions 00411 * 00412 @verbatim 00413 =============================================================================== 00414 ##### IO operation functions ##### 00415 =============================================================================== 00416 [..] This section provides functions allowing to: 00417 (+) Start conversion of regular channel. 00418 (+) Stop conversion of regular channel. 00419 (+) Start conversion of regular channel and enable interrupt. 00420 (+) Stop conversion of regular channel and disable interrupt. 00421 (+) Start conversion of regular channel and enable DMA transfer. 00422 (+) Stop conversion of regular channel and disable DMA transfer. 00423 (+) Handle ADC interrupt request. 00424 00425 @endverbatim 00426 * @{ 00427 */ 00428 00429 /** 00430 * @brief Enables ADC and starts conversion of the regular channels. 00431 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00432 * the configuration information for the specified ADC. 00433 * @retval HAL status 00434 */ 00435 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) 00436 { 00437 __IO uint32_t counter = 0U; 00438 ADC_Common_TypeDef *tmpADC_Common; 00439 00440 /* Check the parameters */ 00441 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); 00442 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 00443 00444 /* Process locked */ 00445 __HAL_LOCK(hadc); 00446 00447 /* Enable the ADC peripheral */ 00448 /* Check if ADC peripheral is disabled in order to enable it and wait during 00449 Tstab time the ADC's stabilization */ 00450 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) 00451 { 00452 /* Enable the Peripheral */ 00453 __HAL_ADC_ENABLE(hadc); 00454 00455 /* Delay for ADC stabilization time */ 00456 /* Compute number of CPU cycles to wait for */ 00457 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 00458 while(counter != 0U) 00459 { 00460 counter--; 00461 } 00462 } 00463 00464 /* Start conversion if ADC is effectively enabled */ 00465 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) 00466 { 00467 /* Set ADC state */ 00468 /* - Clear state bitfield related to regular group conversion results */ 00469 /* - Set state bitfield related to regular group operation */ 00470 ADC_STATE_CLR_SET(hadc->State, 00471 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, 00472 HAL_ADC_STATE_REG_BUSY); 00473 00474 /* If conversions on group regular are also triggering group injected, */ 00475 /* update ADC state. */ 00476 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 00477 { 00478 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 00479 } 00480 00481 /* State machine update: Check if an injected conversion is ongoing */ 00482 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 00483 { 00484 /* Reset ADC error code fields related to conversions on group regular */ 00485 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 00486 } 00487 else 00488 { 00489 /* Reset ADC all error code fields */ 00490 ADC_CLEAR_ERRORCODE(hadc); 00491 } 00492 00493 /* Process unlocked */ 00494 /* Unlock before starting ADC conversions: in case of potential */ 00495 /* interruption, to let the process to ADC IRQ Handler. */ 00496 __HAL_UNLOCK(hadc); 00497 00498 /* Pointer to the common control register to which is belonging hadc */ 00499 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ 00500 /* control register) */ 00501 tmpADC_Common = ADC_COMMON_REGISTER(hadc); 00502 00503 /* Clear regular group conversion flag and overrun flag */ 00504 /* (To ensure of no unknown state from potential previous ADC operations) */ 00505 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); 00506 00507 /* Check if Multimode enabled */ 00508 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) 00509 { 00510 /* if no external trigger present enable software conversion of regular channels */ 00511 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 00512 { 00513 /* Enable the selected ADC software conversion for regular group */ 00514 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; 00515 } 00516 } 00517 else 00518 { 00519 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ 00520 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) 00521 { 00522 /* Enable the selected ADC software conversion for regular group */ 00523 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; 00524 } 00525 } 00526 } 00527 00528 /* Return function status */ 00529 return HAL_OK; 00530 } 00531 00532 /** 00533 * @brief Disables ADC and stop conversion of regular channels. 00534 * 00535 * @note Caution: This function will stop also injected channels. 00536 * 00537 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00538 * the configuration information for the specified ADC. 00539 * 00540 * @retval HAL status. 00541 */ 00542 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) 00543 { 00544 /* Check the parameters */ 00545 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00546 00547 /* Process locked */ 00548 __HAL_LOCK(hadc); 00549 00550 /* Stop potential conversion on going, on regular and injected groups */ 00551 /* Disable ADC peripheral */ 00552 __HAL_ADC_DISABLE(hadc); 00553 00554 /* Check if ADC is effectively disabled */ 00555 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) 00556 { 00557 /* Set ADC state */ 00558 ADC_STATE_CLR_SET(hadc->State, 00559 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 00560 HAL_ADC_STATE_READY); 00561 } 00562 00563 /* Process unlocked */ 00564 __HAL_UNLOCK(hadc); 00565 00566 /* Return function status */ 00567 return HAL_OK; 00568 } 00569 00570 /** 00571 * @brief Poll for regular conversion complete 00572 * @note ADC conversion flags EOS (end of sequence) and EOC (end of 00573 * conversion) are cleared by this function. 00574 * @note This function cannot be used in a particular setup: ADC configured 00575 * in DMA mode and polling for end of each conversion (ADC init 00576 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). 00577 * In this case, DMA resets the flag EOC and polling cannot be 00578 * performed on each conversion. Nevertheless, polling can still 00579 * be performed on the complete sequence. 00580 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00581 * the configuration information for the specified ADC. 00582 * @param Timeout Timeout value in millisecond. 00583 * @retval HAL status 00584 */ 00585 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) 00586 { 00587 uint32_t tickstart = 0U; 00588 00589 /* Verification that ADC configuration is compliant with polling for */ 00590 /* each conversion: */ 00591 /* Particular case is ADC configured in DMA mode and ADC sequencer with */ 00592 /* several ranks and polling for end of each conversion. */ 00593 /* For code simplicity sake, this particular case is generalized to */ 00594 /* ADC configured in DMA mode and polling for end of each conversion. */ 00595 if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && 00596 HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) 00597 { 00598 /* Update ADC state machine to error */ 00599 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 00600 00601 /* Process unlocked */ 00602 __HAL_UNLOCK(hadc); 00603 00604 return HAL_ERROR; 00605 } 00606 00607 /* Get tick */ 00608 tickstart = HAL_GetTick(); 00609 00610 /* Check End of conversion flag */ 00611 while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) 00612 { 00613 /* Check if timeout is disabled (set to infinite wait) */ 00614 if(Timeout != HAL_MAX_DELAY) 00615 { 00616 if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) 00617 { 00618 /* Update ADC state machine to timeout */ 00619 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 00620 00621 /* Process unlocked */ 00622 __HAL_UNLOCK(hadc); 00623 00624 return HAL_TIMEOUT; 00625 } 00626 } 00627 } 00628 00629 /* Clear regular group conversion flag */ 00630 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 00631 00632 /* Update ADC state machine */ 00633 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 00634 00635 /* Determine whether any further conversion upcoming on group regular */ 00636 /* by external trigger, continuous mode or scan sequence on going. */ 00637 /* Note: On STM32F4, there is no independent flag of end of sequence. */ 00638 /* The test of scan sequence on going is done either with scan */ 00639 /* sequence disabled or with end of conversion flag set to */ 00640 /* of end of sequence. */ 00641 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 00642 (hadc->Init.ContinuousConvMode == DISABLE) && 00643 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 00644 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) 00645 { 00646 /* Set ADC state */ 00647 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 00648 00649 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 00650 { 00651 SET_BIT(hadc->State, HAL_ADC_STATE_READY); 00652 } 00653 } 00654 00655 /* Return ADC state */ 00656 return HAL_OK; 00657 } 00658 00659 /** 00660 * @brief Poll for conversion event 00661 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00662 * the configuration information for the specified ADC. 00663 * @param EventType the ADC event type. 00664 * This parameter can be one of the following values: 00665 * @arg ADC_AWD_EVENT: ADC Analog watch Dog event. 00666 * @arg ADC_OVR_EVENT: ADC Overrun event. 00667 * @param Timeout Timeout value in millisecond. 00668 * @retval HAL status 00669 */ 00670 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) 00671 { 00672 uint32_t tickstart = 0U; 00673 00674 /* Check the parameters */ 00675 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00676 assert_param(IS_ADC_EVENT_TYPE(EventType)); 00677 00678 /* Get tick */ 00679 tickstart = HAL_GetTick(); 00680 00681 /* Check selected event flag */ 00682 while(!(__HAL_ADC_GET_FLAG(hadc,EventType))) 00683 { 00684 /* Check for the Timeout */ 00685 if(Timeout != HAL_MAX_DELAY) 00686 { 00687 if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) 00688 { 00689 /* Update ADC state machine to timeout */ 00690 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 00691 00692 /* Process unlocked */ 00693 __HAL_UNLOCK(hadc); 00694 00695 return HAL_TIMEOUT; 00696 } 00697 } 00698 } 00699 00700 /* Analog watchdog (level out of window) event */ 00701 if(EventType == ADC_AWD_EVENT) 00702 { 00703 /* Set ADC state */ 00704 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 00705 00706 /* Clear ADC analog watchdog flag */ 00707 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); 00708 } 00709 /* Overrun event */ 00710 else 00711 { 00712 /* Set ADC state */ 00713 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); 00714 /* Set ADC error code to overrun */ 00715 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); 00716 00717 /* Clear ADC overrun flag */ 00718 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); 00719 } 00720 00721 /* Return ADC state */ 00722 return HAL_OK; 00723 } 00724 00725 00726 /** 00727 * @brief Enables the interrupt and starts ADC conversion of regular channels. 00728 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00729 * the configuration information for the specified ADC. 00730 * @retval HAL status. 00731 */ 00732 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) 00733 { 00734 __IO uint32_t counter = 0U; 00735 ADC_Common_TypeDef *tmpADC_Common; 00736 00737 /* Check the parameters */ 00738 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); 00739 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 00740 00741 /* Process locked */ 00742 __HAL_LOCK(hadc); 00743 00744 /* Enable the ADC peripheral */ 00745 /* Check if ADC peripheral is disabled in order to enable it and wait during 00746 Tstab time the ADC's stabilization */ 00747 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) 00748 { 00749 /* Enable the Peripheral */ 00750 __HAL_ADC_ENABLE(hadc); 00751 00752 /* Delay for ADC stabilization time */ 00753 /* Compute number of CPU cycles to wait for */ 00754 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 00755 while(counter != 0U) 00756 { 00757 counter--; 00758 } 00759 } 00760 00761 /* Start conversion if ADC is effectively enabled */ 00762 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) 00763 { 00764 /* Set ADC state */ 00765 /* - Clear state bitfield related to regular group conversion results */ 00766 /* - Set state bitfield related to regular group operation */ 00767 ADC_STATE_CLR_SET(hadc->State, 00768 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, 00769 HAL_ADC_STATE_REG_BUSY); 00770 00771 /* If conversions on group regular are also triggering group injected, */ 00772 /* update ADC state. */ 00773 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 00774 { 00775 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 00776 } 00777 00778 /* State machine update: Check if an injected conversion is ongoing */ 00779 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 00780 { 00781 /* Reset ADC error code fields related to conversions on group regular */ 00782 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 00783 } 00784 else 00785 { 00786 /* Reset ADC all error code fields */ 00787 ADC_CLEAR_ERRORCODE(hadc); 00788 } 00789 00790 /* Process unlocked */ 00791 /* Unlock before starting ADC conversions: in case of potential */ 00792 /* interruption, to let the process to ADC IRQ Handler. */ 00793 __HAL_UNLOCK(hadc); 00794 00795 /* Pointer to the common control register to which is belonging hadc */ 00796 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ 00797 /* control register) */ 00798 tmpADC_Common = ADC_COMMON_REGISTER(hadc); 00799 00800 /* Clear regular group conversion flag and overrun flag */ 00801 /* (To ensure of no unknown state from potential previous ADC operations) */ 00802 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); 00803 00804 /* Enable end of conversion interrupt for regular group */ 00805 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); 00806 00807 /* Check if Multimode enabled */ 00808 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) 00809 { 00810 /* if no external trigger present enable software conversion of regular channels */ 00811 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 00812 { 00813 /* Enable the selected ADC software conversion for regular group */ 00814 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; 00815 } 00816 } 00817 else 00818 { 00819 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ 00820 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) 00821 { 00822 /* Enable the selected ADC software conversion for regular group */ 00823 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; 00824 } 00825 } 00826 } 00827 00828 /* Return function status */ 00829 return HAL_OK; 00830 } 00831 00832 /** 00833 * @brief Disables the interrupt and stop ADC conversion of regular channels. 00834 * 00835 * @note Caution: This function will stop also injected channels. 00836 * 00837 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00838 * the configuration information for the specified ADC. 00839 * @retval HAL status. 00840 */ 00841 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) 00842 { 00843 /* Check the parameters */ 00844 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00845 00846 /* Process locked */ 00847 __HAL_LOCK(hadc); 00848 00849 /* Stop potential conversion on going, on regular and injected groups */ 00850 /* Disable ADC peripheral */ 00851 __HAL_ADC_DISABLE(hadc); 00852 00853 /* Check if ADC is effectively disabled */ 00854 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) 00855 { 00856 /* Disable ADC end of conversion interrupt for regular group */ 00857 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); 00858 00859 /* Set ADC state */ 00860 ADC_STATE_CLR_SET(hadc->State, 00861 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 00862 HAL_ADC_STATE_READY); 00863 } 00864 00865 /* Process unlocked */ 00866 __HAL_UNLOCK(hadc); 00867 00868 /* Return function status */ 00869 return HAL_OK; 00870 } 00871 00872 /** 00873 * @brief Handles ADC interrupt request 00874 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00875 * the configuration information for the specified ADC. 00876 * @retval None 00877 */ 00878 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) 00879 { 00880 uint32_t tmp1 = 0U, tmp2 = 0U; 00881 00882 /* Check the parameters */ 00883 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); 00884 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); 00885 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); 00886 00887 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC); 00888 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC); 00889 /* Check End of conversion flag for regular channels */ 00890 if(tmp1 && tmp2) 00891 { 00892 /* Update state machine on conversion status if not in error state */ 00893 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 00894 { 00895 /* Set ADC state */ 00896 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 00897 } 00898 00899 /* Determine whether any further conversion upcoming on group regular */ 00900 /* by external trigger, continuous mode or scan sequence on going. */ 00901 /* Note: On STM32F4, there is no independent flag of end of sequence. */ 00902 /* The test of scan sequence on going is done either with scan */ 00903 /* sequence disabled or with end of conversion flag set to */ 00904 /* of end of sequence. */ 00905 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 00906 (hadc->Init.ContinuousConvMode == DISABLE) && 00907 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 00908 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) 00909 { 00910 /* Disable ADC end of single conversion interrupt on group regular */ 00911 /* Note: Overrun interrupt was enabled with EOC interrupt in */ 00912 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ 00913 /* by overrun IRQ process below. */ 00914 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); 00915 00916 /* Set ADC state */ 00917 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 00918 00919 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 00920 { 00921 SET_BIT(hadc->State, HAL_ADC_STATE_READY); 00922 } 00923 } 00924 00925 /* Conversion complete callback */ 00926 HAL_ADC_ConvCpltCallback(hadc); 00927 00928 /* Clear regular group conversion flag */ 00929 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 00930 } 00931 00932 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC); 00933 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC); 00934 /* Check End of conversion flag for injected channels */ 00935 if(tmp1 && tmp2) 00936 { 00937 /* Update state machine on conversion status if not in error state */ 00938 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 00939 { 00940 /* Set ADC state */ 00941 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 00942 } 00943 00944 /* Determine whether any further conversion upcoming on group injected */ 00945 /* by external trigger, scan sequence on going or by automatic injected */ 00946 /* conversion from group regular (same conditions as group regular */ 00947 /* interruption disabling above). */ 00948 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && 00949 (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || 00950 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && 00951 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 00952 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 00953 (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) 00954 { 00955 /* Disable ADC end of single conversion interrupt on group injected */ 00956 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 00957 00958 /* Set ADC state */ 00959 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 00960 00961 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 00962 { 00963 SET_BIT(hadc->State, HAL_ADC_STATE_READY); 00964 } 00965 } 00966 00967 /* Conversion complete callback */ 00968 HAL_ADCEx_InjectedConvCpltCallback(hadc); 00969 00970 /* Clear injected group conversion flag */ 00971 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); 00972 } 00973 00974 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD); 00975 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD); 00976 /* Check Analog watchdog flag */ 00977 if(tmp1 && tmp2) 00978 { 00979 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) 00980 { 00981 /* Set ADC state */ 00982 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 00983 00984 /* Level out of window callback */ 00985 HAL_ADC_LevelOutOfWindowCallback(hadc); 00986 00987 /* Clear the ADC analog watchdog flag */ 00988 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); 00989 } 00990 } 00991 00992 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR); 00993 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR); 00994 /* Check Overrun flag */ 00995 if(tmp1 && tmp2) 00996 { 00997 /* Note: On STM32F4, ADC overrun can be set through other parameters */ 00998 /* refer to description of parameter "EOCSelection" for more */ 00999 /* details. */ 01000 01001 /* Set ADC error code to overrun */ 01002 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); 01003 01004 /* Clear ADC overrun flag */ 01005 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); 01006 01007 /* Error callback */ 01008 HAL_ADC_ErrorCallback(hadc); 01009 01010 /* Clear the Overrun flag */ 01011 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); 01012 } 01013 } 01014 01015 /** 01016 * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral 01017 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 01018 * the configuration information for the specified ADC. 01019 * @param pData The destination Buffer address. 01020 * @param Length The length of data to be transferred from ADC peripheral to memory. 01021 * @retval HAL status 01022 */ 01023 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) 01024 { 01025 __IO uint32_t counter = 0U; 01026 ADC_Common_TypeDef *tmpADC_Common; 01027 01028 /* Check the parameters */ 01029 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); 01030 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 01031 01032 /* Process locked */ 01033 __HAL_LOCK(hadc); 01034 01035 /* Enable the ADC peripheral */ 01036 /* Check if ADC peripheral is disabled in order to enable it and wait during 01037 Tstab time the ADC's stabilization */ 01038 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) 01039 { 01040 /* Enable the Peripheral */ 01041 __HAL_ADC_ENABLE(hadc); 01042 01043 /* Delay for ADC stabilization time */ 01044 /* Compute number of CPU cycles to wait for */ 01045 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 01046 while(counter != 0U) 01047 { 01048 counter--; 01049 } 01050 } 01051 01052 /* Start conversion if ADC is effectively enabled */ 01053 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) 01054 { 01055 /* Set ADC state */ 01056 /* - Clear state bitfield related to regular group conversion results */ 01057 /* - Set state bitfield related to regular group operation */ 01058 ADC_STATE_CLR_SET(hadc->State, 01059 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, 01060 HAL_ADC_STATE_REG_BUSY); 01061 01062 /* If conversions on group regular are also triggering group injected, */ 01063 /* update ADC state. */ 01064 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 01065 { 01066 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 01067 } 01068 01069 /* State machine update: Check if an injected conversion is ongoing */ 01070 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 01071 { 01072 /* Reset ADC error code fields related to conversions on group regular */ 01073 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 01074 } 01075 else 01076 { 01077 /* Reset ADC all error code fields */ 01078 ADC_CLEAR_ERRORCODE(hadc); 01079 } 01080 01081 /* Process unlocked */ 01082 /* Unlock before starting ADC conversions: in case of potential */ 01083 /* interruption, to let the process to ADC IRQ Handler. */ 01084 __HAL_UNLOCK(hadc); 01085 01086 /* Pointer to the common control register to which is belonging hadc */ 01087 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ 01088 /* control register) */ 01089 tmpADC_Common = ADC_COMMON_REGISTER(hadc); 01090 01091 /* Set the DMA transfer complete callback */ 01092 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 01093 01094 /* Set the DMA half transfer complete callback */ 01095 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 01096 01097 /* Set the DMA error callback */ 01098 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 01099 01100 01101 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ 01102 /* start (in case of SW start): */ 01103 01104 /* Clear regular group conversion flag and overrun flag */ 01105 /* (To ensure of no unknown state from potential previous ADC operations) */ 01106 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); 01107 01108 /* Enable ADC overrun interrupt */ 01109 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 01110 01111 /* Enable ADC DMA mode */ 01112 hadc->Instance->CR2 |= ADC_CR2_DMA; 01113 01114 /* Start the DMA channel */ 01115 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 01116 01117 /* Check if Multimode enabled */ 01118 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) 01119 { 01120 /* if no external trigger present enable software conversion of regular channels */ 01121 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 01122 { 01123 /* Enable the selected ADC software conversion for regular group */ 01124 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; 01125 } 01126 } 01127 else 01128 { 01129 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ 01130 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) 01131 { 01132 /* Enable the selected ADC software conversion for regular group */ 01133 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; 01134 } 01135 } 01136 } 01137 01138 /* Return function status */ 01139 return HAL_OK; 01140 } 01141 01142 /** 01143 * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral 01144 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 01145 * the configuration information for the specified ADC. 01146 * @retval HAL status 01147 */ 01148 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) 01149 { 01150 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 01151 01152 /* Check the parameters */ 01153 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 01154 01155 /* Process locked */ 01156 __HAL_LOCK(hadc); 01157 01158 /* Stop potential conversion on going, on regular and injected groups */ 01159 /* Disable ADC peripheral */ 01160 __HAL_ADC_DISABLE(hadc); 01161 01162 /* Check if ADC is effectively disabled */ 01163 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) 01164 { 01165 /* Disable the selected ADC DMA mode */ 01166 hadc->Instance->CR2 &= ~ADC_CR2_DMA; 01167 01168 /* Disable the DMA channel (in case of DMA in circular mode or stop while */ 01169 /* DMA transfer is on going) */ 01170 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); 01171 01172 /* Disable ADC overrun interrupt */ 01173 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); 01174 01175 /* Set ADC state */ 01176 ADC_STATE_CLR_SET(hadc->State, 01177 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 01178 HAL_ADC_STATE_READY); 01179 } 01180 01181 /* Process unlocked */ 01182 __HAL_UNLOCK(hadc); 01183 01184 /* Return function status */ 01185 return tmp_hal_status; 01186 } 01187 01188 /** 01189 * @brief Gets the converted value from data register of regular channel. 01190 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 01191 * the configuration information for the specified ADC. 01192 * @retval Converted value 01193 */ 01194 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) 01195 { 01196 /* Return the selected ADC converted value */ 01197 return hadc->Instance->DR; 01198 } 01199 01200 /** 01201 * @brief Regular conversion complete callback in non blocking mode 01202 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 01203 * the configuration information for the specified ADC. 01204 * @retval None 01205 */ 01206 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) 01207 { 01208 /* Prevent unused argument(s) compilation warning */ 01209 UNUSED(hadc); 01210 /* NOTE : This function Should not be modified, when the callback is needed, 01211 the HAL_ADC_ConvCpltCallback could be implemented in the user file 01212 */ 01213 } 01214 01215 /** 01216 * @brief Regular conversion half DMA transfer callback in non blocking mode 01217 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 01218 * the configuration information for the specified ADC. 01219 * @retval None 01220 */ 01221 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) 01222 { 01223 /* Prevent unused argument(s) compilation warning */ 01224 UNUSED(hadc); 01225 /* NOTE : This function Should not be modified, when the callback is needed, 01226 the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file 01227 */ 01228 } 01229 01230 /** 01231 * @brief Analog watchdog callback in non blocking mode 01232 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 01233 * the configuration information for the specified ADC. 01234 * @retval None 01235 */ 01236 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) 01237 { 01238 /* Prevent unused argument(s) compilation warning */ 01239 UNUSED(hadc); 01240 /* NOTE : This function Should not be modified, when the callback is needed, 01241 the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file 01242 */ 01243 } 01244 01245 /** 01246 * @brief Error ADC callback. 01247 * @note In case of error due to overrun when using ADC with DMA transfer 01248 * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"): 01249 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". 01250 * - If needed, restart a new ADC conversion using function 01251 * "HAL_ADC_Start_DMA()" 01252 * (this function is also clearing overrun flag) 01253 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 01254 * the configuration information for the specified ADC. 01255 * @retval None 01256 */ 01257 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) 01258 { 01259 /* Prevent unused argument(s) compilation warning */ 01260 UNUSED(hadc); 01261 /* NOTE : This function Should not be modified, when the callback is needed, 01262 the HAL_ADC_ErrorCallback could be implemented in the user file 01263 */ 01264 } 01265 01266 /** 01267 * @} 01268 */ 01269 01270 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions 01271 * @brief Peripheral Control functions 01272 * 01273 @verbatim 01274 =============================================================================== 01275 ##### Peripheral Control functions ##### 01276 =============================================================================== 01277 [..] This section provides functions allowing to: 01278 (+) Configure regular channels. 01279 (+) Configure injected channels. 01280 (+) Configure multimode. 01281 (+) Configure the analog watch dog. 01282 01283 @endverbatim 01284 * @{ 01285 */ 01286 01287 /** 01288 * @brief Configures for the selected ADC regular channel its corresponding 01289 * rank in the sequencer and its sample time. 01290 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 01291 * the configuration information for the specified ADC. 01292 * @param sConfig ADC configuration structure. 01293 * @retval HAL status 01294 */ 01295 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) 01296 { 01297 __IO uint32_t counter = 0U; 01298 ADC_Common_TypeDef *tmpADC_Common; 01299 01300 /* Check the parameters */ 01301 assert_param(IS_ADC_CHANNEL(sConfig->Channel)); 01302 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); 01303 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); 01304 01305 /* Process locked */ 01306 __HAL_LOCK(hadc); 01307 01308 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ 01309 if (sConfig->Channel > ADC_CHANNEL_9) 01310 { 01311 /* Clear the old sample time */ 01312 hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); 01313 01314 /* Set the new sample time */ 01315 hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); 01316 } 01317 else /* ADC_Channel include in ADC_Channel_[0..9] */ 01318 { 01319 /* Clear the old sample time */ 01320 hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel); 01321 01322 /* Set the new sample time */ 01323 hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel); 01324 } 01325 01326 /* For Rank 1 to 6 */ 01327 if (sConfig->Rank < 7U) 01328 { 01329 /* Clear the old SQx bits for the selected rank */ 01330 hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank); 01331 01332 /* Set the SQx bits for the selected rank */ 01333 hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank); 01334 } 01335 /* For Rank 7 to 12 */ 01336 else if (sConfig->Rank < 13U) 01337 { 01338 /* Clear the old SQx bits for the selected rank */ 01339 hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank); 01340 01341 /* Set the SQx bits for the selected rank */ 01342 hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank); 01343 } 01344 /* For Rank 13 to 16 */ 01345 else 01346 { 01347 /* Clear the old SQx bits for the selected rank */ 01348 hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank); 01349 01350 /* Set the SQx bits for the selected rank */ 01351 hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); 01352 } 01353 01354 /* Pointer to the common control register to which is belonging hadc */ 01355 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ 01356 /* control register) */ 01357 tmpADC_Common = ADC_COMMON_REGISTER(hadc); 01358 01359 /* if ADC1 Channel_18 is selected enable VBAT Channel */ 01360 if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT)) 01361 { 01362 /* Enable the VBAT channel*/ 01363 tmpADC_Common->CCR |= ADC_CCR_VBATE; 01364 } 01365 01366 /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ 01367 if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT))) 01368 { 01369 /* Enable the TSVREFE channel*/ 01370 tmpADC_Common->CCR |= ADC_CCR_TSVREFE; 01371 01372 if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) 01373 { 01374 /* Delay for temperature sensor stabilization time */ 01375 /* Compute number of CPU cycles to wait for */ 01376 counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 01377 while(counter != 0U) 01378 { 01379 counter--; 01380 } 01381 } 01382 } 01383 01384 /* Process unlocked */ 01385 __HAL_UNLOCK(hadc); 01386 01387 /* Return function status */ 01388 return HAL_OK; 01389 } 01390 01391 /** 01392 * @brief Configures the analog watchdog. 01393 * @note Analog watchdog thresholds can be modified while ADC conversion 01394 * is on going. 01395 * In this case, some constraints must be taken into account: 01396 * The programmed threshold values are effective from the next 01397 * ADC EOC (end of unitary conversion). 01398 * Considering that registers write delay may happen due to 01399 * bus activity, this might cause an uncertainty on the 01400 * effective timing of the new programmed threshold values. 01401 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 01402 * the configuration information for the specified ADC. 01403 * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure 01404 * that contains the configuration information of ADC analog watchdog. 01405 * @retval HAL status 01406 */ 01407 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) 01408 { 01409 #ifdef USE_FULL_ASSERT 01410 uint32_t tmp = 0U; 01411 #endif /* USE_FULL_ASSERT */ 01412 01413 /* Check the parameters */ 01414 assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode)); 01415 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); 01416 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); 01417 01418 #ifdef USE_FULL_ASSERT 01419 tmp = ADC_GET_RESOLUTION(hadc); 01420 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold)); 01421 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold)); 01422 #endif /* USE_FULL_ASSERT */ 01423 01424 /* Process locked */ 01425 __HAL_LOCK(hadc); 01426 01427 if(AnalogWDGConfig->ITMode == ENABLE) 01428 { 01429 /* Enable the ADC Analog watchdog interrupt */ 01430 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); 01431 } 01432 else 01433 { 01434 /* Disable the ADC Analog watchdog interrupt */ 01435 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); 01436 } 01437 01438 /* Clear AWDEN, JAWDEN and AWDSGL bits */ 01439 hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN); 01440 01441 /* Set the analog watchdog enable mode */ 01442 hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode; 01443 01444 /* Set the high threshold */ 01445 hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; 01446 01447 /* Set the low threshold */ 01448 hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; 01449 01450 /* Clear the Analog watchdog channel select bits */ 01451 hadc->Instance->CR1 &= ~ADC_CR1_AWDCH; 01452 01453 /* Set the Analog watchdog channel */ 01454 hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel)); 01455 01456 /* Process unlocked */ 01457 __HAL_UNLOCK(hadc); 01458 01459 /* Return function status */ 01460 return HAL_OK; 01461 } 01462 01463 /** 01464 * @} 01465 */ 01466 01467 /** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions 01468 * @brief ADC Peripheral State functions 01469 * 01470 @verbatim 01471 =============================================================================== 01472 ##### Peripheral State and errors functions ##### 01473 =============================================================================== 01474 [..] 01475 This subsection provides functions allowing to 01476 (+) Check the ADC state 01477 (+) Check the ADC Error 01478 01479 @endverbatim 01480 * @{ 01481 */ 01482 01483 /** 01484 * @brief return the ADC state 01485 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 01486 * the configuration information for the specified ADC. 01487 * @retval HAL state 01488 */ 01489 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) 01490 { 01491 /* Return ADC state */ 01492 return hadc->State; 01493 } 01494 01495 /** 01496 * @brief Return the ADC error code 01497 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 01498 * the configuration information for the specified ADC. 01499 * @retval ADC Error Code 01500 */ 01501 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) 01502 { 01503 return hadc->ErrorCode; 01504 } 01505 01506 /** 01507 * @} 01508 */ 01509 01510 /** @addtogroup ADC_Private_Functions 01511 * @{ 01512 */ 01513 01514 /** 01515 * @brief Initializes the ADCx peripheral according to the specified parameters 01516 * in the ADC_InitStruct without initializing the ADC MSP. 01517 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 01518 * the configuration information for the specified ADC. 01519 * @retval None 01520 */ 01521 static void ADC_Init(ADC_HandleTypeDef* hadc) 01522 { 01523 ADC_Common_TypeDef *tmpADC_Common; 01524 01525 /* Set ADC parameters */ 01526 /* Pointer to the common control register to which is belonging hadc */ 01527 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ 01528 /* control register) */ 01529 tmpADC_Common = ADC_COMMON_REGISTER(hadc); 01530 01531 /* Set the ADC clock prescaler */ 01532 tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE); 01533 tmpADC_Common->CCR |= hadc->Init.ClockPrescaler; 01534 01535 /* Set ADC scan mode */ 01536 hadc->Instance->CR1 &= ~(ADC_CR1_SCAN); 01537 hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode); 01538 01539 /* Set ADC resolution */ 01540 hadc->Instance->CR1 &= ~(ADC_CR1_RES); 01541 hadc->Instance->CR1 |= hadc->Init.Resolution; 01542 01543 /* Set ADC data alignment */ 01544 hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN); 01545 hadc->Instance->CR2 |= hadc->Init.DataAlign; 01546 01547 /* Enable external trigger if trigger selection is different of software */ 01548 /* start. */ 01549 /* Note: This configuration keeps the hardware feature of parameter */ 01550 /* ExternalTrigConvEdge "trigger edge none" equivalent to */ 01551 /* software start. */ 01552 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 01553 { 01554 /* Select external trigger to start conversion */ 01555 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); 01556 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv; 01557 01558 /* Select external trigger polarity */ 01559 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); 01560 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge; 01561 } 01562 else 01563 { 01564 /* Reset the external trigger */ 01565 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); 01566 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); 01567 } 01568 01569 /* Enable or disable ADC continuous conversion mode */ 01570 hadc->Instance->CR2 &= ~(ADC_CR2_CONT); 01571 hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode); 01572 01573 if(hadc->Init.DiscontinuousConvMode != DISABLE) 01574 { 01575 assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion)); 01576 01577 /* Enable the selected ADC regular discontinuous mode */ 01578 hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN; 01579 01580 /* Set the number of channels to be converted in discontinuous mode */ 01581 hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM); 01582 hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion); 01583 } 01584 else 01585 { 01586 /* Disable the selected ADC regular discontinuous mode */ 01587 hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN); 01588 } 01589 01590 /* Set ADC number of conversion */ 01591 hadc->Instance->SQR1 &= ~(ADC_SQR1_L); 01592 hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion); 01593 01594 /* Enable or disable ADC DMA continuous request */ 01595 hadc->Instance->CR2 &= ~(ADC_CR2_DDS); 01596 hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests); 01597 01598 /* Enable or disable ADC end of conversion selection */ 01599 hadc->Instance->CR2 &= ~(ADC_CR2_EOCS); 01600 hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection); 01601 } 01602 01603 /** 01604 * @brief DMA transfer complete callback. 01605 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 01606 * the configuration information for the specified DMA module. 01607 * @retval None 01608 */ 01609 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) 01610 { 01611 /* Retrieve ADC handle corresponding to current DMA handle */ 01612 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 01613 01614 /* Update state machine on conversion status if not in error state */ 01615 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) 01616 { 01617 /* Update ADC state machine */ 01618 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 01619 01620 /* Determine whether any further conversion upcoming on group regular */ 01621 /* by external trigger, continuous mode or scan sequence on going. */ 01622 /* Note: On STM32F4, there is no independent flag of end of sequence. */ 01623 /* The test of scan sequence on going is done either with scan */ 01624 /* sequence disabled or with end of conversion flag set to */ 01625 /* of end of sequence. */ 01626 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 01627 (hadc->Init.ContinuousConvMode == DISABLE) && 01628 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 01629 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) 01630 { 01631 /* Disable ADC end of single conversion interrupt on group regular */ 01632 /* Note: Overrun interrupt was enabled with EOC interrupt in */ 01633 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ 01634 /* by overrun IRQ process below. */ 01635 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); 01636 01637 /* Set ADC state */ 01638 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 01639 01640 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 01641 { 01642 SET_BIT(hadc->State, HAL_ADC_STATE_READY); 01643 } 01644 } 01645 01646 /* Conversion complete callback */ 01647 HAL_ADC_ConvCpltCallback(hadc); 01648 } 01649 else 01650 { 01651 /* Call DMA error callback */ 01652 hadc->DMA_Handle->XferErrorCallback(hdma); 01653 } 01654 } 01655 01656 /** 01657 * @brief DMA half transfer complete callback. 01658 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 01659 * the configuration information for the specified DMA module. 01660 * @retval None 01661 */ 01662 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) 01663 { 01664 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 01665 /* Conversion complete callback */ 01666 HAL_ADC_ConvHalfCpltCallback(hadc); 01667 } 01668 01669 /** 01670 * @brief DMA error callback 01671 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 01672 * the configuration information for the specified DMA module. 01673 * @retval None 01674 */ 01675 static void ADC_DMAError(DMA_HandleTypeDef *hdma) 01676 { 01677 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 01678 hadc->State= HAL_ADC_STATE_ERROR_DMA; 01679 /* Set ADC error code to DMA error */ 01680 hadc->ErrorCode |= HAL_ADC_ERROR_DMA; 01681 HAL_ADC_ErrorCallback(hadc); 01682 } 01683 01684 /** 01685 * @} 01686 */ 01687 01688 /** 01689 * @} 01690 */ 01691 01692 #endif /* HAL_ADC_MODULE_ENABLED */ 01693 /** 01694 * @} 01695 */ 01696 01697 /** 01698 * @} 01699 */ 01700 01701 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/