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STM32F439xx HAL User Manual
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Defines | |
| #define | LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U |
| #define | LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 |
| #define | LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 |
| #define | LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) |
| #define | LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 |
| #define | LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) |
| #define | LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) |
| #define | LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) |
| #define | LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 |
| #define | LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) |
| #define | LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) |
| #define | LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) |
| #define | LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) |
| #define | LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) |
| #define | LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) |
| #define | LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) |
| #define | LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 |
| #define | LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) |
| #define | LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) |
| #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) |
TIMx_ARR register is the DMA base address for DMA burst
Definition at line 857 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) |
TIMx_BDTR register is the DMA base address for DMA burst
Definition at line 863 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 |
TIMx_CCER register is the DMA base address for DMA burst
Definition at line 854 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) |
TIMx_CCMR1 register is the DMA base address for DMA burst
Definition at line 852 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) |
TIMx_CCMR2 register is the DMA base address for DMA burst
Definition at line 853 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) |
TIMx_CCR1 register is the DMA base address for DMA burst
Definition at line 859 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) |
TIMx_CCR2 register is the DMA base address for DMA burst
Definition at line 860 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) |
TIMx_CCR3 register is the DMA base address for DMA burst
Definition at line 861 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 |
TIMx_CCR4 register is the DMA base address for DMA burst
Definition at line 862 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) |
TIMx_CNT register is the DMA base address for DMA burst
Definition at line 855 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U |
TIMx_CR1 register is the DMA base address for DMA burst
Definition at line 846 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 |
TIMx_CR2 register is the DMA base address for DMA burst
Definition at line 847 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) |
TIMx_DIER register is the DMA base address for DMA burst
Definition at line 849 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) |
TIMx_EGR register is the DMA base address for DMA burst
Definition at line 851 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) |
Definition at line 864 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) |
TIMx_PSC register is the DMA base address for DMA burst
Definition at line 856 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) |
TIMx_RCR register is the DMA base address for DMA burst
Definition at line 858 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 |
TIMx_SMCR register is the DMA base address for DMA burst
Definition at line 848 of file stm32f4xx_ll_tim.h.
| #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 |
TIMx_SR register is the DMA base address for DMA burst
Definition at line 850 of file stm32f4xx_ll_tim.h.
1.7.6.1