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STM32F439xx HAL User Manual
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Defines | |
| #define | IS_LL_ADC_COMMON_CLOCK(__CLOCK__) |
| #define | IS_LL_ADC_RESOLUTION(__RESOLUTION__) |
| #define | IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) |
| #define | IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) |
| #define | IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) |
| #define | IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) |
| #define | IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) |
| #define | IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) |
| #define | IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) |
| #define | IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) |
| #define | IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) |
| #define | IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) |
| #define | IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) |
| #define | IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) |
| #define | IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) |
| #define | IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) |
| #define | IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) |
| #define | IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) |
| #define | IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) |
| #define | IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) |
| #define | __ADC_MASK_SHIFT(__BITS__, __MASK__) (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) |
| Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0). | |
| #define | __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) |
| Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied. | |
| #define __ADC_MASK_SHIFT | ( | __BITS__, | |
| __MASK__ | |||
| ) | (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) |
Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).
| __BITS__ | Bits in register 32 bits |
| __MASK__ | Mask in register 32 bits |
| Bits | in register 32 bits |
Definition at line 290 of file stm32f4xx_ll_adc.h.
Referenced by LL_ADC_GetChannelSamplingTime(), LL_ADC_INJ_GetOffset(), LL_ADC_INJ_ReadConversionData10(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData32(), LL_ADC_INJ_ReadConversionData6(), LL_ADC_INJ_ReadConversionData8(), LL_ADC_INJ_SetOffset(), LL_ADC_REG_GetSequencerRanks(), LL_ADC_REG_SetSequencerRanks(), and LL_ADC_SetChannelSamplingTime().
| #define __ADC_PTR_REG_OFFSET | ( | __REG__, | |
| __REG_OFFFSET__ | |||
| ) | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) |
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
| __REG__ | Register basis from which the offset is applied. |
| __REG_OFFFSET__ | Offset to be applied (unit number of registers). |
| Pointer | to register address |
Definition at line 301 of file stm32f4xx_ll_adc.h.
Referenced by LL_ADC_GetAnalogWDThresholds(), LL_ADC_GetChannelSamplingTime(), LL_ADC_INJ_GetOffset(), LL_ADC_INJ_ReadConversionData10(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData32(), LL_ADC_INJ_ReadConversionData6(), LL_ADC_INJ_ReadConversionData8(), LL_ADC_INJ_SetOffset(), LL_ADC_REG_GetSequencerRanks(), LL_ADC_REG_SetSequencerRanks(), LL_ADC_SetAnalogWDThresholds(), and LL_ADC_SetChannelSamplingTime().
| #define IS_LL_ADC_COMMON_CLOCK | ( | __CLOCK__ | ) |
( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \ )
Definition at line 68 of file stm32f4xx_ll_adc.c.
Referenced by LL_ADC_CommonInit().
| #define IS_LL_ADC_DATA_ALIGN | ( | __DATA_ALIGN__ | ) |
( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ )
Definition at line 84 of file stm32f4xx_ll_adc.c.
Referenced by LL_ADC_Init().
| #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE | ( | __INJ_SEQ_DISCONT_MODE__ | ) |
( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ )
Definition at line 207 of file stm32f4xx_ll_adc.c.
Referenced by LL_ADC_INJ_Init().
| #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH | ( | __INJ_SEQ_SCAN_LENGTH__ | ) |
( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ )
Definition at line 200 of file stm32f4xx_ll_adc.c.
Referenced by LL_ADC_INJ_Init().
| #define IS_LL_ADC_INJ_TRIG_AUTO | ( | __INJ_TRIG_AUTO__ | ) |
( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ )
Definition at line 195 of file stm32f4xx_ll_adc.c.
Referenced by LL_ADC_INJ_Init().
| #define IS_LL_ADC_INJ_TRIG_EXT_EDGE | ( | __INJ_TRIG_EXT_EDGE__ | ) |
( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ )
Definition at line 189 of file stm32f4xx_ll_adc.c.
| #define IS_LL_ADC_INJ_TRIG_SOURCE | ( | __INJ_TRIG_SOURCE__ | ) |
( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ )
Definition at line 169 of file stm32f4xx_ll_adc.c.
Referenced by LL_ADC_INJ_Init().
| #define IS_LL_ADC_MULTI_DMA_TRANSFER | ( | __MULTI_DMA_TRANSFER__ | ) |
( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \ )
Definition at line 245 of file stm32f4xx_ll_adc.c.
Referenced by LL_ADC_CommonInit().
| #define IS_LL_ADC_MULTI_MASTER_SLAVE | ( | __MULTI_MASTER_SLAVE__ | ) |
( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ )
Definition at line 274 of file stm32f4xx_ll_adc.c.
| #define IS_LL_ADC_MULTI_MODE | ( | __MULTI_MODE__ | ) |
( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \ )
Definition at line 216 of file stm32f4xx_ll_adc.c.
Referenced by LL_ADC_CommonInit().
| #define IS_LL_ADC_MULTI_TWOSMP_DELAY | ( | __MULTI_TWOSMP_DELAY__ | ) |
( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \ )
Definition at line 255 of file stm32f4xx_ll_adc.c.
Referenced by LL_ADC_CommonInit().
| #define IS_LL_ADC_REG_CONTINUOUS_MODE | ( | __REG_CONTINUOUS_MODE__ | ) |
( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ )
Definition at line 120 of file stm32f4xx_ll_adc.c.
Referenced by LL_ADC_REG_Init().
| #define IS_LL_ADC_REG_DMA_TRANSFER | ( | __REG_DMA_TRANSFER__ | ) |
( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ )
Definition at line 125 of file stm32f4xx_ll_adc.c.
Referenced by LL_ADC_REG_Init().
| #define IS_LL_ADC_REG_FLAG_EOC_SELECTION | ( | __REG_FLAG_EOC_SELECTION__ | ) |
( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \ || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \ )
Definition at line 131 of file stm32f4xx_ll_adc.c.
| #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE | ( | __REG_SEQ_DISCONT_MODE__ | ) |
( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ )
Definition at line 155 of file stm32f4xx_ll_adc.c.
Referenced by LL_ADC_REG_Init().
| #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH | ( | __REG_SEQ_SCAN_LENGTH__ | ) |
( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ )
Definition at line 136 of file stm32f4xx_ll_adc.c.
Referenced by LL_ADC_REG_Init().
| #define IS_LL_ADC_REG_TRIG_SOURCE | ( | __REG_TRIG_SOURCE__ | ) |
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ )
Definition at line 101 of file stm32f4xx_ll_adc.c.
Referenced by LL_ADC_REG_Init().
| #define IS_LL_ADC_RESOLUTION | ( | __RESOLUTION__ | ) |
( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ )
Definition at line 77 of file stm32f4xx_ll_adc.c.
Referenced by LL_ADC_Init().
| #define IS_LL_ADC_SCAN_SELECTION | ( | __SCAN_SELECTION__ | ) |
( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ )
Definition at line 89 of file stm32f4xx_ll_adc.c.
Referenced by LL_ADC_Init().
| #define IS_LL_ADC_SEQ_SCAN_MODE | ( | __SEQ_SCAN_MODE__ | ) |
( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ )
Definition at line 94 of file stm32f4xx_ll_adc.c.
1.7.6.1