STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_tim.c 00004 * @author MCD Application Team 00005 * @brief TIM LL module driver. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 #if defined(USE_FULL_LL_DRIVER) 00036 00037 /* Includes ------------------------------------------------------------------*/ 00038 #include "stm32l4xx_ll_tim.h" 00039 #include "stm32l4xx_ll_bus.h" 00040 00041 #ifdef USE_FULL_ASSERT 00042 #include "stm32_assert.h" 00043 #else 00044 #define assert_param(expr) ((void)0U) 00045 #endif 00046 00047 /** @addtogroup STM32L4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7) 00052 00053 /** @addtogroup TIM_LL 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 /* Private constants ---------------------------------------------------------*/ 00060 /* Private macros ------------------------------------------------------------*/ 00061 /** @addtogroup TIM_LL_Private_Macros 00062 * @{ 00063 */ 00064 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ 00065 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ 00066 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ 00067 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ 00068 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) 00069 00070 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ 00071 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ 00072 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) 00073 00074 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ 00075 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ 00076 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ 00077 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ 00078 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ 00079 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ 00080 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ 00081 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ 00082 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ 00083 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ 00084 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ 00085 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ 00086 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ 00087 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2)) 00088 00089 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ 00090 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) 00091 00092 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ 00093 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) 00094 00095 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ 00096 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) 00097 00098 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ 00099 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ 00100 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) 00101 00102 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ 00103 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ 00104 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ 00105 || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) 00106 00107 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ 00108 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ 00109 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ 00110 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ 00111 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ 00112 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ 00113 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ 00114 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ 00115 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ 00116 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ 00117 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ 00118 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ 00119 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ 00120 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ 00121 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ 00122 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) 00123 00124 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ 00125 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ 00126 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) 00127 00128 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ 00129 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ 00130 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) 00131 00132 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ 00133 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) 00134 00135 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ 00136 || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) 00137 00138 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ 00139 || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) 00140 00141 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ 00142 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ 00143 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ 00144 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) 00145 00146 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ 00147 || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) 00148 00149 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ 00150 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) 00151 00152 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \ 00153 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \ 00154 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \ 00155 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \ 00156 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \ 00157 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \ 00158 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \ 00159 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \ 00160 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \ 00161 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \ 00162 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \ 00163 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \ 00164 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \ 00165 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ 00166 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ 00167 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) 00168 00169 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \ 00170 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) 00171 00172 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \ 00173 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) 00174 00175 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \ 00176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ 00177 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ 00178 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ 00179 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ 00180 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ 00181 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ 00182 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ 00183 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ 00184 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ 00185 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ 00186 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ 00187 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ 00188 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ 00189 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ 00190 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) 00191 00192 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ 00193 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) 00194 /** 00195 * @} 00196 */ 00197 00198 00199 /* Private function prototypes -----------------------------------------------*/ 00200 /** @defgroup TIM_LL_Private_Functions TIM Private Functions 00201 * @{ 00202 */ 00203 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); 00204 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); 00205 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); 00206 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); 00207 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); 00208 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); 00209 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); 00210 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); 00211 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); 00212 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); 00213 /** 00214 * @} 00215 */ 00216 00217 /* Exported functions --------------------------------------------------------*/ 00218 /** @addtogroup TIM_LL_Exported_Functions 00219 * @{ 00220 */ 00221 00222 /** @addtogroup TIM_LL_EF_Init 00223 * @{ 00224 */ 00225 00226 /** 00227 * @brief Set TIMx registers to their reset values. 00228 * @param TIMx Timer instance 00229 * @retval An ErrorStatus enumeration value: 00230 * - SUCCESS: TIMx registers are de-initialized 00231 * - ERROR: invalid TIMx instance 00232 */ 00233 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) 00234 { 00235 ErrorStatus result = SUCCESS; 00236 00237 /* Check the parameters */ 00238 assert_param(IS_TIM_INSTANCE(TIMx)); 00239 00240 if (TIMx == TIM1) 00241 { 00242 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1); 00243 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); 00244 } 00245 else if (TIMx == TIM2) 00246 { 00247 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); 00248 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); 00249 } 00250 #if defined(TIM3) 00251 else if (TIMx == TIM3) 00252 { 00253 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); 00254 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); 00255 } 00256 #endif 00257 #if defined(TIM4) 00258 else if (TIMx == TIM4) 00259 { 00260 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); 00261 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); 00262 } 00263 #endif 00264 #if defined(TIM5) 00265 else if (TIMx == TIM5) 00266 { 00267 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); 00268 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); 00269 } 00270 #endif 00271 else if (TIMx == TIM6) 00272 { 00273 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); 00274 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); 00275 } 00276 #if defined (TIM7) 00277 else if (TIMx == TIM7) 00278 { 00279 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); 00280 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); 00281 } 00282 #endif 00283 #if defined(TIM8) 00284 else if (TIMx == TIM8) 00285 { 00286 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8); 00287 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8); 00288 } 00289 #endif 00290 else if (TIMx == TIM15) 00291 { 00292 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15); 00293 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15); 00294 } 00295 else if (TIMx == TIM16) 00296 { 00297 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16); 00298 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16); 00299 } 00300 #if defined(TIM17) 00301 else if (TIMx == TIM17) 00302 { 00303 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17); 00304 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17); 00305 } 00306 #endif 00307 else 00308 { 00309 result = ERROR; 00310 } 00311 00312 return result; 00313 } 00314 00315 /** 00316 * @brief Set the fields of the time base unit configuration data structure 00317 * to their default values. 00318 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure) 00319 * @retval None 00320 */ 00321 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) 00322 { 00323 /* Set the default configuration */ 00324 TIM_InitStruct->Prescaler = (uint16_t)0x0000; 00325 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; 00326 TIM_InitStruct->Autoreload = 0xFFFFFFFFU; 00327 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 00328 TIM_InitStruct->RepetitionCounter = (uint8_t)0x00; 00329 } 00330 00331 /** 00332 * @brief Configure the TIMx time base unit. 00333 * @param TIMx Timer Instance 00334 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure) 00335 * @retval An ErrorStatus enumeration value: 00336 * - SUCCESS: TIMx registers are de-initialized 00337 * - ERROR: not applicable 00338 */ 00339 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) 00340 { 00341 uint32_t tmpcr1; 00342 00343 /* Check the parameters */ 00344 assert_param(IS_TIM_INSTANCE(TIMx)); 00345 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); 00346 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); 00347 00348 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); 00349 00350 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 00351 { 00352 /* Select the Counter Mode */ 00353 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); 00354 } 00355 00356 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 00357 { 00358 /* Set the clock division */ 00359 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); 00360 } 00361 00362 /* Write to TIMx CR1 */ 00363 LL_TIM_WriteReg(TIMx, CR1, tmpcr1); 00364 00365 /* Set the Autoreload value */ 00366 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); 00367 00368 /* Set the Prescaler value */ 00369 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); 00370 00371 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 00372 { 00373 /* Set the Repetition Counter value */ 00374 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter); 00375 } 00376 00377 /* Generate an update event to reload the Prescaler 00378 and the repetition counter value (if applicable) immediately */ 00379 LL_TIM_GenerateEvent_UPDATE(TIMx); 00380 00381 return SUCCESS; 00382 } 00383 00384 /** 00385 * @brief Set the fields of the TIMx output channel configuration data 00386 * structure to their default values. 00387 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure) 00388 * @retval None 00389 */ 00390 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) 00391 { 00392 /* Set the default configuration */ 00393 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; 00394 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; 00395 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; 00396 TIM_OC_InitStruct->CompareValue = 0x00000000U; 00397 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; 00398 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; 00399 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; 00400 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; 00401 } 00402 00403 /** 00404 * @brief Configure the TIMx output channel. 00405 * @param TIMx Timer Instance 00406 * @param Channel This parameter can be one of the following values: 00407 * @arg @ref LL_TIM_CHANNEL_CH1 00408 * @arg @ref LL_TIM_CHANNEL_CH2 00409 * @arg @ref LL_TIM_CHANNEL_CH3 00410 * @arg @ref LL_TIM_CHANNEL_CH4 00411 * @arg @ref LL_TIM_CHANNEL_CH5 00412 * @arg @ref LL_TIM_CHANNEL_CH6 00413 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure) 00414 * @retval An ErrorStatus enumeration value: 00415 * - SUCCESS: TIMx output channel is initialized 00416 * - ERROR: TIMx output channel is not initialized 00417 */ 00418 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) 00419 { 00420 ErrorStatus result = ERROR; 00421 00422 switch (Channel) 00423 { 00424 case LL_TIM_CHANNEL_CH1: 00425 result = OC1Config(TIMx, TIM_OC_InitStruct); 00426 break; 00427 case LL_TIM_CHANNEL_CH2: 00428 result = OC2Config(TIMx, TIM_OC_InitStruct); 00429 break; 00430 case LL_TIM_CHANNEL_CH3: 00431 result = OC3Config(TIMx, TIM_OC_InitStruct); 00432 break; 00433 case LL_TIM_CHANNEL_CH4: 00434 result = OC4Config(TIMx, TIM_OC_InitStruct); 00435 break; 00436 case LL_TIM_CHANNEL_CH5: 00437 result = OC5Config(TIMx, TIM_OC_InitStruct); 00438 break; 00439 case LL_TIM_CHANNEL_CH6: 00440 result = OC6Config(TIMx, TIM_OC_InitStruct); 00441 break; 00442 default: 00443 break; 00444 } 00445 00446 return result; 00447 } 00448 00449 /** 00450 * @brief Set the fields of the TIMx input channel configuration data 00451 * structure to their default values. 00452 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure) 00453 * @retval None 00454 */ 00455 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) 00456 { 00457 /* Set the default configuration */ 00458 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; 00459 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; 00460 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; 00461 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; 00462 } 00463 00464 /** 00465 * @brief Configure the TIMx input channel. 00466 * @param TIMx Timer Instance 00467 * @param Channel This parameter can be one of the following values: 00468 * @arg @ref LL_TIM_CHANNEL_CH1 00469 * @arg @ref LL_TIM_CHANNEL_CH2 00470 * @arg @ref LL_TIM_CHANNEL_CH3 00471 * @arg @ref LL_TIM_CHANNEL_CH4 00472 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure) 00473 * @retval An ErrorStatus enumeration value: 00474 * - SUCCESS: TIMx output channel is initialized 00475 * - ERROR: TIMx output channel is not initialized 00476 */ 00477 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) 00478 { 00479 ErrorStatus result = ERROR; 00480 00481 switch (Channel) 00482 { 00483 case LL_TIM_CHANNEL_CH1: 00484 result = IC1Config(TIMx, TIM_IC_InitStruct); 00485 break; 00486 case LL_TIM_CHANNEL_CH2: 00487 result = IC2Config(TIMx, TIM_IC_InitStruct); 00488 break; 00489 case LL_TIM_CHANNEL_CH3: 00490 result = IC3Config(TIMx, TIM_IC_InitStruct); 00491 break; 00492 case LL_TIM_CHANNEL_CH4: 00493 result = IC4Config(TIMx, TIM_IC_InitStruct); 00494 break; 00495 default: 00496 break; 00497 } 00498 00499 return result; 00500 } 00501 00502 /** 00503 * @brief Fills each TIM_EncoderInitStruct field with its default value 00504 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure) 00505 * @retval None 00506 */ 00507 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) 00508 { 00509 /* Set the default configuration */ 00510 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; 00511 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; 00512 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; 00513 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; 00514 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; 00515 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; 00516 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; 00517 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; 00518 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; 00519 } 00520 00521 /** 00522 * @brief Configure the encoder interface of the timer instance. 00523 * @param TIMx Timer Instance 00524 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure) 00525 * @retval An ErrorStatus enumeration value: 00526 * - SUCCESS: TIMx registers are de-initialized 00527 * - ERROR: not applicable 00528 */ 00529 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) 00530 { 00531 uint32_t tmpccmr1; 00532 uint32_t tmpccer; 00533 00534 /* Check the parameters */ 00535 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); 00536 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); 00537 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); 00538 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); 00539 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); 00540 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); 00541 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); 00542 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); 00543 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); 00544 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); 00545 00546 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ 00547 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); 00548 00549 /* Get the TIMx CCMR1 register value */ 00550 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); 00551 00552 /* Get the TIMx CCER register value */ 00553 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 00554 00555 /* Configure TI1 */ 00556 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); 00557 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); 00558 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); 00559 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); 00560 00561 /* Configure TI2 */ 00562 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); 00563 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); 00564 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); 00565 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); 00566 00567 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ 00568 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); 00569 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); 00570 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); 00571 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); 00572 00573 /* Set encoder mode */ 00574 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); 00575 00576 /* Write to TIMx CCMR1 */ 00577 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); 00578 00579 /* Write to TIMx CCER */ 00580 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 00581 00582 return SUCCESS; 00583 } 00584 00585 /** 00586 * @brief Set the fields of the TIMx Hall sensor interface configuration data 00587 * structure to their default values. 00588 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure) 00589 * @retval None 00590 */ 00591 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) 00592 { 00593 /* Set the default configuration */ 00594 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; 00595 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; 00596 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; 00597 TIM_HallSensorInitStruct->CommutationDelay = 0U; 00598 } 00599 00600 /** 00601 * @brief Configure the Hall sensor interface of the timer instance. 00602 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR 00603 * to the TI1 input channel 00604 * @note TIMx slave mode controller is configured in reset mode. 00605 Selected internal trigger is TI1F_ED. 00606 * @note Channel 1 is configured as input, IC1 is mapped on TRC. 00607 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed 00608 * between 2 changes on the inputs. It gives information about motor speed. 00609 * @note Channel 2 is configured in output PWM 2 mode. 00610 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. 00611 * @note OC2REF is selected as trigger output on TRGO. 00612 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used 00613 * when TIMx operates in Hall sensor interface mode. 00614 * @param TIMx Timer Instance 00615 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure) 00616 * @retval An ErrorStatus enumeration value: 00617 * - SUCCESS: TIMx registers are de-initialized 00618 * - ERROR: not applicable 00619 */ 00620 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) 00621 { 00622 uint32_t tmpcr2; 00623 uint32_t tmpccmr1; 00624 uint32_t tmpccer; 00625 uint32_t tmpsmcr; 00626 00627 /* Check the parameters */ 00628 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); 00629 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity)); 00630 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler)); 00631 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter)); 00632 00633 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ 00634 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); 00635 00636 /* Get the TIMx CR2 register value */ 00637 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); 00638 00639 /* Get the TIMx CCMR1 register value */ 00640 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); 00641 00642 /* Get the TIMx CCER register value */ 00643 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 00644 00645 /* Get the TIMx SMCR register value */ 00646 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR); 00647 00648 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ 00649 tmpcr2 |= TIM_CR2_TI1S; 00650 00651 /* OC2REF signal is used as trigger output (TRGO) */ 00652 tmpcr2 |= LL_TIM_TRGO_OC2REF; 00653 00654 /* Configure the slave mode controller */ 00655 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS); 00656 tmpsmcr |= LL_TIM_TS_TI1F_ED; 00657 tmpsmcr |= LL_TIM_SLAVEMODE_RESET; 00658 00659 /* Configure input channel 1 */ 00660 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); 00661 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); 00662 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); 00663 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); 00664 00665 /* Configure input channel 2 */ 00666 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE); 00667 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); 00668 00669 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ 00670 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); 00671 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); 00672 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); 00673 00674 /* Write to TIMx CR2 */ 00675 LL_TIM_WriteReg(TIMx, CR2, tmpcr2); 00676 00677 /* Write to TIMx SMCR */ 00678 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr); 00679 00680 /* Write to TIMx CCMR1 */ 00681 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); 00682 00683 /* Write to TIMx CCER */ 00684 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 00685 00686 /* Write to TIMx CCR2 */ 00687 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay); 00688 00689 return SUCCESS; 00690 } 00691 00692 /** 00693 * @brief Set the fields of the Break and Dead Time configuration data structure 00694 * to their default values. 00695 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) 00696 * @retval None 00697 */ 00698 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) 00699 { 00700 /* Set the default configuration */ 00701 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; 00702 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; 00703 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; 00704 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00; 00705 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; 00706 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; 00707 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; 00708 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE; 00709 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW; 00710 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1; 00711 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; 00712 } 00713 00714 /** 00715 * @brief Configure the Break and Dead Time feature of the timer instance. 00716 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR 00717 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it 00718 * can be necessary to configure all of them during the first write access to 00719 * the TIMx_BDTR register. 00720 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 00721 * a timer instance provides a break input. 00722 * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 00723 * a timer instance provides a second break input. 00724 * @param TIMx Timer Instance 00725 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) 00726 * @retval An ErrorStatus enumeration value: 00727 * - SUCCESS: Break and Dead Time is initialized 00728 * - ERROR: not applicable 00729 */ 00730 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) 00731 { 00732 uint32_t tmpbdtr = 0; 00733 00734 /* Check the parameters */ 00735 assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); 00736 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); 00737 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); 00738 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); 00739 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); 00740 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); 00741 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); 00742 00743 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, 00744 the OSSI State, the dead time value and the Automatic Output Enable Bit */ 00745 00746 /* Set the BDTR bits */ 00747 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); 00748 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); 00749 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); 00750 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); 00751 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); 00752 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); 00753 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); 00754 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); 00755 if (IS_TIM_ADVANCED_INSTANCE(TIMx)) 00756 { 00757 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); 00758 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); 00759 } 00760 00761 if (IS_TIM_BKIN2_INSTANCE(TIMx)) 00762 { 00763 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State)); 00764 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity)); 00765 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter)); 00766 00767 /* Set the BREAK2 input related BDTR bit-fields */ 00768 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter)); 00769 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State); 00770 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); 00771 } 00772 00773 /* Set TIMx_BDTR */ 00774 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); 00775 00776 return SUCCESS; 00777 } 00778 /** 00779 * @} 00780 */ 00781 00782 /** 00783 * @} 00784 */ 00785 00786 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions 00787 * @brief Private functions 00788 * @{ 00789 */ 00790 /** 00791 * @brief Configure the TIMx output channel 1. 00792 * @param TIMx Timer Instance 00793 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure 00794 * @retval An ErrorStatus enumeration value: 00795 * - SUCCESS: TIMx registers are de-initialized 00796 * - ERROR: not applicable 00797 */ 00798 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) 00799 { 00800 uint32_t tmpccmr1; 00801 uint32_t tmpccer; 00802 uint32_t tmpcr2; 00803 00804 /* Check the parameters */ 00805 assert_param(IS_TIM_CC1_INSTANCE(TIMx)); 00806 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); 00807 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); 00808 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); 00809 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); 00810 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); 00811 00812 /* Disable the Channel 1: Reset the CC1E Bit */ 00813 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); 00814 00815 /* Get the TIMx CCER register value */ 00816 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 00817 00818 /* Get the TIMx CR2 register value */ 00819 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); 00820 00821 /* Get the TIMx CCMR1 register value */ 00822 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); 00823 00824 /* Reset Capture/Compare selection Bits */ 00825 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); 00826 00827 /* Set the Output Compare Mode */ 00828 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); 00829 00830 /* Set the Output Compare Polarity */ 00831 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); 00832 00833 /* Set the Output State */ 00834 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); 00835 00836 if (IS_TIM_BREAK_INSTANCE(TIMx)) 00837 { 00838 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); 00839 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); 00840 00841 /* Set the complementary output Polarity */ 00842 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); 00843 00844 /* Set the complementary output State */ 00845 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); 00846 00847 /* Set the Output Idle state */ 00848 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); 00849 00850 /* Set the complementary output Idle state */ 00851 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); 00852 } 00853 00854 /* Write to TIMx CR2 */ 00855 LL_TIM_WriteReg(TIMx, CR2, tmpcr2); 00856 00857 /* Write to TIMx CCMR1 */ 00858 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); 00859 00860 /* Set the Capture Compare Register value */ 00861 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); 00862 00863 /* Write to TIMx CCER */ 00864 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 00865 00866 return SUCCESS; 00867 } 00868 00869 /** 00870 * @brief Configure the TIMx output channel 2. 00871 * @param TIMx Timer Instance 00872 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure 00873 * @retval An ErrorStatus enumeration value: 00874 * - SUCCESS: TIMx registers are de-initialized 00875 * - ERROR: not applicable 00876 */ 00877 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) 00878 { 00879 uint32_t tmpccmr1; 00880 uint32_t tmpccer; 00881 uint32_t tmpcr2; 00882 00883 /* Check the parameters */ 00884 assert_param(IS_TIM_CC2_INSTANCE(TIMx)); 00885 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); 00886 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); 00887 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); 00888 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); 00889 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); 00890 00891 /* Disable the Channel 2: Reset the CC2E Bit */ 00892 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); 00893 00894 /* Get the TIMx CCER register value */ 00895 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 00896 00897 /* Get the TIMx CR2 register value */ 00898 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); 00899 00900 /* Get the TIMx CCMR1 register value */ 00901 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); 00902 00903 /* Reset Capture/Compare selection Bits */ 00904 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); 00905 00906 /* Select the Output Compare Mode */ 00907 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); 00908 00909 /* Set the Output Compare Polarity */ 00910 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); 00911 00912 /* Set the Output State */ 00913 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); 00914 00915 if (IS_TIM_BREAK_INSTANCE(TIMx)) 00916 { 00917 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); 00918 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); 00919 00920 /* Set the complementary output Polarity */ 00921 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); 00922 00923 /* Set the complementary output State */ 00924 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); 00925 00926 /* Set the Output Idle state */ 00927 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); 00928 00929 /* Set the complementary output Idle state */ 00930 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); 00931 } 00932 00933 /* Write to TIMx CR2 */ 00934 LL_TIM_WriteReg(TIMx, CR2, tmpcr2); 00935 00936 /* Write to TIMx CCMR1 */ 00937 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); 00938 00939 /* Set the Capture Compare Register value */ 00940 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); 00941 00942 /* Write to TIMx CCER */ 00943 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 00944 00945 return SUCCESS; 00946 } 00947 00948 /** 00949 * @brief Configure the TIMx output channel 3. 00950 * @param TIMx Timer Instance 00951 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure 00952 * @retval An ErrorStatus enumeration value: 00953 * - SUCCESS: TIMx registers are de-initialized 00954 * - ERROR: not applicable 00955 */ 00956 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) 00957 { 00958 uint32_t tmpccmr2; 00959 uint32_t tmpccer; 00960 uint32_t tmpcr2; 00961 00962 /* Check the parameters */ 00963 assert_param(IS_TIM_CC3_INSTANCE(TIMx)); 00964 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); 00965 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); 00966 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); 00967 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); 00968 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); 00969 00970 /* Disable the Channel 3: Reset the CC3E Bit */ 00971 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); 00972 00973 /* Get the TIMx CCER register value */ 00974 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 00975 00976 /* Get the TIMx CR2 register value */ 00977 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); 00978 00979 /* Get the TIMx CCMR2 register value */ 00980 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); 00981 00982 /* Reset Capture/Compare selection Bits */ 00983 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); 00984 00985 /* Select the Output Compare Mode */ 00986 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); 00987 00988 /* Set the Output Compare Polarity */ 00989 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); 00990 00991 /* Set the Output State */ 00992 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); 00993 00994 if (IS_TIM_BREAK_INSTANCE(TIMx)) 00995 { 00996 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); 00997 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); 00998 00999 /* Set the complementary output Polarity */ 01000 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); 01001 01002 /* Set the complementary output State */ 01003 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); 01004 01005 /* Set the Output Idle state */ 01006 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); 01007 01008 /* Set the complementary output Idle state */ 01009 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); 01010 } 01011 01012 /* Write to TIMx CR2 */ 01013 LL_TIM_WriteReg(TIMx, CR2, tmpcr2); 01014 01015 /* Write to TIMx CCMR2 */ 01016 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); 01017 01018 /* Set the Capture Compare Register value */ 01019 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); 01020 01021 /* Write to TIMx CCER */ 01022 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 01023 01024 return SUCCESS; 01025 } 01026 01027 /** 01028 * @brief Configure the TIMx output channel 4. 01029 * @param TIMx Timer Instance 01030 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure 01031 * @retval An ErrorStatus enumeration value: 01032 * - SUCCESS: TIMx registers are de-initialized 01033 * - ERROR: not applicable 01034 */ 01035 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) 01036 { 01037 uint32_t tmpccmr2; 01038 uint32_t tmpccer; 01039 uint32_t tmpcr2; 01040 01041 /* Check the parameters */ 01042 assert_param(IS_TIM_CC4_INSTANCE(TIMx)); 01043 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); 01044 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); 01045 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); 01046 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); 01047 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); 01048 01049 /* Disable the Channel 4: Reset the CC4E Bit */ 01050 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); 01051 01052 /* Get the TIMx CCER register value */ 01053 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 01054 01055 /* Get the TIMx CR2 register value */ 01056 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); 01057 01058 /* Get the TIMx CCMR2 register value */ 01059 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); 01060 01061 /* Reset Capture/Compare selection Bits */ 01062 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); 01063 01064 /* Select the Output Compare Mode */ 01065 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); 01066 01067 /* Set the Output Compare Polarity */ 01068 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); 01069 01070 /* Set the Output State */ 01071 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); 01072 01073 if (IS_TIM_BREAK_INSTANCE(TIMx)) 01074 { 01075 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); 01076 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); 01077 01078 /* Set the Output Idle state */ 01079 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); 01080 } 01081 01082 /* Write to TIMx CR2 */ 01083 LL_TIM_WriteReg(TIMx, CR2, tmpcr2); 01084 01085 /* Write to TIMx CCMR2 */ 01086 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); 01087 01088 /* Set the Capture Compare Register value */ 01089 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); 01090 01091 /* Write to TIMx CCER */ 01092 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 01093 01094 return SUCCESS; 01095 } 01096 01097 /** 01098 * @brief Configure the TIMx output channel 5. 01099 * @param TIMx Timer Instance 01100 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure 01101 * @retval An ErrorStatus enumeration value: 01102 * - SUCCESS: TIMx registers are de-initialized 01103 * - ERROR: not applicable 01104 */ 01105 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) 01106 { 01107 uint32_t tmpccmr3; 01108 uint32_t tmpccer; 01109 01110 /* Check the parameters */ 01111 assert_param(IS_TIM_CC5_INSTANCE(TIMx)); 01112 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); 01113 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); 01114 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); 01115 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); 01116 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); 01117 01118 /* Disable the Channel 5: Reset the CC5E Bit */ 01119 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); 01120 01121 /* Get the TIMx CCER register value */ 01122 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 01123 01124 /* Get the TIMx CCMR3 register value */ 01125 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); 01126 01127 /* Select the Output Compare Mode */ 01128 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode); 01129 01130 /* Set the Output Compare Polarity */ 01131 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U); 01132 01133 /* Set the Output State */ 01134 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U); 01135 01136 if (IS_TIM_BREAK_INSTANCE(TIMx)) 01137 { 01138 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); 01139 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); 01140 01141 /* Set the Output Idle state */ 01142 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U); 01143 01144 } 01145 01146 /* Write to TIMx CCMR3 */ 01147 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); 01148 01149 /* Set the Capture Compare Register value */ 01150 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue); 01151 01152 /* Write to TIMx CCER */ 01153 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 01154 01155 return SUCCESS; 01156 } 01157 01158 /** 01159 * @brief Configure the TIMx output channel 6. 01160 * @param TIMx Timer Instance 01161 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure 01162 * @retval An ErrorStatus enumeration value: 01163 * - SUCCESS: TIMx registers are de-initialized 01164 * - ERROR: not applicable 01165 */ 01166 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) 01167 { 01168 uint32_t tmpccmr3; 01169 uint32_t tmpccer; 01170 01171 /* Check the parameters */ 01172 assert_param(IS_TIM_CC6_INSTANCE(TIMx)); 01173 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); 01174 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); 01175 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); 01176 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); 01177 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); 01178 01179 /* Disable the Channel 5: Reset the CC6E Bit */ 01180 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); 01181 01182 /* Get the TIMx CCER register value */ 01183 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 01184 01185 /* Get the TIMx CCMR3 register value */ 01186 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); 01187 01188 /* Select the Output Compare Mode */ 01189 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U); 01190 01191 /* Set the Output Compare Polarity */ 01192 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U); 01193 01194 /* Set the Output State */ 01195 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U); 01196 01197 if (IS_TIM_BREAK_INSTANCE(TIMx)) 01198 { 01199 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); 01200 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); 01201 01202 /* Set the Output Idle state */ 01203 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U); 01204 } 01205 01206 /* Write to TIMx CCMR3 */ 01207 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); 01208 01209 /* Set the Capture Compare Register value */ 01210 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue); 01211 01212 /* Write to TIMx CCER */ 01213 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 01214 01215 return SUCCESS; 01216 } 01217 01218 /** 01219 * @brief Configure the TIMx input channel 1. 01220 * @param TIMx Timer Instance 01221 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure 01222 * @retval An ErrorStatus enumeration value: 01223 * - SUCCESS: TIMx registers are de-initialized 01224 * - ERROR: not applicable 01225 */ 01226 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) 01227 { 01228 /* Check the parameters */ 01229 assert_param(IS_TIM_CC1_INSTANCE(TIMx)); 01230 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); 01231 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); 01232 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); 01233 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); 01234 01235 /* Disable the Channel 1: Reset the CC1E Bit */ 01236 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; 01237 01238 /* Select the Input and set the filter and the prescaler value */ 01239 MODIFY_REG(TIMx->CCMR1, 01240 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), 01241 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); 01242 01243 /* Select the Polarity and set the CC1E Bit */ 01244 MODIFY_REG(TIMx->CCER, 01245 (TIM_CCER_CC1P | TIM_CCER_CC1NP), 01246 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); 01247 01248 return SUCCESS; 01249 } 01250 01251 /** 01252 * @brief Configure the TIMx input channel 2. 01253 * @param TIMx Timer Instance 01254 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure 01255 * @retval An ErrorStatus enumeration value: 01256 * - SUCCESS: TIMx registers are de-initialized 01257 * - ERROR: not applicable 01258 */ 01259 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) 01260 { 01261 /* Check the parameters */ 01262 assert_param(IS_TIM_CC2_INSTANCE(TIMx)); 01263 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); 01264 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); 01265 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); 01266 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); 01267 01268 /* Disable the Channel 2: Reset the CC2E Bit */ 01269 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; 01270 01271 /* Select the Input and set the filter and the prescaler value */ 01272 MODIFY_REG(TIMx->CCMR1, 01273 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), 01274 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); 01275 01276 /* Select the Polarity and set the CC2E Bit */ 01277 MODIFY_REG(TIMx->CCER, 01278 (TIM_CCER_CC2P | TIM_CCER_CC2NP), 01279 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E)); 01280 01281 return SUCCESS; 01282 } 01283 01284 /** 01285 * @brief Configure the TIMx input channel 3. 01286 * @param TIMx Timer Instance 01287 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure 01288 * @retval An ErrorStatus enumeration value: 01289 * - SUCCESS: TIMx registers are de-initialized 01290 * - ERROR: not applicable 01291 */ 01292 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) 01293 { 01294 /* Check the parameters */ 01295 assert_param(IS_TIM_CC3_INSTANCE(TIMx)); 01296 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); 01297 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); 01298 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); 01299 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); 01300 01301 /* Disable the Channel 3: Reset the CC3E Bit */ 01302 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; 01303 01304 /* Select the Input and set the filter and the prescaler value */ 01305 MODIFY_REG(TIMx->CCMR2, 01306 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), 01307 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); 01308 01309 /* Select the Polarity and set the CC3E Bit */ 01310 MODIFY_REG(TIMx->CCER, 01311 (TIM_CCER_CC3P | TIM_CCER_CC3NP), 01312 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E)); 01313 01314 return SUCCESS; 01315 } 01316 01317 /** 01318 * @brief Configure the TIMx input channel 4. 01319 * @param TIMx Timer Instance 01320 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure 01321 * @retval An ErrorStatus enumeration value: 01322 * - SUCCESS: TIMx registers are de-initialized 01323 * - ERROR: not applicable 01324 */ 01325 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) 01326 { 01327 /* Check the parameters */ 01328 assert_param(IS_TIM_CC4_INSTANCE(TIMx)); 01329 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); 01330 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); 01331 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); 01332 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); 01333 01334 /* Disable the Channel 4: Reset the CC4E Bit */ 01335 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; 01336 01337 /* Select the Input and set the filter and the prescaler value */ 01338 MODIFY_REG(TIMx->CCMR2, 01339 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), 01340 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); 01341 01342 /* Select the Polarity and set the CC2E Bit */ 01343 MODIFY_REG(TIMx->CCER, 01344 (TIM_CCER_CC4P | TIM_CCER_CC4NP), 01345 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); 01346 01347 return SUCCESS; 01348 } 01349 01350 01351 /** 01352 * @} 01353 */ 01354 01355 /** 01356 * @} 01357 */ 01358 01359 #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */ 01360 01361 /** 01362 * @} 01363 */ 01364 01365 #endif /* USE_FULL_LL_DRIVER */ 01366 01367 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/